JPH033363A - Manufacture of semiconductor thin film - Google Patents

Manufacture of semiconductor thin film

Info

Publication number
JPH033363A
JPH033363A JP13597089A JP13597089A JPH033363A JP H033363 A JPH033363 A JP H033363A JP 13597089 A JP13597089 A JP 13597089A JP 13597089 A JP13597089 A JP 13597089A JP H033363 A JPH033363 A JP H033363A
Authority
JP
Japan
Prior art keywords
inp
layer
grown
single crystal
lattice constant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13597089A
Other languages
Japanese (ja)
Inventor
Hideaki Horikawa
英明 堀川
Yasuhiro Matsui
康浩 松井
Hiroshi Wada
浩 和田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP13597089A priority Critical patent/JPH033363A/en
Publication of JPH033363A publication Critical patent/JPH033363A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a method wherein problems of crystal defect and surface roughness caused by lattice unconformity are solved, by a method wherein an InP single crystal layer is grown after a specified buffer layer is formed on an Si substrate, thereon an InP single crystal layer is grown and heat-treated, and thereon a GaInAsP multilayer film whose lattice constant is changed stepwise is grown. CONSTITUTION:On an Si substrate 1, amorphous or polycrystalline GaAs buffer layer 2 and InP buffer layer 3 are formed in order; an InP single crystal layer 4 is grown on the InP buffer layer 3, and heattreated in a PH3 atmosphere. After a GaInAsP multilayer film 5 whose lattice constant is changed stepwise is formed on the InP single crystal layer 4, an InP single crystal layer 6 is grown on the GaInAsP multilayer film 5. For example, the above GaInAsP multilayer film 5 is grown first by using GaInAsP whose lattice constant is nearly equal to that of the InP layer 4, and then grown to be a multilayer whose lattice constant approaches the original lattice constant of InP. The thickness of each layer is made so thin that lattice defect does not occur even if lattice discrepancy exists. For example, the thickness is about 10-100Angstrom .

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は、S#基板上に結晶欠陥の少ない単結晶In
Pを成長させる半導体薄膜の製造方法に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) This invention is a method for manufacturing single crystal In with few crystal defects on an S# substrate.
The present invention relates to a method for manufacturing a semiconductor thin film in which P is grown.

(従来の技術) 従来、この種の結晶成長方法は、IK33回応用物理学
関係連合講演予稿集第723頁4P−W−2(1986
年春)に開示されるものがあり、以下に図を用いて簡単
に説明する。
(Prior art) Conventionally, this type of crystal growth method has been described in IK 33rd Applied Physics Conference Proceedings, p. 723, 4P-W-2 (1986
There is one that will be disclosed in the spring of 2018, and it will be briefly explained below using the diagram.

この成長方法は原料に水素化合物と有機金属を用い熱分
解反応を利用する有機金属気相成長法(MOVPE :
 ?1etal Organic Vapor Pha
se EpitaxyまたはMOVPE  : Met
al Organic Chemical Vappo
rDeposltion)を用いた方法である。
This growth method is called metal organic vapor phase epitaxy (MOVPE), which uses a hydrogen compound and an organic metal as raw materials and utilizes a thermal decomposition reaction.
? 1etal Organic Vapor Pha
se Epitaxy or MOVPE: Met
al Organic Chemical Vappo
This is a method using

第2図に示すように(100)表面をもっSt基板11
上に、Inの原料であるトリエチルインジウム(T E
 I 、 (cAL)sin ) 、Pの原料としてホ
スフィン(PHI)を用いて単結晶InP12を直接成
長させている。
As shown in FIG. 2, the St substrate 11 has a (100) surface.
On top is triethyl indium (T E
Single crystal InP12 is directly grown using phosphine (PHI) as a raw material for I, (cAL)sin) and P.

(発明が解決しようとする課S) しかしながら、上記の成長方法では、格子定数がSiに
比べて約8%大きいInP12を直接成長させているた
め、この格子不整合に起因する結晶欠陥が多く発生する
(Problem S to be solved by the invention) However, in the above growth method, since InP12, whose lattice constant is approximately 8% larger than that of Si, is directly grown, many crystal defects occur due to this lattice mismatch. do.

また、それに伴なって、表面が平坦で鏡面である結晶が
得にくいという問題があった。
Additionally, there is a problem in that it is difficult to obtain a crystal with a flat, mirror-like surface.

この発明は、前記従来技術がもっている問題点のうち、
格子不整合に起因する結晶欠陥が多発する点と、表面荒
れの問題点について解決した半導体1IIIlの製造方
法を提供するものである。
This invention solves the problems of the above-mentioned prior art.
The present invention provides a method for manufacturing semiconductor 1III1 that solves the problems of frequent occurrence of crystal defects due to lattice mismatch and surface roughness.

(課題を解決するための手段) この発明は、半導体薄膜の製造方法において、Sl基板
上にアモルファスまたは多結晶のGaAsバッファ層と
I+lIPバッファ層を順次形成する工程と、このIn
Pバシファn上877P単結晶層を成長してPKs雰囲
気中で加熱処理する工程と、このInP層の上に格子定
数を段階的に変化させたGaInAsP多層膜を形成す
る工程とを導入したものである。
(Means for Solving the Problems) The present invention provides a method for manufacturing a semiconductor thin film, including a step of sequentially forming an amorphous or polycrystalline GaAs buffer layer and an I+lIP buffer layer on an Sl substrate, and
This method introduces the steps of growing an 877P single crystal layer on P Bacifern and heat-treating it in a PKs atmosphere, and forming a GaInAsP multilayer film with a stepwise change in lattice constant on this InP layer. be.

(作 用) この発明は、半導体mllの製造方法において、以上の
ような工程を導入したので、Si基板上にGaAsバッ
ファ層とInPnツバ2フフの成長温度よりも低温で形
成してアモルファス状または多結晶状とし、格子定数の
異なるSi基板上でも平坦になり、この上にInP単結
晶層を成長させてPH,雰囲気中で加熱処理することに
より、InP単結晶層の結晶性を改善した状態で、この
InP単結晶層の格子定数にほぼ等しいGaInAsP
多層膜を成長させ、したがって前記問題点を除去できる
(Function) The present invention introduces the above-mentioned steps into a method for manufacturing a semiconductor MLL, and thus forms an amorphous or A state in which the crystallinity of the InP single crystal layer is improved by making it polycrystalline and flattening it even on a Si substrate with a different lattice constant, and growing an InP single crystal layer on this and heat-treating it in a PH atmosphere. The lattice constant of GaInAsP is approximately equal to that of this InP single crystal layer.
Multilayer films can be grown, thus eliminating the aforementioned problems.

(実施例) 以下、この発明の半導体薄膜の製造方法の実施例につい
て図面に基づき説明する。
(Example) Hereinafter, an example of the method for manufacturing a semiconductor thin film of the present invention will be described based on the drawings.

第1図はこの発明により単結晶InP層をSi基板上に
成長させた場合の結晶構造断面を示す0次にこの第1図
を用いて説明する。
FIG. 1 shows a cross section of a crystal structure when a single crystal InP layer is grown on a Si substrate according to the present invention.

従来と同じMOVPH法や分子ビーム成長法(MBE 
:Plolecular Beam Epltaxy)
が考えられるが、この実施例ではN0VPEを用いた方
法について述べる。
Same as conventional MOVPH method and molecular beam growth method (MBE)
: Plolecular Beam Epltaxy)
However, in this example, a method using N0VPE will be described.

まず、(100)結晶面を表面にもつSt基板1上に、
以下の方法でGaAsバッファJI2、InPバッファ
層3を形成し、InP単結晶4を成長させる。
First, on the St substrate 1 having a (100) crystal plane on the surface,
A GaAs buffer JI2 and an InP buffer layer 3 are formed by the following method, and an InP single crystal 4 is grown.

この方法は、文献rJournal of Cryst
al Growth。
This method is described in the literature Journal of Cryst
al Growth.

vat,93.(19BB)第523 〜526 Jに
記述しであるものである。
vat, 93. (19BB) Nos. 523 to 526 J.

まず、Sl基!j1を化学エツチング(フッ酸で表面酸
化物の除去)し、成長装置に導入する。
First, Sl group! j1 is chemically etched (removal of surface oxide with hydrofluoric acid) and introduced into a growth apparatus.

次に、アルシン(AsHs)雰囲気中で1000℃以上
に加熱し表面のクリーニングを行う。
Next, the surface is cleaned by heating to 1000° C. or higher in an arsine (AsHs) atmosphere.

次にAsB5とトリエチルガリウム(TEG)を原料と
して450℃以下(この場合430°Cであり、下限は
約300℃)で2On−以下の厚さにGaAs8777
層2を成長させる。
Next, using AsB5 and triethyl gallium (TEG) as raw materials, GaAs8777
Grow layer 2.

さらに、550℃以下(下限は約300℃)の温度でT
MI,PHaを用いて、厚さ2Onm以下のIfiPバ
ッファ層3を成長させる。
Furthermore, T
An IfiP buffer layer 3 having a thickness of 2 Onm or less is grown using MI and PHa.

この2層のバッファ層は通常のGaAs、InPの成長
温度(600℃〜750℃)より低い温度で成長してい
るため、単結晶とはならず、多結晶またはアモルファス
状になる。
Since these two buffer layers are grown at a temperature lower than the normal growth temperature of GaAs and InP (600° C. to 750° C.), they do not become single crystal but become polycrystalline or amorphous.

このため、格子定数の異なるSi基板上でも平坦な層が
得られる(ただし、結晶欠陥は非常に多く、結晶性が悪
い)。
Therefore, a flat layer can be obtained even on a Si substrate with a different lattice constant (however, there are many crystal defects and poor crystallinity).

次に、InP単結晶層4の単結晶を通常のIMPの成長
温度(600℃〜700℃)で成長する゛。
Next, a single crystal of the InP single crystal layer 4 is grown at a normal IMP growth temperature (600° C. to 700° C.).

その後、Pyls雰囲気中で730〜780℃で加熱処
理することにより、InP単結晶層4の結晶性が改善さ
れる。
Thereafter, the crystallinity of the InP single crystal layer 4 is improved by heat treatment at 730 to 780° C. in a Pyls atmosphere.

しかし、InPの格子定数はStに比べ、8%も大きい
ため、InP単結晶層4の格子定数は本来もっている格
子定数より小さくなっている。
However, since the lattice constant of InP is 8% larger than that of St, the lattice constant of the InP single crystal layer 4 is smaller than its original lattice constant.

そこで、次にGaInAsP多層膜5を成長させ、Ir
+P単結晶層6を所望の厚さに成長させる。
Therefore, next, a GaInAsP multilayer film 5 was grown, and an IrAsP multilayer film 5 was grown.
+P single crystal layer 6 is grown to a desired thickness.

このGaInAsP多層膜5はまずInP層4の格子定
数にほぼ等しいGaInAsPを用い、その後本来のI
nPの格子定数に近ずくように多層に成長する。
This GaInAsP multilayer film 5 first uses GaInAsP whose lattice constant is approximately equal to that of the InP layer 4, and then the original I
It grows in multiple layers so that the lattice constant approaches that of nP.

各層の厚さは格子ずれがあっても、それによる格子欠陥
が入らない程度に薄くする.たとえば、10人〜100
人変度にする.また層数はIN以上(1層の場合はIn
P単結晶層4とInP単結晶層6の格子定数の中間の値
をとるようにする)適正な層数にする。
The thickness of each layer is made thin enough that even if there is lattice misalignment, no lattice defects will occur. For example, 10 to 100
Make it personal. In addition, the number of layers is IN or more (in the case of 1 layer, In
The number of layers is determined to be an appropriate number (so that the lattice constant is between the values of the P single crystal layer 4 and the InP single crystal layer 6).

(発明の効果) 以上、詳細に説明したように、この発明によれば、まず
Si基板上にGaAsバッファ層とInPバ。
(Effects of the Invention) As described above in detail, according to the present invention, first, a GaAs buffer layer and an InP layer are formed on a Si substrate.

ファ層を多結晶またはアモルファス状に成長後、InP
単結晶層を形成した後に、その上にさらに格子不整合差
を埋め合せるため、GaInAsP多層膜を成長させる
ようにしたので、その上のInP単結晶層は従来と比較
して結晶欠陥がより少なく、表面の平坦性が良(なると
期待できる。
After growing the phase layer in polycrystalline or amorphous form, InP
After forming the single crystal layer, a GaInAsP multilayer film was grown on top of it to compensate for the lattice mismatch difference, so the InP single crystal layer above it had fewer crystal defects than before. , the surface flatness is expected to be good.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の半導体薄膜の製造方法の一実施例に
より製造された半導体薄膜の断面図、第2図は従来の半
導体薄膜の断面図である。 1・・・5ill、2・・・GaAaバッファ眉、3・
・・InPバッファ層、4,6・・・InP単結晶層、
5・・・Ga1n^3P層。
FIG. 1 is a cross-sectional view of a semiconductor thin film manufactured by an embodiment of the semiconductor thin film manufacturing method of the present invention, and FIG. 2 is a cross-sectional view of a conventional semiconductor thin film. 1...5ill, 2...GaAa buffer eyebrow, 3.
...InP buffer layer, 4,6...InP single crystal layer,
5...Ga1n^3P layer.

Claims (1)

【特許請求の範囲】 (a)Si基板上にアモルファス状または多結晶のGa
Asバッファ層とInPバッファ層とを順次形成する工
程と、 (2)上記InPバッファ層上にInP単結晶層を成長
してPH、雰囲気中で加熱処理する工程と、(c)上記
InP単結晶層上に格子定数を段階的に変化させたGa
InAsP多層膜を形成する工程と、(2)上記GaI
nAsP多層膜上にInP層単結晶層を成長する工程と
、 よりなる半導体薄膜の製造方法。
[Claims] (a) Amorphous or polycrystalline Ga on a Si substrate
a step of sequentially forming an As buffer layer and an InP buffer layer; (2) a step of growing an InP single crystal layer on the InP buffer layer and heat-treating the layer in a PH atmosphere; (c) a step of forming the InP single crystal Ga layer with stepwise changes in lattice constant
(2) the step of forming an InAsP multilayer film; and (2) the step of forming an InAsP multilayer film;
A method for manufacturing a semiconductor thin film, comprising the steps of growing an InP single crystal layer on an nAsP multilayer film.
JP13597089A 1989-05-31 1989-05-31 Manufacture of semiconductor thin film Pending JPH033363A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13597089A JPH033363A (en) 1989-05-31 1989-05-31 Manufacture of semiconductor thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13597089A JPH033363A (en) 1989-05-31 1989-05-31 Manufacture of semiconductor thin film

Publications (1)

Publication Number Publication Date
JPH033363A true JPH033363A (en) 1991-01-09

Family

ID=15164122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13597089A Pending JPH033363A (en) 1989-05-31 1989-05-31 Manufacture of semiconductor thin film

Country Status (1)

Country Link
JP (1) JPH033363A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007190167A (en) * 2006-01-19 2007-08-02 Nohmi Bosai Ltd High expansion foam generator with extensible mechanism
CN111668090A (en) * 2020-07-31 2020-09-15 广东省大湾区集成电路与系统应用研究院 Semiconductor structure and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007190167A (en) * 2006-01-19 2007-08-02 Nohmi Bosai Ltd High expansion foam generator with extensible mechanism
CN111668090A (en) * 2020-07-31 2020-09-15 广东省大湾区集成电路与系统应用研究院 Semiconductor structure and manufacturing method thereof
CN111668090B (en) * 2020-07-31 2023-03-14 广东省大湾区集成电路与系统应用研究院 Semiconductor structure and manufacturing method thereof

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