JPH0496320A - Method of growing thin film semiconductor crystal - Google Patents
Method of growing thin film semiconductor crystalInfo
- Publication number
- JPH0496320A JPH0496320A JP21416990A JP21416990A JPH0496320A JP H0496320 A JPH0496320 A JP H0496320A JP 21416990 A JP21416990 A JP 21416990A JP 21416990 A JP21416990 A JP 21416990A JP H0496320 A JPH0496320 A JP H0496320A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- layer
- iii
- compound semiconductor
- semiconductor thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 239000010409 thin film Substances 0.000 title claims abstract description 62
- 239000013078 crystal Substances 0.000 title claims description 20
- 238000000034 method Methods 0.000 title description 16
- 150000001875 compounds Chemical class 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000002109 crystal growth method Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 abstract description 85
- 239000002344 surface layer Substances 0.000 abstract description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 28
- 239000000463 material Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000002994 raw material Substances 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 4
- 239000010408 film Substances 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 230000003993 interaction Effects 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- -1 InP) group compound Chemical class 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野 ]
本発明は、S i、GaAys等の単結晶基板上へ高品
質なIII−V族化合物半導体薄膜層を成投させる方法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for depositing a high quality III-V compound semiconductor thin film layer onto a single crystal substrate such as Si or GaAys.
[従来の技術 コ
111−V族化合物半導体は、半導体レーザ、発光ダイ
オードなどのオブト工1/クトロニクスデバイスの材料
として、また、超高速で動作が可能なトランジスタの材
料ど;2で、半導体産業の中で近年益々その重要性を増
1.つつある。[Prior art] 111-V group compound semiconductors are used as materials for optical devices such as semiconductor lasers and light emitting diodes, and as materials for transistors that can operate at ultra-high speeds. Among them, its importance has been increasing in recent years1. It's coming.
これらのIII−V族化合物半導体林料の中で、最も重
要な材料であるGaAsおよびAl2G a A sに
着目すると、上記各種デバイスは、G a A S基板
結晶上にエピタキシャル成長法により形成された10μ
m以下の厚さの高品質なGaAs、At!GaAs薄層
の中に形成される。Focusing on GaAs and Al2GaAs, which are the most important materials among these III-V compound semiconductor materials, the various devices described above are made of 10μ
High quality GaAs, At! It is formed in a thin layer of GaAs.
これらのデバイスはSiを用いたものに比べて特性的に
圧倒的に優れているにも拘らず、半導体産業のうち電子
デバイス部門に限って言えば、これらの材料のシェアは
主流を占めるSiに比べて極くわずかに過ぎない。その
理由は、以下の3点に集約される。Although these devices have overwhelmingly superior characteristics compared to those using Si, in terms of the electronic device sector of the semiconductor industry, the share of these materials is far behind Si, which is the mainstream. It's only a small amount in comparison. The reasons for this can be summarized into the following three points.
(i)基板材料(G、aAs)が高価である。(i) The substrate material (G, aAs) is expensive.
(if)基板材料(GaAs)の機械的強度が低い。(if) The mechanical strength of the substrate material (GaAs) is low.
(iii)基板材料(GaAs)の結晶品質がSiに比
べて不十分である。(iii) The crystal quality of the substrate material (GaAs) is insufficient compared to Si.
係る事情は、他のIII−V族化合物半導体材料である
I nPs I nGaAs等においても同じである。The same situation applies to other III-V compound semiconductor materials such as InPs InGaAs.
前記問題点に対して、III−V族化合物半導体に比べ
て圧倒的に安価であり、結晶学的な完全性がより高く、
かつ機械的強度が優れているSiを基板として用い、
その上に薄いGaAs (またはInP等のIII−V
族化合物半導体層)を成長させ、それを新たなIII−
V族化合物半導体として用いる方法が提案され、これま
でに多くの研究が行われてきた。Regarding the above problems, it is overwhelmingly cheaper than III-V compound semiconductors, has higher crystallographic perfection,
Using Si as the substrate, which also has excellent mechanical strength,
On top of that, thin GaAs (or III-V such as InP)
group compound semiconductor layer) and convert it into a new III-
A method for using it as a group V compound semiconductor has been proposed, and much research has been conducted so far.
しかし、例えば、Si基板上のGaAsの成長にのみに
限って述べれば、両者の間で、格子定数と、熱膨張係数
および結晶構造(主として、共有結合結晶かイオン結合
結晶かという極性の違い)に、大きな相違がある。この
ため、エピタキシャル成長したIII−V族化合物半導
体には格子不整合に基づくミスフィツト転位、および成
長温度からの冷却に伴う歪やその他の原因によって生じ
る貫通転位が多−く、その結晶学的な品質は極めて低い
。However, for example, if we talk only about the growth of GaAs on a Si substrate, there are differences between the two in terms of lattice constant, coefficient of thermal expansion, and crystal structure (mainly the polarity of covalently bonded crystal or ionic bonded crystal). There is a big difference. For this reason, epitaxially grown III-V compound semiconductors have many misfit dislocations due to lattice mismatch, threading dislocations caused by strain caused by cooling from the growth temperature, and other causes, and their crystallographic quality is poor. Extremely low.
このため、Si基板上に成長させたGaAsを用いて各
種デバイスをつくっても、その特性は低く、また、現時
点ではGaAs等のIII−V族化合物半導体基板につ
いて述べれば、Si基板と比較して基板そのものの転位
密度が未だに高く、これが薄膜層中の貫通転位となり、
エピタキシャル層の結晶性を劣化させているという現状
は見逃せない。For this reason, even if various devices are made using GaAs grown on a Si substrate, its characteristics are low, and at present, when talking about III-V compound semiconductor substrates such as GaAs, compared to Si substrates, The dislocation density of the substrate itself is still high, which leads to threading dislocations in the thin film layer.
The current situation of deteriorating the crystallinity of the epitaxial layer cannot be overlooked.
転位密度の低減は、これまで様々な方法が検討されてき
たが、最も効果的であったのは、熱処理による転位の会
合、消滅や、超格子層の導入による転位の上方伝播阻止
などの方法である。ここで、超格子層とは、多層エピタ
キシャル成長層の各層の厚みが100A程度の小さい場
合を示すものである。なお、前記各層の厚みが数百へと
いう比較的厚い場合は、交互層と称される。Various methods have been studied to reduce dislocation density, but the most effective methods include association and annihilation of dislocations through heat treatment, and prevention of upward propagation of dislocations by introducing a superlattice layer. It is. Here, the superlattice layer refers to a multilayer epitaxially grown layer in which each layer has a small thickness of about 100A. In addition, when the thickness of each layer is relatively thick, up to several hundred, it is called an alternating layer.
ところで、これまでに前記の方法によって到達できた最
良の結果は、Si基板上に4μm程度のGaAsを成長
させたもので、その転位密度は1〜2X10’/cm”
である。 この値は通常のGaAs基板゛の値の約10
00倍であり、III−V族化合物半導体の本来の特性
を生かしたデバイス制作の実用に用いることは殆ど不可
能である。By the way, the best result achieved so far by the above method was to grow GaAs of about 4 μm on a Si substrate, and the dislocation density was 1 to 2 x 10'/cm.
It is. This value is approximately 10 times higher than that of a normal GaAs substrate.
00 times, and it is almost impossible to use it for practical purposes in producing devices that take advantage of the original characteristics of III-V compound semiconductors.
も゛し、転位め−ないGaAs薄膜がSi上に成長でき
れば、半導体市場におけるIII−V族化合物半導体の
シェアは飛躍的な増大が期待でき、Asなど寡少な資源
の省資源化等、その効果は□著しいものとなるが、−上
記の理由により、この技術は実現していないのが現状で
ある。If a dislocation-free GaAs thin film can be grown on Si, the share of III-V compound semiconductors in the semiconductor market can be expected to increase dramatically, and its effects include saving scarce resources such as As. □This would be significant, but for the reasons mentioned above, this technology has not yet been realized.
[発明が解決しようとする課題 ]
Si単結晶基板上のIII−V族化合物半導体の成長に
おいて、前記のような超格子層の導入が転位密度低減の
有力な手法として知られている。[Problems to be Solved by the Invention] In the growth of III-V group compound semiconductors on Si single crystal substrates, the introduction of a superlattice layer as described above is known as an effective method for reducing dislocation density.
第4図は、その−例としてSi基板1上に成長させたG
aAs薄膜層2中にInGaAs薄膜3aとGaAs薄
膜3bとからなる超格子層3を形成した場合の転位4の
伝播の様子を断面図として模式的の示したものである。FIG. 4 shows, as an example, G grown on a Si substrate 1.
This is a schematic cross-sectional view showing how dislocations 4 propagate when a superlattice layer 3 consisting of an InGaAs thin film 3a and a GaAs thin film 3b is formed in the aAs thin film layer 2.
転位4は、超格子層3の歪や、超格子層3界面に形成さ
れるミスフィツト転位6との相互作用によって、その多
くが基板1面と平行な方向に曲折し、上方への伝播が阻
止される。転位4の曲折5は、このように超格子層3の
歪または超格子層3界面のミスフィツト転位6との相互
作用で起こると考えられているが、超格子層3による転
位の曲折5による薄膜層2の低転位密度化には限度があ
り、十分に転位密度を下げることができない。Due to the strain in the superlattice layer 3 and the interaction with misfit dislocations 6 formed at the interface of the superlattice layer 3, most of the dislocations 4 are bent in a direction parallel to the substrate 1 surface, and upward propagation is blocked. be done. The bending 5 of the dislocations 4 is thought to occur due to the strain in the superlattice layer 3 or the interaction with the misfit dislocations 6 at the interface of the superlattice layer 3. There is a limit to lowering the dislocation density of layer 2, and the dislocation density cannot be lowered sufficiently.
その理由は、通常GaAs等のIII−V族化合物半導
体の結晶成長では、少なくとも600℃程度の基板温度
を必要と!−1こうした温度で1.を歪超格子層を構成
する分子層の厚さが臨界膜厚を越えると、容易にミスフ
ィツト転位を発生1−1格子歪を緩和するために、超格
子層3のJ一部界面に発生するミスフィツト転位が相互
作用等により新たに表面方向へ貫通する転位4を生じる
からである。超格子層3の名薄膜の厚さや、超格−子層
3を構成jる利料を適宜選択すれば、このようなミスフ
ィツト転位の発生を抑えることは可能であるが、一方で
超格子層3の歪が小さくなり、転位の曲折5が起こりに
くく、超格子層3を貫通l、5、さらに薄膜層2表面へ
伝播する転位4の割合が増λることむ−なる。The reason is that crystal growth of III-V compound semiconductors such as GaAs usually requires a substrate temperature of at least 600°C! -1 At these temperatures 1. When the thickness of the molecular layers constituting the strained superlattice layer exceeds the critical film thickness, misfit dislocations easily occur.1-1 Misfit dislocations are generated at the J interface of the superlattice layer 3 in order to alleviate the lattice strain. This is because misfit dislocations generate new dislocations 4 penetrating toward the surface due to interaction or the like. Although it is possible to suppress the occurrence of such misfit dislocations by appropriately selecting the thickness of the thin film of the superlattice layer 3 and the components of the superlattice layer 3, it is possible to suppress the occurrence of such misfit dislocations. 3 becomes smaller, bending 5 of dislocations is less likely to occur, and the proportion of dislocations 4 penetrating through the superlattice layer 3, 5, and further propagating to the surface of the thin film layer 2 increases.
本発明の目的は、Si、GaAs等の単結晶基板上にI
IN−V族化合物半導体を成膜させる場合に、III−
V族化合物半導体薄膜層中に発生ずる高密度の転位の伝
播な成長途中で停止させ、表面が低転位密度のIII−
V族化合物半導体薄膜の制作を可能にする技術を提供す
ることにある。The purpose of the present invention is to provide an I
When forming an IN-V group compound semiconductor, III-
The high-density dislocations generated in the group V compound semiconductor thin film layer are stopped mid-propagation, and the surface is formed with a low-dislocation-density III-
The purpose of the present invention is to provide a technology that enables the production of Group V compound semiconductor thin films.
[課題を解決するための手段おノニび作用 ]前記課題
を解決するために、本発明は、以下のような構成を有す
る。[Means and effects for solving the problems] In order to solve the above problems, the present invention has the following configuration.
すなわち、本発明に係る薄膜半導体結晶成長法は、半導
体単結晶基板」−に、IIN−V族化合物半導体おJ−
びそれらの混晶体を成長、成膜させるにおいて、この半
導体薄膜層の中間部分に、2種類の異なるIII−V族
化合物半導体薄膜を交互に積層してなる交互層または超
格子層と呼称される格子歪を内包した構造を、400℃
以下の低い基板温度下で形成することを特徴とする。That is, in the thin film semiconductor crystal growth method according to the present invention, IIN-V group compound semiconductor and J-
In growing and forming films of these mixed crystals, two different types of III-V compound semiconductor thin films are alternately laminated in the middle part of this semiconductor thin film layer, which is called an alternating layer or a superlattice layer. The structure containing lattice strain was heated to 400℃.
It is characterized by being formed at a low substrate temperature of:
以下に、本発明方法を図面を参照1〜で詳しく説明する
。The method of the present invention will be explained in detail below with reference to the drawings.
本発明は、先に出Hされた特開昭(’)2−22262
8を応用することによって容易に達成することができる
1、この特開昭(’)2−222628に記載の技術は
、基板に2種の原料を交互に供給することにノ、って化
合物半導体を結晶成長させて基板上に薄膜を得る方法で
あり、この交互供給成長方法では、通常の結晶成長法と
比較1.て大幅な基板温度の低減が可能となるという特
徴が得られる。The present invention is based on the previously published Japanese Patent Application Laid-open No. 2-22262.
1. The technique described in Japanese Patent Application Laid-open No. 2-222628 (1999) can be easily achieved by applying 8. This is a method to obtain a thin film on a substrate by growing crystals of 1. This provides the advantage that it is possible to significantly reduce the substrate temperature.
この交互供給成長方法を本発明に適用プる場合、第1図
に示すように、単結晶基板1上にIII族原判2AとV
族原判2Bとを交互に供給することによりIII−V族
化合物半導体を結晶成fi= 8ぜてIII−V族化合
物半導体薄膜層2を得ることになる。When this alternate supply growth method is applied to the present invention, as shown in FIG.
By alternately supplying the group original layer 2B, the III-V compound semiconductor is crystallized fi=8, and the III-V compound semiconductor thin film layer 2 is obtained.
このような成長法を半導体薄膜層中に形成する超格子層
の成長に用いることで、III−V族化合物半導体薄膜
層の中間部分に超格子J!1!(または交互層)の形成
を低温(400℃以下)で行うという本発明の主張点が
可能となる。このような低温条件で超格子層(J−たけ
交互層)を半導体薄膜層の中間部分に形成することによ
り、臨界膜厚に達1.でもミスフィツト転位を発生させ
ずに、歪を内在した超格子層くまたは交互層)を得るこ
とができ、その結果、表面に歪のない半導体薄膜層を彫
結晶基板上に得ることができる。By using such a growth method to grow a superlattice layer formed in a semiconductor thin film layer, a superlattice J! 1! The present invention's claim that the formation of (or alternating layers) is performed at a low temperature (400° C. or lower) becomes possible. By forming the superlattice layer (J-take alternating layer) in the middle part of the semiconductor thin film layer under such low temperature conditions, the critical film thickness can be reached.1. However, a strained superlattice layer or alternating layers can be obtained without generating misfit dislocations, and as a result, a semiconductor thin film layer with no surface strain can be obtained on a carved crystal substrate.
第2図は、本発明に従って低温で超格子層3を化合物半
導体薄膜層2中に導入1−だ場合の半導体薄膜層2中に
おける転位伝播の様子を断面図として模式的に示したも
のである。400℃以下”で超格子層3を形成すること
にJ、って、超格子層3の上部界面でのミスフィツト転
位の発生を抑えつつ、超格子層3に下部の化合物半導体
薄膜層2中の転位を曲げ得るに十分な歪みを内包さセる
ことができるため、はとA7ど完全に下部の半導体薄膜
層2中の転位の伝播を超格子層3で阻止でき、転位密度
の低い表面層(上部の半導体薄膜層2)を得る。−とが
できる。FIG. 2 is a cross-sectional view schematically showing the state of dislocation propagation in the semiconductor thin film layer 2 when the superlattice layer 3 is introduced into the compound semiconductor thin film layer 2 at a low temperature according to the present invention. . Forming the superlattice layer 3 at a temperature of 400° C. or less suppresses the occurrence of misfit dislocations at the upper interface of the superlattice layer 3 while allowing the formation of the superlattice layer 3 in the lower compound semiconductor thin film layer 2. Since it is possible to contain enough strain to bend dislocations, the superlattice layer 3 can completely prevent the propagation of dislocations in the semiconductor thin film layer 2 below, and the surface layer with a low dislocation density can be completely blocked. (Upper semiconductor thin film layer 2) is obtained.
[実施例 ]
第1図に示!−だ交互供給(特開昭62−222628
)による結晶成長法によりIII−V族化合物半導体を
III族原料と■族原料から51基板上にG aAs薄
膜層を成長させ、その中にInGaAs薄膜どGaAs
薄膜とからなる超格子層を導入1〜だ場合をもって実施
例の説明を行う。[Example] Shown in Figure 1! -Alternate supply (Japanese Patent Application Laid-Open No. 62-222628
), a GaAs thin film layer is grown on a 51 substrate using a III-V group compound semiconductor from a group III raw material and a group II raw material.
Examples 1 to 1 will be described in which a superlattice layer consisting of a thin film is introduced.
通常、GaAs等の111−V族化a物半導体の結晶成
長では、前記したように少なくとも600℃程度の基板
温度を必要とするのに対し、この成長方法では通常の結
晶成長法でほとんど不可能であった300℃程度の低温
での結晶成長が可能となる。Normally, crystal growth of 111-V group a compound semiconductors such as GaAs requires a substrate temperature of at least 600°C as described above, whereas this growth method is almost impossible with normal crystal growth methods. Crystal growth becomes possible at a low temperature of about 300°C.
第3図は、前記成長法により、基板温度300℃で、S
i基板l上にGa、As分子線の交互供給で成長させた
GaAs薄膜層2中に、Ga。FIG. 3 shows S
In the GaAs thin film layer 2 grown on the i-substrate l by alternately supplying Ga and As molecular beams, Ga.
InおよびAs分子線の交互供給により成長させたI
n01Ga0.As薄膜3aと、 GaおよびAs分子
線の交互供給で成長させたGaAs薄膜3bとで構成さ
れる超格子層3を導入した様子を模式的に示したもので
ある。なお、この第3図は実質的に前記第2図と同一内
容を示すものであるが、第2図が特に材料を限定せずに
転位伝播の抑制作用を強調して示したものであるのに対
し、この第3図は実施例そのもののを直接示すものであ
る。 また、In、、Ga、、As薄膜3aおよびGa
As薄膜3bの各々の厚さは、100Aであり、周期は
10周期であった。I grown by alternating supply of In and As molecular beams
n01Ga0. This diagram schematically shows the introduction of a superlattice layer 3 composed of an As thin film 3a and a GaAs thin film 3b grown by alternately supplying Ga and As molecular beams. This figure 3 shows substantially the same contents as the above-mentioned figure 2, but the difference is that figure 2 emphasizes the effect of suppressing dislocation propagation without particularly limiting the material. On the other hand, this FIG. 3 directly shows the embodiment itself. Moreover, In, Ga, As thin film 3a and Ga
The thickness of each As thin film 3b was 100A, and the period was 10 periods.
得られた半導体薄膜層の透過型電子顕微鏡による断面観
察の結果では、はとんどの転位が超格子層3の下部界面
で曲げられ、かつ、高温成長に見られるような超格子層
3の上部界面でのミスフィツト転位は、観察されなかっ
た。The results of cross-sectional observation of the obtained semiconductor thin film layer using a transmission electron microscope show that most dislocations are bent at the lower interface of the superlattice layer 3 and are bent at the upper part of the superlattice layer 3 as seen in high-temperature growth. No misfit dislocations at the interface were observed.
こうした効果は、GaAsに限らず、他のIII−V族
化合物半導体材料でも認められ、 またGaAsなど
Si以外の単結晶基板を用いた場合にも認められた。These effects were observed not only in GaAs but also in other III-V group compound semiconductor materials, and were also observed in cases where single crystal substrates other than Si, such as GaAs, were used.
前記のように低温成長した超格子層3はIII−V族化
合物半導体薄膜層2の転位の伝播を阻止し、低転位密度
のエピタキシャル層(半導体薄膜層2)表面を得る上で
極めて有効なことが確認された。The superlattice layer 3 grown at a low temperature as described above is extremely effective in preventing the propagation of dislocations in the III-V compound semiconductor thin film layer 2 and obtaining a surface of the epitaxial layer (semiconductor thin film layer 2) with a low dislocation density. was confirmed.
こうした低温成長を実現するためには原料交互供給法を
用いて、成長時の基板温度を低減することが重要なポイ
ントとなる。In order to achieve such low-temperature growth, it is important to reduce the substrate temperature during growth by using an alternate supply method of raw materials.
以上説明した実施例は、本発明の一実施態様であり、本
発明にはその他に様々な変形態様があることは明かであ
り、前記実施例はなんら本発明を限定するものではない
。The embodiment described above is one embodiment of the present invention, and it is clear that the present invention has various other modifications, and the embodiment described above is not intended to limit the present invention in any way.
[発明の効果 ]
以上説明したように、Si、GaAs等の単結晶基板上
にIII−V族化合物半導体を成長させる薄膜半導体結
晶成長技術において、III−V族化合物半導体薄膜層
内に発生する転位の伝播が、この半導体薄膜層の中間部
分に低温成長させた超格子層により阻止することができ
るため、表面における転位密度が低いIII−V族化合
物半導体薄膜層を容易に作製することができる。[Effects of the Invention] As explained above, in a thin film semiconductor crystal growth technique for growing a III-V compound semiconductor on a single crystal substrate such as Si or GaAs, dislocations occurring in a III-V compound semiconductor thin film layer can be avoided. Since the propagation of can be inhibited by the superlattice layer grown at a low temperature in the middle portion of the semiconductor thin film layer, a III-V compound semiconductor thin film layer with a low dislocation density on the surface can be easily produced.
第1図はIII−V族化合物半導体を基板上にIII族
原料および■族原料の交互供給で結晶成長させる様子を
示した模式図、
第2図は本発明方法に従って単結晶基板上に成長させた
III−V族化合物半導体薄膜層の中間部分に超格子層
を形成した場合の転位伝播の様子を示した模式図、
第3図は本発明の実施例を示すもので、Si単結晶基板
上に成長させたGaAs薄膜層中にI n、、Ga、、
As薄膜とGaAs薄膜とで構成される超格子層を導入
した様子を模式的に示した模式図、
第4図はSi基板上に成長させたGaAs1膜層の中間
部分に従来技術によりI nGaAs薄膜とGaAs薄
膜とからなる超格子層を形成した場合の転位伝播の様子
を示した模式図である。
l・・・Si単結晶基板、
2・・・GaAs薄膜層、
3 ・・−I n、、G a、、As薄膜とG aAs
薄膜とで構成される超格子層、
3 a ・・・I n、、Ga、、As薄膜、3b・・
・GaAs薄膜。Figure 1 is a schematic diagram showing how a III-V compound semiconductor is grown on a substrate by alternately supplying Group III raw materials and Group II raw materials, and Figure 2 is a schematic diagram showing how a III-V compound semiconductor is grown on a single crystal substrate according to the method of the present invention. A schematic diagram showing the state of dislocation propagation when a superlattice layer is formed in the middle part of a III-V group compound semiconductor thin film layer. In a GaAs thin film layer grown on
A schematic diagram showing how a superlattice layer composed of an As thin film and a GaAs thin film is introduced. FIG. 3 is a schematic diagram showing dislocation propagation when a superlattice layer consisting of a GaAs thin film and a GaAs thin film is formed. l...Si single crystal substrate, 2...GaAs thin film layer, 3...-In,, Ga,, As thin film and GaAs
A superlattice layer composed of a thin film, 3a...In, ,Ga,,As thin film, 3b...
・GaAs thin film.
Claims (1)
それらの混晶体を成長させてIII−V族化合物半導体薄
膜層を得る薄膜半導体結晶成長法において、 前記III−V族化合物半導体薄膜層の中間部分に、2種
類の異なるIII−V族化合物半導体薄膜を交互に積層し
た超格子層もしくは交互層と呼称される格子歪を内包し
た構造を400℃以下の低い基板温度で形成することを
特徴とする薄膜半導体結晶成長法。[Scope of Claims] A thin film semiconductor crystal growth method for obtaining a III-V compound semiconductor thin film layer by growing a III-V compound semiconductor and a mixed crystal thereof on a semiconductor single crystal substrate, comprising: A structure containing lattice strain called a superlattice layer or alternating layer, in which two different types of III-V group compound semiconductor thin films are alternately laminated in the middle part of the compound semiconductor thin film layer, is created at a low substrate temperature of 400°C or less. A thin film semiconductor crystal growth method characterized by forming.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21416990A JPH0496320A (en) | 1990-08-13 | 1990-08-13 | Method of growing thin film semiconductor crystal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21416990A JPH0496320A (en) | 1990-08-13 | 1990-08-13 | Method of growing thin film semiconductor crystal |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0496320A true JPH0496320A (en) | 1992-03-27 |
Family
ID=16651381
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21416990A Pending JPH0496320A (en) | 1990-08-13 | 1990-08-13 | Method of growing thin film semiconductor crystal |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0496320A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016039314A (en) * | 2014-08-08 | 2016-03-22 | 旭化成株式会社 | Compound semiconductor substrate |
-
1990
- 1990-08-13 JP JP21416990A patent/JPH0496320A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016039314A (en) * | 2014-08-08 | 2016-03-22 | 旭化成株式会社 | Compound semiconductor substrate |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6495868B2 (en) | Relaxed InxGa1−xAs buffers | |
JP2669368B2 (en) | Method for manufacturing compound semiconductor laminated structure on Si substrate | |
JPS6012724A (en) | Growing method of compound semiconductor | |
US4935385A (en) | Method of forming intermediate buffer films with low plastic deformation threshold using lattice mismatched heteroepitaxy | |
US4789421A (en) | Gallium arsenide superlattice crystal grown on silicon substrate and method of growing such crystal | |
JPH0760791B2 (en) | Compound semiconductor substrate | |
US6594293B1 (en) | Relaxed InxGa1-xAs layers integrated with Si | |
US6589335B2 (en) | Relaxed InxGa1-xAs layers integrated with Si | |
JPH0496320A (en) | Method of growing thin film semiconductor crystal | |
JP2687445B2 (en) | Heteroepitaxial growth method | |
JPH04186824A (en) | Semiconductor substrate and manufacture thereof | |
JPS63186416A (en) | Compound semiconductor substrate | |
JPH02221196A (en) | Formation of thin film of iii-v compound semiconductor | |
JPH0645249A (en) | Growth method of gaas layer | |
JP2900946B2 (en) | Semiconductor device | |
JPH01227424A (en) | Compound semiconductor substrate | |
JP3124616B2 (en) | Method for growing compound semiconductor thin film | |
JPH02263427A (en) | Compound semiconductor substrate and manufacture thereof | |
JPH01120011A (en) | Inp semiconductor thin film | |
JPH05283336A (en) | Formation of compound semiconductor layer | |
JPH04199812A (en) | Semiconductor crystal growth method | |
JPH0461286A (en) | Semiconductor device | |
Alberts | Influence of initial growth parameters on the structural and optical properties of GaAs on (001) Si | |
JPH0417323A (en) | Compound semiconductor substrate | |
JPH01270594A (en) | Production of compound semiconductor |