JPH05283336A - Formation of compound semiconductor layer - Google Patents

Abstract

PURPOSE:To form a group III-V semiconductor epitaxial layer of high quality and good surface flatness on a single crystal of non-polar or different lattice constant. CONSTITUTION:An Al layer 2 of one atomic layer is formed on an Si substrate 1 at a low temperature of 400 deg.C or below and then P is supplied successively. The processes are repeated to form an Al P low temperature buffer layer 3. A GaP low temperature buffer layer 4, an AlAs low temperature buffer layer 5 and a GaAs low temperature buffer layer 6 are made to grow one by one thereon by a similar alternate supply method. A temperature is made to rise while supplying As and a Gaps buffer layer 8 is formed by an ordinary simultaneous supply method. Then, a temperature is lowered and an InAlAs low temperature buffer layer 9 and an InP low temperature buffer layer 10 are made to grow one by one by the alternate supply method. Thereafter, a temperature is made to rise while supplying P and an InP layer 11 is formed by the simultaneous supply method. Since two dimensional growth from an initial stage can be thereby acquired even on a single crystal of non-polar or different lattice constant, interface defective density can be reduced and dislocation due to thermal strain can be restrained from rising again.

Description

Detailed Description of the Invention

[0001]

INDUSTRIAL APPLICABILITY The present invention provides high quality and excellent surface flatness on non-polar or single crystals having different lattice constants.
The present invention relates to a technique for forming a Group 3-5 compound semiconductor layer for forming a Group semiconductor epitaxial layer.

[0002]

2. Description of the Related Art In recent years, heteroepitaxial growth on a crystal substrate having a non-polarity or a different lattice constant, in particular, a Group 3-5 compound semiconductor single crystal layer typified by GaAs on a Group 4 semiconductor single crystal substrate typified by Si. There are many active attempts to grow. This is because if such a structure can be formed, the group 3-5 compound semiconductor high-performance element can be manufactured with inexpensive Si.
This is because it can be fabricated on a substrate, and the high thermal conductivity of Si can be expected to improve the performance of optical devices and the like. Furthermore Si
This is because if a super high-integrated circuit and a 3-5 group compound semiconductor ultra high-speed device or an optical device can be formed on the same substrate, the development of a new high-performance device is expected.

In the following, mainly, on a Si single crystal substrate,
The growth of a Group 5 compound semiconductor single crystal will be described as an example. Three
The group-5 compound semiconductor is a polar crystal composed of two kinds of elements of groups 3 and 5, whereas Si belonging to the group 4 is a nonpolar crystal composed of a single element. Therefore, when attempting to epitaxially grow a group 3-5 compound semiconductor thin film on a Si substrate having a (100) plane orientation that is commonly used, a region where the arrangement of the groups 3 and 5 is out of phase and the polarity is reversed, that is, the so-called anti・ It is easy to create a phase domain.

The problem was solved by the magazine "Japanese Journal of Applied Physics (Jp.
n. J. Appl. Phys. ) ”Vol. 24, No. 6 (1
985), page L391-393, referred to as "two-step growth method". That is, (10
0) to the <011> direction off the Si substrate,
After depositing a fine polycrystalline or amorphous GaAs buffer layer of about 200 Å at a low temperature of 450 ° C. or lower, the temperature of the Si substrate is set to a normal growth temperature, 600 ° C. in the case of the above literature, and GaAs is set. This is a method of growing a single crystal thin film. By this method, a single domain single crystal thin film can be surely obtained. The fine polycrystalline or amorphous GaAs thin film is annealed while raising the temperature to 600 ° C. to be a single crystal. The results of the above-mentioned documents are based on metal organic chemical vapor deposition (MOCVD).
However, it was confirmed that the molecular beam epitaxial growth method (MBE method) is also effective.

The low-temperature buffer layer in the two-step growth method grows in an island shape, but if the islands are sufficiently small and are in contact with each other, rearrangement to the predominant azimuth occurs in subsequent annealing, and it is considered that a single domain is formed. ing. Alternatively, it is considered that only the dominant orientation remains during the growth, resulting in single-dimerization, but high-temperature annealing is necessary even in this case. This is because the buffer layer grown at a low temperature contains many defects, and it is necessary to anneal it while it is as thin as about 200 Å to recover the crystallinity.

From the viewpoint of device application of the semiconductor thin film, it is important to improve the crystal quality and the surface flatness together with the single domain. But usually 3 on Si substrate
When a Group-5 compound semiconductor is grown in two steps, much more dislocations and stacking faults are generated at the interface with Si than expected due to the lattice mismatch between the substrate and the growth layer. To the upper layer and become threading dislocations. Most dislocations, stacking faults, etc. are thought to occur when islands are united in the island-shaped growth in the initial stage of growth, and the dislocation density of the GaAs layer grown by the two-step growth method is about 10 μm on the growth surface of several μm thick. ⁸
cm ^- also reaches ^2. Also, in the case of the two-step growth method, the flatness is generally poor due to the island-shaped growth in the initial stage of growth. If the growth of the buffer layer is carried out at a lower temperature, the flatness will be improved because the islands will be smaller and the density will be higher, but the lower the temperature, the less the migration of atoms and the worse the crystal quality. The annealing for recovering the crystallinity needs to be performed while the film thickness is sufficiently thin, but if this annealing is performed too much, solid-phase growth causes large irregularities on the surface.

[0007] Then, in the method and thermal cycle annealing bending the dislocations in-plane direction by the insertion of the distortion super lattice intermediate layer was proposed to reduce the threading dislocations, these by about 10 ⁶ cm ^- up to ² dislocation density Was rapidly improved (magazine "Applied Physics Letter (Appl. Ph.
ys. Lett. ) ”Vol. 54, No. 1 (1989), pp. 24-26). However, in these methods, from about 10 ⁶ cm ^- then the ² dislocation density as a large wall is in a state not seen progress. As a cause of this, a problem of a difference in thermal expansion coefficient between the Si substrate and the group 3-5 compound semiconductor has recently been pointed out (Journal "Applied Physics Letter (A
ppl. Phys. Lett. ), Vol. 56, No. 22 (1990), pages 2225-2227). That is, the growth temperature (650
10 ⁵ cm in ° C.) ^- dislocation density up to ² or less is reduced, but the stress due to thermal expansion coefficient difference (450 ° C. about the movement of dislocations is frozen (GaAs) in the after growth cooled to below) 10 ⁶ cm ^{- 2} units dislocations is that is introduced. It is considered that this is because many dislocations remaining near the interface with the Si substrate rise due to thermal strain. For dislocations that rise during growth,
It is generally inserted in a strained superlattice intermediate layer for the purpose of preventing it from reaching the upper layer by bending it in the lateral direction, and a great effect is obtained.
However, there is a problem that the effect of inserting the strained superlattice intermediate layer cannot be sufficiently obtained with respect to dislocations that rise due to thermal strain. Furthermore, such a problem is that the lattice constant difference from Si is 8%.
And is more pronounced in InP growth on large Si, the dislocation density of about 10 ⁷ cm ^{- 2} has been a wall (the magazine "Journal of Crystal Growth (J.Crysta
lGrowth) ", Volume 99 (1990), 365
-370 page).

As one method for solving the problem of thermal strain, it is considered to avoid island-shaped growth in the initial stage of growth to realize layered growth and reduce many dislocations themselves remaining near the interface with the Si substrate. Be done. For example, the magazine “Japanese Journal of Applied Physics (Jpn.
J. Appl. Phys. ) "Vol. 29, No. 12 (19
90) L2457-2459, the AlAs layer is grown at 500 ° C. by the atomic layer epitaxial growth method (ALE method) alternately supplying trimethylaluminum (TMA) and arsine (AsH ₃ ). Layered growth and improved flatness have been obtained from the outset.

On the other hand, as an attempt to fundamentally avoid the problem of the difference in coefficient of thermal expansion, there is a method of directly supplying a Group 3 raw material and a Group 5 raw material at a low temperature to directly grow a single crystal film. For example, the magazine Japanese Journal of Applied
Physics (Jpn. J. Appl. Phys.) Vol. 30, No. 4B (1991), L668-671, migration enhancement for alternately supplying Ga and As atoms in a high vacuum. In the epitaxial growth method (MEE method), GaAs is grown at a low temperature of 300 ° C. except for annealing at 580 ° C. on the way. Dislocation density 1 by introducing strained superlattice intermediate layer
0 ⁶ cm ^{- 2} wall breakthrough to 7 × 10 ⁴ cm ^{- 2} a is obtained.

[0010]

Consider the problems of the above-mentioned prior art in the epitaxial growth method of the group 3-5 compound semiconductor layer.

Trimethyl aluminum (TM) at 500 ° C.
In the ALE method in which A) and arsine (AsH ₃ ) are alternately supplied, a transition from a very early stage of growth to a layered growth is performed and flatness is also improved. However, the island-shaped growth still occurs, and many defects occur in the AlAs layer. Further, some of the defects penetrate into the GaAs layer grown on the GaAs layer, so that the fundamental reduction of dislocation density has not been successful.

On the other hand, in the MEE method in which the Group 3 raw material and the Group 5 raw material are alternately supplied at a low temperature, since the dislocations grow at a low temperature of 300 ° C., which is already in a frozen state, new strain due to thermal strain during cooling is added. generation of dislocations is suppressed, the distortion super lattice intermediate layer also works effectively result 7 × 10 ⁴ cm ^{- 2} can be obtained. With this method, the crystallinity is relatively good from the beginning of growth,
Since the initial annealing may be performed at a stage where the film thickness is relatively large, there is no concern that large irregularities will occur on the surface. However, if annealing is performed after the thick film growth, the dislocations will rise again, so it is necessary to grow to the end even with a complicated device structure by this method. The MEE method has a problem that it takes a very long time to grow because the growth rate is considerably slower than that of MBE.

The object of the present invention is to overcome such drawbacks of the prior art and form a Group 3-5 semiconductor epitaxial layer of high quality and excellent surface flatness on a non-polar or single crystal having a different lattice constant. It is to provide a technique for forming a Group-5 compound semiconductor layer.

[0014]

Means for Solving the Problems The present invention includes groups 4 and 3-5.
On the underlying single crystal consisting of group 3 or 2-6
A step of forming a buffer layer made of a Group 5 compound semiconductor,
And a step of forming a second group 3-5 compound semiconductor layer on the buffer layer, wherein the buffer layer contains Al as a group 3 element in a part or all thereof. And the lattice constant of the buffer layer matches the lattice constant of the second Group 3-5 compound semiconductor layer within 1%, and when the buffer layer is formed, the Group 3 group constituting the buffer layer is formed. It is characterized in that the raw materials of No. 1 and the raw materials of Group 5 are alternately supplied.

The formation of the buffer layer containing Al is 400
It is good to carry out at a low temperature of ℃ or less.

Further, it is preferable that the raw material of the group 3 and the raw material of the group 5 are alternately supplied in the whole formation of the second group 3-5 compound semiconductor layer or at least a part of the initial stage thereof.

Further, when the base crystal is a Group 4 single crystal,
When the buffer layer containing Al is formed on the underlying Group 4 single crystal, the Group 4 single crystal surface is cleaned, then the Group 3 raw material is first supplied, and then the Group 5 raw material is supplied, whereby initial growth occurs. It is desirable from the viewpoint of two-dimensionalization.

[0018]

[Function] In the growth of a lattice-mismatched system of a 3-5 group compound semiconductor such as InP / GaAs, misfit dislocations are first introduced when two-dimensional growth is accompanied by strain and the film thickness exceeds a certain critical point. The strain is released and the three-dimensional island growth usually starts from this point.

On the other hand, it is considered that the island-shaped growth of GaAs on Si is caused, in part, by the large difference in lattice constant between the Si crystal and the GaAs crystal. However, as described in, for example, pages 107-112 of the journal "J. Crystal Growth", Vol. Even if they are supplied alternately, the island-like growth starts from the very early stage below the GaAsl molecular layer and the surface coverage decreases. Further, GaP growth on Si, which should have a sufficiently small lattice constant difference of 0.37%, also results in island growth (Journal of Applied Physics (J. Appl. Phys.)).
Vol. 64, No. 9 (1988) No. 4526-4530
page).

Therefore, the cause of the island-like growth in the growth of the 3-5 group compound semiconductor on Si is not merely due to the difference in the lattice constant, but rather between the surface Si atom and the group 3 or 5 atom at the initial stage of the growth. It is considered that the size relationship of the surface energies related to the chemical bond state and the surface rearrangement structure is deeply related.

That is, dangling bonds remain on the Si surface even after rearrangement, and the surface energy is considerably high. On the other hand, for example, when As is deposited on the Si (100) surface,
The surface is completely covered by As for one atomic layer of As
An s-As dimer is formed. Since Group 5 As has only one valence electron than Group 4 Si, As has only stable loan pairs and no dangling bonds. The surface energy of such an As attachment structure is very low and extremely stable. Extremely stable As adhesion surface with 1 atomic layer of G
When covered with a, the surface energy increases. Therefore, Ga becomes a droplet and tries to reduce the surface energy. If more As is supplied in that state, island-shaped GaA
s grows.

On the other hand, when Ga is deposited on Si, theoretically, it does not have a dangling bond. But A
It is considered to be more unstable than the s-attached structure, and more stable when the entire surface is covered with As, and as a result, layered growth is more likely to occur. However, when the temperature is high, As easily penetrates under Ga, and if As forms a dimer, it may cause island growth. Even in the conventional technique by MEE, a two-dimensional initial growth is obtained when Ga is first supplied at 300 ° C.

Based on the above consideration, a buffer layer containing Al substantially lattice-matched with the upper layer of the present invention was obtained.
This is a method of introducing the group 3 raw material and the group 5 raw material by the alternate supply method. Particularly, when the underlayer is a group 4 crystal, after cleaning the surface of the group 4 crystal, first, the group 3 raw material containing Al is supplied. ,
Next, it is a method of supplying Group 5 raw materials.

From the above consideration, it is considered that the group III bond structure on Si also needs to have appropriate stability. In the case of Ga on Si, it becomes unstable especially at a high temperature, and there is a possibility that it is a surface-melted liquid. This is considered to correspond to the extremely low melting point of Ga, which is about 30 ° C. On the other hand, with Al having a high melting point of about 660 ° C., a relatively stable rearrangement structure is formed on Si,
It is unlikely that it will become an island because As does not easily submerge. After that, according to the method of alternately supplying the Group 3 raw material and the Group 5 raw material, the surface diffusion of the Group 3 atoms is promoted, so that the growth of the three-dimensional nucleus can be suppressed. However, in order to suppress the alloying reaction between Si and Al, the Al layer is preferably formed at a low temperature of 400 ° C. or lower. In the conventional technique using ALE, the growth temperature is as high as 500 ° C. due to the problem of TMA decomposition,
Therefore, it is necessary to supply As first, and it seems that sufficient two-dimensional initial growth cannot be obtained.

Even in the growth of lattice mismatched systems between 3-5 group compound semiconductors or in 2-6 group compound semiconductors, the buffer layer containing Al is formed at a low temperature by the alternate supply method of the group 3 raw material and the group 5 raw material. If grown, a strong bond between Al and the underlying layer can be expected and a relatively stable rearranged surface can be maintained, so that two-dimensional growth can be maintained even after misfit dislocations are introduced beyond the critical film thickness.

Further, if the lattice constant of the buffer layer containing Al is selected so as to match with the lattice constant of the second Group III-V compound semiconductor layer laminated thereon within 1%, even in the growth after the buffer layer. Two-dimensional growth can be continuously maintained.

Further, even in the growth of the second Group 3-5 compound semiconductor layer, according to the method in which the Group 3 raw material and the Group 5 raw material are alternately supplied at a low temperature until at least a sufficient thickness is obtained,
Since unevenness due to a solid-phase reaction during annealing can be prevented, therefore, a group 3-5 semiconductor epitaxial layer having high quality and excellent surface flatness is formed on a single crystal having no polarity or different lattice constants 3-5 A technique for forming a group compound semiconductor layer can be realized.

[0028]

Embodiments of the present invention will now be described in detail with reference to the drawings. Example 1 Using a gas source MBE device capable of cracking and supplying arsine (AsH ₃ ) and phosphine (PH ₃ ) under high vacuum, GaA on a Si single crystal substrate was used.
s growth was performed. Si (100) 4 ° off to
<011> attached without using In fused to the substrate mounting molybdenum block cleaned substrate, 10 ^{- 9} Torr table below 900 ° C. under high vacuum, after performing thermal cleaning for 20 minutes, the substrate temperature Was set to 300 ° C., and then, as shown in FIG. 1A, Al of one atomic layer was supplied onto the Si substrate 1 to grow the Al layer 2. Then P (PH
₃ ) was supplied and this cycle was repeated 10 times to grow an AlP low temperature buffer layer 3 of 10 molecular layers as shown in FIG. 1 (b).

Further, as shown in FIG.
20 molecular layers of GaP low temperature buffer layer 4 by alternating supply of Ga and P (PH ₃ ) at 0 ° C., Al and this time As (AsH
AlAs low-temperature buffer layer 5 of the 10 molecular layers by alternately supplying ₃₎ were further sequentially growing a GaAs low temperature buffer layer 6 of the 70 molecular layers by alternately supplying Ga and As (AsH _3). Here, the lattice constant of the GaP low temperature buffer layer 4 is AlP.
The lattice constant of the low temperature buffer layer 3 and the lattice constant of the GaAs low temperature buffer layer 6 are substantially equal to the lattice constant of the AlAs low temperature buffer layer 5. During this time, although the RHEED pattern had a slight decrease in strength, streaks were almost maintained and two-dimensional growth was maintained.

Finally, the substrate temperature was raised to 550 ° C. while supplying As (AsH ₃ ) and annealed for 15 minutes, and then GaAs (AsH ₃ ) was added as shown in FIG. 1 (d).
GaA with a thickness of 2 μm by the usual MBE method
The s layer 7 was grown.

The epitaxially grown layer thus obtained was a single domain and had an extremely flat surface. The dislocation density of about 10 ⁵ cm ^- as low as ^2, high temperature 5
Even when MBE growth was performed at 50 ° C., the rise of dislocations due to thermal strain could be sufficiently suppressed.

(Embodiment 2) Using the same apparatus as in Embodiment 1,
InP on Si (100) 4 ° off <011> substrate
Grow. First, high quality GaAs is grown on a Si substrate by the same procedure as in the first embodiment. Specifically, first, in a procedure similar to that shown in FIGS.
As shown in (c), the AlP low temperature buffer layer 3, the GaP low temperature buffer layer 4, the AlAs low temperature buffer layer 5, and the G
The aAs low temperature buffer layer 6 is sequentially grown. Further, the substrate temperature was raised to 550 ° C. while supplying As (AsH ₃ ) in the same manner as in Example 1, and after annealing for 15 minutes,
As shown in FIG. 2D, a normal MBE method in which Ga and As (AsH ₃ ) are simultaneously supplied. In this case, the thickness is 0.3 μm.
m GaAs buffer layer 8 is grown.

Next, the substrate temperature is lowered to 300 ° C. again, and thereafter, as shown in FIG. 2E, In + Al and As (A
10 molecular layers of InAlAs low-temperature buffer layer 9 by alternately supplying sH ₃ ) and 70 molecular layers of InP low-temperature buffer layer 10 by alternately supplying In and P (PH ₃ ) are sequentially grown.

Finally, the substrate temperature was raised to 480 ° C. while supplying P (PH ₃ ), and after annealing for 15 minutes, In and P (PH ₃ ) were mixed with each other as shown in FIG. InP layer 11 having a thickness of 2 μm, which is supplied by the ordinary MBE method
Grew up.

The resulting InP epitaxial layer is very flat, and dislocation density 5 × 10 ⁵ cm ^- was significantly reduced compared to the ^{2 - 2} following the conventional about 10 ⁷ cm.

The case where AlP is used as the low temperature buffer layer containing Al on Si has been described above. Part Ga
Even if it replaces with AlGaP containing, the effect is acquired. Similarly A
lAs is AlGaAs or InAl (Ga) P,
InAlAs is InAlGaAs or Al (Ga)
It may be replaced with AsSb or the like, and a superlattice structure including these may be used. In the case of a superlattice structure, a strained superlattice whose average lattice constant is almost matched with that of a crystal laminated thereon may be used.

A large effect can be expected when the film thickness of the low-temperature buffer layer is appropriately thick. However, even in the case of a low-temperature buffer layer containing Al, the effect can be obtained from one molecular layer or more.

The crystal plane orientation usually used (1
Although the (00) plane has been described, other (111)
The same effect can be expected to some extent on a surface, a high-order surface such as (211) and (311), and a surface off from these by an appropriate angle.

Although the gas source MBE apparatus was used as the growth apparatus, it is not limited to this as long as the raw materials can be alternately supplied. For example, MBE of normal all metal source
A device may be used, but in this case, a special source is required for the source of P having a high vapor pressure. Further, a MONBE apparatus or MOCVD apparatus using a Group 3 organic metal raw material may be used. In this case, it is desirable to select an organometallic raw material that is easily pyrolyzed so that the low temperature buffer layer containing at least Al can be grown at 400 ° C. or lower. Further, in the case of the MOCVD apparatus, it is desirable to provide a sub-chamber capable of thermally cleaning the substrate in a clean atmosphere in which no reaction products adhere to the surroundings. On the other hand, the substrate may be cleaned by another method, for example, HF: H ₂
The oxide film may be removed by the O liquid and H passivation may be performed by rinsing with pure water before the introduction into the reaction vessel.

In the embodiment, the growth of GaAs and InP on the Si substrate has been described as an example.
It can also be applied to the growth of s, and also to the growth of mixed crystals of GaAsP, InGaAs, or InGaAsP having a lattice constant in the middle of these crystals. In the example, when InP was grown on a Si substrate, the growth was performed with a GaAs buffer layer sandwiched between them. However, when the difference in lattice constant is large, it is easier to obtain a high-quality crystal by performing such growth in stages. Further, the present invention can be widely applied to the growth of lattice mismatched systems when the substrate is Ge, GaAs or InP of 3-5 group, and ZnS or ZnSe of 2-6 group.

Further, in order to further reduce threading dislocations, it may be combined with another strained superlattice introduction method or a dislocation pinning method by impurities.

[0042]

As described above, according to the present invention, groups 4 and 3
Since the two-dimensional 3-5 group compound semiconductor layer can be grown from the initial stage on the underlying single crystal of -5 group or 2-6 group, the defect density at the interface can be reduced, and due to thermal strain. Since re-raising of dislocations can be suppressed and threading dislocations can be significantly reduced, therefore, a high-quality Group 3-5 semiconductor epitaxial layer having high surface flatness can be formed on a non-polar or single crystal having a different lattice constant. The technology for forming the group-5 compound semiconductor layer was realized, and the effects of the invention were shown.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a crystal growth step as an example according to an example of the present invention.

FIG. 2 is a cross-sectional view showing a crystal growth step as an example according to another embodiment of the present invention.

[Explanation of symbols]

 1 Si substrate 2 Al layer 3 AlP low temperature buffer layer 4 GaP low temperature buffer layer 5 AlAs low temperature buffer layer 6 GaAs low temperature buffer layer 7 GaAs layer 8 GaAs buffer layer 9 InAlAs low temperature buffer layer 10 InP low temperature buffer layer 11 InP layer

Claims (4)

[Claims] 1. A step of forming a buffer layer made of a first 3-5 group compound semiconductor on a base single crystal made of 4 group, 3-5 group, or 2-6 group, and on the buffer layer. And a step of forming a second Group 3-5 compound semiconductor layer 3
-5. In the method for forming a Group 5 compound semiconductor layer, the buffer layer contains Al as a Group 3 element in a part or all thereof, and the lattice constant of the buffer layer is the lattice constant of the second Group 3-5 compound semiconductor layer. And 3% or less, and when the buffer layer is formed, the group 3 raw material and the group 5 raw material forming the buffer layer are alternately supplied. Method of forming layer. 2. The formation of a buffer layer containing Al is 40
The method for forming a Group 3-5 compound semiconductor layer according to claim 1, wherein the method is performed at a low temperature of 0 ° C. or lower. 3. The whole or at least part of the initial formation of the second Group 3-5 compound semiconductor layer is based on a method of alternately supplying Group 3 raw material and Group 5 raw material. The method for forming a Group 3-5 compound semiconductor layer according to claim 1 or 2. 4. The base crystal is a Group 4 single crystal,
When the buffer layer containing Al is formed on the Group 1 single crystal, the Group 4 single crystal surface is cleaned, and then the Group 3 raw material is supplied first, and then the Group 5 raw material is supplied. The method for forming a 3-5 group compound semiconductor layer according to claim 1, 2, or 3.