JP2560601B2 - Method for manufacturing metal film / compound semiconductor laminated structure on elemental semiconductor substrate - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal film / group III-V compound semiconductor laminate having a high-quality group III-V compound semiconductor single crystal layer with small residual thermal strain formed on a group IV semiconductor single crystal substrate. A method of manufacturing a structure.

[0002]

2. Description of the Related Art At present, active attempts are being made to form a group III-V compound semiconductor single crystal thin film represented by GaAs on a group IV semiconductor single crystal substrate represented by Si. This means that when such a thin film structure can be formed, II
This is because a high-performance I-V compound semiconductor device can be produced on an inexpensive Si substrate, and the high thermal conductivity of Si can be expected to improve the performance of optical devices and the like. Furthermore, since the Si ultra-high integrated circuit and the III-V group compound semiconductor ultra-high-speed element and the optical element can be formed on the same substrate, the development of a new high-performance element is expected.

By the way, III-V formed on a Si substrate
In order to apply a group compound semiconductor thin film to device fabrication, it is important to improve crystal quality. For example, the magazine "Japanese
Journal of Applied Physics (Jpn.
J. Appl. Phys. ) Vol. 24, No. 6 (198)
5 years), page 391-393, the "two-step growth method" is used to ensure that a single domain single crystal thin film in which the group III and group V arrays are aligned in phase on the entire substrate surface. Also, the crystallinity is improved as compared with the conventional direct growth. This is a method in which a thin polycrystalline or amorphous buffer layer is first deposited at a low temperature, and then a single-crystal thin film is grown at a normal growth temperature. I do. However, when, for example, GaAs is grown on a Si substrate, much more dislocations and stacking faults occur at the Si / GaAs interface than expected from the lattice mismatch rate, and a part of the dislocations and the stacking layer easily reach the upper layer. It extends and becomes threading dislocation. The dislocation density of the case of two-stage growth method is about 10 ⁸ cm several μm thick growth surface ^- as high as ^2.

What was introduced there was a strained superlattice intermediate layer and a thermal cycle annealing method, and about 10 ⁶ cm
^- up to ² dislocation density has been rapidly improved (magazine "Applied Physics Letters (Appl.Phys.Let
t. Vol. 54 No. 1 (1989) 24-26
page). However about 10 ⁶ cm ^{- 2} The below results not easily obtained, Si substrate and the III-V as its cause
It was pointed out that the difference in the coefficient of thermal expansion from the group compound semiconductors (magazine “Applied Physics Letter (Appl.
Phys. Lett. ) Vol. 56, No. 22 (1990)
2225-2227). That 10 ⁵ cm in the growth temperature (650 ° C.), such as by introduction of thermal cycle annealing ^- the dislocation density to ² or less is reduced but,
10 ⁶ by stress due to thermal expansion coefficient difference in cooling (about 450 ° C. or less) after growth cm ^- is that the ^two dislocations are introduced. It is considered that this is because many dislocations remaining near the interface with the Si substrate rise due to thermal strain. For dislocations that rise during growth,
Generally, a strained superlattice intermediate layer is inserted for the purpose of bending this in the lateral direction and preventing it from reaching the upper layer portion, which is very effective.
However, it is difficult to bend dislocations rising due to thermal strain after growth in the strained superlattice intermediate layer portion.

Further, even when a high-density current is injected into the manufactured light emitting device, if the residual thermal strain is large, it causes the proliferation of defects and causes the life to be remarkably reduced, so that it is important to reduce it.

Therefore, in order to reduce this thermal strain, GaAs is used.
A method of partially separating the growth layer from the substrate has been proposed (Journal: Japanese Journal of Applied Physics (Jpn. J. Appl. Phys.)).
Vol. 29, No. 10 (1990), No. 2077-208
1 page). 2 (a) to 2 (c) schematically show the process according to this conventional technique.

That is, first, as shown in FIG.
AlGaAs spacer layer 3, GaAs layer 2 on i substrate 1
1 to grow sequentially.

Next, the GaAs layer 21 and the AlGaAs spacer layer 3 are etched by using the patterned SiO ₂ film 5 as a mask as shown in FIG. 2B to form a mesa.

Next, as shown in FIG. 2C, the AlGaAs spacer layer 3 is selectively removed by etching from the cross-section portion exposed on the side surface of the mesa. However, the GaAs layer 21 is made of Si
AlGaAs spacer layer 3 for supporting it on the substrate 1
Leave some of them unremoved. Finally, the SiO ₂ film 5 is removed.

[0010]

[Problems to be Solved by the Invention]
Consider the problems of the above-mentioned prior art adopted to obtain a II-V group compound semiconductor film.

By the method of partially separating the GaAs growth layer from the substrate, the thermal strain in the separated eaves was greatly reduced. However, G of this eaves part
The aAs growth layer is as thin as several μm, which is several tens to several hundreds μm.
With the width above, it is in a state of floating from the substrate. Therefore, when manufacturing a light emitting device or the like on this eaves portion, there are problems that it is easily damaged during a complicated process and that heat generated during device operation is also difficult to escape.

The object of the present invention is to overcome the drawbacks of the prior art and to provide a metal film / III- having a high quality group III-V semiconductor single crystal layer with a small residual thermal strain on a group IV semiconductor single crystal substrate. It is an object of the present invention to provide a method for manufacturing a group V compound semiconductor laminated structure.

[0013]

According to the present invention, a step of growing a group III-V compound semiconductor spacer layer on a group IV semiconductor substrate via a group III-V compound semiconductor buffer layer, and group III-V. a step of growing a compound semiconductor device layer, a mask pattern formed in an island shape using, III-V group
In the step of forming a mesa by etching so that a groove reaching the compound semiconductor buffer layer is formed, and in the next step
By etching only the III-V group compound semiconductor spacer layer
It is possible to use this removal area as a void while removing it.
Support layer on the surface of the compound semiconductor layer stack.
And a step of selectively forming a group III-V compound semiconductor spacer.
And remove only the laser layer by etching.
Check with a step to pass the air gap portion, the anisotropic sputtering
A step of forming an insulating film on the entire surface of the laminated body of the compound semiconductor layers excluding the inner surface of the void portion, and a void using a vapor phase growth method.
Selectively forming an In-based metal layer on the inner surface of the portion , and a III-V group compound semiconductor buffer via the In- based metal layer.
1. A method for manufacturing a metal film / compound semiconductor laminated structure on an elemental semiconductor substrate, which comprises at least a step of pressure-bonding a semiconductor layer and a III-V compound semiconductor device layer .
Further, a step of growing a group III-V compound semiconductor spacer layer on the group IV semiconductor substrate, a step of growing a group III-V compound semiconductor device layer, and using a mask pattern formed in an island shape to reach a group IV semiconductor substrate. So that a groove is formed
The process of forming a mesa by etching and the next process
Etching only III-V compound semiconductor spacer layer
It is possible to use this removal area as a void while removing it.
So that a supporting film can be formed on the surface of the compound semiconductor layer stack.
Selectively forming a group III-V compound semiconductor semiconductor
Etching and removing only the pacer layer and this removal
Using the process of making a region a void and using anisotropic sputtering
Forming an entire surface insulating film of the laminate of the compound semiconductor layer excluding the inner surface of the gap portion, the sky by a vapor deposition method
A step of selectively forming an In-based metal layer on the inner surface of the gap, and a group IV semiconductor substrate and a group III-V through the In- based metal layer.
A metal film on an elemental semiconductor substrate, which comprises at least a step of pressure bonding with a compound semiconductor device layer /
Method for manufacturing compound semiconductor laminated structure.

Further, in the step of forming the In-based metal layer, first, the metal diffusion barrier layer is selectively formed on the inner surface of the void portion by the vapor deposition method, and then the In-based metal layer is selectively formed. Metal film on elemental semiconductor substrate characterized by
/ Method for manufacturing compound semiconductor laminated structure.

In the step of pressure bonding, the In- based metal layer is melted by keeping the In-based metal layer at a melting point or higher, applying ultrasonic vibration to the In- based metal layer, or by using these means together. element semiconductor, characterized in that the
A method for manufacturing a metal film / compound semiconductor laminated structure on a substrate.

[0016]

In order to avoid the occurrence of thermal strain due to the difference in thermal expansion coefficient between the Si substrate and the III-V group compound semiconductor, it is sufficient to insert a sufficiently soft substance that can easily alleviate this, as an intermediate layer. However, it is not necessary to completely separate it from the substrate. For example, metals, especially metal In, are ideal because they have a low elastic modulus and a melting point of about 157 ° C. which is extremely low. During crystal growth at high temperature, and even during cooling after growth, thermal strain is almost 1 due to the liquid metal In intermediate layer up to near the melting point.
Can absorb 00%.

The method of forming the metal In intermediate layer is as follows.
At least on the liquid metal In layer, the target III-
In principle, it is impossible to grow a group V compound semiconductor single crystal layer.

Since the manufacturing method of the present invention has a step of forming a gap by selective etching from the cross section of the mesa structure, a metal In layer is then formed on the inner surface of the side opening of the mesa by a vapor deposition method. Can be formed. Then I
The melting point of n may be pressed from above while being heated to about 157 ° C. or higher or applying ultrasonic vibration, and the upper and lower layers may be pressure-bonded via the metal In layer. In addition, the metal In layer easily reacts with the III-V compound semiconductor single crystal layer. To suppress this, for example, a metal W having a high melting point is formed before the metal In layer is formed.
It is sufficient to form a layer.

[0019]

Embodiments of the present invention will now be described in detail with reference to the drawings.

1A to 1E are sectional views showing the manufacturing steps of an example of the manufacturing method according to the present invention.

As shown in FIG. 1A, for example, first, a GaAs buffer layer 2, 1.5 having a thickness of 2.5 μm is formed on a Si substrate 1.
A μm thick AlGaAs spacer layer 3 and finally a 1 μm thick first GaAs device layer 4 are grown, and the compound semiconductor layer is etched using the patterned SiO ₂ film 5 as a mask to form a mesa. For the growth, a molecular beam epitaxial growth method (MBE method), a gas source MBE method, or, for example, triethylgallium (TEG) and triethylaluminum (TE) as Group III organic metal raw materials is used.
As the materials A) and V, a metal organic chemical vapor deposition method (MOCVD method) using arsine (AsH ₃ ) can be used.

Next, as shown in FIG. 1 (b), Si is formed on the entire surface.
After forming the O ₂ film, the SiO ₂ film in the portion including at least a part of the side surface of the mesa is removed to form the SiO ₂ support film 6, and A
The 1GaAs spacer layer 3 is removed by selective etching from the cross-section portion exposed on the side surface of the mesa.

Next, as shown in FIG. 1C, S is applied to the entire surface excluding the inside of the mesa side opening by using an anisotropic sputtering method.
An iO ₂ thin film 7 was formed, and 0.1 μm was formed inside the side opening of the mesa first by a vapor deposition method using this as a mask.
Thick metal W bottom barrier layer 8 and metal W top barrier layer 9
Are selectively formed, and a metal In lower surface layer 10 and a metal In upper surface layer 11 each having a thickness of 0.3 μm are selectively formed. For forming the metal W barrier layer, for example, a vapor deposition method using tungsten hexafluoride (WF ₆ ) as a source gas can be used. Further, for the formation of the metal In layer, a vapor phase deposition method using a group III organic metal source gas such as trimethylindium (TMIn) can be used.

Next, as shown in FIG. 1D, the In melting point of about 157 ° C. or higher is pressed down from above to lower the metal In lower surface layer 10 and the metal In upper surface layer 11 and further the metal W lower surface barrier layer 8.
After the GaAs buffer layer 2 and the first GaAs device layer 4 are pressure-bonded to each other via the metal W upper surface barrier layer 9,
The O ₂ film 5, the SiO ₂ support film 6 and the SiO ₂ thin film 7 are removed. Through the above steps, a laminated structure is obtained by the manufacturing method of the present invention.

The residual thermal strain of the first GaAs device layer 4 can be reduced by the above process.

Further, the case of growing an appropriate defect reduction layer on the mesa will be described. Also in this case, it is necessary to substantially separate the upper portion of the mesa from the metal In layer and the other portions. In the above process, the mesa side wall may be formed vertically by, for example, anisotropic dry etching, and may be grown by applying a molecular beam from above by the MBE method.

For example, as shown in FIG. 1 (e), first, a second GaAs device layer 12 having a thickness of 0.7 μm is grown while performing thermal cycle annealing at 900 ° C. to 450 ° C. twice about halfway. in InGaAs / GaAs strained superlattice layer _{13 (in 0 2 Ga 0 8} As:.. 10nm, GaA
s: 20 nm, × 10 cycles), and further, for example, 1
A third GaAs device layer 14 with a thickness of μm is grown.

From the photoluminescence (PL) measurement performed to examine the crystal quality of the obtained GaAs layer, GaA was obtained.
It was found that an emission intensity comparable to that of the growth layer on the s substrate was obtained and the strain was completely relaxed without any shift in emission wavelength. The result of TEM observation, the dislocation density much 10 ⁴ ~10 ⁵ cm ^- it was found ^{that 2} very good crystal quality is obtained.

Although the SiO ₂ film is used as the insulating film in the above embodiments, an amorphous film other than this, such as AlN or Si ₃ N ₄ , may be used. Further, although the amorphous insulating film is used as an etching mask, a supporting film, a selective growth mask, etc. in the examples, other semiconductor crystals or metals, if they have these functions and are compatible with other processes, Alternatively, an organic material such as a resist film may be used.

Although the MBE method is used as the growth method of the defect reduction layer in the embodiment, other MOCVD method or halogen transport method may be used. In these cases, for example, if a thin SiO2 film is first formed on the entire surface, then only the upper part of the mesa is removed to form an opening, and the defect-reducing layer is selectively grown. It can be separated.

In the embodiment, when the upper and lower layers are pressure-bonded via the metal In layer, they are heated to a melting point of In of about 157 ° C. or higher, but other methods such as ultrasonic vibration may be used.

Although the metal In is used for the metal layer, it may be alloyed with another metal according to the purpose, for example, Ga.
Is added, the alloy becomes an In-Ga alloy and the melting point can be lowered.

Although metal W is used as the barrier layer,
For example, other than metals, WSi _x with Si added, or TiN _x may be used. Further, in the embodiment, the metal / GaAs laminated structure on the Si substrate has been described as an example.
When the group substrate is Ge, and when the group III-V compound semiconductor is another InP, GaP, or InGaP mixed crystal,
Further, the present invention can be widely applied even when a plurality of kinds of III-V group compound semiconductor layers are mixed.

[0034]

As described above, according to the present invention, the thermal strain due to the difference in thermal expansion coefficient between the group IV single crystal substrate and the group III-V epitaxial layer can be relaxed almost completely, and therefore new dislocations are generated by the thermal strain. Therefore, a metal film / III-V compound semiconductor laminated structure having a high-quality III-V compound semiconductor single crystal layer on a IV semiconductor single crystal substrate can be realized.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a step of an embodiment of a manufacturing method of the present invention.

FIG. 2 is a cross-sectional view showing the steps of a conventional manufacturing method.

[Explanation of symbols]

1 Si substrate 2 GaAs buffer layer 3 AlGaAs spacer layer 4 First GaAs device layer 5 SiO ₂ film 6 SiO ₂ support film 7 SiO ₂ thin film 8 metal W lower surface barrier layer 9 metal W upper surface barrier layer 10 metal In lower surface layer 11 metal In upper surface layer 12 second GaAs device layer 13 InGaAs / GaAs strained superlattice layer 14 third GaAs device layer 21 GaAs layer

Claims (4)

(57) [Claims] 1. A step of growing a group III-V compound semiconductor spacer layer on a group IV semiconductor substrate via a group III-V compound semiconductor buffer layer, and a step of growing a group III-V compound semiconductor device layer. Using the island-shaped mask pattern to reach the III-V group compound semiconductor buffer layer
A step of forming a mesa by etching so that a groove is formed, and a III-V group compound semiconductor spacer in the next step.
Only the layer is etched and removed, and this removed area is
The product of compound semiconductor layers so that voids can be formed.
A step of selectively forming a support film on the surface of the layered body, III-
Only Group V compound semiconductor spacer layer is removed by etching
And a step of forming the removed region into a void, a step of forming an insulating film on the entire surface of the compound semiconductor layer stack excluding the inner surface of the void using an anisotropic sputtering method, and a vapor phase growth Selectively forming an In-based metal layer on the inner surface of the void by using the method, and III-V via the In- based metal layer
Group compound semiconductor buffer layer and III-V group compound semiconductor device
A method of manufacturing a metal film / compound semiconductor laminated structure on an elemental semiconductor substrate, which comprises at least a step of pressure-bonding a vice layer . 2. A step of growing a group III-V compound semiconductor spacer layer on a group IV semiconductor substrate, a step of growing a group III-V compound semiconductor device layer, and a mask pattern formed in an island shape, IV A groove extending to the group semiconductor substrate is formed.
Forming a mesa by etching as the following Engineering
Only the III-V compound semiconductor spacer layer is
And remove this area to make a void.
Surface of the compound semiconductor layer stack so that
Selectively forming a support film on the substrate, and a III-V group compound
While removing only the semiconductor spacer layer by etching
This removal region is used as a void portion, a step of forming an insulator film on the entire surface of the compound semiconductor layer stack excluding the inner surface of the void portion using an anisotropic sputtering method, and a vapor deposition method are used. A step of selectively forming an In-based metal layer on the inner surface of the cavity using the group IV semiconductor substrate and an I- based metal substrate through the In- based metal layer.
A method for manufacturing a metal film / compound semiconductor laminated structure on an elemental semiconductor substrate, which comprises at least a step of pressure-bonding a II-V group compound semiconductor device layer . 3. A method for forming an In-based metal layer is a void portion.
First, a metal diffusion barrier layer is selectively formed on the inner surface of the substrate using a vapor deposition method, and then an In-based metal layer is vapor deposited.
Selectively forming method for producing a metal film / the compound semiconductor multilayer structure on elemental semiconductor substrate according to claim 1, wherein that the using. 4. A process of crimping, or hold the In-based metal layer above its melting point, or to ultrasonic vibrations in an In-based metal layer, or by a combination of these means I
4. The method for producing a metal film / compound semiconductor laminated structure on an elemental semiconductor substrate according to claim 1, wherein the n- based metal layer is melted .