JPH0722312A - Method for manufacturing strain semiconductor film - Google Patents
Method for manufacturing strain semiconductor filmInfo
- Publication number
- JPH0722312A JPH0722312A JP15048793A JP15048793A JPH0722312A JP H0722312 A JPH0722312 A JP H0722312A JP 15048793 A JP15048793 A JP 15048793A JP 15048793 A JP15048793 A JP 15048793A JP H0722312 A JPH0722312 A JP H0722312A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- layer
- growth
- film thickness
- strained semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Recrystallisation Techniques (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、高性能半導体レーザや
高性能電子デバイスに用いられる歪半導体膜の製造方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a strained semiconductor film used in high performance semiconductor lasers and high performance electronic devices.
【0002】[0002]
【従来の技術】基板と異なる格子定数を有する半導体層
を基板上に積層させると、半導体層は2軸性応力により
変形し、歪半導体層が形成される。この歪半導体層中で
は、歪の大きさ、層厚に応じて、主に価電子帯のエネル
ギーバンド構造を変化させることが出来るため、この歪
半導体層を例えば半導体レーザの活性層に用いることに
より、低発振閾値化や高速応答化等の高性能化が可能と
なる。しかし、歪半導体層を積層する場合、歪によるエ
ネルギーが膜内に蓄えられ、ある層厚に達すると膜内に
転位が発生したり成長が3次元に島状成長に変化したり
する。この臨界の膜厚は臨界膜厚と呼ばれ、歪半導体を
用いる際の大きな制約条件となる。臨界膜厚は本来、歪
半導体層の歪量や弾性定数で定まる量であるが、低温成
長やTe,Sb等のサーファクタントを用いた成長を行
うことにより、臨界膜厚以上の歪半導体層が準安定状態
として形成されることが知られている(G.J.Whaley et
al.Appl. Phys. Lett. 57, 144(1990),N.Gramdjean et
al.Phys. Rev.Lett. 69, 796(1992))。2. Description of the Related Art When a semiconductor layer having a lattice constant different from that of a substrate is laminated on the substrate, the semiconductor layer is deformed by biaxial stress to form a strained semiconductor layer. In this strained semiconductor layer, the energy band structure of the valence band can be changed mainly according to the magnitude of strain and the layer thickness. Therefore, by using this strained semiconductor layer as an active layer of a semiconductor laser, for example, Higher performance such as lower oscillation threshold and faster response becomes possible. However, when a strained semiconductor layer is stacked, energy due to strain is stored in the film, and when a certain layer thickness is reached, dislocations are generated in the film or the growth changes three-dimensionally into island-shaped growth. This critical film thickness is called a critical film thickness, which is a great constraint when using a strained semiconductor. The critical film thickness is originally an amount determined by the strain amount or elastic constant of the strained semiconductor layer, but by performing low temperature growth or growth using a surfactant such as Te or Sb, the strained semiconductor layer having the critical film thickness or more is quasi It is known to form as a stable state (GJWhaley et
al.Appl. Phys. Lett. 57 , 144 (1990), N. Gramdjean et
Rev. Lett. 69 , 796 (1992)).
【0003】[0003]
【発明が解決しようとする課題】上に説明した低温成長
やサーファクタントを用いた歪半導体成長では、ミスフ
ィット転位の少ない平坦なエピタキシャル膜がある程度
の層厚まで積層出来るが、デバイスを作製するアニール
等のプロセスによって、準安定状態にある歪半導体層に
転位や欠陥の導入による歪緩和が生じ、初期に意図した
歪効果が消失する。またデバイス駆動中にも歪緩和が生
じ、特性劣化を生じる。本発明の目的は、エネルギー的
に安定で信頼性の高い歪半導体膜の製造方法を提供する
ことにある。In the above-described low temperature growth or strained semiconductor growth using a surfactant, a flat epitaxial film with few misfit dislocations can be stacked up to a certain layer thickness, but annealing for device fabrication, etc. This process causes strain relaxation due to the introduction of dislocations and defects in the strained semiconductor layer in the metastable state, and the strain effect initially intended disappears. In addition, strain relaxation occurs during device driving, resulting in characteristic deterioration. An object of the present invention is to provide a method of manufacturing a strained semiconductor film which is energetically stable and highly reliable.
【0004】[0004]
【課題を解決するための手段】本発明の歪半導体膜の製
造方法では、第1の半導体からなる基板上に第1の半導
体とは異なる格子定数を有する第2の半導体を結晶性を
損わない程度の低温成長、又はサーファクタントのうち
の一方の結晶成長法を利用した成長を用いてダブルヘテ
ロ構造における臨界膜厚程度以内で積層し、引続き第1
の半導体と格子整合している構造か又は第2の半導体と
反対方向に歪んでいる構造かのうちのいずれか一方の構
造の第3の半導体層を積層することに特徴がある。In the method for manufacturing a strained semiconductor film according to the present invention, the crystallinity of a second semiconductor having a lattice constant different from that of the first semiconductor is impaired on a substrate made of the first semiconductor. Low temperature growth, or growth using one of the surfactants' crystal growth method, and stacking within the critical film thickness of the double hetero structure, and continuing.
The third semiconductor layer is characterized by laminating the third semiconductor layer having either one of the structure lattice-matched with the semiconductor of 1) and the structure distorted in the opposite direction to the second semiconductor.
【0005】[0005]
【作用】本発明の作用を図を用いて説明する。図2は、
歪量fと膜厚の関係を示したものである。図2の点線
は、単一ヘテロ構造の臨界膜厚を示した線であり、実線
はダブルヘテロ構造の臨界膜厚を示したものである。歪
量f1 の歪半導体膜を成長すると、この膜は、通常の成
長条件下では、膜厚hC1で臨界膜厚に達しミスフィット
転位が膜内に導入され始めるが、低温成長やサーファク
タントを用いることによりhC1を越えても歪半導体層内
にミスフィット転位が生じさせないで積層することが出
来る。歪半導体層厚をダブルヘテロ構造の臨界膜厚N2
(これは単一ヘテロ構造の臨界膜厚より大きい)以下に
して、その上に基板と同じ格子定数あるいは、歪半導体
層と反対方向の歪を有する半導体層を引き続き積層する
と、この歪半導体膜はエネルギー的に安定となりプロセ
ス中あるいはデバイス駆動中にミスフィット転位が発生
することが極めて少なくなる。このように本発明では、
高信頼性の歪半導体で同一歪量ではより厚い歪半導体層
を、同一膜厚ではより大きな歪量の歪半導体層の成長が
可能となる。The operation of the present invention will be described with reference to the drawings. Figure 2
The relationship between the strain amount f and the film thickness is shown. The dotted line in FIG. 2 shows the critical film thickness of the single hetero structure, and the solid line shows the critical film thickness of the double hetero structure. When a strained semiconductor film having a strain amount f 1 is grown, this film reaches a critical film thickness at a film thickness h C1 under normal growth conditions and misfit dislocations start to be introduced into the film, but low temperature growth and surfactant are not generated. By using it, it is possible to stack without causing misfit dislocations in the strained semiconductor layer even if h C1 is exceeded. The thickness of the strained semiconductor layer is the critical thickness N 2 of the double hetero structure.
(This is larger than the critical film thickness of the single hetero structure), and if a semiconductor layer having the same lattice constant as that of the substrate or strain in the opposite direction to the strained semiconductor layer is successively laminated thereon, this strained semiconductor film will be formed. It becomes energetically stable, and the occurrence of misfit dislocations during the process or device driving is extremely reduced. Thus, in the present invention,
It is possible to grow a strained semiconductor layer having a high reliability with the same strain amount and a strained semiconductor layer having a larger strain amount with the same film thickness with high reliability.
【0006】[0006]
【実施例】以下、図面を用いて本発明の実施例を説明す
る。図1は、本発明により作製される歪半導体膜の断面
図である。第1の半導体11からなる基板上に、格子定
数の異なる第2の半導体12を低温成長もしくはサーフ
ァクタントを利用した成長を用いて、ダブルヘテロ構造
の臨界膜厚以内の層厚で積層する。引き続き第1の半導
体11と同じ格子定数あるいは第2の半導体12と反対
方向の歪を有する第3の半導体13を積層する。本発明
の歪半導体膜の製造方法では、歪半導体成長中の転位が
少なくまた最終的な歪半導体層がエネルギー的に安定で
あるので、プロセス中あるいはデバイス駆動中の歪半導
体層の劣化は少ない。また臨界膜厚によるデバイス設計
の制約も大幅に改善されている。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a strained semiconductor film manufactured according to the present invention. A second semiconductor 12 having a different lattice constant is laminated on a substrate made of the first semiconductor 11 by low temperature growth or growth using a surfactant to a layer thickness within the critical film thickness of the double hetero structure. Subsequently, a third semiconductor 13 having the same lattice constant as the first semiconductor 11 or strain in the opposite direction to the second semiconductor 12 is laminated. In the method for manufacturing a strained semiconductor film of the present invention, there are few dislocations during growth of the strained semiconductor and the final strained semiconductor layer is energetically stable, so that the strained semiconductor layer is less deteriorated during the process or device driving. The restrictions on device design due to the critical film thickness have also been greatly improved.
【0007】以下に具体的な例を用いて本発明の実施例
を説明する。Embodiments of the present invention will be described below with reference to specific examples.
【0008】図3は、歪半導体である第2の半導体層を
低温で成長した場合の工程図である。(100)面方位
のGaAs基板31上に分子線エピタキシャル法を用い
てGaAs層32を1000Å積層する。このときの成
長温度は600℃であり、成長速度は0.7μm/h、
As圧は1×10-6Torrとした。続いてIn組成
0.3の歪半導体層を成長する際に、成長温度が550
℃程度であると単一ヘテロ構造の臨界膜厚は約30Åで
ある。ここで、成長温度を460℃まで下げ、ダブルヘ
テロ構造の臨界膜厚である約60Åの低温成長InGa
As層33を積層する。この際30Åを越えてもミスフ
ィット転位や三次元島状成長はRHEED観察からは観
測されず、平坦性の高いコヒーレントな歪半導体層が形
成されている。引き続き成長温度を600℃まで上げな
がらGaAsキャップ層34を1000Å積層する。表
面には、クロスハッチやスリップライン等のモホロジー
は観測されず、また、フォトルミネスセンススペクトル
からこの低温成長InGaAs層33は完全に歪んだ状
態にあり、またその半値全幅、強度共に良好であり欠陥
の少ない歪半導体層が形成されている。またこの歪半導
体膜を650℃1時間As雰囲気中でアニールしても、
表面モホロジーは変化せずまたフォトルミネスセンスス
ペクトルもアニール前と変化せずこの歪半導体膜が熱的
に安定であることがわかる。FIG. 3 is a process chart in the case where the second semiconductor layer which is a strained semiconductor is grown at a low temperature. A GaAs layer 32 of 1000 liters is laminated on a GaAs substrate 31 having a (100) plane orientation by a molecular beam epitaxial method. The growth temperature at this time is 600 ° C., the growth rate is 0.7 μm / h,
The As pressure was 1 × 10 −6 Torr. Then, when a strained semiconductor layer having an In composition of 0.3 is grown, the growth temperature is 550
The critical film thickness of the single heterostructure is about 30Å at about ° C. Here, the growth temperature is lowered to 460 ° C., and low-temperature growth InGa having a critical film thickness of the double hetero structure of about 60 Å
The As layer 33 is laminated. At this time, misfit dislocations and three-dimensional island-shaped growth were not observed by RHEED observation even if the thickness exceeded 30 Å, and a coherent strained semiconductor layer having high flatness was formed. Subsequently, while increasing the growth temperature to 600 ° C., the GaAs cap layer 34 is laminated to 1000 Å. No morphology such as crosshatch or slip line is observed on the surface, and the low temperature grown InGaAs layer 33 is in a completely distorted state from the photoluminescence spectrum, and the full width at half maximum and the strength are both good and there are no defects. A strained semiconductor layer having a small number of layers is formed. Moreover, even if this strained semiconductor film is annealed in an As atmosphere at 650 ° C. for 1 hour,
It can be seen that the surface morphology does not change and the photoluminescence spectrum does not change from that before annealing, and this strained semiconductor film is thermally stable.
【0009】図4は歪半導体である第2の半導体層をサ
ーファクタントを利用して成長した場合の工程図であ
る。(100)面GaAs基板41上に分子線エピタキ
シャル法を用いてGaAs層42を1000Å積層す
る。この時の成長温度は600℃、成長速度は0.7μ
m/h、As圧は1×10-6Torrとした。次にTe
原子を一原子層分だけGaAs層42上に照射してTe
原子層43を形成する。成長温度を550℃と少し下げ
た後、In組成0.3のInGaAs層44を60Å積
層する。この場合でも60ÅのInGaAs層44成長
後もRHEEDはストリークであり転位や三次元島状化
することなしに平坦性の高い歪半導体層が得られる。引
き続き成長温度500℃で、In組成0.4、InGa
P層45を300Å積層する。このInGaP層45は
GaAsよりも小さな格子定数を有し、InGaAs層
44とは反対方向の歪を有する。このようにして作製さ
れた歪半導体膜も前記実施例同様良好な表面モホロジ
ー、フォトルミネスセンススペクトルを有し、また熱的
安定性にも優れている。FIG. 4 is a process diagram in the case where a second semiconductor layer which is a strained semiconductor is grown by using a surfactant. The GaAs layer 42 is laminated on the (100) plane GaAs substrate 41 by the molecular beam epitaxy method to 1000 Å. The growth temperature at this time is 600 ° C, and the growth rate is 0.7μ.
The m / h and As pressure were 1 × 10 −6 Torr. Next Te
A single atomic layer of atoms is irradiated onto the GaAs layer 42 to Te.
The atomic layer 43 is formed. After slightly lowering the growth temperature to 550 ° C., an InGaAs layer 44 having an In composition of 0.3 is laminated by 60 Å. Even in this case, the RHEED is a streak even after the growth of the 60 Å InGaAs layer 44, and a strained semiconductor layer having high flatness can be obtained without dislocation or three-dimensional island formation. Then, at a growth temperature of 500 ° C., In composition 0.4, InGa
The P layer 45 is laminated by 300Å. The InGaP layer 45 has a lattice constant smaller than that of GaAs and has a strain in the opposite direction to the InGaAs layer 44. The strained semiconductor film produced in this manner has the same good surface morphology and photoluminescence spectrum as in the above-mentioned examples, and is also excellent in thermal stability.
【0010】以上の実施例では、InGaAs/GaA
s系を例にとって説明したが、これがInGaAsP/
InP系であっても、InGaP/GaAs,SiGe
/Si系であっても構わない。また用いるサーファクタ
ントもSb,As,Snであってもよい。In the above embodiments, InGaAs / GaA is used.
Although the s series was used as an example, this is InGaAsP /
Even InP-based, InGaP / GaAs, SiGe
It may be a / Si system. The surfactant used may also be Sb, As, Sn.
【0011】本実施例では歪半導体層としてInGaA
sよりなる単一の層を用いて説明したが、本発明では、
この歪半導体層が複数の層から構成されていても同様の
効果が有る。この場合には、歪半導体層の格子定数とし
てはそれを構成する複数の層の層厚を加味した平均格子
定数に基づく歪量を用いればよい。In this embodiment, InGaA is used as the strained semiconductor layer.
Although a single layer composed of s is used for the description, in the present invention,
Even if this strained semiconductor layer is composed of a plurality of layers, the same effect can be obtained. In this case, as the lattice constant of the strained semiconductor layer, the strain amount based on the average lattice constant in consideration of the layer thickness of the plurality of layers forming the strained semiconductor layer may be used.
【0012】[0012]
【発明の効果】本発明を用いると、歪半導体膜を利用す
る際の成長上の制約条件である臨界膜厚を大幅に緩和し
かつ高品質性、高信頼性を有する歪半導体膜を形成する
ことが可能であり、これを用いた歪半導体量子井戸レー
ザやヘテロバイポーラトランジスタ等の高性能化が可能
となる。According to the present invention, a strained semiconductor film having a high quality and a high reliability can be formed by significantly relaxing the critical film thickness, which is a constraint condition on the growth when the strained semiconductor film is used. It is possible to improve the performance of a strained semiconductor quantum well laser, a hetero bipolar transistor, etc. using the same.
【図1】本発明の一実施例による歪半導体膜の断面図。FIG. 1 is a sectional view of a strained semiconductor film according to an embodiment of the present invention.
【図2】本発明の作用を説明するための説明図。FIG. 2 is an explanatory diagram for explaining the operation of the present invention.
【図3】第2の半導体層を低温で成長する本発明の第1
の実施例の工程図。FIG. 3 is a first of the present invention for growing a second semiconductor layer at low temperature.
Process drawing of the embodiment of FIG.
【図4】第2の半導体層をサーファクタントを利用して
成長する本発明の第2の実施例の工程図。FIG. 4 is a process drawing of a second embodiment of the present invention in which a second semiconductor layer is grown by using a surfactant.
11 第1の半導体 12 第2の半導体 13 第3の半導体 31 GaAs基板 32 GaAs基板 33 低温成長InGaAs層 34 GaAsキャップ層 41 GaAs基板 42 GaAs層 43 Te原子層 44 InGaAs層 45 InGaP層 11 First Semiconductor 12 Second Semiconductor 13 Third Semiconductor 31 GaAs Substrate 32 GaAs Substrate 33 Low Temperature Growth InGaAs Layer 34 GaAs Cap Layer 41 GaAs Substrate 42 GaAs Layer 43 Te Atomic Layer 44 InGaAs Layer 45 InGaP Layer
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成6年9月21日[Submission date] September 21, 1994
【手続補正1】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】特許請求の範囲[Name of item to be amended] Claims
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【特許請求の範囲】[Claims]
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 29/73 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01L 29/73
Claims (1)
半導体とは異なる格子定数を有する第2の半導体を結晶
性を損わない程度の低温成長又はサーファクタントを利
用した成長のうちの一方の結晶成長法を用いて、ダブル
ヘテロ構造における臨界膜厚程度以内で積層し、引続き
第1の半導体と格子整合している構造か又は第2の半導
体と反対方向に歪んでいる構造かのうちのいずれか一方
の構造の第3の半導体層を積層することを特徴とする歪
半導体膜の製造方法。1. A low temperature growth of a second semiconductor having a lattice constant different from that of the first semiconductor on a substrate made of the first semiconductor, or a growth utilizing a surfactant. One of the crystal growth methods is used to determine whether the structure is stacked within the critical film thickness in the double hetero structure and is subsequently lattice-matched with the first semiconductor or is distorted in the opposite direction to the second semiconductor. A method for manufacturing a strained semiconductor film, comprising laminating a third semiconductor layer having any one of the structures.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15048793A JPH0722312A (en) | 1993-06-22 | 1993-06-22 | Method for manufacturing strain semiconductor film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15048793A JPH0722312A (en) | 1993-06-22 | 1993-06-22 | Method for manufacturing strain semiconductor film |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0722312A true JPH0722312A (en) | 1995-01-24 |
Family
ID=15497952
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15048793A Pending JPH0722312A (en) | 1993-06-22 | 1993-06-22 | Method for manufacturing strain semiconductor film |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0722312A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002305354A (en) * | 2001-04-05 | 2002-10-18 | Furukawa Electric Co Ltd:The | Surface emission-type semiconductor laser element |
JP2003051644A (en) * | 2001-08-02 | 2003-02-21 | Furukawa Electric Co Ltd:The | Semiconductor device, semiconductor light-receiving device, semiconductor light-emitting device, semiconductor laser and surface-emitting semiconductor laser |
JP2007329191A (en) * | 2006-06-06 | 2007-12-20 | Sumitomo Electric Ind Ltd | Process for fabricating semiconductor laser |
US7698096B2 (en) | 2008-01-21 | 2010-04-13 | Nintendo Co., Ltd. | Information processing apparatus, storage medium, and methodology for calculating an output value based on a tilt angle of an input device |
JP2011054787A (en) * | 2009-09-02 | 2011-03-17 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and method for manufacturing semiconductor device |
US9700806B2 (en) | 2005-08-22 | 2017-07-11 | Nintendo Co., Ltd. | Game operating device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0393221A (en) * | 1989-09-05 | 1991-04-18 | Fujitsu Ltd | Semiconductor substrate |
-
1993
- 1993-06-22 JP JP15048793A patent/JPH0722312A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0393221A (en) * | 1989-09-05 | 1991-04-18 | Fujitsu Ltd | Semiconductor substrate |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002305354A (en) * | 2001-04-05 | 2002-10-18 | Furukawa Electric Co Ltd:The | Surface emission-type semiconductor laser element |
JP2003051644A (en) * | 2001-08-02 | 2003-02-21 | Furukawa Electric Co Ltd:The | Semiconductor device, semiconductor light-receiving device, semiconductor light-emitting device, semiconductor laser and surface-emitting semiconductor laser |
US9700806B2 (en) | 2005-08-22 | 2017-07-11 | Nintendo Co., Ltd. | Game operating device |
US10155170B2 (en) | 2005-08-22 | 2018-12-18 | Nintendo Co., Ltd. | Game operating device with holding portion detachably holding an electronic device |
US10238978B2 (en) | 2005-08-22 | 2019-03-26 | Nintendo Co., Ltd. | Game operating device |
US10661183B2 (en) | 2005-08-22 | 2020-05-26 | Nintendo Co., Ltd. | Game operating device |
JP2007329191A (en) * | 2006-06-06 | 2007-12-20 | Sumitomo Electric Ind Ltd | Process for fabricating semiconductor laser |
US7698096B2 (en) | 2008-01-21 | 2010-04-13 | Nintendo Co., Ltd. | Information processing apparatus, storage medium, and methodology for calculating an output value based on a tilt angle of an input device |
JP2011054787A (en) * | 2009-09-02 | 2011-03-17 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and method for manufacturing semiconductor device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0329400B1 (en) | Semiconductor thin film and process for fabricating the same | |
US6232138B1 (en) | Relaxed InxGa(1-x)as buffers | |
JP3286921B2 (en) | Silicon substrate compound semiconductor device | |
JP3114809B2 (en) | Semiconductor device | |
JPH0562452B2 (en) | ||
JPH06296060A (en) | Manufacture of visible light semiconductor laser diode | |
US5016065A (en) | Compound semiconductor substrate with InGaP layer | |
KR930004240B1 (en) | Semiconductor substrate including strained layer supperlattice | |
JPH0722312A (en) | Method for manufacturing strain semiconductor film | |
US6594293B1 (en) | Relaxed InxGa1-xAs layers integrated with Si | |
JP2925004B2 (en) | Gallium nitride crystal growth method | |
US6589335B2 (en) | Relaxed InxGa1-xAs layers integrated with Si | |
JPH03161922A (en) | Hetero-epitaxial growth of group iii-v compound semiconductor on dissimilar substrate | |
JPH1032165A (en) | Growing method for compound semiconductor layer | |
JPH05267175A (en) | Compound semiconductor substrate | |
JP2560601B2 (en) | Method for manufacturing metal film / compound semiconductor laminated structure on elemental semiconductor substrate | |
JP3441773B2 (en) | Semiconductor thin film device and method of manufacturing the same | |
JPH0620968A (en) | Metal film/compound semiconductor laminated structure on element semiconductor substrate and manufacture thereof | |
JP3169064B2 (en) | Fabrication method of semiconductor three-dimensional quantum structure | |
JP2719868B2 (en) | Semiconductor substrate and method of manufacturing the same | |
JPH0774100A (en) | Manufacture of semiconductor device | |
JP3255798B2 (en) | Compound semiconductor device and method of manufacturing the same | |
JP3224118B2 (en) | Epitaxial growth method | |
JPH08264456A (en) | Growing method for crystal of compound semiconductor | |
JP2734355B2 (en) | Method of manufacturing metal film / compound semiconductor laminated structure on elemental semiconductor substrate |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19990406 |