JP4303379B2 - Manufacturing method of semiconductor substrate - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor substrate in which an epitaxial layer including a III-V compound semiconductor layer is transferred onto a silicon substrate.
[0002]
[Prior art]
By forming a compound semiconductor on a silicon substrate, a multi-functional device having both excellent light emitting and receiving characteristics and high frequency characteristics of the compound semiconductor can be constructed on the silicon substrate. A silicon substrate has higher mechanical strength than a GaAs substrate or an InP substrate, and can significantly improve yield reduction due to substrate cracking and chipping in a device trial manufacturing process. In addition, an inexpensive device using a large-diameter silicon substrate can significantly reduce the manufacturing cost of the device compared to a device using a GaAs substrate or an InP substrate. For this reason, techniques for directly growing a compound semiconductor on a silicon substrate and techniques for bonding the compound semiconductor substrate to the silicon substrate have been proposed.
[0003]
For example, when GaAs is directly grown on a silicon substrate, it is formed by a two-step growth method using MBE (Molecular Beam Epitaxy) method or MOCVD (Metal Organic Chemical Vapor Deposition) method. That is, the natural oxide film on the surface of the silicon substrate is removed at 850 ° C. to 1000 ° C., cooled to about 400 ° C., and then amorphous GaAs is formed to a thickness of 100 to 1000 mm. Thereafter, the temperature is raised to 500 to 700 ° C. to epitaxially grow the GaAs layer.
[0004]
Further, as disclosed in Japanese Patent Laid-Open Nos. 6-90061 and 9-63951, there has been proposed a technique in which the surfaces of a silicon substrate and a compound semiconductor substrate are bonded to each other and different substrates are bonded.
[0005]
Here, a technique for transferring a compound semiconductor epitaxial layer to a silicon substrate will be described with reference to FIG.
[0006]
First, as shown in FIG. 4A, a buffer layer 2 made of gallium arsenide is grown on the gallium arsenide substrate 1 by about 0.1 to 2 μm.
[0007]
Next, an aluminum arsenic layer 3 is grown as a selective etching layer by 100 to 1000 mm, and an epitaxial layer 4 including an active layer of the device is grown.
[0008]
Next, as shown in FIG. 4B, bonding is performed by bringing the silicon substrate 5 into contact and annealing in hydrogen gas.
[0009]
Thereafter, as shown in FIG. 4C, the aluminum arsenic layer 3 is etched with a hydrofluoric acid-based etchant. Thereby, the epitaxial layer 4 including the active layer of the device can be transferred to the silicon substrate 5.
[0010]
[Problems to be solved by the invention]
However, when the compound semiconductor 4 is directly epitaxially grown on the silicon substrate 5, 1 × 10 ⁶ cm ⁻² or more exists in the compound semiconductor epitaxial layer due to the difference in lattice constant and thermal expansion coefficient between the substrate 5 and the epitaxial layer 4. This causes crystal defects. Therefore, even if a laser diode, a light emitting diode, a field effect transistor, or the like is formed, there is a problem that the characteristics and reliability are greatly lowered and it cannot be put to practical use.
[0011]
Further, in order to transfer the compound semiconductor epitaxial layer 4 from the compound semiconductor substrate 1 by the lift-off method after the compound semiconductor layer 4 is bonded to the silicon substrate 5, it is necessary to remove the selective etching layer 3 with an etching solution. Bonding at a size of several centimeters is limited by the wraparound distance of the liquid, and in the method disclosed in Japanese Patent Laid-Open Nos. 6-90061 and 9-63951, 4 inches or 6 inches. There is a problem that transfer onto a large-diameter substrate is impossible.
[0012]
Furthermore, after bonding, there has been a problem that dislocations due to differences in thermal expansion coefficient and lattice constant between the silicon substrate 5 and the compound semiconductor layer 4 occur in the compound semiconductor epitaxial layer 4 including the active layer of the device.
[0013]
[Means for Solving the Problems]
In order to solve the above-described problem, in the method for manufacturing a semiconductor substrate according to claim 1, Al _y Ga _1-y As (0) is formed on a germanium substrate, a gallium arsenide substrate, or an indium phosphide substrate having a groove formed on the surface. .9 ≦ y ≦ 1.0) layer and III-V compound semiconductor layer are epitaxially grown, and the Al _y Ga _1-y As layer (0.9 ≦ y ≦ ₁₎ is removed so as to remove the portion corresponding to the groove. 1.0) and a step of mesa-etching the III-V compound semiconductor layer , an amorphous gallium arsenide layer is formed on the silicon substrate, and In _x Ga _1-x As (0) is formed on the amorphous gallium arsenide layer. .05 ≦ x ≦ 0.6) layer is epitaxially grown, and the III-V group compound semiconductor layer and the In _x Ga _1-x As (0.05 ≦ x ≦ 0.6) layer are bonded together. after the _Al y _{Ga 1-y} As ( .9 ≦ y ≦ 1.0) layer by etching, comprising the the steps of removing the germanium substrate, a gallium arsenide substrate or an indium phosphide substrate.
[0014]
In the method for manufacturing a semiconductor substrate, a dislocation density of an In _x Ga _1-x As (0.05 ≦ x ≦ 0.6) layer on the silicon substrate is 1 × 10 ⁸ cm ⁻² or less, and It is desirable that the radius of curvature due to warpage of the silicon substrate is 70 m or more.
[0016]
Furthermore, in the manufacturing method of the semiconductor substrate,
It is desirable to form a groove in a portion corresponding to the groove of the silicon substrate to form the In _x Ga _1-x As (0.05 ≦ x ≦ 0.6) layer.
[0017]
[Action]
When prepared as described above, the compound semiconductor epitaxial layers including an active layer of the device, the transferred _{In x Ga 1-x As (} 0.05 ≦ x ≦ 0.6) layer on a silicon substrate epitaxially grown, an In _x Ga _{Since the 1-x} As (0.05 ≦ x ≦ 0.6) layer functions as a buffer layer, dislocations are not introduced into the compound semiconductor layer including the active layer of the device.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
[0019]
FIG. 1 is a diagram showing an embodiment of a method for manufacturing a semiconductor substrate according to claim 1, wherein 6 is a germanium substrate, gallium arsenide substrate, or indium phosphorus substrate, and 7 is a buffer layer made of gallium arsenide, indium phosphorus, or the like. , 8 is an epitaxial layer including an active layer of a device made of a III-V group compound semiconductor such as GaAs, AlGaAs, InAlGaP, InGaAs, InAlAs, InP, GaAsP, InAlGaAs, or InAlGaAsP, and 9 is an epitaxially grown In on the silicon substrate 5. _x Ga _1-x As (0.05 ≦ x ≦ 0.6) layer.
[0020]
Compared to the case of directly growing a III-V group compound semiconductor such as GaAs on a Si substrate, the Ge substrate, GaAs substrate, and InP substrate have a lower dislocation density (1 × 10 ⁴ cm ⁻² or less). A group III-V compound semiconductor with good crystal can be formed. Further, the buffer layer can be formed by inserting a selective etching layer of AlAs, and the substrate is limited to a Ge substrate, a GaAs substrate, and an InP substrate.
[0021]
First, a buffer layer 7 made of gallium arsenide, indium phosphide, or the like is grown on a germanium substrate, a gallium arsenide substrate, or an indium phosphide substrate 6 by a well-known vapor phase epitaxial method such as MBE or MOCVD.
[0022]
Thereafter, an Al _y Ga _1-y As (0.9 ≦ y ≦ 1.0) layer 3 serving as a selective etching layer is grown by 100 to 1000 mm. If the film thickness is not set to be thicker as the width W of the mesa region shown in FIG. 1B is wider, the selective etching described later becomes difficult. For example, when the width W of the mesa region is 100 μm, selective etching can be performed at 200 mm or more.
[0023]
After the growth of the Al _y Ga _1-y As (0.9 ≦ y ≦ 1.0) layer 3 serving as a selective etching layer, an epitaxial layer 8 including an active layer of a device made of a III-V compound semiconductor is grown. And take out from the epitaxial apparatus.
[0024]
Thereafter, as shown in FIG. 1B, a mesa region having a width W is formed by normal photolithography and etching. At this time, the etching is performed by wet etching using a mixed solution of sulfuric acid / hydrogen peroxide solution / water or vapor phase etching using plasma of chlorine gas, and an Al _y Ga _1-y As (0.9 ≦ y ≦ 1.0) layer. Etching is performed until the side wall 3 is completely exposed.
[0025]
Next, as shown in FIG. _{1 (c), In x Ga} 1-x As (0.05 ≦ x ≦ 0.6) layer 9 is bonded to a silicon substrate 5 is epitaxially grown, the bonding surface 10 Bonding is completed by pressurizing at a pressure of 50 Pa and annealing at 200 to 500 ° C. in a hydrogen atmosphere for 30 minutes to several hours.
[0026]
Incidentally, the epitaxial growth of the silicon substrate 5 in the _{In x Ga 1-x As (} 0.05 ≦ x ≦ 0.6) layer 9 is carried out in two step growth method according to the MBE method and the MOCVD method. That is, a natural oxide film or the like on the surface of the silicon substrate 5 is removed at 850 to 1000 ° C., and after cooling to around 400 ° C., an amorphous gallium arsenide layer is formed to a thickness of 100 to 1000 mm.
[0027]
Thereafter, the temperature is raised to 500 to 600 ° C., and an In _x Ga _1-x As (0.05 ≦ x ≦ 0.6) layer 9 is grown.
[0028]
When the indium composition is larger than 0.6, a single crystal thin film cannot be grown, and good bonding strength cannot be obtained. That is, when the dislocation density of the In _x Ga _1-x As (0.05 ≦ x ≦ 0.6) layer 9 is 1 ra 10 ⁸ cm ⁻² or less, a good bonding strength can be obtained. When the composition of indium is smaller than 0.05, the radius of curvature due to the wrinkles of the silicon substrate is smaller than 70 m, the wrinkles of the silicon substrate are increased, and uniform bonding cannot be performed.
[0029]
The curvature radius due to warpage of the silicon substrate 5 on which the In _x Ga _1-x As (0.05 ≦ x ≦ 0.6) layer 9 is grown needs to be 70 m or more. Generation of cracks or the like occurs, and a desired semiconductor substrate cannot be obtained.
[0030]
Next, as shown in FIG. 1D, the Al _y Ga _1-y As (0.9 ≦ y ≦ 1.0) layer 3 is removed with a hydrofluoric acid-based etchant to include the active layer of the device. The epitaxial layer 8 is transferred to the silicon substrate 5 via the In _x Ga _1-x As (0.05 ≦ x ≦ 0.6) layer 9.
[0031]
FIG. 2 is a view showing a method for manufacturing a semiconductor substrate according to a third aspect. As shown in FIG. 2A, when a groove 10 of several tens to several hundreds of μm is formed in advance on a germanium substrate, a gallium arsenide substrate, or an indium phosphorous substrate 6, Al _y Ga ₁ in FIG. _-y As (0.9 ≦ y ≦ 1.0) The selective removal of the layer 3 can be performed in a short time and more uniformly. That is, since the aluminum arsenic layer 3 can be selectively removed by supplying a hydrofluoric acid-based etchant through the epitaxial layer 8 or the groove 10 of the substrate 6, the transfer of the epitaxial layer on the large-diameter substrate 6 of 4 inches or more can be performed. It becomes possible.
[0032]
FIG. 3 is a view showing a method for manufacturing a semiconductor substrate according to a fourth aspect. As shown in FIG. 3 (c), a silicon substrate on which a groove ′ of several tens to several hundreds μm is formed in advance on a germanium substrate, a gallium arsenide substrate, or an indium phosphorous substrate 6 and the grooves 10 are formed in advance. 5 is bonded to a substrate on which an In _x Ga _1-x As (0.05 ≦ x ≦ 0.6) layer 9 is epitaxially grown, whereby Al _y Ga _1-y As (0.9) in FIG. ≦ y ≦ 1.0) The selective removal of the layer 3 can be performed in a short time and more uniformly. That is, since the aluminum arsenic layer 3 can be selectively removed by supplying a hydrofluoric acid-based etching solution through the epitaxial layer 8 or the groove 10 of the substrate 6, the epitaxial layer can be transferred on a large-diameter substrate of 4 inches or more. It becomes.
[0033]
【The invention's effect】
As described above, according to the semiconductor substrate manufacturing method of the first aspect, a III-V compound semiconductor epitaxial layer with few dislocation defects can be formed on the silicon substrate. This makes it possible to integrate devices such as compound semiconductor lasers, photodiodes, and other high-speed electronic elements such as compound semiconductor field effect transistors that utilize the characteristics of silicon substrates with high mechanical strength and good thermal conductivity. Can be manufactured.
[0034]
Further, selective etching can be performed through the mesa portion and the substrate groove, and the III-V compound semiconductor epitaxial layer can be uniformly transferred to the silicon substrate even in a large-diameter substrate of 4 inches or more.
[0035]
Furthermore, since a germanium substrate, a gallium arsenide substrate, or an indium phosphorus substrate can be used repeatedly, the device can be manufactured at low cost.
[Brief description of the drawings]
FIG. 1 is a view showing an embodiment of a semiconductor substrate according to claim 1;
FIG. 2 is a diagram showing an embodiment of a method for manufacturing a semiconductor substrate according to claim 3;
FIG. 3 is a diagram showing an embodiment of a method for producing a semiconductor substrate according to claim 4;
FIG. 4 is a view showing a conventional method for manufacturing a semiconductor substrate.
[Sharpness of sign]
1: Gallium arsenide substrate, 2: Buffer layer, 3: Al _y Ga _1-y As (0.9 ≦ y ≦ 1.0) selective etching layer, 4: Epitaxial layer including device active layer, 5: Silicon substrate , 6: germanium substrate, gallium arsenide substrate, or indium phosphide substrate, 7: buffer layer, 8: epitaxial layer including the active layer of the device, 9: In _x Ga _1-x As (0.05 ≦ x ≦ 0.6) )layer

Claims (3)

Epitaxial growth of Al _y Ga _1-y As (0.9 ≦ y ≦ 1.0) layer and III-V group compound semiconductor layer on germanium substrate, gallium arsenide substrate, or indium phosphide substrate with grooves formed on the surface And mesa-etching the Al _y Ga _1-y As layer (0.9 ≦ y ≦ 1.0) and the group III-V compound semiconductor layer so as to remove a portion corresponding to the groove ;
Forming an amorphous gallium arsenide layer on a silicon substrate, and epitaxially growing an In _x Ga _1-x As (0.05 ≦ x ≦ 0.6) layer on the amorphous gallium arsenide layer;
After the III-V group compound semiconductor layer and the In _x Ga _1-x As (0.05 ≦ x ≦ 0.6) layer are bonded together, the Al _y Ga _1-y As (0.9 ≦ y) ≦ 1.0) layer by etching, the germanium substrate, a gallium arsenide substrate or a method of manufacturing a semiconductor substrate comprising the steps, a removing an indium phosphide substrate. The dislocation density of the In _x Ga _1-x As (0.05 ≦ x ≦ 0.6) layer on the silicon substrate is 1 × 10 ⁸ cm ⁻² or less, and the radius of curvature due to warpage of the silicon substrate is 70 m. The method for manufacturing a semiconductor substrate according to claim 1, wherein the method is as described above. A groove is formed in a portion corresponding to the groove of the silicon substrate, and the In _x Ga _1-x The semiconductor substrate manufacturing method according to claim 1, wherein an As (0.05 ≦ x ≦ 0.6) layer is formed.

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