JP3667124B2 - Method for manufacturing compound semiconductor substrate - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention provides a compound semiconductor layer such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), and indium gallium nitride (InGaN) on the (100) surface of a Si substrate. The present invention relates to a method for manufacturing a compound semiconductor substrate that forms a substrate.
[0002]
[Background Art and Problems to be Solved by the Invention]
Compound semiconductor substrates such as GaAs and InP are mechanically fragile and difficult to handle. In addition, there is a problem that it is difficult to obtain a crystal substrate having a high quality and a large area. In order to solve this problem, a method for crystal growth of a compound semiconductor such as GaAs on an inexpensive, large-area, high-strength Si substrate has been proposed.
[0003]
However, when a compound semiconductor such as GaAs is grown on a Si substrate, there is a problem that the crystal defect density is 1 × 10 ⁹ cm ⁻² or more. This problem is caused by a difference in lattice constant and thermal expansion coefficient between Si and a compound semiconductor such as GaAs. In order to absorb the stress and crystal defects caused by the difference in lattice constant and thermal expansion coefficient between compound semiconductors such as Si and GaAs, a so-called two-stage growth method in which a low-temperature growth intermediate layer is inserted, or an improved growth method thereof. As described above, the crystal defect density can be reduced to about 1 × 10 ⁶ cm ⁻² by a thermal cycle annealing method or a superlattice method. However, a crystal defect density of about 1 × 10 ⁶ cm ⁻² adversely affects the characteristics of the semiconductor device due to a decrease in carrier lifetime.
[0004]
In recent years, as a method of reducing the crystal defect density of GaAs on a Si substrate to about 1 × 10 ⁴ cm ⁻² , holographic photolithography is performed on the Si substrate 1 as shown in FIGS. There has been reported a method in which the formed sawtooth-like grating 2 with an interval of 200 nm is formed, and a GaAs film 3 is epitaxially grown on the substrate 1 by a two-step growth method (Appl. Phys. Lett. 59, 2418 (991)). ).
[0005]
That is, in the photolithography for forming the sawtooth pattern 3 with an interval of 200 nm, an Si ₃ N ₄ film (not shown) is formed on the Si substrate 1 as a pattern, and an antireflection film (not shown) and the photoresist are formed. A film (not shown) is formed, this photoresist film is exposed and patterned at a pitch of 200 nm, and then the SiO _x film is obliquely deposited by 40 ° using this photoresist pattern. Next, after the RIE etching of the antireflection film with O ₂ gas, the Si ₃ N ₄ film is RIE etched with CF ₄ gas. Next, the photoresist and the antireflection film are removed with NH ₄ OH: H ₂ O ₂ : H ₂ O, and then the surface of the silicon substrate is anisotropically etched using the remaining Si ₃ N ₄ film as a mask to form a sawtooth shape. The V-groove 2 is formed.
[0006]
However, as described above, the grapho epitaxial growth for forming the 200 nm sawtooth V-groove 2 by the holographic photolithography method is an anisotropic etching of Si. It is difficult to control the shape of the substrate, and there is a limit to finer texture (> 200 nm) due to the limitations of the photo process due to the wavelength of light, and a very complicated process is required. Cost cannot be achieved.
[0007]
The present invention has been made in view of such problems of the prior art, and is a compound semiconductor that eliminates the problems of the prior art that the deposition of an antireflection film and special photolithography are necessary and the process is complicated. An object is to provide a method for manufacturing a substrate.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, in the method of manufacturing a compound semiconductor substrate according to claim 1, a step of forming an isotropic surface texture of 50 nm to 500 nm on a Si substrate, and a III-V group compound on the Si substrate The method includes a step of growing a semiconductor buffer layer, a step of growing a compound semiconductor layer on the buffer layer, and a step of growing a plurality of compound semiconductor layers on the compound semiconductor layer.
[0009]
In the method for manufacturing a compound semiconductor substrate according to claim 2, a step of forming an isotropic surface texture of 50 nm to 500 nm on the Si substrate, and a III-V group compound semiconductor buffer layer are grown on the Si substrate. A step of growing a compound semiconductor layer on the buffer layer, a step of mirror polishing the compound semiconductor layer, and a step of growing a second compound semiconductor layer on the mirror-polished compound semiconductor layer. It is characterized by including.
[0010]
[Action]
In the invention according to claim 1, after forming a surface texture controlled in a uniform shape in a short time on the (100) surface of the Si substrate by the RIE method, an ordinary two-step growth method is performed by the MBE method or the MOCVD method. After forming a buffer layer made of a compound semiconductor using grapho-epitaxial growth and performing a heat treatment, a target compound semiconductor layer is formed, whereby a dislocation density of about 1 × 10 ⁴ cm ⁻² is obtained. A compound semiconductor layer is obtained.
[0011]
In the invention according to claim 2, the surface roughness is reduced by forming one or more compound semiconductor layers after mirror-polishing the outermost surface of the target compound semiconductor layer.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the invention according to each claim will be described with reference to the accompanying drawings.
In the method for manufacturing a compound semiconductor substrate according to claim 1, as shown in FIGS. 1A and 1B, a surface texture 10 is provided on the (100) surface of the Si substrate 1 by the RIE method. Next, a case where the GaAs layers 2 to 4 are epitaxially grown by a vapor phase growth method (for example, MOCVD method) using an organometallic compound (for example, trimethylgallium (hereinafter abbreviated as TMG)) and arsine will be described.
[0013]
First, after cleaning the Si substrate 1, the surface natural oxide film is removed by immersing in hydrofluoric acid (HF). Then, after washing with water and drying with a rinser dryer, the substrate is immediately set on the RIE apparatus.
[0014]
In the present invention, a fine surface texture is formed on the Si substrate 1 by the RIE method as reported in Solar Energy Materials and Solar Cells 43,237 (1977). Ar, CF ₄ , Cl ₂ , N ₂ O, O ₂ or the like is used as an etching gas for RIE. For example, as shown in FIGS. 2A and 2B, the flow rate of Cl ₂ is set to 1 to 100 sccm, and a pyramidal or columnar surface texture 10 having a height of 50 to 500 nm is formed on the Si substrate 1. The shape of the surface texture 10 can be controlled by the flow rate of Cl ₂ and the etching time.
[0015]
After forming the surface texture 10 on the Si substrate 1 in this way, the Si substrate 1 is set in an MOCVD apparatus.
[0016]
Then, as shown in FIGS. 1 and 4, first, as a process 1, while flowing hydrogen and arsine gas, the Si substrate 1 on which the surface texture 10 is formed at 850 ° C. for 10 minutes is subjected to heat treatment, and a natural oxide film on the surface Remove. Next, as step 2, TMG is added while flowing hydrogen or arsine gas at 350 to 400 ° C. to grow the amorphous first buffer layer 2 to 10 to 30 nm. Next, as Step 3, the temperature is raised to 550 to 750 ° C. while flowing hydrogen or arsine gas to crystallize the first buffer layer, and TMG is further added to grow the second buffer layer 3 to 1 to 3 μm. Further, if necessary, the first buffer layer 2 and the second buffer layer 3 are formed by four thermal cycle annealings at 350 ° C. and 750 ° C. while flowing hydrogen or arsine gas as in step 4 in order to reduce the dislocation density. Heat treatment. Then, as step 5, a target GaAs layer 4 having better crystallinity is grown by 1 to 3 μm. In this way, the target GaAs layer 4 having a dislocation density of about 10 ⁴ cm ⁻² can be grown on the Si substrate.
[0017]
The height of the surface texture 10 is optimally in the range of 100 to 300 nm, and the target dislocation density in the GaAs layer 4 can be about 1 × 10 ⁴ cm ⁻² .
[0018]
The range of the height of the surface texture 10 is 50 to 500 nm. However, outside this range, normal heteroepitaxial growth occurs without graphoepitaxial growth, and the dislocation density cannot be reduced.
[0019]
Next, a method for manufacturing a compound semiconductor substrate according to claim 2 will be described. The step of forming an isotropic surface texture having a height of 50 to 500 nm on the Si substrate, the step of growing a III-V compound semiconductor buffer layer on the Si substrate, and the growth of the compound semiconductor layer on the buffer layer The step of performing is the same as the method of manufacturing a compound semiconductor substrate according to claim 1.
[0020]
In the method for manufacturing a compound semiconductor substrate according to claim 2, as shown in FIG. 4, after the compound semiconductor layer 4 is grown on the buffer layers 2 and 1 to 3 μm, the compound semiconductor layer 4 is grown to 0.5 to 1 μm. Mirror finish. For example, the polishing is performed on a polyurethane cloth using colloidal silica as abrasive grains. Polishing pressure is 200 g / cm ² , and chemical mechanical polishing is performed while supplying abrasive grains adjusted to an alkaline solution having a pH of about 10.
[0021]
A target second compound semiconductor layer 5 is further grown on the mirror-polished compound semiconductor layer 4. In this case, homoepitaxial growth occurs, and the dislocation density does not decrease.
[0022]
【The invention's effect】
As mentioned above, according to the manufacturing method of the compound semiconductor substrate which concerns on Claim 1, the process of forming an isotropic surface texture whose height is 50-500 nm on Si substrate, and III-V on this Si substrate A step of growing a group compound semiconductor buffer layer, a step of growing a compound semiconductor layer on the buffer layer, and a step of growing a plurality of compound semiconductor layers on the compound semiconductor layer. There is an advantage that a compound semiconductor having a dislocation density of about 1 × 10 ⁴ cm ⁻² can be grown, and a compound semiconductor can be formed on a large-area Si substrate at a low cost. Cost reduction can be achieved.
[0023]
According to the method for manufacturing a compound semiconductor substrate according to claim 2, a step of forming an isotropic surface texture having a height of 50 to 500 nm on the Si substrate, and a III-V group compound semiconductor on the Si substrate. A step of growing a buffer layer; a step of growing a compound semiconductor layer on the buffer layer; a step of mirror polishing the compound semiconductor layer; and a second compound semiconductor layer further on the mirror-polished compound semiconductor layer Therefore, it is possible to form a compound semiconductor device layer in which the crystal defect density is reduced to about 1 × 10 ⁴ cm ⁻² and the standard deviation of the surface roughness is reduced to 13.0 mm.
[Brief description of the drawings]
1 is a view showing a method for manufacturing a compound semiconductor substrate according to claim 1;
FIG. 2 is a view showing a silicon substrate used for manufacturing a compound semiconductor substrate according to claim 1;
FIG. 3 is a diagram showing a manufacturing process and a substrate temperature of a compound semiconductor substrate according to claim 1;
4 is a view showing a method of manufacturing a compound semiconductor substrate according to claim 2. FIG.
FIG. 5 is a diagram showing a conventional method of manufacturing a compound semiconductor substrate.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Si substrate (100), 2 ... 1st buffer layer, 3 ... 2nd buffer layer, 4 ... Compound semiconductor layer, 5 ... 2nd compound semiconductor layer

Claims (2)

Forming an isotropic surface texture having a height of 50 to 500 nm on the Si substrate; growing a III-V group compound semiconductor buffer layer on the Si substrate; and forming a compound semiconductor layer on the buffer layer. A method for producing a compound semiconductor substrate, comprising a step of growing and a step of further growing a plurality of compound semiconductor layers on the compound semiconductor layer. Forming an isotropic surface texture having a height of 50 to 500 nm on the Si substrate; growing a III-V group compound semiconductor buffer layer on the Si substrate; and forming a compound semiconductor layer on the buffer layer. A method of manufacturing a compound semiconductor substrate, comprising: a step of growing; a step of mirror polishing the compound semiconductor layer; and a step of further growing a second compound semiconductor layer on the mirror-polished compound semiconductor layer. .

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