JP2001102668A - Manufacturing method of semiconductor substrate - Google Patents
Manufacturing method of semiconductor substrateInfo
- Publication number
- JP2001102668A JP2001102668A JP27535199A JP27535199A JP2001102668A JP 2001102668 A JP2001102668 A JP 2001102668A JP 27535199 A JP27535199 A JP 27535199A JP 27535199 A JP27535199 A JP 27535199A JP 2001102668 A JP2001102668 A JP 2001102668A
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- Prior art keywords
- substrate
- layer
- compound semiconductor
- silicon substrate
- manufacturing
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- Semiconductor Lasers (AREA)
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Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明はIII-V族化合物半導
体層を含むエピタキシャル層をシリコン基板上に転写す
る半導体基板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor substrate by transferring an epitaxial layer including a III-V compound semiconductor layer onto a silicon substrate.
【0002】[0002]
【従来の技術】シリコン基板に化合物半導体を形成する
ことで、化合物半導体の優れた受発光特性と高周波特性
を兼ね備えた多機能のデバイスがシリコン基板上に構築
できる。シリコン基板はGaAs基板やInP基板に比
べて機械的強度が高く、デバイス試作プロセスにおける
基板の割れ、カケに起因する歩留りの低下を大幅に改善
できる。また、安価で大口径のシリコン基板を用いたデ
バイスは、GaAs基板やInP基板を用いたデバイス
よりも、デバイスの製造コストを大幅に低減することが
できる。このため、化合物半導体をシリコン基板に直接
成長する技術や化合物半導体基板をシリコン基板に貼り
合せる手法が提案されている。2. Description of the Related Art By forming a compound semiconductor on a silicon substrate, a multifunctional device having both excellent light receiving / emitting characteristics and high frequency characteristics of the compound semiconductor can be constructed on the silicon substrate. A silicon substrate has higher mechanical strength than a GaAs substrate or an InP substrate, and can significantly reduce the yield reduction due to substrate cracking and chipping in a device trial manufacturing process. In addition, a device using an inexpensive large-diameter silicon substrate can significantly reduce the device manufacturing cost as compared with a device using a GaAs substrate or an InP substrate. For this reason, a technique for directly growing a compound semiconductor on a silicon substrate and a technique for bonding a compound semiconductor substrate to a silicon substrate have been proposed.
【0003】例えばシリコン基板上にGaAsを直接成
長する場合には、MBE(Molecular Beam Epitaxy)法
やMOCVD(Metal Organic Chemical Vapor Deposit
ion)法による2段階成長法で形成する。つまり、85
0℃〜1000℃でシリコン基板表面の自然酸化膜を除
去し、400℃前後へ冷却した後、非晶質GaAsを1
00〜1000Å成膜する。その後500〜700℃に
昇温してGaAs層をエピタキシャル成長する。For example, when GaAs is directly grown on a silicon substrate, MBE (Molecular Beam Epitaxy) or MOCVD (Metal Organic Chemical Vapor Deposit) is used.
(ion) method. That is, 85
After removing the natural oxide film on the surface of the silicon substrate at 0 ° C. to 1000 ° C. and cooling it to about 400 ° C., the amorphous GaAs
The film is formed at a thickness of 00 to 1000 °. Thereafter, the temperature is raised to 500 to 700 ° C. to epitaxially grow the GaAs layer.
【0004】また、特開平6−90061号公報や特開
平9−63951号公報に示されているように、シリコ
ン基板と化合物半導体基板の表面同志を接合し、異種基
板を接合する手法が提案されている。Further, as disclosed in Japanese Patent Application Laid-Open Nos. 6-90061 and 9-63951, a technique has been proposed in which the surfaces of a silicon substrate and a compound semiconductor substrate are joined together to join different kinds of substrates. ing.
【0005】ここで、図4を用いて、シリコン基板への
化合物半導体エピタキシャル層の転写技術を説明する。Here, a technique for transferring a compound semiconductor epitaxial layer to a silicon substrate will be described with reference to FIG.
【0006】まず、図4(a)に示すように、ガリウム
砒素基板1にガリウム砒素から成るバッファ層2を0.
1〜2μm程度成長する。First, as shown in FIG. 4A, a buffer layer 2 made of gallium arsenide is placed on a gallium arsenide substrate 1 in a thickness of 0.1 mm.
It grows about 1-2 μm.
【0007】次に、選択エッチング層としてアルミニウ
ム砒素層3を100〜1000Å成長し、デバイスの活
性層を含むエピタキシャル層4を成長する。Next, an aluminum arsenide layer 3 is grown as a selective etching layer by 100 to 1000.degree., And an epitaxial layer 4 including an active layer of the device is grown.
【0008】次に、図4(b)に示すように、シリコン
基板5を接触させて水素ガス中でアニールすることで貼
り合わせる。Next, as shown in FIG. 4B, the silicon substrates 5 are brought into contact with each other and annealed in a hydrogen gas for bonding.
【0009】その後、図4(c)に示すように、ふっ酸
系のエッチング液でアルミニウム砒素層3をエッチング
する。これによりデバイスの活性層を含むエピタキシャ
ル層4をシリコン基板5に転写することができる。Thereafter, as shown in FIG. 4C, the aluminum arsenide layer 3 is etched with a hydrofluoric acid-based etchant. Thereby, the epitaxial layer 4 including the active layer of the device can be transferred to the silicon substrate 5.
【0010】[0010]
【発明が解決しようとする課題】ところが、シリコン基
板5上に化合物半導体4を直接エピタキシャル成長する
場合、基板5とエピタキシャル層4の格子定数や熱膨張
係数の差に起因して、化合物半導体エピタキシャル層に
1×106個cm-2以上の結晶欠陥が発生する。そのた
め、レーザーダイオード、発光ダイオード、あるいは電
界効果トランジスター等を形成しても、その特性と信頼
性が大幅に低下し、実用に供することができないという
問題があった。However, in the case where the compound semiconductor 4 is directly epitaxially grown on the silicon substrate 5, the compound semiconductor 4 may not be formed on the compound semiconductor epitaxial layer due to a difference in lattice constant or thermal expansion coefficient between the substrate 5 and the epitaxial layer 4. Crystal defects of 1 × 10 6 cm −2 or more occur. Therefore, even if a laser diode, a light emitting diode, a field effect transistor, or the like is formed, there is a problem that the characteristics and reliability are significantly reduced, and the device cannot be put to practical use.
【0011】また、シリコン基板5に化合物半導体層4
を貼り合せた後に、化合物半導体基板1から化合物半導
体エピタキシャル層4をリフトオフ法で転写するには、
エッチング液による選択エッチング層3の除去が必要で
あり、エッチング液の回り込み距離に制限されて、数c
m角の大きさでの貼り合せが限界であり、特開平6−9
0061号公報や特開平9−63951号公報に示され
る手法では、4インチや6インチの大口径基板への転写
は不可能であるという問題があった。A compound semiconductor layer 4 is formed on a silicon substrate 5.
After transferring the compound semiconductor epitaxial layer 4 from the compound semiconductor substrate 1 by the lift-off method,
It is necessary to remove the selective etching layer 3 with an etching solution, and the number c
The lamination at the size of m square is the limit.
The method disclosed in Japanese Patent Application Laid-Open No. 0061 and Japanese Patent Application Laid-Open No. 9-63951 has a problem that transfer to a large-diameter substrate of 4 inches or 6 inches is impossible.
【0012】さらに、貼り合せた後に、シリコン基板5
と化合物半導体層4との熱膨張係数や格子定数の差に起
因する転位がデバイスの活性層を含む化合物半導体エピ
タキシャル層4に発生するという問題があった。After bonding, the silicon substrate 5
There is a problem that dislocation due to a difference in thermal expansion coefficient or lattice constant between the compound semiconductor layer 4 and the compound semiconductor layer 4 occurs in the compound semiconductor epitaxial layer 4 including the active layer of the device.
【0013】[0013]
【課題を解決するための手投】上記課題を解決するため
に、請求項1に係る半導体基板の製造方法では、ゲルマ
ニウム基板、ガリウム砒素基板、またはインジウム燐基
板にAlyGa1-yAs(0.9≦y≦1.0)層を含む
バッファ層とIII-V族化合物半導体層をエピタキシャル
成長してメサエッチングするとともに、シリコン基板に
InxGa1-xAs(0.05≦x≦0.6)層をエピタ
キシャル成長し、前記III-V族化合物半導体層と前記I
nxGa1-xAs(0.05≦x≦0.6)層とを貼り合
わせた後、前記AlyGa1-yAs(0.9≦y≦1.
0)層をエッチングして、前記ゲルマニウム基板、ガリ
ウム砒素基板、またはインジウム燐基板を除去する。In order to solve the above-mentioned problems, in the method of manufacturing a semiconductor substrate according to the first aspect, a method of manufacturing a semiconductor substrate comprising a germanium substrate, a gallium arsenide substrate, or an indium phosphide substrate, comprising Al y Ga 1-y As ( 0.9 ≦ y ≦ 1.0) layer with mesa etch the buffer layer and the group III-V compound semiconductor layer epitaxially grown including, in x Ga 1-x as (0.05 ≦ x ≦ 0 in the silicon substrate .6) a layer is epitaxially grown, and the III-V compound semiconductor layer and the I
n x Ga 1-x As after bonding the (0.05 ≦ x ≦ 0.6) layer, the Al y Ga 1-y As ( 0.9 ≦ y ≦ 1.
0) Etch the layer to remove the germanium substrate, gallium arsenide substrate, or indium phosphide substrate.
【0014】また、上記半導体基板の製造方法では、前
記シリコン基板上のInxGa1-xAs(0.05≦x≦
0.6)層の転位密度が1×108cm-2以下であり、
かつこのシリコン基板の反りによる曲率半径が70m以
上であることが望ましい。In the method of manufacturing a semiconductor substrate, the In x Ga 1 -x As (0.05 ≦ x ≦
0.6) the dislocation density of the layer is 1 × 10 8 cm −2 or less;
In addition, it is desirable that the radius of curvature due to the warpage of the silicon substrate is 70 m or more.
【0015】また、上記半導体基板の製造方法では、前
記ゲルマニウム基板、ガリウム砒素基板、またはインジ
ウム燐基板に溝を形成して前記III-V族化合物半導体層
をエピタキシャル成長することが望ましい。In the method of manufacturing a semiconductor substrate, it is preferable that a groove is formed in the germanium substrate, the gallium arsenide substrate, or the indium phosphide substrate to epitaxially grow the III-V compound semiconductor layer.
【0016】さらに、上記半導体基板の製造方法では、
前記シリコン基板に溝を形成して前記InxGa1-xAs
(0.05≦x≦0.6)層を形成することが望まし
い。Further, in the method of manufacturing a semiconductor substrate,
Forming a groove in the silicon substrate to form the In x Ga 1-x As;
It is desirable to form a layer (0.05 ≦ x ≦ 0.6).
【0017】[0017]
【作用】上記のように製造すると、デバイスの活性層を
含む化合物半導体エピタキシャル層は、InxGa1-xA
s(0.05≦x≦0.6)層をエピタキシャル成長し
たシリコン基板に転写され、InxGa1-xAs(0.0
5≦x≦0.6)層が緩衝層として働くため、デバイス
の活性層を含む化合物半導体層に転位が導入されること
がない。When manufactured as described above, the compound semiconductor epitaxial layer including the active layer of the device becomes In x Ga 1 -x A
s (0.05 ≦ x ≦ 0.6) layer was transferred to a silicon substrate epitaxially grown, and In x Ga 1-x As (0.0
(5 ≦ x ≦ 0.6) The layer functions as a buffer layer, so that no dislocation is introduced into the compound semiconductor layer including the active layer of the device.
【0018】[0018]
【発明の実施の形態】以下、本発明の実施形態を添付図
面に基づき詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
【0019】図1は、請求項1に係る半導体基板の製造
方法の一実施形態を示す図であり、6はゲルマニウム基
板、ガリウム砒素基板、またはインジウム燐基板、7は
ガリウム砒素やインジウム燐等からなるバッファ層、8
はGaAs、AlGaAs、InAlGaP、InGa
As、InAlAs、InP、GaAsP、InAlG
aAs、またはInAlGaAsPなどのIII-V族化合
物半導体から成るデバイスの活性層を含むエピタキシャ
ル層、9はシリコン基板5にエピタキシャル成長された
InxGa1-xAs(0.05≦x≦0.6)層である。FIG. 1 is a view showing one embodiment of a method of manufacturing a semiconductor substrate according to claim 1, wherein 6 is a germanium substrate, a gallium arsenide substrate or an indium phosphorus substrate, and 7 is a gallium arsenide or indium phosphorus substrate. Buffer layer, 8
Are GaAs, AlGaAs, InAlGaP, InGa
As, InAlAs, InP, GaAsP, InAlG
an epitaxial layer including an active layer of a device made of a group III-V compound semiconductor such as aAs or InAlGaAsP; and 9, an In x Ga 1-x As epitaxially grown on a silicon substrate 5 (0.05 ≦ x ≦ 0.6) Layer.
【0020】Si基板上に、直接、GaAsなどのIII-
V族化合物半導体を成長する場合と比較して、Ge基
板、GaAs基板、InP基板には転位密度の低い(1
×10 4個cm-2以下)結晶の良好なIII-V族化合物半
導体が形成できる。また、AlAsの選択エッチング層
を挿入してバッファ層を形成できるのも基板は、Ge基
板、GaAs基板、InP基板に限定される。On a Si substrate, a GaAs or other III-
Compared to growing a group V compound semiconductor,
Plate, GaAs substrate, and InP substrate have low dislocation densities (1
× 10 FourPieces cm-2Below) III-V compound semi-crystalline with good crystallinity
Conductors can be formed. Also, a selective etching layer of AlAs
The substrate that can form the buffer layer by inserting
Plate, GaAs substrate, and InP substrate.
【0021】まず、周知のMBE法やMOCVD法等の
気相エピタキシャル法で、ゲルマニウム基板、ガリウム
砒素基板、またはインジウム燐基板6にガリウム砒素や
インジウム燐等からなるバッファ層7を成長する。First, a buffer layer 7 made of gallium arsenide, indium phosphide, or the like is grown on a germanium substrate, a gallium arsenide substrate, or an indium phosphide substrate 6 by a known vapor phase epitaxial method such as the MBE method or the MOCVD method.
【0022】その後、選択エッチング層となるAlyG
a1-yAs(0.9≦y≦1.0)層3を100〜10
00Å成長する。この膜厚は、図1(b)に示すメサ領
域の幅Wが広い程、厚く設定しないと、後に示す選択エ
ッチングが困難となる。たとえばメサ領域の幅Wが10
0μmの時は、200Å以上で選択エッチングが可能と
なる。Thereafter, Al y G serving as a selective etching layer is formed.
a 1-y As (0.9 ≦ y ≦ 1.0) layer 3 is 100 to 10
Grows $ 00. If this film thickness is not set thicker as the width W of the mesa region shown in FIG. 1B is wider, it becomes difficult to perform selective etching described later. For example, when the width W of the mesa region is 10
In the case of 0 μm, selective etching becomes possible at 200 ° or more.
【0023】選択エッチング層となるAlyGa1-yAs
(0.9≦y≦1.0)層3の成長の後、III-V族化合
物半導体から成るデバイスの活性層を含むエピタキシャ
ル層8を成長して、エピタキシャル装置から取り出す。Al y Ga 1 -y As serving as a selective etching layer
(0.9 ≦ y ≦ 1.0) After the growth of the layer 3, an epitaxial layer 8 including an active layer of a device made of a group III-V compound semiconductor is grown and taken out of the epitaxial apparatus.
【0024】その後、図1(b)に示すように、通常の
フォトリソグラフィとエッチングで幅Wを持つメサ領域
を形成する。この際、エッチングは硫酸/過酸化水素水
/水の混合液によるウエットエッチングまたは塩素ガス
のプラズマによる気相エッチングで行ない、AlyGa
1-yAs(0.9≦y≦1.0)層3の側壁が完全に露
出するまでエッチングを行なう。Thereafter, as shown in FIG. 1B, a mesa region having a width W is formed by ordinary photolithography and etching. At this time, etching is performed in the gas phase etching with plasma of wet etching or chlorine gas with a mixture of sulfuric acid / hydrogen peroxide / water, Al y Ga
The etching is performed until the side wall of the 1-y As (0.9 ≦ y ≦ 1.0) layer 3 is completely exposed.
【0025】次に、図1(c)に示すように、InxG
a1-xAs(0.05≦x≦0.6)層9がエピタキシ
ャル成長されたシリコン基板5と貼り合せ、貼り合せ面
を10〜50Paの圧力で加圧して、水素雰囲気の20
0〜500℃で30分から数時間のアニールを行なうこ
とで、貼り合せを完了する。Next, as shown in FIG. 1C, In x G
a 1-x As (0.05 ≦ x ≦ 0.6) layer 9 is bonded to the epitaxially grown silicon substrate 5, and the bonding surface is pressurized at a pressure of 10 to 50 Pa to form a hydrogen atmosphere 20 μm.
The bonding is completed by performing annealing at 0 to 500 ° C. for 30 minutes to several hours.
【0026】なお、InxGa1-xAs(0.05≦x≦
0.6)層9のシリコン基板5へのエピタキシャル成長
は、MBE法やMOCVD法による2段階成長法で行
う。つまり、850〜1000℃でシリコン基板5の表
面の自然酸化膜等を除去し、400℃前後に冷却した後
に非晶質ガリウム砒素層を100〜1000Å成膜す
る。Note that In x Ga 1 -x As (0.05 ≦ x ≦
0.6) The epitaxial growth of the layer 9 on the silicon substrate 5 is performed by a two-stage growth method by MBE or MOCVD. That is, a natural oxide film or the like on the surface of the silicon substrate 5 is removed at 850 to 1000 ° C., and after cooling to about 400 ° C., an amorphous gallium arsenide layer is formed at 100 to 1000 °.
【0027】その後、500〜600℃に昇温しInx
Ga1-xAs(0.05≦x≦0.6)層9を成長す
る。Thereafter, the temperature was raised to 500 to 600 ° C. to raise In x
A Ga 1-x As (0.05 ≦ x ≦ 0.6) layer 9 is grown.
【0028】インジウム組成が0.6より大きい場合は
単結晶薄膜を成長することができず、良好な貼り合せ強
度が得られない。つまり、InxGa1-xAs(0.05
≦x≦0.6)層9の転位密度を1ラ108cm- 2以下に
することで、良好な貼り合せ強度を得ることができる。
インジウムの組成が0.05より小さくなると、シリコ
ン基板の橇による曲率半径が70mより小さくなり、シ
リコン基板の橇が大きくなり、均一な貼り合わせができ
なくなる。When the indium composition is larger than 0.6, a single crystal thin film cannot be grown, and good bonding strength cannot be obtained. That is, In x Ga 1 -x As (0.05
≦ x ≦ 0.6) layer 9 dislocation density 1 la 10 8 cm - 2 by the following, it is possible to obtain good bonding strength.
If the composition of indium is smaller than 0.05, the radius of curvature of the silicon substrate by the sled becomes smaller than 70 m, the sled of the silicon substrate becomes large, and uniform bonding cannot be performed.
【0029】InxGa1-xAs(0.05≦x≦0.
6)層9が成長されたシリコン基板5の反りによる曲率
半径は70m以上が必要で、70mより小さい場合、貼
り合せ強度の低下やクラックの発生等が生じ、所望の半
導体基板を得ることができない。In x Ga 1 -x As (0.05 ≦ x ≦ 0.
6) The radius of curvature of the silicon substrate 5 on which the layer 9 has been grown due to the warpage must be 70 m or more. If the radius of curvature is smaller than 70 m, a decrease in bonding strength, cracks, etc. occur, and a desired semiconductor substrate cannot be obtained. .
【0030】次に、図1(d)に示すように、ふっ酸系
のエッチング液でAlyGa1-yAs(0.9≦y≦1.
0)層3を除去し、デバイスの活性層を含むエピタキシ
ャル層8をInxGa1-xAs(0.05≦x≦0.6)
層9を介してシリコン基板5に転写する。Next, as shown in FIG. 1D, Al y Ga 1 -y As (0.9 ≦ y ≦ 1.
0) Remove layer 3 and replace epitaxial layer 8 including the active layer of the device with In x Ga 1 -x As (0.05 ≦ x ≦ 0.6)
It is transferred to the silicon substrate 5 via the layer 9.
【0031】図2は、請求項3に係る半導体基板の製造
方法を示す図である。図2(a)に示すように、ゲルマ
ニウム基板、ガリウム砒素基板、またはインジウム燐基
板6にあらかじめ数十〜数百μmの溝10を形成してお
くと、図2(d)におけるAlyGa1-yAs(0.9≦
y≦1.0)層3の選択的除去を短時間にかつより均一
に行なうことができる。すなわち、エピタキシャル層8
または基板6の溝10を通してふっ酸系のエッチング液
を供給してアルミニウム砒素層3を選択的にエッチング
除去できるため、4インチ以上の大口径基板6でのエピ
タキシャル層の転写が可能となる。FIG. 2 is a diagram showing a method of manufacturing a semiconductor substrate according to claim 3. As shown in FIG. 2 (a), when the germanium substrate, a gallium arsenide substrate or formed in advance several tens to several hundreds μm grooves 10 of the indium phosphide substrate 6,, Al y Ga 1 in FIG. 2 (d) -y As (0.9 ≦
(y ≦ 1.0) The layer 3 can be selectively removed in a short time and more uniformly. That is, the epitaxial layer 8
Alternatively, the aluminum arsenic layer 3 can be selectively removed by etching by supplying a hydrofluoric acid-based etchant through the groove 10 of the substrate 6, so that the epitaxial layer can be transferred on the large-diameter substrate 6 of 4 inches or more.
【0032】図3は、請求項4に係る半導体基板の製造
方法を示す図である。図3(c)に示すように、ゲルマ
ニウム基板、ガリウム砒素基板、またはインジウム燐基
板6にあらかじめ数十〜数百μmの溝‘10を形成して
おき、かつあらかじめ溝10が形成されたシリコン基板
5にInxGa1-xAs(0.05≦x≦0.6)層9が
エピタキシャル成長された基板と貼り合せることによ
り、図3(d)におけるAlyGa1-yAs(0.9≦y
≦1.0)層3の選択的除去を短時間にかつより均一に
行なうことができる。すなわち、エピタキシャル層8ま
たは基板6の溝10を通してふっ酸系のエッチング液を
供給してアルミニウム砒素層3を選択的にエッチング除
去できるため、4インチ以上の大口径基板でのエピタキ
シャル層の転写が可能となる。FIG. 3 is a view showing a method of manufacturing a semiconductor substrate according to claim 4. As shown in FIG. 3C, a groove '10 of several tens to several hundreds μm is formed in advance on a germanium substrate, a gallium arsenide substrate, or an indium phosphide substrate 6 and a silicon substrate on which the groove 10 is formed in advance. 5 is bonded to a substrate on which an In x Ga 1-x As (0.05 ≦ x ≦ 0.6) layer 9 is epitaxially grown, thereby forming an Al y Ga 1-y As (0.9 in FIG. 3D). ≤y
.Ltoreq.1.0) The layer 3 can be selectively removed in a short time and more uniformly. That is, since the aluminum arsenic layer 3 can be selectively etched and removed by supplying a hydrofluoric acid-based etchant through the epitaxial layer 8 or the groove 10 of the substrate 6, the epitaxial layer can be transferred to a substrate having a large diameter of 4 inches or more. Becomes
【0033】[0033]
【発明の効果】以上のように、請求項1に係る半導体基
板の製造方法によれば、シリコン基板に転位欠陥の少な
いIII-V族化合物半導体エピタキシャル層が形成でき
る。これにより、機械的強度が高く、熱伝導性の良好な
シリコン基板の特徴を活かした化合物半導体レーザー、
フォトダイオード等のアレイや、化合物半導体の電界効
果トランジスター等による高速電子素子を一体化したデ
バイスを製造することができる。As described above, according to the method of manufacturing a semiconductor substrate according to the first aspect, a III-V compound semiconductor epitaxial layer having few dislocation defects can be formed on a silicon substrate. As a result, compound semiconductor lasers that utilize the characteristics of silicon substrates with high mechanical strength and good thermal conductivity,
It is possible to manufacture a device in which a high-speed electronic element such as an array of photodiodes or a compound semiconductor field-effect transistor is integrated.
【0034】また、メサ部や基板溝を通して選択エッチ
ングを行なうことができ、4インチ以上の大口径基板に
おいてもIII-V族化合物半導体エピタキシャル層を均一
にシリコン基板に転写することができる。Further, selective etching can be performed through the mesa portion and the substrate groove, and the III-V compound semiconductor epitaxial layer can be uniformly transferred to the silicon substrate even on a large-diameter substrate of 4 inches or more.
【0035】さらに、ゲルマニウム基板、ガリウム砒素
基板、またはインジウム燐基板は繰り返して使用できる
ため、素子を安価に製造することができる。Further, since a germanium substrate, a gallium arsenide substrate, or an indium phosphorus substrate can be used repeatedly, the device can be manufactured at low cost.
【図1】請求項1に係る半導体基板の一実施形態を示す
図である。FIG. 1 is a view showing one embodiment of a semiconductor substrate according to claim 1;
【図2】請求項3に係る半導体基板の製造方法の一実施
形態を示す図である。FIG. 2 is a view showing one embodiment of a method of manufacturing a semiconductor substrate according to claim 3;
【図3】請求項4に係る半導体基板の製造方法の一実施
形態を示す図である。FIG. 3 is a view showing one embodiment of a method for manufacturing a semiconductor substrate according to claim 4;
【図4】従来の半導体基板の製造方法を示す図である。FIG. 4 is a diagram showing a conventional method for manufacturing a semiconductor substrate.
1:ガリウム砒素基板、2:バッファ層、3:AlyG
a1-yAs(0.9≦y≦1.0)選択エッチング層、
4:デバイスの活性層を含むエピタキシャル層、5:シ
リコン基板、6:ゲルマニウム基板、ガリウム砒素基
板、またはインジウム燐基板、7:バッファ層、8:デ
バイスの活性層を含むエピタキシャル層、9:InxG
a1-xAs(0.05≦x≦0.6)層1: gallium arsenide substrate, 2: buffer layer, 3: Al y G
a 1-y As (0.9 ≦ y ≦ 1.0) selective etching layer,
4: Epitaxial layer including active layer of device, 5: Silicon substrate, 6: Germanium substrate, gallium arsenide substrate, or indium phosphide substrate, 7: Buffer layer, 8: Epitaxial layer including active layer of device, 9: In x G
a 1-x As (0.05 ≦ x ≦ 0.6) layer
Claims (4)
またはインジウム燐基板上にAlyGa1-yAs(0.9
≦y≦1.0)層とIII-V族化合物半導体層をエピタキ
シャル成長してメサエッチングするとともに、シリコン
基板にInxGa1-xAs(0.05≦x≦0.6)層を
エピタキシャル成長し、前記III-V族化合物半導体層と
前記InxGa1-xAs(0.05≦x≦0.6)層とを
貼り合わせた後、前記AlyGa1-yAs(0.9≦y≦
1.0)層をエッチングして、前記ゲルマニウム基板、
ガリウム砒素基板、またはインジウム燐基板を除去する
半導体基板の製造方法。A germanium substrate, a gallium arsenide substrate,
Alternatively, Al y Ga 1 -y As (0.9
≦ y ≦ 1.0) layer and with the Group III-V compound semiconductor layer is epitaxially grown to mesa etching, In x Ga 1-x As (0.05 ≦ x ≦ 0.6) layer epitaxially grown on a silicon substrate After bonding the III-V group compound semiconductor layer and the In x Ga 1-x As (0.05 ≦ x ≦ 0.6) layer, the Al y Ga 1-y As (0.9 ≦ y ≦
1.0) etching the layer, the germanium substrate,
A method for manufacturing a semiconductor substrate for removing a gallium arsenide substrate or an indium phosphorus substrate.
(0.05≦x≦0.6)層の転位密度が1×108c
m-2以下であり、かつこのシリコン基板の反りによる曲
率半径が70m以上であることを特徴とする請求項1に
記載の半導体基板の製造方法。2. In x Ga 1 -x As on said silicon substrate
(0.05 ≦ x ≦ 0.6) The dislocation density of the layer is 1 × 10 8 c
m -2 or less, and a semiconductor substrate manufacturing method according to claim 1, wherein the warp by the radius of curvature of the silicon substrate is not less than 70m.
板、またはインジウム燐基板に溝を形成して前記III-V
族化合物半導体層をエピタキシャル成長することを特徴
とする請求項1または請求項2に記載の半導体基板の製
造方法。Forming a groove in the germanium substrate, the gallium arsenide substrate, or the indium phosphorus substrate to form the III-V substrate;
3. The method according to claim 1, wherein the group III compound semiconductor layer is epitaxially grown.
nxGa1-xAs(0.05≦x≦0.6)層を形成する
ことを特徴とする請求項1ないし請求項3に記載の半導
体基板の製造方法。4. A method for forming a groove in the silicon substrate,
n x Ga 1-x As ( 0.05 ≦ x ≦ 0.6) The method of manufacturing a semiconductor substrate according to claims 1 to 3, characterized in that to form the layer.
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