JP2005108943A - Semiconductor wafer and method for manufacturing semiconductor device using same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor wafer which is equipped with a qualification for obtaining a semiconductor epitaxial film whose lifting surface has a planarity of nano order, and a method for manufacturing a semiconductor device using the semiconductor wafer. <P>SOLUTION: The semiconductor wafer 100 comprises a GaAs substrate 101 and a buffer layer 102, a lifting layer 103 formed on the substrate 101 and the layer 102, and a semiconductor epitaxial layer 104 formed on the layer 103. The thickness of the lifting layer 103 is made at least 10 nm and less than 200 nm. The method for manufacturing a semiconductor device comprises a process for preparing the semiconductor wafer, a process wherein patterning of the semiconductor epitaxial layer is performed by using an etching mask and an etching trench is formed, and a process wherein bonding of the semiconductor epitaxial film is performed on a substrate which film is obtained by etching the lifting layer and exfoliating the semiconductor epitaxial layer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor wafer having a peelable semiconductor epitaxial layer and a method for manufacturing a semiconductor device using the same.

A Ga _0.3 Al _0.7 As layer having a thickness of 5 μm is provided between the GaAs substrate and the GaAs epitaxial layer, the Ga _0.3 Al _0.7 As layer is removed by etching, and the upper GaAs epitaxial layer is removed. A technique for peeling and pasting on a different substrate has been proposed (see, for example, Non-Patent Document 1).

Kogai Makoto et al., Journal of Crystal Grouse 45 (1978), pp. 277-280, “High Efficiency GaAs Thin Film Solar Cells by Peeled Film Technology (Moonto Konagai et al., Journal of Crystal Growth 78). pp. 277-280 “High Efficiency GaAs Thin Film Solar Cells by Peeled Film Technology”)

  However, when the semiconductor epitaxial layer is peeled off by etching away the layer (peeling layer) disposed between the substrate and the semiconductor epitaxial layer, the flatness of the peeled surface depends on the thickness of the peeling layer. When the thickness of the release layer is large, the flatness of the release surface of the semiconductor epitaxial film, which is the peeled semiconductor epitaxial layer, is poor, and good adhesion cannot be obtained when pasted on a different substrate. However, it became clear from experiment of the inventors of this application.

  Therefore, the present invention has been made to solve the problems of the prior art as described above, and the object thereof is a semiconductor wafer having a condition for obtaining a semiconductor epitaxial film having a separation surface with nano-order flatness. And it is providing the manufacturing method of a semiconductor device using the same.

  The semiconductor wafer of the present invention has a substrate, a release layer formed on the substrate, and a semiconductor epitaxial layer formed on the release layer, and the thickness of the release layer is 10 nm or more and less than 200 nm. It is characterized by this.

  The method for manufacturing a semiconductor device of the present invention includes a step of preparing the semiconductor wafer, a step of patterning the semiconductor epitaxial layer with an etching mask to form an etching groove, a step of etching the release layer, And a step of bonding a semiconductor epitaxial film obtained by peeling off the semiconductor epitaxial layer onto another substrate.

  In the semiconductor wafer of the present invention, the flatness of the peeling surface of the semiconductor epitaxial film can be made extremely high by making the thickness of the peeling layer appropriate, so that when the semiconductor epitaxial film is bonded to another substrate The effect that the adhesive force can be increased is obtained.

  In addition, according to the method for manufacturing a semiconductor device of the present invention, a semiconductor epitaxial film with extremely high flatness can be bonded to another substrate, so that the semiconductor device has excellent adhesion between the semiconductor epitaxial film and the other substrate. The effect that can be obtained is obtained.

<First Embodiment>
FIG. 1 is a cross-sectional view schematically showing the configuration of a semiconductor wafer according to the first embodiment of the present invention, and FIG. 2 is a plan view schematically showing the configuration of the semiconductor wafer according to the first embodiment. It is. FIG. 1 corresponds to a surface obtained by cutting the semiconductor wafer of FIG. 2 along line S ₁ -S ₁ .

  As shown in FIG. 1, a semiconductor wafer 100 includes a GaAs substrate 101, a GaAs buffer layer 102, a release layer (sacrificial layer) 103 formed thereon, and a semiconductor epitaxial layer formed on the release layer 103. The thickness of the peeling layer 103 is set to a value within the range of 10 nm to less than 200 nm.

Semiconductor epitaxial layer 104 in this order from the release layer 103 side, n-GaAs layer (lower contact _{layer) 111, n-Al x Ga} 1-x As layer (lower cladding _{layer) 112, n-Al y Ga} 1- _This is a laminated structure in which a _y As layer (active layer) 113, a p-Al _z Ga _1-z As layer (upper cladding layer) 114, and a p-GaAs layer (upper contact layer) 115 are laminated. Here, for example, when z> y and x> y, the semiconductor epitaxial layer 104 emits light of a double hetero-epitaxial layer structure in which the n-Al _y Ga _1-y As layer (active layer) 113 is a light emitting layer. Become a diode. The constituent material and the number of layers of the semiconductor epitaxial layer 104 are not limited to the above example, and the type of semiconductor element formed in the semiconductor epitaxial layer 104 is not limited to the light emitting diode.

Further, the release layer 103 is, for example, an Al _t Ga _1-t As layer (0 ≦ t ≦ 1). The release layer 103 can be an AlAs layer. The constituent material of the release layer 103 may be selected according to the constituent material of the semiconductor epitaxial layer 104. Further, the substrate on which the release layer 103 is formed is not limited to the laminated structure of the GaAs substrate 101 and the GaAs buffer layer 102 shown in the drawing.

  Next, a procedure for peeling the semiconductor epitaxial layer 104 from the substrate will be described. FIGS. 3 to 6A and 6B are cross-sectional views (parts 1 to 5) schematically showing a peeling process of the semiconductor epitaxial layer 104. FIG.

When the semiconductor epitaxial layer 104 is peeled off, an etching mask 120 is first formed on the semiconductor epitaxial layer 104 as shown in FIG. Next, as shown in FIG. 4, an etching groove pattern 130 is formed on the etching mask 120 by, for example, a standard photolithography method. Next, as shown in FIG. 5, an etching groove 131 is formed in the semiconductor epitaxial layer 104, the release layer 103, and the GaAs buffer layer 102. In this etching groove formation, for example, sulfuric acid / hydrogen peroxide (sulfuric acid + H ₂ O ₂ + H ₂ O) or phosphoric acid / hydrogen peroxide (phosphoric acid + H ₂ O ₂ + H ₂ O) can be used. Here, although the etching groove 131 shows an etching groove reaching the GaAs buffer layer, the etching groove 131 may be formed so that at least the peeling layer is exposed. Next, the peeling layer 103 shown in FIG. 6A is etched away by being immersed in an etching solution, and the semiconductor epitaxial layer 104 is peeled from the substrate as shown in FIG. 6B.

  The peeled semiconductor epitaxial layer 104 is bonded as a semiconductor epitaxial film 104a on a dissimilar substrate (for example, directly on a Si substrate on which a driving IC circuit is formed or on a metal layer formed on a Si substrate). . In order for the bonded semiconductor epitaxial film 104a to have a good adhesion to the Si substrate, the release surface 105 of the semiconductor epitaxial film 104a needs to have high flatness. When the flatness of the peeling surface 105 of the semiconductor epitaxial film 104a is poor, the semiconductor epitaxial film 104a cannot be bonded well to the Si substrate. FIG. 7 is a diagram conceptually showing a case where undulations are formed on the peeling surface 105 of the semiconductor epitaxial film 104a, and foreign matter 202 adheres near the end of the peeling surface 105, resulting in poor flatness. In this case, as shown in FIG. 7, the semiconductor epitaxial film 104a cannot be satisfactorily bonded to the Si substrate 201.

  Next, the measurement result of the surface roughness of the peeling surface 105 of the semiconductor epitaxial film 104a will be described. The measurement was performed when the release layer 103 was an AlAs layer and the thickness of the release layer 103 was 200 nm, 100 nm, 50 nm, and 20 nm. The measurement was performed by measuring the peeling surface 105 of the semiconductor epitaxial film 104a with an AFM (atomic force microscope). The measurement results are shown in FIG. In FIG. 8, the horizontal axis indicates the thickness (nm) of the release layer 103, and the vertical axis indicates the average surface roughness Ra (nm) or the maximum surface roughness Rmax (nm) of the release surface 105. In FIG. 8, white circles indicate measurement points for average surface roughness Ra (nm), and black circles indicate measurement points for maximum surface roughness Rmax (nm). As can be seen from FIG. 8, if the thickness of the release layer 103 is 10 nm or more and less than 200 nm, the surface roughness of the release surface 105 of the semiconductor epitaxial film 104a can be suppressed to a range that can be bonded to another substrate. . However, in the case where higher flatness is required for the peeling surface 105, it is necessary to narrow the allowable thickness range of the peeling layer 103.

  As can be seen from FIG. 8, when the thickness of the release layer 103 is 50 nm, the surface roughness of the release surface 105 of the semiconductor epitaxial film 104a is minimized. Further, when the thickness of the release layer 103 is greater than 50 nm, the surface roughness of the release surface 105 of the semiconductor epitaxial film 104a increases. When the thickness of the release layer 103 is less than 50 nm, the release surface 105 of the semiconductor epitaxial film 104a is increased. The surface roughness of increases.

The reason why the surface roughness of the peeling surface 105 increases as the thickness of the peeling layer 103 increases will be described. The peeling layer 103 is in a narrow (thin) region between the buffer layer 102 and the semiconductor epitaxial layer 104 on the GaAs substrate 101, and etching of the peeling layer 103 is performed while the etching solution penetrates the narrow region where the peeling layer 103 exists. proceed. When the thickness of the release layer 103 is increased, the etching rate of the release layer 103 is decreased. There are two possible reasons for this.
1) The volume of the release layer 103 to be etched increases.
2) When the release layer 103 becomes thicker, the LED epitaxial film 104 is deformed by the gap between the LED epitaxial film 104 and the substrate due to the progress of etching of the release layer 103 (for example, the release surface 105 of the LED epitaxial film 104 is changed to the release surface of the substrate). 2), the etching solution hardly penetrates into the etching region (etching space) due to the deformation (that is, the penetration of the etching solution is hindered). When the penetration rate of the etching solution is slowed, the concentration of the component dissolved in the etching solution (Al or As when the peeling layer 103 is an AlAs layer) in the etching region increases, and the high concentration of the dissolved component is etched. The time spent in the region also becomes longer. As a result, the surface-dissolved component of the GaAs layer exposed once the peeling layer 103 is etched may be deposited or recrystallized. Since As has a lower binding energy to Ga and As compared to Al, it is considered that Al rather than As is likely to be deposited or recrystallized on the GaAs surface. Actually, qualitative analysis was performed on deposits or recrystallized materials that deteriorate the flatness of the GaAs surface. As a result, it was confirmed that the deposit or recrystallized product was Al or Al fluoride (Al-F). The cause of the confirmation of Al fluoride is considered to be that the HF solution was used as the etching solution.

  Thus, on the peeling surface (GaAs surface) 105 of the LED epitaxial film 104, Al (including HF fluoride when HF solution is used as an etching solution) is deposited or recrystallized to form a surface. The roughness is increased. In addition, the phenomenon of deposition or recrystallization on the surface is related to the etching rate of the peeling layer 103, and the phenomenon of deposition or recrystallization on the surface becomes more remarkable as the etching rate decreases (larger deposition). Region or recrystallization region).

  Next, the reason why the surface roughness of the peeling surface 105 increases as the thickness of the peeling layer 103 decreases will be described. Although the phenomenon associated with the increase in the thickness of the release layer 103 has already been described, even when the release layer 103 is very thin, the penetration space is narrowed due to the very thin thickness of the release layer 103, and etching is performed. It is thought that liquid becomes difficult to penetrate. Therefore, even when the release layer 103 becomes very thin, deposition of the release layer component dissolved in the etching solution on the LED epitaxial film 104 is similar to the phenomenon accompanying the increase in the thickness of the release layer 103 described above. Or it is thought that the phenomenon of recrystallization is accelerated | stimulated.

  As shown in FIG. 8, when the thickness T of the release layer (AlAs layer) 103 is in the range of 20 nm ≦ T ≦ 100 nm, the average surface roughness Ra is at least Ra = 0.3 nm when T = 50 nm. It is. The maximum height difference (maximum surface roughness Rmax) in the measurement region is also minimum when T = 50 nm, and Rmax = 3.4 nm. Further, if the flatness of the LED epitaxial film 104 is at least Ra = 1 nm or less and Rmax = 8 nm or less, good bonding can be performed.

Next, using data in the range of 50 nm ≦ T ≦ 100 nm, in the range of d ≧ 50 nm,
Rmax [nm]
= A × (d [nm] −50 [nm]) ² + b × (d [nm] −50 [nm]) + c
... (1)
Assuming that the range of 100 nm ≦ T ≦ 200 nm is supplemented and the data in the range of 50 nm ≦ T ≦ 100 nm is used in equation (1), a = 1.93 × 10 ⁻⁹ , b = −0.0725 , C = 3.4, and d for Rmax = 8 nm is obtained, d = 122 nm. If Rmax = 10 nm is the limit of the maximum surface roughness Rmax with some tolerance, d = 130 nm is obtained. Further, for the average surface roughness Ra, using data in the range of 50 nm ≦ T ≦ 100 nm, in the range of d ≧ 50 nm,
Ra [nm]
= A × (d [nm] −50 [nm]) ² + b × (d [nm] −50 [nm]) + c
... (2)
Assuming that the range of 100 nm ≦ T ≦ 200 nm is supplemented and the data in the range of 50 nm ≦ T ≦ 100 nm is used in equation (2), a = 1.93 × 10 ⁻⁴ , b = −5.65 × 10 ⁻³ , c = 0.3 is obtained. When d which satisfies Ra = 1.00 nm is obtained, d = 127 nm, and approximately d = 130 nm is obtained.

Furthermore, in the case where the thickness of the release layer 103 is less than 20 nm, in the range of d ≦ 50 nm,
Ra [nm] = α × (50 [nm] −d [nm]) ² + β (3)
Is extrapolated to obtain α = 4.44 × 10 ⁻⁴ , β = 0.3. Here, when d is obtained such that Ra = 1 nm, d = 10 nm is obtained. Therefore, when d is determined such that Ra = 1 nm as the lower limit of the thickness of the release layer 103, d = 10 nm is obtained. Therefore, the lower limit of the thickness of the release layer 103 can be 10 nm.

  As described above, if it is within the range of 10 nm ≦ T ≦ 130 nm, Ra is 1 nm or less or Rmax is 10 nm or less, and good bonding can be performed.

  Considering more preferable conditions, the flatness of the peeling surface 105 of the LED epitaxial film 104 is set to Ra = 0.5 nm and Rmax = 5 nm. When the thickness range of the release layer (AlAs layer) 103 such that Ra = 0.5 nm and Rmax = 5 nm is obtained, the thickness range of the release layer 103 is 30 nm ≦ T ≦ 100 nm based on the result of FIG. That's fine.

  FIG. 9 is an electron micrograph of the peeling surface of the semiconductor epitaxial film when the thickness of the peeling layer 103 is 200 nm, and FIG. 10 is an enlarged photograph of a part of FIG. FIG. 9 shows a peeled surface after the semiconductor epitaxial layer 104 is peeled with a width of 100 μm and a length of 8 mm, and FIG. 10 is an enlarged photograph of the vicinity of the end of the peeled surface. FIG. 11 is an optical micrograph of the peeled surface after peeling off the semiconductor epitaxial layer 104 with a width of 100 μm and a length of 8 mm when the thickness of the peeling layer is 50 nm. As shown in FIG. 9 and FIG. 10, when the thickness of the peeling layer 103 is 200 nm, some foreign matter is present, but when the thickness of the peeling layer 103 is 50 nm as shown in FIG. There is almost no foreign matter.

  As described above, in the semiconductor wafer 100 of the first embodiment, the flatness of the peeling surface 105 of the semiconductor epitaxial film 104a is made extremely high by setting the thickness of the peeling layer 103 within an appropriate range. Therefore, the adhesion when the semiconductor epitaxial film 104a is bonded to another substrate can be increased.

<Second Embodiment>
Next, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described. First, the semiconductor chip 100 shown in FIG. 1 (first embodiment) is prepared. Next, according to the procedure shown in FIGS. 2 to 5, the semiconductor epitaxial layer 104 is patterned using the etching mask 120 to form an etching groove 131. Next, the peeling layer 103 is etched according to the procedure shown in FIGS.

In the case where the release layer 103 is made of AlAs or an Al _x Ga _1-x As-based material, an HF (hydrofluoric acid) liquid can be used as an etching liquid. The concentration of the HF solution is usually 10%, but can be appropriately selected within a range of about 1% to 50%. When selecting the concentration of the HF solution, the upper limit value is considered in consideration of conditions such as the durability of the support that supports the LED epitaxial film 104 in the peeling step and whether the adhesion between the support and the semiconductor layer surface can be maintained. May be determined as appropriate. Further, when the concentration of the HF solution is lowered, the etching rate is lowered. However, the lower limit value of the concentration of the HF solution may be selected as appropriate based on the etching rate.

Moreover, the temperature of the etching solution can be appropriately selected within a range of about 0 ° C to 60 ° C. On the high temperature side, the reaction rate between the etchant and the release layer 103 is increased, but the foaming (H ₂ generation) accompanying the reaction impedes contact between the etchant and the release layer 103, and with thermal expansion. Since it is conceivable that the semiconductor epitaxial layer 104 is deformed in the direction in which the penetration of the etching solution is hindered, the temperature condition on the high temperature side may be selected based on the etching rate. On the low temperature side, the reaction rate decreases, but the deformation of the semiconductor epitaxial layer 104 is deformed in a direction that promotes etching, so that the etching can be increased due to this deformation. For the conditions on the low temperature side, the etching rate may be selected as a criterion.

Further, hydrochloric acid (HCl) or hydrobromic acid (HBr) can be used as an etchant instead of HF. The concentration of these etching solutions is in the range of about 1% to 30%, and the temperature is in the range of about 0 ° C to 25 ° C. When the release layer 103 is an (Al _x Ga _1-x ) _y In _1-y P layer, hydrochloric acid (concentration of about 1% to 30%, hydrochloric acid of about 0 ° C. to 25 ° C. is used as an etchant. Alternatively, an etching solution in which hydrochloric acid, phosphoric acid, and water are mixed can be used, and when the release layer 103 is AlN, hot phosphoric acid (about 50 ° C. to 100 ° C.) can be used as the etching solution. The peeling layer 103 can also be made of Al ₂ O ₃ .

  Next, the semiconductor epitaxial film 104a obtained by peeling the semiconductor epitaxial layer 104 is formed on a heterogeneous substrate (for example, directly on a Si substrate having a driving IC or a metal layer formed on the Si substrate). Bond. Thereafter, a thin film wiring layer is formed in a region from the individual operation region (light emitting portion) of the semiconductor epitaxial film 104a to the substrate. FIG. 12 is a schematic perspective view showing a part of the semiconductor device manufactured by the above steps. In FIG. 12, 201 is a Si substrate, 211 is a metal layer, 212 is an individual wiring layer (thin film wiring), and 213 is a drive IC formed in the Si substrate.

  As described above, according to the manufacturing method of the semiconductor device of the second embodiment, the semiconductor epitaxial film 104a having extremely high flatness can be bonded to the substrate, so that the semiconductor epitaxial film 10a and the substrate 201 are in close contact with each other. A semiconductor device with excellent strength can be obtained.

<Third Embodiment>
FIG. 13 is a cross-sectional view schematically showing a semiconductor wafer according to the third embodiment of the present invention.

  As shown in FIG. 13, the semiconductor wafer 300 includes a GaAs substrate 301, a release layer (sacrificial layer) 303 formed thereon, and a semiconductor epitaxial layer 304 formed on the release layer 303. The thickness of the release layer is set to a value in the range of 10 nm or more and less than 200 nm.

The semiconductor epitaxial layer 304 includes, for example, an n-GaAs layer (lower contact layer) 311, an n-Al _x Ga _1-x As layer (lower clad layer) 312, and n-Al _y Ga in order from the release layer 303 side. A stacked structure in which a _1-y As layer (active layer) 313, a p-Al _z Ga _1-z As layer (upper cladding layer) 314, and a p-GaAs layer (upper contact layer) 315 is stacked. it can. For example, when z> y and x> y, the semiconductor epitaxial layer 304 emits light of a double hetero-epitaxial layer structure in which the n-Al _y Ga _1-y As layer (active layer) 313 is a light emitting layer. Become a diode.

The release layer 303 is an Al _t Ga _1-t As layer (x <t <1). The release layer 303 is, for example, an Al _0.95 Ga _0.05 As layer. The constituent material and the number of layers of the semiconductor epitaxial layer 304 are not limited to the above example, and the type of the semiconductor element formed in the semiconductor epitaxial layer 304 is not limited to the light emitting diode. Further, the substrate on which the release layer 303 is formed is not limited to the illustrated GaAs substrate 301.

  Also in the case of the third embodiment, the same reaction as in the first embodiment occurs when the release layer 303 is etched, so that the same effect as in the first embodiment can be obtained. In the third embodiment, the points other than the above are the same as in the case of the first embodiment. Further, the semiconductor wafer 300 can be used in the manufacturing method of the second embodiment.

<Fourth Embodiment>
FIG. 14 is a cross-sectional view schematically showing a semiconductor wafer according to the fourth embodiment of the present invention.

  As shown in FIG. 14, a semiconductor wafer 400 includes a GaAs substrate 401, a GaAs buffer layer 402, a release layer (sacrificial layer) 403 formed thereon, and a semiconductor epitaxial layer formed on the release layer 403. 404, and the thickness of the release layer is in the range of 10 nm or more and less than 200 nm.

The release layer 403 is, for example, an AlAs layer. The semiconductor epitaxial layer 404, the peeling layer 403 _{side, n- (Al x Ga 1-} x) y In 1-y P layer 411, for _{example, n- (Al x Ga 1-} x) 0.51 In 0 _.49 P layer included. Although the upper layer of the n- (Al _x Ga _1-x ) _y In _1-y P layer 411 is not particularly limited, for example, a structure including a semiconductor element such as a light emitting diode is used. Further, the substrate on which the release layer 403 is formed is not limited to the illustrated one.

  Also in the case of the fourth embodiment, the same reaction as in the first embodiment occurs when the release layer 403 is etched, so that the same effect as in the first embodiment is obtained. In the fourth embodiment, points other than those described above are the same as in the case of the first embodiment. Further, the semiconductor wafer 400 can be used in the manufacturing method of the second embodiment.

<Other variations>
Incidentally, it is possible to make the release layer between the substrate and the semiconductor epitaxial layer _{(Al x Ga 1-x)} y In 1-y P layer. In this case, the release layer can be etched with hydrochloric acid (for example, room temperature) or a mixed solution of hydrochloric acid, phosphoric acid, and water (for example, 30 ° C.). Also in this case, the peeling layer can be selectively removed by etching without almost etching the semiconductor substrate or the semiconductor epitaxial layer.

  Also, when a III-IV group nitride material such as GaN, InGaN, AlGaN, AlInN is used as the semiconductor thin film layer, an AlN layer is provided as a peeling layer between the semiconductor thin film layer and the substrate. It can be removed by etching with hot phosphoric acid (eg, 80 ° C.). Also in this case, the peeling layer can be selectively removed by etching without almost etching the semiconductor substrate or the semiconductor epitaxial layer.

In the description of the above embodiment, the example in which the semiconductor epitaxial layer is peeled off before providing the element in the semiconductor epitaxial film has been described as a specific example. However, after the element is formed in the semiconductor epitaxial layer, the semiconductor epitaxial layer is peeled off. Also, the present invention can be applied. For example, the semiconductor epitaxial layer is formed as n-type GaAs / n-type Al _x Ga _1-x As / n-type Al _y Ga _1-y As / n-type Al _z Ga _1-z As / n-type GaAs in order from the bottom. As described in the first embodiment, Zn diffusion is performed so that the diffusion front reaches the active layer (n-type Al _y Ga _1-y As) to form an LED array (arrangement of pn junctions). Similar to the method, the semiconductor epitaxial layer can be peeled off.

  Further, the heterogeneous substrate for bonding the semiconductor epitaxial layer may not be the Si substrate. For example, a glass substrate, a metal substrate, a ceramic substrate, etc. may be used. Bonding of the semiconductor epitaxial layer on the different substrate may be performed directly on the surface of the substrate, or a metal layer, an insulating film layer, or the like may be provided on the substrate and bonded thereto.

1 is a cross-sectional view schematically showing a configuration of a semiconductor wafer according to a first embodiment of the present invention. 1 is a plan view schematically showing a configuration of a semiconductor wafer according to a first embodiment. It is sectional drawing (the 1) which shows schematically the process of peeling a semiconductor epitaxial layer from the semiconductor wafer which concerns on 1st Embodiment. It is sectional drawing (the 2) which shows schematically the process of peeling a semiconductor epitaxial layer from the semiconductor wafer which concerns on 1st Embodiment. It is sectional drawing (the 3) which shows schematically the process of peeling a semiconductor epitaxial layer from the semiconductor wafer which concerns on 1st Embodiment. (A) And (b) is sectional drawing (the 4 and 5) which shows schematically the process of peeling a semiconductor epitaxial layer from the semiconductor wafer which concerns on 1st Embodiment. It is a figure which shows a bonding state in case the joint surface of the semiconductor epitaxial film peeled from the semiconductor wafer is a rough state. It is a graph which shows the measurement result of the surface roughness of the semiconductor epitaxial film peeled from the semiconductor wafer which concerns on 1st Embodiment. It is an electron micrograph of the peeling surface of a semiconductor epitaxial film in case the thickness of a peeling layer is 200 nm. 10 is an enlarged photograph of a part of FIG. 9. It is an optical microscope photograph of the peeling surface of a semiconductor epitaxial film in case the thickness of a peeling layer is 50 nm. It is a schematic perspective view which shows a part of semiconductor device manufactured by the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows roughly the structure of the semiconductor wafer which concerns on the modification of the 3rd Embodiment of this invention. It is sectional drawing which shows schematically the structure of the semiconductor wafer which concerns on the 4th Embodiment of this invention.

Explanation of symbols

100, 300, 400 semiconductor wafer,
101, 301, 401 GaAs substrate,
102, 402 GaAs buffer layer,
103,303,403 release layer,
104, 304, 404 Semiconductor epitaxial layer,
104a Semiconductor epitaxial film (peeled semiconductor epitaxial layer),
105 peeling surface of the semiconductor epitaxial film,
111, 311, 411 Lower contact layer,
112 lower cladding layer,
113 active layer,
114 upper cladding layer,
115 upper contact layer,
120 etching mask,
130 Etching groove pattern of etching mask,
131 Etch grooves of LED epitaxial layer and release layer,
200 semiconductor devices,
201 heterogeneous substrates,
202 Foreign matter,
211 metal layer,
212 Individual wiring layer (thin film wiring),
213 Drive IC formed in the Si substrate.

Claims (15)

A substrate,
A release layer formed on the substrate;
A semiconductor epitaxial layer formed on the release layer;
A semiconductor wafer, wherein a thickness of the release layer is 10 nm or more and less than 200 nm.   The semiconductor wafer according to claim 1, wherein a thickness of the release layer is 10 nm or more and 130 nm or less.   The semiconductor wafer according to claim 2, wherein the release layer has a thickness of 30 nm to 100 nm.   The semiconductor wafer according to claim 1, wherein the substrate includes a GaAs substrate.   5. The semiconductor wafer according to claim 1, wherein the substrate includes a GaAs buffer layer in contact with the release layer. The semiconductor wafer according to claim 1, wherein the release layer is an Al _t Ga _1-t As layer (0 ≦ t ≦ 1).   The semiconductor wafer according to claim 6, wherein the release layer is an AlAs layer. The semiconductor wafer according to claim 1, wherein the release layer is an (Al _x Ga _1-x ) _y In _1-y P layer.   The semiconductor wafer according to claim 1, wherein the release layer is an AlN layer. The semiconductor wafer according to claim 1, wherein the release layer is an Al ₂ O ₃ layer. The semiconductor wafer according to claim 1, wherein the semiconductor epitaxial layer includes an Al _x Ga _1-x As layer (0 ≦ x ≦ 0.4) in contact with the release layer. The semiconductor wafer according to claim 11, wherein the Al _x Ga _1-x As layer is a GaAs layer.   The semiconductor wafer according to claim 9, wherein the semiconductor epitaxial layer is made of a group III-IV nitride material. Preparing a semiconductor wafer according to any one of claims 1 to 13;
Patterning the semiconductor epitaxial layer with an etching mask to form an etching groove;
Etching the release layer;
Bonding the semiconductor epitaxial film obtained by peeling the semiconductor epitaxial layer onto another substrate. 15. The method of manufacturing a semiconductor device according to claim 14, further comprising a step of forming a thin film wiring layer in a region from the semiconductor epitaxial film after bonding to the other substrate.

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