JP2011049565A - Method of manufacturing semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a high-reliability semiconductor substrate without causing damage of a compound semiconductor layer or transition of a crystal by influence due to natural oxidation in etching a selection etching layer. <P>SOLUTION: The method of manufacturing a high-reliability semiconductor substrate includes: a lamination step of sequentially laminating, on a compound semiconductor substrate 8 by an epitaxial growth method, a selection etching layer 3, a stress relaxing layer 9 and a compound semiconductor layer 4 having Young's modulus larger than that of the stress relaxing layer 9 and formed of a group III-V compound semiconductor; an etching step of etching and removing the selection etching layer 3, the stress relaxing layer 9 and the compound semiconductor layer 4 to be formed into a predetermined pattern; a joining step of sticking the compound semiconductor substrate 8 with the selection etching layer 3, the stress relaxing layer 9 and the compound semiconductor layer 4 laminated thereon by joining the upper surface of the compound semiconductor layer 4 to a principal surface of a Si substrate 5 by a direct joining method; and a separation step of separating the Si substrate 5 from the compound semiconductor substrate 8 by further etching and removing the selection etching layer 3 left in the etching step. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor substrate in which a compound semiconductor layer is stacked on a silicon (Si) substrate and a semiconductor substrate, and more particularly, to a method for manufacturing a semiconductor substrate and a semiconductor for manufacturing a semiconductor substrate by transferring a compound semiconductor layer onto a silicon substrate. Regarding the substrate.

  Conventionally, compound semiconductor substrates such as gallium arsenide (GaAs) and indium phosphide (InP) are mechanically fragile, difficult to handle, and difficult to obtain a high-quality, large-area crystal substrate. A method of epitaxially growing a compound semiconductor layer such as gallium arsenide on a high-strength Si substrate has been proposed. A semiconductor substrate formed by forming a compound semiconductor layer on such a Si substrate includes a Si device that can be formed by VLSI technology, a high-speed and low-power consumption electronic device using a compound semiconductor, a light emitting diode (LED), and a semiconductor laser. It has been attracting attention as a technology that can be integrated with compound semiconductor devices such as (LD).

However, when a compound semiconductor such as GaAs is epitaxially grown on a Si substrate, it is difficult to form a compound semiconductor device having good characteristics. This is because crystal defects of 1 × 10 ⁶ cm ⁻² or more are generated on the surface of the epitaxial layer due to the difference in lattice constant and thermal expansion coefficient between the Si substrate and the compound semiconductor epitaxial layer. Due to the crystal defects, the compound semiconductor device formed on the Si substrate has a significant decrease in electrical characteristics, light emission characteristics in the case of a light emitting element, light reception characteristics in the case of a light receiving element, and reliability.

  Therefore, as a method for forming a compound semiconductor layer with few defects on a Si substrate, a method is disclosed in which the surfaces of the Si substrate and the compound semiconductor layer formed on the compound semiconductor substrate are directly bonded to each other to bond different types of substrates. (Conventional Example 1; Japanese Patent Laid-Open No. 6-90061, Conventional Example 2; Japanese Patent Laid-Open No. 9-63951).

  A technique for transferring a compound semiconductor layer formed on a compound semiconductor substrate described in the above-mentioned conventional example 1 to a Si substrate will be described with reference to FIG. First, as shown in FIG. 2A, a buffer layer 12 made of GaAs is formed on a GaAs substrate 11 by 0.1-2 μm using MBE (Molecular Beam Epitaxy) method or MOCVD (Metal Organic Chemical Vapor Deposition) method. Next, a GaAlAs layer 13 is grown as a selective etching layer by about 1000 mm, and an epitaxial layer 14 including an active layer of the device is grown.

  Next, as shown in FIG. 4B, the Si substrate 15 is bonded onto the epitaxial layer 14, and directly bonded and bonded by annealing in hydrogen gas.

  Finally, as shown in FIG. 3C, the GaAlAs layer 13 is etched with a hydrofluoric acid-based etchant such as HF. Thereby, the epitaxial layer 14 including the active layer can be transferred onto the Si substrate 15. However, in such a manufacturing method, after the GaAlAs layer 13 is etched, natural oxidation of the GaAlAs layer 13 occurs immediately, and the GaAlAs layer 13 contracts by about 3%, thereby giving damage to the active layer.

  A technique for transferring the compound semiconductor layer formed on the compound semiconductor substrate described in the above-mentioned conventional example 2 to the Si substrate will be described with reference to FIG. In FIG. 4, the same reference numerals are assigned to layers made of the same material as in FIG. 3. First, as shown in FIG. 4A, an AlGaAs layer 13 and a seed crystal adhesive layer 16 made of GaAs are sequentially grown on the GaAs substrate 11 by MBE or MOCVD, and then the adhesive layer 16 is formed. A part is removed by etching.

  Next, as shown in FIG. 4B, the upper surface of the adhesive layer 16 is brought into contact with the main surface of the Si substrate 15 and heated and directly adhered thereto, and then the AlGaAs layer as shown in FIG. Only 13 is removed by etching.

Finally, as shown in FIG. 4D, an SiO ₂ film 17 is formed on the Si substrate 15 so that only the upper surface of the adhesive layer 16 is exposed, and an active layer of the device is formed on the exposed surface of the adhesive layer 16. An epitaxial layer 14 made of a compound semiconductor is grown by MBE or MOCVD.

JP-A-6-90061 JP-A-9-63951

  However, in the above technique described in the conventional example 1, after the Si substrate 15 is bonded, the epitaxial layer 14 of the compound semiconductor is transferred from the GaAs substrate 11 by the lift-off method, but GaAlAs as a selective etching layer is used. It is necessary to remove the layer 13 by wet etching, and this etching rate becomes extremely small as the wraparound distance of the etching solution to the remaining portion of the GaAlAs layer 13 increases. Therefore, the bonding of the GaAs substrate 11 and Si substrate 15 having a size of several centimeters square is actually a limit, limited by the wraparound distance that can be etched, and transfer to a large-diameter substrate of 4 inches or 6 inches is not possible. There was a problem that it was practically impossible.

  Further, when the GaAlAs layer 13 is etched or when the GaAs substrate 11 and the Si substrate 15 are bonded together, the GaAlAs layer 13 contracts by about 3% due to natural oxidation to damage the active layer of the device, New crystal dislocations occurred. These crystal defects have caused a problem that the light receiving and emitting characteristics and reliability of device parts such as a semiconductor laser (LD) part and a photodiode (PD) part made of a compound semiconductor are deteriorated.

  In the technique described in Conventional Example 2, only the AlGaAs layer 13 is removed by etching, and then the epitaxial layer 14 is grown again by a high-cost MBE method or MOCVD method. Therefore, a semiconductor substrate and a semiconductor element obtained therefrom are obtained. It was expensive, and the productivity was lowered and the production yield was likely to be lowered.

  Accordingly, the present invention has been completed in view of the above problems, and its object is not to damage the active layer or generate new crystal dislocations in the manufacturing process, and as a result, LD, PD, etc. It is possible to maintain the light emitting and receiving characteristics and reliability of the device portion, to manufacture the semiconductor substrate at low cost, and to improve the productivity.

In the method for producing a semiconductor substrate of the present invention, a compound semiconductor layer comprising a selective etching layer, a stress relaxation layer, and a III-V group compound semiconductor having a Young's modulus larger than the stress relaxation layer is sequentially formed on the compound semiconductor substrate by an epitaxial growth method. A stacking step of stacking, an etching step of etching and removing the selective etching layer, the stress relaxation layer, and the compound semiconductor layer so as to have a predetermined pattern; and a method of directly bonding the upper surface of the compound semiconductor layer to the main surface of the Si substrate By bonding, the bonding step of bonding the compound semiconductor substrate on which the selective etching layer, the stress relaxation layer, and the compound semiconductor layer are stacked, and the selective etching layer remaining in the etching step are removed by etching. , A separation step of separating the Si substrate and the compound semiconductor substrate Characterized by comprising a.

  In the present invention, the stress relaxation layer blocks the influence of natural oxidation during etching of the selective etching layer due to the above configuration. Therefore, damage to the compound semiconductor layer and crystal transition in the manufacturing process do not occur, and a highly reliable material can be manufactured.

  The present invention suppresses the progress of the natural oxidation of the selective etching layer and removes only the selective etching layer by the above structure, thereby transferring the compound semiconductor layer including the active layer having a good crystallinity onto the Si substrate. It has the effect that it can be done.

  In the method for manufacturing a semiconductor substrate according to the present invention, the compound semiconductor substrate is made of a Ge substrate or a GaAs substrate, and the selective etching layer is made of AlGaAs.

  Furthermore, in the method for manufacturing a semiconductor substrate of the present invention, in the above configuration, the stress relaxation layer is made of InGaAs.

  In the method of manufacturing a semiconductor substrate according to the present invention, the compound semiconductor layer is made of an InP substrate and the selective etching layer is made of AlGaAs.

  Furthermore, the semiconductor substrate manufacturing method of the present invention is made of InGaAs in the above configuration.

  Moreover, the manufacturing method of the semiconductor substrate of this invention comprises the process of forming a groove | channel in the main surface on which the said selective etching layer of the said compound semiconductor substrate is laminated | stacked in the said lamination process.

  According to the present invention, when the selective etching layer is removed by etching in the separation step, the etching solution spreads over the entire surface of the compound semiconductor substrate.

  The present invention provides a stacking step of sequentially stacking a compound semiconductor layer comprising a selective etching layer, a stress relaxation layer and a III-V group compound semiconductor having a Young's modulus larger than the stress relaxation layer on a compound semiconductor substrate by an epitaxial growth method; Etching and removing the selective etching layer, the stress relaxation layer and the compound semiconductor layer so as to form a predetermined pattern, and bonding the upper surface of the compound semiconductor layer to the main surface of the Si substrate by a direct bonding method, A bonding step of bonding the compound semiconductor substrate on which the selective etching layer, the stress relaxation layer, and the compound semiconductor layer are laminated; and removing the selective etching layer remaining in the etching step by etching to remove the Si substrate and the A separation step of separating the compound semiconductor substrate; Affected by natural oxidation during etching selective etching layer is blocked by the stress relaxation layer. Therefore, damage to the compound semiconductor layer and crystal transition in the manufacturing process do not occur, and a highly reliable material can be manufactured.

  In addition, since an epitaxial layer of III-V compound semiconductor with few dislocations and defects can be formed on the Si substrate, LD and photodiode (PD) utilizing the characteristics of Si substrate with high mechanical strength and good thermal conductivity A device in which an array, a light emitting diode (LED) array, a compound semiconductor field effect transistor (FET), or the like is integrated with a Si LSI can be manufactured.

Furthermore, the growth of each layer by the MBE method or the MOCVD method, which is costly and has a large environmental load, is only once, and the compound semiconductor layer and the stress relaxation layer are transferred to the Si substrate,
Since the remaining compound semiconductor substrate can be used repeatedly, the semiconductor element can be efficiently manufactured at low cost.

  Further, the present invention includes a step of forming a groove in a main surface on which the selective etching layer of the compound semiconductor substrate is laminated in the stacking step, so that the selective etching layer is formed in the separation step. When the etching is removed, the etching solution spreads over the entire surface of the compound semiconductor substrate.

(A)-(d) shows each manufacturing process of the semiconductor substrate of this invention, and is sectional drawing of a semiconductor substrate, respectively. 1A and 1B show an embodiment of a semiconductor substrate according to the present invention, in which FIG. 1A is a cross-sectional view showing a state having a buffer layer before etching, and FIG. 2B is a cross-sectional view showing a state in which the contact layer is exposed by etching the buffer layer. (A)-(c) shows each manufacturing process of the conventional semiconductor substrate, and is sectional drawing of a semiconductor substrate, respectively. (A)-(d) shows each manufacturing process of the conventional semiconductor substrate, and is sectional drawing of a semiconductor substrate, respectively.

Hereinafter, embodiments of a method for manufacturing a semiconductor substrate of the present invention will be described in detail below. FIG. 1 is a diagram showing an embodiment of a manufacturing method of the present invention, and a case where a compound semiconductor substrate is made of Ge or GaAs will be described. In the figure, 8 is a Ge or GaAs compound semiconductor substrate, 2 is a GaAs buffer layer, 3 is an Al _x Ga _1-x As (0.9 ≦ x ≦ 1) layer having a thickness of preferably 500 mm or less, 9 is A buffer layer including an In _y Ga _1-y As layer (0.05 ≦ y ≦ 0.6), 4 is a compound semiconductor layer including an active layer of a device made of a III-V group compound semiconductor such as GaAs, AlGaAs, InGaAs, etc. (Epitaxial layer) 5 is a Si substrate.

In the present invention, compared to the case where a III-V compound semiconductor such as GaAs is directly grown on the Si substrate 5, the dislocation density is 1 × 10 ⁴ cm ⁻ on the Ge substrate, GaAs substrate, and InP substrate. ^A group III-V compound semiconductor having a crystallinity as low as ² or less can be formed. Further, substrates that can be satisfactorily epitaxially grown by forming a selective etching layer of Al _x Ga _1-x As (0.9 ≦ x ≦ 1) are limited to Ge substrates, GaAs substrates, and InP substrates.

  The manufacturing method of the present invention will be specifically described. First, the GaAs buffer layer 2 is grown on the compound semiconductor substrate 8 made of Ge or GaAs by a well-known vapor phase epitaxial method such as MBE method or MOCVD method.

  The thickness of the GaAs buffer layer 2 is preferably 100 to 2 μm. If the thickness is less than 100 μm, dislocations and the like are likely to enter the compound semiconductor layer 4 including the active layer of the device. If it exceeds 2 μm, the thickness becomes excessive and the cost increases.

Thereafter, an Al _x Ga _1-x As (0.9 ≦ x ≦ 1) layer 3 to be a selective etching layer is grown to a thickness of 500 mm or less by a vapor phase epitaxial method, and then an In _y Ga _1-y As layer is formed. The buffer layer 9 including (0.05 ≦ y ≦ 0.6) and the compound semiconductor layer 4 including the active layer of the device are continuously grown in the vapor phase epitaxial growth apparatus and then taken out from the vapor phase epitaxial growth apparatus. The film thickness of the Al _x Ga _1-x As layer 3, when thicker than 500 Å, Al _x Ga natural oxidation of _1-x As layer 3 progresses very quickly, Al _x Ga _1-x As layer 3, a compound semiconductor layer 4. When the buffer layer 9 is etched, the rapid natural oxidation of the Al _x Ga _1-x As layer 3 is liable to damage the active layer.

Note that 0.9 ≦ x ≦ 1 with respect to the Al _x Ga _1-x As layer 3 is that when x <0.9, the Al _x Ga _1-x As layer 3 with hydrofluoric acid in FIG. The etching rate becomes slow, and there is a tendency that good selective etching cannot be performed as distinguished from other compound semiconductor layers.

In addition, the In _y Ga _1-y As layer was set to 0.05 ≦ y ≦ 0.6 when y <0.05, the stress due to the natural oxidation during the etching of the Al _x Ga _1-x As layer 3. It becomes easy to damage the compound semiconductor layer 4 and to newly generate dislocations. This is because when 0.6 <y, a single crystal layer cannot be formed when the Al _x Ga _1-x As layer 3 is formed, and good crystallinity cannot be obtained.

The thickness of the In _y Ga _1-y As layer is preferably, for example, 0.1 to 0.2 μm when y = 0.2, and less than 0.1 μm is insufficient to relieve the stress. When the thickness exceeds 2 μm, it is difficult to obtain good crystallinity when formed on the Al _x Ga _1-x As layer 3.

  The thickness of the compound semiconductor layer 4 is not particularly limited, but is generally about 0.5 μm to 1 μm.

The buffer layer 9 including the In _y Ga _{1 -y} As layer generally has a configuration in which a GaAs layer, an In _y Ga _{1 -y} As layer, and a GaAs layer are sequentially stacked.

  Specifically, the compound semiconductor layer 4 has a layer configuration in which an n-type (n-) GaAs cladding layer, an n-AlGaAs active layer, a p-type (p-) GaAs cladding layer, and a GaAs adhesion layer are sequentially stacked, or For example, the n-GaAs cladding layer, the n-AlGaAs layer, the GaAs active layer, the p-AlGaAs cladding layer, and the GaAs adhesion layer are sequentially stacked.

Thereafter, as shown in FIG. 1B, the Al _x Ga _1-x As layer 3 and the compound semiconductor layer 4 are removed by etching so as to form a predetermined pattern by photolithography and etching, and a mesa-shaped region is formed. Form. At this time, the etching is performed by wet etching using a mixed solution of sulfuric acid, hydrogen peroxide water, and water, or vapor phase etching using plasma of a chlorine-based gas, and at least a part of the end face of the Al _x Ga _1-x As layer 3 is formed. Etching is preferably performed until the entire end face is exposed.

  Next, as shown in FIG. 1C, the adhesive layer of the compound semiconductor layer 4 of the compound semiconductor substrate 8 is bonded to a predetermined region of the main surface of the Si substrate 5, and a pressure of 10 to 50 Pa is applied to the bonding surface. By applying pressure in the manner described above and annealing in a hydrogen atmosphere at 200 to 500 ° C. for 30 minutes to several hours, direct bonding is performed to complete the bonding.

Since the In _y Ga _{1 -y} As layer has a Young's modulus smaller than that of GaAs or the like, the buffer layer 9 including the In _y Ga _{1 -y} As layer is formed of Al _x Ga _{1 -x} at the time of bonding or the like. It functions to alleviate the occurrence of stress in the compound semiconductor layer 4 due to the natural oxidation of the As layer 3. For this reason, the stress due to the natural oxidation of the Al _x Ga _1-x As layer 3 does not damage the compound semiconductor layer 4 including the active layer of the device or cause new dislocations in the compound semiconductor layer 4.

Next, as shown in FIG. 1D, the Al _x Ga _1-x As layer 3 is removed with a hydrofluoric acid-based etchant, and the compound semiconductor layer 4 including the active layer of the device is transferred to the Si substrate 5. . In this case, in order to selectively remove the Al _x Ga _1-x As layer 3 uniformly in a short time, a depth of about 10 μm to 300 μm is previously formed on the main surface of the compound semiconductor substrate 8 on which the buffer layer 2 is laminated. It is preferable to form a groove having a length of about 10 μm to 30 μm. More preferably, a groove is formed in a portion of the main surface of the compound semiconductor substrate 8 on which the buffer layer 2 is stacked, immediately below the pattern of the Al _x Ga _1-x As layer 3. The pattern shape of the groove is not particularly specified, but it is preferably formed uniformly on the main surface or a part of the compound semiconductor substrate 8 on which the buffer layer 2 is laminated.

In the manufacturing method of the present invention, when the compound semiconductor substrate 8 is an InP substrate, the GaAs buffer layer 2 is an InP buffer layer, the Al _x Ga _1-x As layer 3 is an Al _x Ga _1-x As layer, and Al _x Ga. _1-x AsP layer or the like, and the In _y Ga _1-y As layer is an InGaAs layer. The preferred thickness of each of these layers and the layer structure of the buffer layer 9 and the compound semiconductor layer 4 are the same as those described above. However, the active layer of the compound semiconductor layer 4 is InGaAs, InAlAs, InAlGaP, InP, GaAsP, InAlGaAs, InAlGaAsP, or the like.

A semiconductor substrate obtained by the manufacturing method of the present invention is shown in FIG. As shown in FIG. 2B, in a predetermined region on the Si substrate 5, a compound semiconductor layer 4 including an active layer, n-In _y Ga _1-y As (0.05 ≦ y ≦ 0.5 μm or less) is formed. A contact layer 10 made of 0.6) is laminated.

In the semiconductor substrate in the state of FIG. 2A after the process shown in FIG. 1, the buffer layer 9 including the In _y Ga _1-y As layer is mixed with a photolithographic method, potassium ferrocyanide and potassium ferricyanide. The In _y Ga _1-y As layer (the contact layer 10 made of n-In _y Ga _1-y As) is etched by wet etching using a liquid until it is exposed.

In the semiconductor substrate manufactured in this way, the dislocation density of the compound semiconductor layer 4 including the p-type active layer or the n-type active layer is as low as 1 × 10 ⁴ cm ⁻² or less, and the compound semiconductor layer 4 is formed on the Si substrate 5. Compared with the case where the contact layer 10 is directly grown, it is easy to increase the resistance of the buffer layer, and the electrical isolation of the light emitting part such as the LD including the active layer can be easily achieved.

2: Buffer layer 3: Al _x Ga _1-x As layer 4: Compound semiconductor layer 5: Si substrate 8: Compound semiconductor substrate 9: Buffer layer including In _y Ga _1-y As layer 10: n-In _y Ga _{1 -y} As contact layer

Claims (6)

A stacking step of sequentially stacking a compound semiconductor layer made of a III-V group compound semiconductor having a Young's modulus larger than the selective etching layer, the stress relaxation layer, and the stress relaxation layer on the compound semiconductor substrate by an epitaxial growth method;
An etching step of etching and removing the selective etching layer, the stress relaxation layer, and the compound semiconductor layer to have a predetermined pattern;
A bonding step of bonding the upper surface of the compound semiconductor layer to the main surface of the Si substrate by a direct bonding method, and bonding the compound semiconductor substrate on which the selective etching layer, the stress relaxation layer, and the compound semiconductor layer are laminated;
A method for manufacturing a semiconductor substrate, comprising: a separation step of separating the Si substrate and the compound semiconductor substrate by further etching away the selective etching layer remaining in the etching step.   2. The method of manufacturing a semiconductor substrate according to claim 1, wherein the compound semiconductor substrate is made of a Ge substrate or a GaAs substrate, and the selective etching layer is made of AlGaAs.   3. The method of manufacturing a semiconductor substrate according to claim 2, wherein the stress relaxation layer is made of InGaAs.   2. The method of manufacturing a semiconductor substrate according to claim 1, wherein the compound semiconductor layer is made of an InP substrate, and the selective etching layer is made of AlGaAs.   5. The method of manufacturing a semiconductor substrate according to claim 4, wherein the stress relaxation layer is made of InGaAs. The method for manufacturing a semiconductor substrate according to claim 1, wherein the stacking step includes a step of forming a groove in a main surface on which the selective etching layer of the compound semiconductor substrate is stacked.

Images