JP5946333B2 - Group III nitride semiconductor device and manufacturing method thereof - Google Patents

Group III nitride semiconductor device and manufacturing method thereof Download PDF

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JP5946333B2
JP5946333B2 JP2012130296A JP2012130296A JP5946333B2 JP 5946333 B2 JP5946333 B2 JP 5946333B2 JP 2012130296 A JP2012130296 A JP 2012130296A JP 2012130296 A JP2012130296 A JP 2012130296A JP 5946333 B2 JP5946333 B2 JP 5946333B2
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nitride semiconductor
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iii nitride
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JP2013254876A (en
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近藤 俊行
俊行 近藤
司 北野
司 北野
宏一 難波江
宏一 難波江
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エルシード株式会社
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Description

  The present invention relates to a group III nitride semiconductor device and a method for manufacturing the same.

  Conventionally, an LED element in which a GaN-based semiconductor layer is formed on a SiC substrate is known (for example, see Patent Document 1). In this LED element, a fluorescent SiC substrate having a first SiC layer doped with B and N and a second SiC layer doped with Al and N is used, and near-ultraviolet light is emitted from the multiple quantum well active layer. Near-ultraviolet light is absorbed by the first SiC layer and the second SiC layer, and is converted from green to red visible light by the first SiC layer, and from blue to red visible light by the second SiC layer. As a result, white light close to sunlight is emitted from the fluorescent SiC substrate.

  However, in this LED element, the dislocation density of the GaN-based semiconductor layer increases due to the lattice mismatch and the difference in thermal expansion coefficient between the SiC substrate and the GaN-based semiconductor layer. As a result, there is a problem that it is difficult to increase the thickness and resistance of the GaN-based semiconductor layer.

  A method of forming a nanocolumn by etching a GaN film using a metal and dielectric nanomask after forming a GaN film on the substrate by MOCVD via a buffer layer in order to reduce the dislocation density of the semiconductor layer on the substrate Has been proposed (see, for example, Patent Document 2). According to this method, after the nanocolumn is formed, the GaN-based semiconductor layer is grown on the buffer layer and the nanocolumn using lateral growth.

  However, in the method described in Patent Document 2, the U-GaN film formed on the substrate still has a high dislocation density, and the nanocolumn itself formed by etching the U-GaN film also has a high dislocation density. As a result, dislocations propagate to the GaN-based semiconductor layer formed on the nanocolumn, and the effect of reducing the dislocation density in the GaN-based semiconductor layer is insufficient.

  Further, it has been proposed that a selective growth mask having a large number of patterned openings is arranged on a substrate, and a large number of nanowires made of a group III nitride material are formed through each opening (for example, Patent Document 3). reference). In Patent Document 3, the growth of multiple nanostructure nuclei is continued by terminating the selective growth mode and applying the pulsed growth mode before the multiple nanostructure nuclei protrude from the top of the selective growth mask. Many nanowires are formed. In Patent Document 3, nanowires themselves are used as LED devices.

  Furthermore, a large number of nanorods formed on the Si substrate, an amorphous matrix layer filling the space between the nanorods so that a part of the upper end of the nanorod protrudes, and a GaN layer formed on the matrix layer, A nitride-based semiconductor light-emitting device including this has been proposed (see, for example, Patent Document 4). In this nitride semiconductor light emitting device, each nanorod is self-formed without using a mask or the like, and each nanorod is formed randomly. Therefore, the dislocation density of the GaN layer formed thereafter increases.

Japanese Patent No. 4153455 JP 2010-518615 A Special table 2009-542560 gazette JP 2006-128627 A

  Here, in the invention described in Patent Document 4, when an Si substrate is used instead of an expensive and unsuitable SiC substrate, it is caused by a difference in lattice constant and thermal expansion coefficient between Si and the group III nitride semiconductor. It aims at suppressing the crack which generate | occur | produces. And since the composite layer of a nanorod-matrix layer relieves thermal stress, it is not a technique for reducing the dislocation density of the group III nitride semiconductor layer on the SiC substrate.

  The present invention has been made in view of the above circumstances, and the object of the present invention is to accurately reduce the dislocation density of the semiconductor layer when forming the group III nitride semiconductor layer on the SiC substrate. An object of the present invention is to provide a group III nitride semiconductor device and a method for manufacturing the same.

  In order to achieve the above object, in the present invention, in forming a group III nitride semiconductor layer on a SiC substrate, a guide layer forming step of forming a guide layer having a predetermined thickness on the SiC substrate; and A guide forming step of forming a plurality of guides penetrating in the thickness direction at a predetermined period, and a group III nitride semiconductor is grown in each guide of the guide layer, and the group III nitride semiconductor is formed on the SiC substrate. A nanocolumn growth step of forming a plurality of nanocolumns at a predetermined period so that a side wall of the nanocolumn does not protrude upward from the guide layer and a crystal of the nanocolumn is not deposited on the surface of the guide layer; Removing the guide layer to expose at least a part of the nanocolumn side wall, and filling the nanocolumn in advance. A semiconductor layer growth process of growing the Group III nitride semiconductor layer, the manufacturing method of a group III nitride semiconductor device comprising is provided.

According to the method for manufacturing a group III nitride semiconductor device, since the nanocolumn is selectively grown through the guide layer, the dislocation density of the nanocolumn itself can be reduced. As a result, dislocations propagating from the nanocolumns to the group III nitride semiconductor layer formed on the guide layer are dramatically reduced, and the dislocation density of the group III nitride semiconductor layer is also reduced.
Further, by growing the nanocolumns along the guide of the guide layer, the quality of each nanocolumn can be made good and uniform. Since at least a part of the guide layer is removed to expose the sidewalls of each nanocolumn, the group III nitride semiconductor can be grown from the sidewalls of each nanocolumn.
Here, during the growth of the nanocolumn, the side wall of the nanocolumn does not protrude upward from the guide layer, and the crystal of the nanocolumn is not deposited on the surface of the guide layer. The crystal does not grow abnormally from the −c plane of the nanocolumn during the growth of the group III nitride semiconductor layer.

  The group III nitride semiconductor device manufacturing method may include a base layer forming step of forming a base layer made of a nitride semiconductor containing Al on the SiC substrate.

  According to this Group III nitride semiconductor device manufacturing method, since the underlayer contains Al, the Group III nitride semiconductor containing Ga and the SiC substrate do not react violently at the interface with each other. The group III nitride semiconductor layer that is included can be accurately grown on the SiC substrate.

  In the method for manufacturing a group III nitride semiconductor device, the nanocolumn may be made of a nitride semiconductor containing Al.

  According to this method for producing a group III nitride semiconductor device, the growth nucleus density is increased at the initial stage of nanocolumn growth, so that each nanocolumn can be formed uniformly.

  In the method for manufacturing a group III nitride semiconductor device, the guide of the guide layer may be formed in a tapered shape that narrows toward the base layer in the thickness direction.

  According to this group III nitride semiconductor device manufacturing method, each nanocolumn extends upward along each tapered guide of the guide layer. After this, since a part of the guide layer is removed, the exposed side wall of each nanocolumn has a tapered shape that narrows toward the base layer in the thickness direction. As a result, when a group III nitride semiconductor is grown from the sidewall of each nanocolumn, the propagation of dislocations is suppressed, the dislocation density of the group III nitride semiconductor is reduced, and a high-quality group III nitride semiconductor layer is formed. Can be obtained.

  In the method for manufacturing a group III nitride semiconductor device, a part of the guide layer may be left in the guide layer removing step.

  According to this group III nitride semiconductor device manufacturing method, a part of the guide layer remains, so that the selectivity of the growth of the group III nitride semiconductor from the sidewall of the nanocolumn is improved during the buried growth of each nanocolumn. Thus, the dislocation density can be further reduced.

  Further, in the method for manufacturing a group III nitride semiconductor device, the semiconductor layer growing step initially grows the group III nitride semiconductor layer at a relatively slow growth rate at least at the apex height of the nanocolumn. And a normal growth step of growing the group III nitride semiconductor layer at a growth rate faster than the growth rate of the initial growth step after the initial growth step.

  According to this method for manufacturing a group III nitride semiconductor device, when each nanocolumn is filled with a group III nitride semiconductor, lateral growth is promoted, and propagation of dislocations is suppressed. The dislocation density of the nitride semiconductor is reduced, and a high-quality group III nitride semiconductor layer can be obtained.

  In the method for manufacturing a group III nitride semiconductor device, at least one of a growth temperature and a V / III ratio may be lower in the nanocolumn growth step than in the semiconductor layer growth step.

  According to this method for manufacturing a group III nitride semiconductor device, if the growth temperature is lowered, the growth nucleus density is increased at the initial stage of nanocolumn growth, and if the V / III ratio is lowered, the lateral growth rate is also lowered. Can be formed.

  In the method for manufacturing a group III nitride semiconductor device, the growth temperature may be increased after the lower end of the nanocolumn is grown at a relatively low temperature in the nanocolumn growth step.

  According to the method for manufacturing a group III nitride semiconductor device, the growth nucleus density is high at the initial stage of nanocolumn growth and the lateral growth rate is lowered, so that each nanocolumn can be formed uniformly. On the other hand, by increasing the temperature during the growth, the dislocation density in the nanocolumns can be reduced, and the crystal quality can be improved.

  Further, in the present invention, a SiC substrate, a plurality of nanocolumns formed on the SiC substrate, constricted toward the SiC substrate side in the thickness direction, and formed of a group III nitride semiconductor with a predetermined period; There is provided a group III nitride semiconductor device comprising a group III nitride semiconductor layer formed so as to grow from the inclined sidewall of each nanocolumn and fill each nanocolumn.

  According to this group III nitride semiconductor device, since the group III nitride semiconductor layer is grown from the side wall of each nanocolumn, the upward propagation of dislocations is suppressed. Thereby, the dislocation density of the group III nitride semiconductor layer is reduced, and a high-quality group III nitride semiconductor layer can be obtained.

  Further, in the group III nitride semiconductor device, a base layer made of a nitride semiconductor containing Al is formed on the SiC substrate, and each nanocolumn is formed on the SiC substrate through the base layer. May be.

  According to this group III nitride semiconductor device, since the underlying layer contains Al, the group III nitride semiconductor containing Ga and the SiC substrate do not react violently at the interface with each other, and the group III containing Ga The nitride semiconductor layer can be accurately grown on the SiC substrate.

  The group III nitride semiconductor device further includes a guide layer formed on the SiC substrate and formed with a plurality of guides penetrating in the thickness direction at a predetermined period, and each nanocolumn is a guide of the guide layer. Then, the group III nitride semiconductor layer may be grown from the inclined sidewalls of the nanocolumns.

  According to this group III nitride semiconductor device, the selectivity of growth from the side wall of the group III nitride semiconductor nanocolumn is improved during the buried growth of each nanocolumn, and the dislocation density is further reduced.

  In the group III nitride semiconductor device, the nanocolumn may be made of a nitride semiconductor containing Al.

  According to this group III nitride semiconductor device, since the growth nucleus density is high at the initial stage of nanocolumn growth, each nanocolumn can be formed uniformly.

  In the group III nitride semiconductor device, a −c plane may not exist on the surface of the nanocolumn.

  According to this group III nitride semiconductor device, since the -c plane does not exist on the nanocolumn surface, the crystal does not grow abnormally from the -c plane of the nanocolumn during the growth of the group III nitride semiconductor layer.

  According to the present invention, when forming a group III nitride semiconductor layer on a SiC substrate, it is possible to accurately reduce the dislocation density of the semiconductor layer.

FIG. 1 is a schematic cross-sectional view of an LED element showing an embodiment of the present invention. FIG. 2 is an explanatory top view of the guide layer showing a guide formation state. 3A shows a manufacturing process of an LED element, (a) shows a state of the substrate, (b) shows a state in which the underlayer is grown on the substrate, and (c) shows a guide layer on the underlayer. FIG. 4D shows a state where a mask layer is formed on the guide layer. FIG. 3B shows a manufacturing process of the LED element, (e) shows a state in which a resist film is formed on the mask layer, (f) shows a state in which a mold is brought into contact with the resist film, and (g) Indicates a state in which a pattern is formed on the resist film. FIG. 3C shows a manufacturing process of the LED element, (h) shows a state where the remaining film of the resist film is removed, (i) shows a state where the mask layer is etched using the resist film as a mask, and (j) shows A state in which the guide layer is etched using the mask layer as a mask is shown. 3D shows a manufacturing process of the LED element, (k) shows a state where the resist film is removed from the mask layer, (l) shows a state where the mask layer is removed from the guide layer, and (m) shows the inside of the guide. Shows the state of nanocolumn growth. FIG. 3E shows a manufacturing process of the LED element, (n) shows a state in which a part of the guide layer is removed and the side wall of the nanocolumn is exposed, and (o) shows an n-type of the group III nitride semiconductor layer. The layer is shown grown. FIG. 4 is a flowchart showing the manufacturing process of the LED element. FIG. 5A is a cross-sectional photograph of an SEM showing an example in which a nanocolumn is made of a nitride semiconductor containing Al. FIG. 5B is a cross-sectional photograph of an SEM showing an example of a nanocolumn made of a nitride semiconductor that does not contain Al. FIG. 6A is a top view photograph of an SEM showing an example of the case where the growth rate of the group III nitride semiconductor layer is set to two stages, and FIG. 6B is a diagram showing the change of the growth rate of the group III nitride semiconductor layer. It is the upper surface photograph of SEM which shows an example when there is not.

  1 to 4 show an embodiment of the present invention, and FIG. 1 is a schematic cross-sectional view of an LED element.

As shown in FIG. 1, the LED element 1 as a group III nitride semiconductor device is represented by Al x Ga y In 1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1). The group III nitride semiconductor layer 10 and the SiC substrate 20 having a smaller coefficient of thermal expansion than the group III nitride semiconductor layer 10 are provided. In the present embodiment, the SiC substrate 20 is a single crystal 6H type and has a thermal expansion coefficient of 4.2 × 10 −6 / ° C. The nitride semiconductor layer as the semiconductor light emitting part has a thermal expansion coefficient of 5.6 × 10 −6 / ° C.

  The SiC substrate 20 includes a donor impurity and an acceptor impurity, and emits light having a predetermined wavelength by donor-acceptor pair emission when excited by light emitted from the group III nitride semiconductor layer 10. For example, when a bulk SiC substrate is used, if the donor impurity is N and the acceptor impurity is B, visible light of approximately yellow to orange color is emitted by excitation of ultraviolet light. Further, when a bulk SiC substrate is used, if the donor impurity is N and the acceptor impurity is Al, approximately blue visible light is emitted by excitation of ultraviolet light. It is to be noted that pure white visible light can be obtained by simultaneously adding B and Al as acceptor impurities while N as the donor impurity, and the emission wavelength is shortened by making SiC porous. The emission wavelength of the substrate can be arbitrarily changed.

On the SiC substrate 20, an underlayer 30 made of a group III nitride semiconductor containing Al and represented by the formula of Al x Ga 1-x N (0 <x ≦ 1) is formed.

On the underlayer 30, a guide layer 40 in which a guide 42 corresponding to the nanocolumn 50 is formed is formed. In the present embodiment, SiO 2 is used as the guide layer 40. Of course, other materials such as SiN x (0 <x) may be used for the guide layer 40. Further, as the material of the guide layer 40, a material such as Al 2 O 3 or W can be used. These materials may be polycrystalline or amorphous.

FIG. 2 is an explanatory top view of the guide layer showing a guide formation state.
As shown in FIG. 2, the guides 42 of the guide layer 40 are formed in a circular shape, and each guide 42 has a shape arranged at an intersection of equilateral triangular lattices. For example, the diameter of the guide 42 can be set to 10 to 1000 nm, and the interval between the adjacent guides 42 can be set to 100 to 10000 nm.

A nanocolumn 50 is formed on the SiC substrate 20 through the guide 42 of the guide layer 40 via the underlayer 30. In the present embodiment, Al x Ga 1-x N (0 <x ≦ 1) is used as the nanocolumn 50. The nanocolumns 50 are grown corresponding to the guides 42 and have a lower dislocation density than when grown without the guide layer 40. In the present embodiment, the nanocolumn 50 is formed in a hexagonal columnar shape with a lower cross-sectional area and a top end formed in a hexagonal pyramid shape. The nanocolumn 50 can have a height dimension higher than that of a diagonal line passing through the center. Here, the height of the nanocolumn refers to the length from the bottom of the hexagonal column to the top of the hexagonal pyramid. The nanocolumn 50 may have a shape other than a hexagonal column as long as it is formed in a columnar shape.

  A group III nitride semiconductor layer 10 is formed on the guide layer 40. The group III nitride semiconductor layer 10 includes an n-type layer 12, a multiple quantum well active layer 14, a p-type cladding layer 16, and a p-type contact layer 18 in this order from the SiC substrate 20 side. A part of group III nitride semiconductor layer 10 is removed by etching, a part of n-type layer 12 is exposed, and n-side electrode 60 is provided in this exposed part. A p-side electrode 62 is formed on the p-type contact layer 18.

In the present embodiment, the n-type layer 12 is formed of n-GaN doped with a predetermined amount of n-type dopant (for example, Si). Also, a multiple quantum well active layer 14 has a In x Ga 1-x N ( 0 ≦ x ≦ 1) / Al y Ga 1-y N multiquantum well structure formed from (0 ≦ y ≦ 1). Furthermore, the p-type cladding layer 16 and the p-type contact layer 18 are each formed from p-GaN doped with a predetermined amount of p-type dopant (for example, Mg).

  The n-type layer 12 to the p-type contact layer 18 are formed by epitaxial growth of a group III nitride semiconductor. In addition, when a voltage is applied to the first conductive type layer and the second conductive type layer at least including the first conductive type layer, the active layer, and the second conductive type layer, the active layer is formed by recombination of electrons and holes. The group structure of the group III nitride semiconductor layer 10 is arbitrary.

  The n-side electrode 60 is formed on the n-type layer 12 and is made of, for example, Ni / Au, and is formed by a vacuum deposition method, a sputtering method, a CVD (Chemical Vapor Deposition) method, or the like. The p-side electrode 62 is formed on the p-type contact layer 18, is made of, for example, ITO (Indium Tin Oxide), and is formed by a vacuum deposition method, a sputtering method, a CVD (Chemical Vapor Deposition) method, or the like.

  Next, a method for manufacturing the LED element 1 will be described with reference to FIGS. 3A to 4. 3A to 3E are schematic cross-sectional views of the LED element, and FIG. 4 is a flowchart of the method for manufacturing the LED element. 3A to 3E are shown in units of one element so as to correspond to FIG. 1 for the sake of explanation, but in actuality, the state of the wafer before element division is shown, and other elements are continuously arranged on the left and right. Is formed.

  First, bulk single crystal 6H-type SiC doped with donor impurities and acceptor impurities is generated by a sublimation method. The impurity doping concentration of the SiC crystal can be controlled by adding an impurity gas to the atmospheric gas during crystal growth and adding an impurity element or compound thereof to the raw material powder. As shown in FIG. 3A (a), the SiC substrate 20 is manufactured through a process such as peripheral grinding, slicing, surface grinding, surface polishing, etc., by preparing a bulk crystal of, for example, about 30 mm by bulk growth by a sublimation method. ing. Here, the thickness of the SiC substrate 20 is arbitrary, but is 250 μm, for example.

  Thereafter, as shown in FIG. 3A (b), the underlayer 30 is epitaxially grown on the SiC substrate 20 (underlayer forming step: S1 (FIG. 4)). In the present embodiment, the underlayer 30 is formed on the entire surface of the SiC substrate 20 by MOVPE (Metal Organic Chemical Vapor Deposition). The underlayer 30 can also be formed by sputtering, MBE (Molecular Beam Epitaxy), HVPE (Halide Vapor Phase Epitaxy), or the like. Furthermore, the underlayer 30 can also be formed by a laser ablation method. Here, the thickness of the underlayer 30 is arbitrary, but is, for example, 10 to 200 nm.

  Next, as shown in FIG. 3A (c), a guide layer 40 is formed on the SiC substrate 20 on which the underlayer 30 is formed (guide layer forming step: S2 (FIG. 4)). In the present embodiment, the guide layer 40 is formed on the entire surface of the base layer 30 by a sputtering method. Here, the thickness of the guide layer 40 is arbitrary, but is preferably thicker than the diagonal dimension of the nanocolumn 50. The thickness of the guide layer 40 is, for example, 100 to 1000 nm. The guide layer 40 can also be formed by, for example, EB vapor deposition.

  Then, as shown in FIG. 3A (d), a mask layer 110 is formed on the guide layer 40 (mask layer forming step: S3 (FIG. 4)). In this embodiment, the mask layer 110 is made of Ni and is formed by a sputtering method, a vacuum evaporation method, a CVD method, or the like. Although the thickness of the mask layer 110 is arbitrary, it can be 10-100 nm, for example.

  Next, as shown in FIG. 3B (e), a resist film 120 is formed on the mask layer 110 (resist film forming step: S4 (FIG. 4)). In this embodiment, a thermoplastic resin is used as the resist film 120 and is formed to have a uniform thickness by a spin coating method. The resist film 120 has a thickness of 50 to 300 nm, for example.

  Then, the resist film 120 is heated and softened, and the resist film 120 is pressed with a mold 130 as shown in FIG. 3B (f). An uneven structure 132 is formed on the contact surface of the mold 130, and the resist film 120 is deformed along the uneven structure 132.

  Thereafter, while maintaining the pressed state, resist film 120 is cooled and cured together with SiC substrate 20. Then, by separating the mold 130 from the resist film 120, the concavo-convex structure 122 is transferred to the resist film 120 as shown in FIG. 3B (g) (pattern forming step: S5 (FIG. 4)). Here, the period of the concavo-convex structure 122 is 10 μm or less. In the present embodiment, the period of the concavo-convex structure 122 is 460 nm. In this state, a remaining film 124 is formed in the recess 122 of the resist film 120.

The SiC substrate 20 on which the resist film 120 is formed as described above is attached to the substrate holding table of the plasma etching apparatus. Then, the residual film 124 is removed by, for example, plasma ashing to expose the mask layer 110 as shown in FIG. 3C (h) (residual film removing step: S6 (FIG. 4)). In the present embodiment, O 2 gas is used as a processing gas for plasma ashing.

  Then, as shown in FIG. 3C (i), the mask layer 110 is etched using the resist film 120 as a mask (mask layer etching step: S7 (FIG. 4)). In the present embodiment, Ar gas is used as a processing gas for etching the resist film 120. As a result, a pattern 112 is formed on the mask layer 110.

Next, as shown in FIG. 3C (j), the guide layer 40 is etched using the mask layer 110 as a mask (guide layer etching step: S8 (FIG. 4)). In the present embodiment, etching is performed with the resist film 120 remaining on the mask layer 110. Further, plasma etching is performed using a fluorine-based gas such as SF 6 gas as a processing gas. As the etching proceeds, a guide 42 extending in the thickness direction is formed in the guide layer 40. In the present embodiment, the inner surface of the guide 42 is inclined so as to narrow toward the base layer 30. Here, the inclination angle of the inner surface of the guide 42 can be adjusted by controlling the bias power at the time of plasma etching.

Thereafter, as shown in FIG. 3D (k), the resist film 120 is removed (resist film removal step: S9 (FIG. 4)). In the present embodiment, the resist film 120 is removed by plasma ashing after being dipped in decahydronaphthalene (C 10 H 18 ) at about 150 ° C. and washed with an organic solvent such as acetone or methanol. As a processing gas for plasma ashing, for example, O 2 gas is used.

  Next, as shown in FIG. 3D (l), the mask layer 110 is removed (mask layer removal step: S10 (FIG. 4)). In the present embodiment, the mask layer 110 made of Ni can be removed by soaking in hot nitric acid for 20 minutes. Thereafter, it is washed with water and dried.

  Then, as shown in FIG. 3D (m), the nanocolumn 50 is epitaxially grown in the guide 42 of the guide layer 40 (nanocolumn growth step: S11 (FIG. 4)). In this embodiment, the nanocolumn 50 is formed by a MOVPE (Metal Organic Chemical Vapor Deposition) method. The nanocolumn 50 can also be formed by sputtering, MBE (Molecular Beam Epitaxy), HVPE (Halide Vapor Phase Epitaxy), or the like. As described above, since the nanocolumns 50 are selectively grown on the SiC substrate 20, the dislocation density in the nanocolumns 50 is extremely small as compared with the case where the semiconductor layer is grown on the entire surface of the SiC substrate 20.

  In the case where the guide layer 40 is thick, when the nanocolumn 50 is grown in the guide 42, a void is likely to be generated at the base end portion. This tendency becomes prominent when the aspect ratio of the guide 42 is 1 or more. In the present embodiment, as shown in FIG. 4, in the nanocolumn growth step S11, an initial growth step S111 for growing the lower end portion of the nanocolumn 50 at a relatively low temperature, and a temperature higher than the initial growth step S111. And a normal growth step S112 for growing the nanocolumn 50. As a result, the growth nucleus density is high at the initial growth stage of the nanocolumns 50 and the lateral growth rate is lowered, so that the nanocolumns 50 can be formed uniformly. In particular, even when the aspect ratio of the guide 42 is 1 or more, generation of voids at the base end portion of the nanocolumn 50 can be suppressed. Here, the high growth nucleus density means a state where the generation frequency of crystal nuclei is high. On the other hand, by increasing the temperature during the growth, the dislocation density in the nanocolumn 50 can be reduced, and the crystal quality can be improved.

  Further, in the present embodiment, the nanocolumns 50 are grown so that the side walls 52 of the nanocolumns 50 do not protrude upward from the guide layer 42 and the crystals of the nanocolumns 50 are not deposited on the surface (upper surface) of the guide layer 42. Is done. As a result, the -c plane does not exist on the surface of the nanocolumn 50 to be formed, and the crystal does not grow abnormally from the -c plane of the nanocolumn 50 when the group III nitride semiconductor layer 10 is grown.

  Furthermore, in this embodiment, the nanocolumn 50 is made of a nitride semiconductor containing Al. In this case, since the Al atoms have a shorter surface diffusion length than the Ga atoms, the growth nucleus density is increased at the initial growth stage of the nanocolumns 50, and the nanocolumns 50 can be formed uniformly. In particular, even when the aspect ratio of the guide 42 is 1 or more, generation of voids at the base end portion of the nanocolumn 50 can be suppressed.

Specifically, in the initial growth step S111, the flow rate of NH 3 is 4500 μmol / min, the substrate temperature is 950 ° C., the flow rate of trimethylgallium is 45 μmol / min, the flow rate of trimethylaluminum is 5 μmol / min, and the nanocolumn 50 is only 100 nm. After the growth, in the normal growth step S112, the nanocolumn 50 is grown by 400 nm by setting the NH 3 flow rate to 45000 μmol / min, the substrate temperature to 1000 ° C., and the trimethylgallium flow rate to 45 μmol / min. I was able to grow it. No voids were observed in the nanocolumn 50 formed in this way.

FIG. 5A is a cross-sectional photograph of an SEM showing an example of a nanocolumn made of a nitride semiconductor containing Al, and FIG. 5B is a cross-sectional picture of an SEM showing an example of a nanocolumn made of a nitride semiconductor containing no Al. . In forming the nanocolumns 50, the AlN underlayer 30 and the SiO 2 guide layer 40 were formed on the SiC substrate 20, and then the guide 42 was formed on the guide layer 40. The thickness of the guide layer 40 was 550 nm, and the diameter of the guide 42 was 210 nm at the base end portion. 5A, the NH 3 flow rate is 4500 μmol / min, the substrate temperature is 950 ° C., the trimethylgallium flow rate is 45 μmol / min, the trimethylaluminum flow rate is 5 μmol / min, and the nanocolumn 50 is grown for 80 seconds. Then, the nanocolumn 50 was grown for 180 seconds at a NH 3 flow rate of 45000 μmol / min, a substrate temperature of 950 ° C., and a trimethylgallium flow rate of 45 μmol / min. 5B, the NH 3 flow rate is 4500 μmol / min, the substrate temperature is 950 ° C., the trimethyl gallium flow rate is 45 μmol / min, and the nano column 50 is grown for 80 seconds, and then the NH 3 flow rate is increased. The nanocolumn 50 was grown for 220 seconds at 45000 μmol / min, the substrate temperature was 950 ° C., and the trimethylgallium flow rate was 45 μmol / min. As is apparent from each figure, in the case of the nitride semiconductor not containing Al, voids are generated at the base end portion of the nanocolumn 50. However, in the case of the nitride semiconductor containing Al, no generation of voids was recognized.

  Furthermore, in this embodiment, the growth temperature and the V / III ratio are lower in the nanocolumn growth step S11 than in the semiconductor layer growth step S13 described later. Also by this, the growth nucleus density becomes high at the initial stage of the growth of the nanocolumn 50 due to the low growth temperature, and the lateral growth rate also decreases due to the low V / III ratio, so that each nanocolumn can be formed uniformly. In particular, even when the aspect ratio of the guide 42 is 1 or more, generation of voids at the base end portion of the nanocolumn 50 can be suppressed. One of the growth temperature and the V / III ratio may be lowered.

Next, as shown in FIG. 3E (n), a part of the guide layer 40 is removed to expose the sidewall 52 of the nanocolumn 50 (guide layer removal step: S12 (FIG. 4)). In the present embodiment, the guide layer 40 made of SiO 2 is removed by dry etching. As the etching gas, a fluorine-based gas such as SF 6 gas is used. Thereafter, for example, SiO 2 remaining on the side wall 52 of the nanocolumn 50 is removed using buffered hydrofluoric acid.

  In the present embodiment, the guide layer 40 is left about 1 nm to 200 nm. With such a thickness, the guide layer 40 has a small inhibition effect on the transmission of light emitted from the active layer. In addition, if light is extracted using the interference action of light, it is not necessary to consider the above-described inhibition action. Therefore, the thickness of the guide layer 40 may be set to such an extent that the interference action is obtained.

  After the guide layer 40 is removed, the group III nitride semiconductor layer 10 is grown (semiconductor layer growth step: S13 (FIG. 4)). In this embodiment, as shown in FIG. 3E (o), after the n-type layer 12 is formed so as to fill the nanocolumn 50, the multiple quantum well active layer 14, the p-type cladding layer 16, and the p-type contact layer 18 are guided. The layers are grown sequentially from the layer 40 side. At this time, since the dislocation density of the nanocolumn 50 itself is low, the number of dislocations propagating from the nanocolumn 50 is extremely small.

  In the present embodiment, as shown in FIG. 4, the semiconductor layer growth step S13 is an initial growth step S131 in which the group III nitride semiconductor layer 10 is initially grown at a relatively slow growth rate at least at the apex height of the nanocolumn 50. And a normal growth step S132 for growing the group III nitride semiconductor layer 10 at a growth rate faster than the growth rate of the initial growth step S131 after the initial growth step S131. Thereby, when each nanocolumn 50 is filled with the group III nitride semiconductor 10, the growth in the lateral direction is promoted and the upward propagation of the dislocation is suppressed, so that the dislocation density of the group III nitride semiconductor 10 is reduced. Thus, a high-quality group III nitride semiconductor layer 10 can be obtained.

Specifically, in the initial growth step S131, the group III nitride semiconductor layer 10 has an NH 3 flow rate of 134,000 μmol / min, a substrate temperature of 1050 ° C., a trimethylgallium flow rate of 50 μmol / min, and a growth rate of 1 μm / h. After the growth of 1 μm, in the normal growth step S132, group III nitridation is performed with an NH 3 flow rate of 13000 μmol / min, a substrate temperature of 1050 ° C., a trimethylgallium flow rate of 145 μmol / min, and a growth rate of 3 μm / h. The group III nitride semiconductor layer 10 having a thickness of 4 μm could be grown by growing the semiconductor layer 10 by 3 μm. As a result, as shown in FIG. 6A, the nanocolumns 50 were formed without voids.

FIG. 6A is a top view photograph of an SEM showing an example in which the growth rate of the group III nitride semiconductor layer is set to two stages, and FIG. It is the upper surface photograph of SEM which shows an example when there is not. In producing these group III nitride semiconductor layers 10, the nanocolumns 50 of FIG. 5A described above were formed with a period of 460 nm, and a part of the guide layer 42 was removed. FIG. 6A shows the formation of the group III nitride semiconductor layer 10 under the growth conditions described above. FIG. 6B shows the NH 3 flow rate of 13000 μmol / min, the substrate temperature of 1050 ° C., and the flow rate of trimethylgallium. Was 145 μmol / min, the growth rate was 3 μm / h, and the group III nitride semiconductor layer 10 was formed only for 1 hour. As is clear from each figure, when the growth rate is not changed, the nano-group 50 is not sufficiently embedded and the flat group III nitride semiconductor layer 10 cannot be grown. The physical semiconductor layer 10 could be planarized.

  The thickness of each layer of the group III nitride semiconductor layer 10 is arbitrary. For example, the thickness of the n-type layer 12 is 3 μm, the thickness of the multiple quantum well active layer 14 is 100 nm, and the thickness of the p-type cladding layer 16 is The thickness can be 80 nm and the thickness of the p-type contact layer 18 can be 10 nm. Thus, the thickness of the group III nitride semiconductor layer 10 can be 3 μm or more. After the group III nitride semiconductor layer 10 is grown, a photoresist mask is formed on the p-type contact layer 18 using a photolithography technique and etched from the p-type contact layer 18 to the surface of the n-type layer 12. The mask is removed (semiconductor layer etching step: S14 (FIG. 4)). Thereby, as shown in FIG. 1, a mesa portion composed of a plurality of compound semiconductor layers from the n-type layer 12 to the p-type contact layer 18 is formed.

  Then, the n-side electrode 60 and the p-side electrode 62 are formed using a vacuum vapor deposition method and a photolithography technique (electrode forming step: S15 (FIG. 4)). In this embodiment, the material of the n-side electrode 60 and the material of the p-side electrode 62 are different. However, if these materials are the same, the n-side electrode 40 and the p-side electrode 62 can be formed simultaneously. In order to ensure ohmic contact and adhesion between the electrodes 60 and 62 and the group III nitride semiconductor layer 10, heat treatment can be performed for a predetermined time at a predetermined temperature and a predetermined atmosphere. Then, the LED element 1 is manufactured by dividing into a plurality of LED elements 1 by dicing.

  The LED element 1 configured as described above emits ultraviolet light from the multiple quantum well active layer 14 when a voltage is applied to the p-side electrode 62 and the n-side electrode 60. And after ultraviolet light is converted into visible light by the SiC substrate 20, it is radiated | emitted outside.

  According to this LED element 1, since the nanocolumn 50 is selectively grown through the guide layer 40, the dislocation density of the nanocolumn 50 itself can be reduced. As a result, dislocations propagating from the nanocolumn 50 to the group III nitride semiconductor layer 10 formed on the guide layer 40 are dramatically reduced, and the dislocation density of the group III nitride semiconductor layer 10 is also reduced. Accordingly, it is possible to accurately reduce the dislocation density in the group III nitride semiconductor 10.

  In addition, by forming the guide 42 in the guide layer 40 and growing the nanocolumn 50, the quality of each nanocolumn 50 can be made good and uniform without being influenced by the period, diameter, etc. of each nanocolumn 50. it can. In addition, without the guides 42, the growth conditions of the nanocolumns 50 are restricted in order to grow the nanocolumns 50 in a column shape, but by growing along the guides 42, the degree of freedom of the growth conditions of the nanocolumns 50 jumps dramatically. Improve. Since a part of the guide layer 40 is removed so that the side walls 52 of the nanocolumns 50 are exposed, the group III nitride semiconductor 10 can be grown from the side walls 52 of the high-quality nanocolumns 50.

  Further, according to the LED element 1, since the foundation layer 30 contains Al, for example, when a nitride semiconductor containing Ga is directly grown on a SiC substrate, the group III nitride semiconductor and the substrate are formed. The group III nitride semiconductor layer 10 can be accurately grown on the SiC substrate 20 without reacting violently at the mutual interface.

  In the above embodiment, the example in which the present invention is applied to the LED element 1 as a semiconductor device has been described. However, the present invention can also be applied to other devices such as an LD element. For example, the present invention can be applied to electronic devices such as field effect transistors and bipolar transistors, solar cells, and the like.

  Further, in the above-described embodiment, the SiC substrate 20 using 6H type SiC is shown, but it is needless to say that it may be 4H type or 15R type. Furthermore, the SiC substrate 20 may not have a fluorescence function, and the emission color of the group III nitride semiconductor layer 10 is arbitrary.

  In the above embodiment, the base layer 30 made of a nitride semiconductor containing Al is provided. However, the base layer 30 can be omitted as appropriate. For example, when the nanocolumn 50 is AlN and the guide layer 40 remains on the SiC substrate 10, the nitride semiconductor containing Ga does not come into contact with SiC. Absent.

  In the above embodiment, the nanocolumn 50 is made of a nitride semiconductor containing Al. However, for example, a group III nitride semiconductor containing no Al such as GaN may be used. In this case, it is preferable that the underlayer 30 is provided.

  In the above embodiment, the dislocation of the nanocolumn 50 can be reduced by introducing an uneven shape on the surface of the underlayer 30 by plasma irradiation or the like.

  Moreover, in the said embodiment, although the guide 42 of the guide layer 40 showed what was formed in the taper shape which narrows toward the base layer 30 side about thickness direction, for example, it is the same cross section about thickness direction. It may be made to become. Even in this case, the nanocolumns 50 can be uniformly formed by growing along the guides 42, and the effect of reducing the dislocation density of the group III nitride semiconductor layer 10 grown subsequently can be obtained. it can.

  Moreover, in the said embodiment, although what left a part of guide layer 40 was shown, you may make it remove the guide layer 40 altogether.

  While the embodiments of the present invention have been described above, the embodiments described above do not limit the invention according to the claims. In addition, it should be noted that not all the combinations of features described in the embodiments are essential to the means for solving the problems of the invention.

1 LED element 10 Group III nitride semiconductor layer 12 n-type layer 14 multiple quantum well active layer 16 p-type cladding layer 18 p-type contact layer 20 SiC substrate 30 underlayer 40 guide layer 42 guide 50 nanocolumn 52 side wall 60 n-side electrode 62 p-side electrode 110 mask layer 112 pattern 120 resist film 122 uneven structure 124 remaining film 130 mold 132 uneven structure

Claims (10)

  1. In forming the group III nitride semiconductor layer on the SiC substrate,
    A guide layer forming step of forming a guide layer having a predetermined thickness on the SiC substrate;
    A guide forming step of forming a plurality of guides penetrating the guide layer in the thickness direction at a predetermined period;
    A group III nitride semiconductor is grown in each guide of the guide layer, and a plurality of nanocolumns made of group III nitride semiconductor are formed on the SiC substrate so that the side walls of the nanocolumn do not protrude upward from the guide layer. And a nanocolumn growth step for forming the nanocolumn crystals on the surface of the guide layer so as not to be deposited at a predetermined period;
    Removing at least a portion of the guide layer to expose at least a portion of the sidewall of the nanocolumn; and
    To fill the nanocolumns, and the semiconductor layer growing step of growing the group III nitride semiconductor layer, only including,
    A method for manufacturing a group III nitride semiconductor device, wherein the nanocolumn is made of a nitride semiconductor containing Al .
  2. In forming the group III nitride semiconductor layer on the SiC substrate,
    A guide layer forming step of forming a guide layer having a predetermined thickness on the SiC substrate;
    A guide forming step of forming a plurality of guides penetrating the guide layer in the thickness direction at a predetermined period;
    A group III nitride semiconductor is grown in each guide of the guide layer, and a plurality of nanocolumns made of group III nitride semiconductor are formed on the SiC substrate so that the side walls of the nanocolumn do not protrude upward from the guide layer. And a nanocolumn growth step for forming the nanocolumn crystals on the surface of the guide layer so as not to be deposited at a predetermined period;
    Removing at least a portion of the guide layer to expose at least a portion of the sidewall of the nanocolumn; and
    To fill the nanocolumns, and the semiconductor layer growing step of growing the group III nitride semiconductor layer, only including,
    The method of manufacturing a group III nitride semiconductor device, wherein the guide of the guide layer is formed in a tapered shape constricted toward the base layer side in the thickness direction .
  3. In forming the group III nitride semiconductor layer on the SiC substrate,
    A guide layer forming step of forming a guide layer having a predetermined thickness on the SiC substrate;
    A guide forming step of forming a plurality of guides penetrating the guide layer in the thickness direction at a predetermined period;
    A group III nitride semiconductor is grown in each guide of the guide layer, and a plurality of nanocolumns made of group III nitride semiconductor are formed on the SiC substrate so that the side walls of the nanocolumn do not protrude upward from the guide layer. And a nanocolumn growth step for forming the nanocolumn crystals on the surface of the guide layer so as not to be deposited at a predetermined period;
    Removing at least a portion of the guide layer to expose at least a portion of the sidewall of the nanocolumn; and
    To fill the nanocolumns, and the semiconductor layer growing step of growing the group III nitride semiconductor layer, only including,
    The semiconductor layer growth step includes
    An initial growth step of initially growing the group III nitride semiconductor layer at a relatively slow growth rate at least at the apex height of the nanocolumn;
    A method of manufacturing a group III nitride semiconductor device comprising, after the initial growth step, a normal growth step of growing the group III nitride semiconductor layer at a growth rate faster than the growth rate of the initial growth step .
  4. In forming the group III nitride semiconductor layer on the SiC substrate,
    A guide layer forming step of forming a guide layer having a predetermined thickness on the SiC substrate;
    A guide forming step of forming a plurality of guides penetrating the guide layer in the thickness direction at a predetermined period;
    A group III nitride semiconductor is grown in each guide of the guide layer, and a plurality of nanocolumns made of group III nitride semiconductor are formed on the SiC substrate so that the side walls of the nanocolumn do not protrude upward from the guide layer. And a nanocolumn growth step for forming the nanocolumn crystals on the surface of the guide layer so as not to be deposited at a predetermined period;
    Removing at least a portion of the guide layer to expose at least a portion of the sidewall of the nanocolumn; and
    To fill the nanocolumns, and the semiconductor layer growing step of growing the group III nitride semiconductor layer, only including,
    In the nanocolumn growth process, a method for manufacturing a group III nitride semiconductor device in which at least one of a growth temperature and a V / III ratio is lower than that in the semiconductor layer growth process .
  5. In forming the group III nitride semiconductor layer on the SiC substrate,
    A guide layer forming step of forming a guide layer having a predetermined thickness on the SiC substrate;
    A guide forming step of forming a plurality of guides penetrating the guide layer in the thickness direction at a predetermined period;
    A group III nitride semiconductor is grown in each guide of the guide layer, and a plurality of nanocolumns made of group III nitride semiconductor are formed on the SiC substrate so that the side walls of the nanocolumn do not protrude upward from the guide layer. And a nanocolumn growth step for forming the nanocolumn crystals on the surface of the guide layer so as not to be deposited at a predetermined period;
    Removing at least a portion of the guide layer to expose at least a portion of the sidewall of the nanocolumn; and
    To fill the nanocolumns, and the semiconductor layer growing step of growing the group III nitride semiconductor layer, only including,
    A method of manufacturing a group III nitride semiconductor device, wherein, in the nanocolumn growth step, the lower end portion of the nanocolumn is grown at a relatively low temperature, and then the growth temperature is increased .
  6. A SiC substrate;
    A plurality of nanocolumns formed on the SiC substrate, constricted toward the SiC substrate side in the thickness direction, and formed of a group III nitride semiconductor with a predetermined period;
    A group III nitride semiconductor device comprising: a group III nitride semiconductor layer formed so as to grow from the inclined sidewall of each nanocolumn and fill each nanocolumn.
  7. An underlayer made of a nitride semiconductor containing Al is formed on the SiC substrate,
    The group III nitride semiconductor device according to claim 6 , wherein each of the nanocolumns is formed on the SiC substrate via the base layer.
  8. A guide layer is formed on the SiC substrate, and a plurality of guides penetrating in the thickness direction are formed at a predetermined cycle.
    The group III nitride semiconductor device according to claim 6 or 7 , wherein after each nanocolumn is formed using a guide of the guide layer, the group III nitride semiconductor layer is grown from an inclined side wall of each nanocolumn.
  9. The group III nitride semiconductor device according to claim 8 , wherein the nanocolumn is made of a nitride semiconductor containing Al.
  10. On the surface of the nano-columns are, III-nitride semiconductor device according to any one of claims 6 9, -c plane does not exist.
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