JP2008130606A - Semiconductor light emitting element and its manufacturing method, light source cell unit, backlight, lighting device, display, electronic device, and semiconductor element and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor light emitting element that can suppress quantum confinement Stark effect in an active layer, improve the output of light emission by increasing a volume of the active layer and be easily manufactured, and to provide its manufacturing method. <P>SOLUTION: A substrate 11 is made of a material having a hexagonal crystal structure, and its main face is r plane or a plane. An n-type nitride-based group III-V compound semiconductor layer 12 is grown by priority thereon in a plane orientation, and an n-type nitride-based group III-V compound semiconductor layer 13 and an active layer 14 are sequentially grown thereon by priority in m plane orientation. Furthermore, a p-type nitride-based group III-V compound semiconductor layer 15 is grown by priority thereon in a plane orientation, so as to form a light emitting diode structure. The active layer 14 has a section shape of saw tooth, and slopes 14a and 14b are m-plane facet. The light emitting diode is used to manufacture a light emitting diode backlight. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor light emitting device, a method for manufacturing a semiconductor light emitting device, a light source cell unit, a backlight, a lighting device, a display, an electronic device, a semiconductor device, and a method for manufacturing a semiconductor device. The present invention is suitable for application to light emitting diodes using semiconductors and various devices or equipment using the light emitting diodes.

Conventionally, a method for manufacturing a light-emitting diode using a GaN-based semiconductor is performed by metal organic chemical vapor deposition of a GaN-based semiconductor layer including an n-type layer, an active layer, and a p-type layer on a (0001) plane, that is, a c-plane sapphire substrate. The method of growing as a flat layer with c-axis orientation by the (MOCVD) method is the mainstream.
However, in the conventional light emitting diode manufactured by such a method, it is difficult to structurally further improve the light emission output.

It is said that the luminous efficiency can be improved by increasing the quantum effect by using a quantum dot that performs three-dimensional quantum confinement or a quantum wire that performs two-dimensional quantum confinement in the active layer. Since the volume of the active layer decreases, it is difficult to simultaneously improve the light emission efficiency by the quantum effect and the light emission volume, and it is considered difficult to improve the light emission output by this method.
Further, as is well known, in a c-axis oriented InGaN strained quantum well layer grown on a c-plane sapphire substrate, a large piezo electric field is generated in the direction perpendicular to the well surface (c-axis direction) and positive with electrons. The quantum confinement Stark effect that spatially separates the holes from each other and lowers the probability of electron-hole recombination occurs. For example, in an InGaN / GaN-based light emitting diode, this reduces the internal quantum efficiency, and thus the external quantum efficiency. There is a problem of lowering, and this is one cause that hinders the improvement of the light emission output.

In order to solve this problem, when a semiconductor light emitting device is manufactured by growing a plurality of GaN-based semiconductor layers including a strained quantum well layer, at least the plane direction of the growth surface of the strained quantum well layer has a maximum piezoelectric field. When the GaN-based semiconductor layer has a wurtzite crystal structure, the plane orientation of the growth surface of the strained quantum well layer is inclined by 1 ° or more from the [0001] direction (for example, 40 °, 90 ° It has been proposed to select to have (°, 140 °, etc.) (for example, see Patent Document 1). A semiconductor light-emitting device manufactured by this method is shown in FIG. According to this method, as shown in FIG. 36, an n-type GaN contact layer 102 and an n-type AlGaN cladding layer 103 are {0001} on a substrate 101 made of SiC, GaN or the like via an AlN buffer layer (not shown). The surface is grown sequentially in the surface direction, and a {2-1-14} plane or a {01-12} plane is formed on the surface of the n-type AlGaN cladding layer 103 by selective growth or selective etching, and GaInN / GaN or GaInN is formed thereon. / GaInN multiple quantum well layer 104 is grown, and a p-type AlGaN cladding layer 105 and a p-type GaN contact layer 106 are sequentially grown thereon. In this case, the growth surfaces 104a and 104b of the multiple quantum well layer 104 are {2-1-14} planes or {01-12} planes. The p-type AlGaN cladding layer 105 and the p-type GaN contact layer 106 are grown by changing the crystal structure from the plane orientation of the multiple quantum well layer 104 to the {0001} plane orientation direction. Reference numeral 107 denotes a p-side electrode, and 108 denotes an n-side electrode.
JP-A-11-112029

  In the conventional semiconductor light emitting device shown in FIG. 36, not only can the piezoelectric field of the multiple quantum well layer 104 as an active layer be reduced, but also the multiple quantum well layer 104 has a {2-1-14} plane or a {01− The volume of the active layer is increased as compared with the case where the multiple quantum well layer 104 is flat because it has a sawtooth cross-sectional shape with the 12} plane as an inclined surface, but the {2-1-14} plane or the {01- In practice, it is not always easy to grow the multi-quantum well layer 104 with controllability while projecting the 12} facets on the slope, and it is difficult to manufacture semiconductor light emitting devices with high yield.

Therefore, the problem to be solved by the present invention is that the quantum confined Stark effect in the active layer can be suppressed, and the volume of the active layer can be increased, so that the light emission output can be improved and the manufacturing can be performed. It is an object of the present invention to provide a semiconductor light emitting device and a method for manufacturing the same.
Another problem to be solved by the present invention is to provide a high-performance light source cell unit, a backlight, a lighting device, a display, and an electronic apparatus using the excellent semiconductor light emitting element as described above.
Still another problem to be solved by the present invention is to suppress the quantum confined Stark effect in the active layer, and to improve the performance such as light emission output by increasing the volume or area of the active layer, Moreover, it is an object of the present invention to provide a semiconductor device including a light emitting diode, a semiconductor laser, a transistor and the like, which can be easily manufactured, and a manufacturing method thereof.
The above and other problems will become apparent from the description of this specification with reference to the accompanying drawings.

In order to solve the above problem, the first invention is:
A semiconductor light emitting device having a semiconductor layer including an active layer made of a semiconductor having a hexagonal crystal structure on a substrate made of a substance having a hexagonal crystal structure,
The main surface of the substrate is a {10-12} plane or a {11-20} plane, and the active layer has a slope composed of {1-100} plane facets.

The second invention is
A method for manufacturing a semiconductor light-emitting device having a semiconductor layer including an active layer made of a semiconductor having a hexagonal crystal structure on a substrate made of a substance having a hexagonal crystal structure,
A substrate whose principal surface is a {10-12} plane or a {11-20} plane is used as the substrate, and the active layer is grown on the substrate so as to have a slope composed of {1-100} facets. It is characterized by that.

In this semiconductor light emitting device, in one typical example, the active layer has a sawtooth cross-sectional shape having a slope formed of {1-100} facets. Typically, all of the semiconductor layers including the active layer are made of a semiconductor having a hexagonal crystal structure. A semiconductor having this hexagonal crystal structure typically has a wurtzite structure. Specific examples of the semiconductor having the wurtzite structure include nitride-based III-V group compound semiconductors, oxide semiconductors, and α-ZnS, but are not limited thereto. Nitride III-V compound semiconductor is _{generally, Al X B y Ga 1-} xyz In z As u N 1-uv P v ( however, 0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ z ≦ 1,0 ≦ u ≦ 1,0 ≦ v ≦ 1,0 ≦ x + y + z <1,0 ≦ u + v consists <1), more _{specifically, Al X B y Ga 1-} xyz in z N ( However, it is composed of 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, 0 ≦ x + y + z <1), and typically, Al _x Ga _1-xz In _z N (where 0 ≦ x ≦ 1, 0 ≦ z ≦ 1), and specific examples include GaN, InN, AlN, AlGaN, InGaN, and AlGaInN. This nitride-based III-V compound semiconductor, for example, has an effect of promoting the bending of dislocations when B or Cr is contained in GaN. Therefore, BGaN, GaN doped with B in GaN: B, Cr in GaN It may be made of doped GaN: Cr or the like. As this nitride-based III-V group compound semiconductor, preferably, GaN, In _x Ga _1-x N (0 <x <0.5), Al _x Ga _1-x N (0 <x <0. 5), Al _x In _y Ga _1-xy N (0 <x <0.5, 0 <y <0.2) or the like is used. In addition, as a so-called low-temperature buffer layer that is first grown on the substrate, a GaN buffer layer, an AlN buffer layer, an AlGaN buffer layer, etc. are generally used, and those doped with Cr or CrN buffer layers are used. Also good. Examples of the oxide semiconductor include titanium (IV) oxide (TiO ₂ ), vanadium oxide (V) (V ₂ O ₅ ), chromium oxide (III) (Cr ₂ O ₃ ), manganese oxide (II) (MnO), Iron oxide (III) (Fe ₂ O ₃ ), tricobalt tetroxide (II) (Co ₃ O ₄ ), nickel oxide (II) (NiO), copper (I) oxide (Cu ₂ O), zinc oxide (II ) (ZnO), tin oxide (IV) (SnO ₂ ), gallium oxide (III) (Ga ₂ O ₃ ), indium oxide (III) (In ₂ O ₃ ), bismuth oxide (III) (Bi ₂ O ₃ ) In addition to strontium oxide (II) (SrO), strontium titanate (SrTiO ₃ ), barium titanate (BaTiO ₃ ), yttrium oxide (Y ₂ O ₃ ), etc., oxychalcogenide LnCuOCh (Ln = La, Ce, Nd Pr, Ch = S, Se, Te), for example Examples thereof include CuAlO and SrCu ₂ O ₂ , but are not limited thereto. The semiconductor light emitting element is a light emitting diode or a semiconductor laser. In the semiconductor laser, the resonator length direction is preferably the [0001] direction (c-axis direction).

As a method for growing a semiconductor layer constituting this semiconductor light emitting device, various methods such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxial growth or halide vapor phase epitaxial growth (HVPE), molecular beam epitaxy (MBE), etc. An epitaxial growth method can be used.
As a substrate made of a substance having a hexagonal crystal structure and having a {10-12} plane (r-plane) or {11-20} plane (a-plane) as a principal plane, an active layer is formed thereon with {1 Basically, any material can be used as long as it can be grown so as to have a slope formed of a −100} facet. Specifically, for example, sapphire, SiC (6H, 4H), a substrate made of α-ZnS, ZnO, or the like can be used. As the substrate, a substrate made of a nitride III-V group compound semiconductor (GaN, AlGaInN, AlN, GaInN, etc.) may be used. Alternatively, a substrate obtained by growing a substance having a hexagonal crystal structure on a substrate made of a substance different from the substance having a hexagonal crystal structure may be used.
The substrate may be left as it is in the final semiconductor light emitting device or may be removed.

As the substrate, a substrate having a plurality of protrusions on the main surface other than the entire main surface is flat, and the protrusions are made of a material different from the substrate or the same material as the substrate. Also good. In this case, for example, the first semiconductor layer is grown in the concave portion of the substrate through a state of a triangular, quadrangular, pentagonal, or hexagonal cross-sectional shape with the bottom surface as the base. A second semiconductor layer is laterally grown from the layer onto the substrate, and a third semiconductor layer of the first conductivity type, an active layer, and a fourth semiconductor layer of the second conductivity type are formed on the second semiconductor layer. The semiconductor light emitting device is manufactured by sequentially growing the layers. Typically, convex portions and concave portions are alternately and periodically formed on the main surface of the substrate. In this case, although the period of a convex part and a recessed part is 3-5 micrometers suitably, it is not limited to this. Further, the ratio of the length of the bottom of the convex portion to the length of the bottom of the concave portion is preferably 0.5 to 3, and most preferably around 0.5, but is not limited thereto. . The height of the convex portion as viewed from the main surface of the substrate is preferably 0.3 μm or more, more preferably 1 μm or more, but is not limited thereto. The convex portion preferably has a side surface inclined with respect to the main surface of the substrate (for example, a side surface in contact with one main surface of the substrate), and an angle between the side surface and the main surface of the substrate is θ, From the viewpoint of improving the light extraction efficiency, for example, preferably 100 ° <θ <160 °, more preferably 132 ° <θ <139 ° or 147 ° <θ <154 °, and most preferably Although it is 135 degrees or 152 degrees, it is not limited to this. The cross-sectional shape of the convex portion may be various shapes, and the side surface may be a curved surface as well as a flat surface. For example, an n-gon (where n is an integer of 3 or more), specifically Triangular, quadrangular, pentagonal, hexagonal, etc., or those with their corners cut off, rounded corners, circular, oval, etc. Of these, the highest position when viewed from one main surface of the board Those having one apex are desirable, and in particular, a triangle or a shape obtained by cutting off the apex or rounded apex is most desirable. Although the cross-sectional shape of the recess may be various shapes, for example, an n-gon (where n is an integer of 3 or more), specifically, a triangle, a quadrangle, a pentagon, a hexagon, or the like, or these corners are cut off. Or rounded, oval, etc. From the viewpoint of improving the light extraction efficiency, preferably, the cross-sectional shape of the recess is an inverted trapezoid. Here, the inverted trapezoidal shape means not only an accurate inverted trapezoid but also includes an object that can be approximately regarded as an inverted trapezoid (the same applies hereinafter). In this case, from the viewpoint of minimizing the dislocation density of the second semiconductor layer, preferably, the depth of the concave portion (same as the height of the convex portion) is d, and the width of the bottom surface of the concave portion is W _g , such as a triangular shape. Where d, W _g , and α are determined so that 2d ≧ W _g tan α is satisfied, where α is the angle formed by the slope of the first semiconductor layer in the state of the cross-sectional shape and the principal surface of the substrate. Since α is normally constant, d and W _g are determined so that this equation is satisfied. If d is too large, the source gas is not sufficiently supplied to the inside of the recess, which hinders the growth of the first semiconductor layer from the bottom surface of the recess. Since the first semiconductor layer grows on both convex portions, it is generally selected within the range of 0.5 μm <d <5 μm from the viewpoint of preventing these, and typically 1.0 μm. It is selected within the range of ± 0.2 μm, but is not limited to this. W _g is generally 0.5 to 5 μm and is typically selected within the range of 2 ± 0.5 μm, but is not limited thereto. Further, the width W _t of the upper surface of the convex portion is 0 when the cross-sectional shape of the convex portion is triangular, but when the cross-sectional shape of the convex portion is trapezoidal, the convex portion is formed on the second semiconductor layer. Since this is a region used for lateral growth, the longer the area, the larger the area of the portion with less dislocation density. When the cross-sectional shape of the convex portion is trapezoidal, W _t is generally in the range of 1 to 1000 μm, typically 4 ± 2 μm, but is not limited thereto.

  For example, the convex portion or the concave portion may extend in a stripe shape in one direction on the substrate, or may extend in a stripe shape in at least a first direction and a second direction intersecting each other. As a result, the convex portion has an n-gon shape (where n is an integer of 3 or more), specifically, a triangle, a quadrangle, a pentagon, a hexagon, etc. Alternatively, it may be a two-dimensional pattern such as an ellipse or a dot. In a preferred example, the convex portions have a hexagonal planar shape, the convex portions are two-dimensionally arranged in a honeycomb shape, and concave portions are formed so as to surround the convex portions. By doing so, light emitted from the active layer can be efficiently extracted in all directions of 360 °. Alternatively, the recess may have a hexagonal planar shape, the recesses may be two-dimensionally arranged in a honeycomb shape, and a protrusion may be formed so as to surround the recess. The convex portion is, for example, an n-pyramid (where n is an integer of 3 or more), specifically, a triangular pyramid, a quadrangular pyramid, a pentagonal pyramid, a hexagonal pyramid, etc., or a cut or rounded corner. Things, cones, elliptical cones, etc.

The material of the convex portion may be various, and may or may not be conductive. For example, a dielectric such as an oxide, nitride, or carbide, or a conductor such as a metal or alloy (including a transparent conductor) ) Etc. As the oxide, for example, various oxides such as silicon oxide (SiO _x ), titanium oxide (TiO _x ), and tantalum oxide (TaO _x ) can be used, and two or more of these can be mixed or laminated. It can also be used in the form of a membrane. As the nitride, for example, silicon nitride (SiN _x ), SiON, CrN, CrNO or the like can be used, and two or more of these can be mixed or used in the form of a laminated film. As the carbide, SiC, HfC, ZrC, WC, TiC, CrC or the like can be used, and two or more of these can be mixed or used in the form of a laminated film. As the metal or alloy, B, Al, Ga, In, W, Ni, Co, Pd, Pt, Ag, AgNi, AgPd, AuNi, AuPd, and the like can be used. Alternatively, it can be used in the form of a laminated film. As the transparent conductor, ITO (indium-tin composite oxide), IZO (indium-zinc composite oxide), ZO (zinc oxide), FTO (fluorine-doped tin oxide), tin oxide, and the like can be used. Two or more of these may be mixed or used in the form of a laminated film. Further, two or more of the various materials described above can be mixed or used in the form of a laminated film. A convex portion may be formed of metal or the like, and nitride, oxide, or carbide may be formed by nitriding, oxidizing, or carbonizing at least the surface of the convex portion.
The refractive index of the convex portion is determined by design as needed, but in general, the refractive index of the substrate is selected to be different from the refractive index of the substrate and the refractive index of the semiconductor layer grown on this substrate. Is selected below the refractive index of the substrate.
An electrode on the first conductivity type side is formed on the third semiconductor layer while being electrically connected to the third semiconductor layer. Similarly, an electrode on the second conductivity type side is also formed on the fourth semiconductor layer in a state of being electrically connected thereto.
Typically, when growing the first semiconductor layer, a direction inclined by 120 to 150 ° with respect to one principal surface of the substrate from the interface with the bottom surface of the concave portion of the substrate and a direction perpendicular to the one principal surface When the dislocations reach the slope of the first semiconductor layer or the vicinity thereof in a state where the dislocations have the triangular, quadrangular, pentagonal or hexagonal cross-sectional shape, Bend in a parallel direction away from the triangle, square, pentagon, or hexagon.

The third invention is
In a light source cell unit in which a plurality of cells each including at least one of a red light emitting semiconductor light emitting element, a green light emitting semiconductor light emitting element, and a blue light emitting semiconductor light emitting element are arranged,
At least one of the red light emitting semiconductor light emitting element, the green light emitting semiconductor light emitting element, and the blue light emitting semiconductor light emitting element,
A semiconductor light emitting device having a semiconductor layer including an active layer made of a semiconductor having a hexagonal crystal structure on a substrate made of a substance having a hexagonal crystal structure,
The main surface of the substrate is a {10-12} plane or a {11-20} plane, and the active layer has a slope formed of {1-100} facets. is there.

The fourth invention is:
In a backlight in which a plurality of red light emitting semiconductor light emitting elements, green light emitting semiconductor light emitting elements and blue light emitting semiconductor light emitting elements are arranged,
At least one of the red light emitting semiconductor light emitting element, the green light emitting semiconductor light emitting element, and the blue light emitting semiconductor light emitting element,
A semiconductor light emitting device having a semiconductor layer including an active layer made of a semiconductor having a hexagonal crystal structure on a substrate made of a substance having a hexagonal crystal structure,
The main surface of the substrate is a {10-12} plane or a {11-20} plane, and the active layer has a slope formed of {1-100} facets. is there.

The fifth invention is:
In a lighting device in which a plurality of red light emitting semiconductor light emitting elements, green light emitting semiconductor light emitting elements and blue light emitting semiconductor light emitting elements are arranged,
At least one of the red light emitting semiconductor light emitting element, the green light emitting semiconductor light emitting element, and the blue light emitting semiconductor light emitting element,
A semiconductor light emitting device having a semiconductor layer including an active layer made of a semiconductor having a hexagonal crystal structure on a substrate made of a substance having a hexagonal crystal structure,
The main surface of the substrate is a {10-12} plane or a {11-20} plane, and the active layer has a slope formed of {1-100} facets. is there.

The sixth invention is:
In a display in which a plurality of red light emitting semiconductor light emitting elements, green light emitting semiconductor light emitting elements and blue light emitting semiconductor light emitting elements are arranged,
At least one of the red light emitting semiconductor light emitting element, the green light emitting semiconductor light emitting element, and the blue light emitting semiconductor light emitting element,
A semiconductor light emitting device having a semiconductor layer including an active layer made of a semiconductor having a hexagonal crystal structure on a substrate made of a substance having a hexagonal crystal structure,
The main surface of the substrate is a {10-12} plane or a {11-20} plane, and the active layer has a slope formed of {1-100} facets. is there.
In the third to sixth inventions, for example, a semiconductor using a nitride III-V compound semiconductor is used as the red light emitting semiconductor light emitting device, the green light emitting semiconductor light emitting device, and the blue light emitting semiconductor light emitting device. Can do. As the semiconductor light emitting element emitting red light, for example, an element using an AlGaInP-based semiconductor can be used.

The seventh invention
In an electronic device having one or more semiconductor light emitting elements,
At least one of the semiconductor light emitting elements is
A semiconductor light emitting device having a semiconductor layer including an active layer made of a semiconductor having a hexagonal crystal structure on a substrate made of a substance having a hexagonal crystal structure,
The main surface of the substrate is a {10-12} plane or a {11-20} plane, and the active layer has a slope formed of {1-100} facets. is there.

Here, the electronic equipment includes, for example, a light-emitting diode backlight (such as a backlight of a liquid crystal display), a light-emitting diode illuminating device, a light-emitting diode display, and a projector or rear projection television set using a light-emitting diode as a light source, a grating light valve ( GLV), etc., but in general, any device that has at least one semiconductor light emitting device for display, illumination, optical communication, optical transmission and other purposes is basically Well, including both portable and stationary types, but specific examples other than the above include mobile phones, mobile devices, robots, personal computers, in-vehicle devices, various household electrical appliances, light-emitting diode light Portable devices such as communication devices, light-emitting diode optical transmission devices, and electronic keys Yuriti equipment, and the like. Electronic devices also include light in different wavelength bands, such as far-infrared wavelength band, infrared wavelength band, red wavelength band, yellow wavelength band, green wavelength band, blue wavelength band, purple wavelength band, and ultraviolet wavelength band. A combination of two or more types of semiconductor light emitting devices that emit light is also included. In particular, in a light emitting diode lighting device, a combination of two or more types of light emitting diodes that emit visible light in different wavelength bands among a red wavelength band, a yellow wavelength band, a green wavelength band, a blue wavelength band, a purple wavelength band, and the like, Two or more types of light emitted from these light emitting diodes can be mixed to obtain natural light or white light. In addition, a semiconductor light-emitting element that emits light in at least one of the blue wavelength band, the violet wavelength band, and the ultraviolet wavelength band is used as a light source, and the phosphor is irradiated with light emitted from the semiconductor light-emitting element. Natural light or white light can be obtained by mixing the light obtained by excitation. In addition, these light emitting diodes that emit visible light in different wavelength bands are, for example, cell units, quartet units, cluster units, and other collective units (strictly speaking, the number of light emitting diodes included in one unit of these units is A single unit name when a plurality of light emitting diodes that are not defined and emit light of the same wavelength or different wavelengths are formed in the same group and are mounted on a wiring board, wiring package, wiring housing wall, etc. In particular, for example, a unit composed of three light emitting diodes (for example, one red light emitting diode, one green light emitting diode, and one blue light emitting diode), Or four light emitting diodes (for example, one red light emitting diode, two green light emitting diodes, and blue light emitting diode). 1 unit), or units consisting of five or more light-emitting diodes, etc., and each unit is mounted on a substrate or plate, or on a housing plate in a two-dimensional array or in one or more rows. It may be.
In the third to seventh inventions, what has been described in relation to the first and second inventions is valid as long as it is not contrary to the nature thereof.

The eighth invention
A semiconductor element having a semiconductor layer including an active layer made of a semiconductor having a hexagonal crystal structure on a substrate made of a substance having a hexagonal crystal structure,
The main surface of the substrate is a {10-12} plane or a {11-20} plane, and the active layer has a slope formed of {1-100} facets. is there.
The ninth invention
A method of manufacturing a semiconductor device having a semiconductor layer including an active layer made of a semiconductor having a hexagonal crystal structure on a substrate made of a substance having a hexagonal crystal structure,
A substrate whose principal surface is a {10-12} plane or a {11-20} plane is used as the substrate, and the active layer is grown on the substrate so as to have a slope composed of {1-100} facets. It is characterized by that.

This semiconductor element includes a light emitting element such as a general light emitting diode, an intersubband transition emission type (quantum cascade type) light emitting diode, an ordinary semiconductor laser, and an intersubband transition emission type (quantum cascade type) semiconductor laser. In addition, electrons represented by transistors such as photodiodes and other light receiving elements or sensors, solar cells, and field effect transistors (FET) such as high electron mobility transistors and bipolar transistors such as heterojunction bipolar transistors (HBT). A running element is included. Here, the active layer means a light emitting region in a semiconductor light emitting device, a light receiving region in a semiconductor light receiving device, and a region in which electrons travel in an electron traveling device. One or a plurality of these elements are formed on the same substrate or chip. These elements are configured to be independently driven as necessary. An optoelectronic integrated circuit (OEIC) can be formed by integrating a light emitting element and an electron transit element on the same substrate. If necessary, an optical wiring can be formed. It is also possible to perform illumination communication or optical communication by supplying light using blinking of at least one semiconductor light emitting element (light emitting diode or semiconductor laser). In this case, illumination communication or optical communication may be performed using a plurality of lights of different wavelength bands.
In the eighth and ninth inventions, what has been described in relation to the first and second inventions is valid as long as it is not contrary to the nature thereof.

In the present invention configured as described above, since the {1-100} plane (m-plane) facet is a plane with a piezoelectric field of zero, the quantum confined Stark effect in the active layer can be effectively suppressed. In addition, when the active layer has an inclined surface made of {1-100} facets, and the inclined surface made of {1-100} facets forms an angle of 30 ° with the main surface of the substrate, the active layer is flat. In comparison, the total area of the active layer increases to 1 / cos 30 ° = 2/3 ^1/2 = 1.15 times, and the volume of the active layer can be increased accordingly. Furthermore, the growth of an active layer having a slope composed of {1-100} facets on a substrate whose principal surface is a {10-12} plane (r plane) or {11-20} plane (a plane) is: It can be easily performed with high controllability by controlling the growth conditions.

According to the present invention, the quantum confined Stark effect in the active layer can be suppressed, the volume of the active layer can be increased, the light emission output can be improved, and the semiconductor light emitting device can be easily manufactured. It is. A high-performance light source cell unit, backlight, illumination device, display, various electronic devices, and the like can be realized using this high-performance semiconductor light emitting element.
In addition, in a semiconductor device, particularly an electron transit device, the current drive capability can be increased by increasing the area of the active layer in which electrons travel, and the output can be greatly improved. The traveling element is easy to manufacture.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings of the embodiments, the same or corresponding parts are denoted by the same reference numerals.
FIG. 1 shows a light emitting diode according to a first embodiment of the present invention. This light-emitting diode uses a nitride III-V compound semiconductor such as GaN.
As shown in FIG. 1, this light-emitting diode has a hexagonal crystal structure, is made of a material transparent to visible light, and has a {10-12} plane (r-plane) or {11 On a flat substrate 11 composed of a −20} plane (a-plane), an n-type nitride III-V compound semiconductor layer 12, an n-type nitride III-V compound semiconductor layer 13, a nitride III- An active layer 14 using a V group compound semiconductor and a p-type nitride III-V group compound semiconductor layer 15 are sequentially stacked. The n-type nitride III-V compound semiconductor layer 13, the active layer 14, and the p-type nitride III-V compound semiconductor layer 15 are patterned in a mesa shape. A p-side electrode 16 is formed on the p-type nitride III-V compound semiconductor layer 15 in the mesa portion, and is in ohmic contact with the p-type nitride III-V compound semiconductor layer 15. . As the material of the p-side electrode 16, when light is extracted to the outside through the substrate 11, for example, it is preferable to use an ohmic metal having a high reflectance (for example, Ag or an alloy containing Ag as a main component). However, the present invention is not limited to this. An n-side electrode 17 is formed on the n-type nitride-based III-V compound semiconductor layer 12 adjacent to the mesa, and is in ohmic contact with the n-type nitride-based III-V compound semiconductor layer 12. is doing.

  In this light emitting diode, the n-type nitride III-V compound semiconductor layer 12 is preferentially grown in the {11-20} plane (a-plane) orientation, the n-type nitride III-V compound semiconductor layer 13 and The active layer 14 is preferentially grown in the {1-100} plane (m plane) orientation, and the p-type nitride III-V compound semiconductor layer 15 is preferentially grown in the {11-20} plane (a plane) orientation. Is. In this case, the upper part of the n-type nitride III-V compound semiconductor layer 13 has a sawtooth cross-sectional shape as viewed in a cross section perpendicular to the main surface of the substrate 11, and this n-type nitride III-V The slopes 13a and 13b of the group compound semiconductor layer 13 are formed by m-plane facets. Similarly, the active layer 14 on the n-type nitride III-V compound semiconductor layer 13 has a sawtooth cross-sectional shape as viewed in a cross section perpendicular to the main surface of the substrate 11. Fourteen slopes 14a and 14b are formed by m-plane facets. These m-plane facets are inclined by 30 ° with respect to the main surface of the substrate 11. The protrusions and recesses of these n-type nitride III-V compound semiconductor layer 13 and active layer 14 extend in the [0001] direction (c-axis direction).

Next, a method for manufacturing the light emitting diode will be described.
As shown in FIG. 2A, first, it has a hexagonal crystal structure, is made of a material that is transparent to visible light, and has a {10-12} plane (r-plane) or {11-20} plane as the principal plane. A flat substrate 11 made of (a surface) is prepared.
Next, as shown in FIG. 2B, the surface of the substrate 11 is cleaned by performing thermal cleaning or the like, and a GaN buffer layer or AlN is grown on the substrate 11 at a growth temperature of, for example, about 550 ° C. by a conventionally known method. A buffer layer (not shown) is grown, and an n-type nitride III-V compound semiconductor layer 12 is epitaxially grown thereon, for example, by MOCVD under the condition of preferential growth in the a-plane orientation. The upper surface of the n-type nitride III-V compound semiconductor layer 12 made of the a-plane is parallel to the main surface of the substrate 11.

Next, as shown in FIG. 2C, the n-type nitride III-V compound semiconductor layer 13 is epitaxially grown on the n-type nitride III-V compound semiconductor layer 12 under the condition of preferential growth in the m-plane orientation. . The upper portion of the n-type nitride III-V compound semiconductor layer 13 has a sawtooth cross-sectional shape, and the inclined surfaces 13a and 13b are m-plane facets.
Next, as shown in FIG. 3A, the active layer 14 is epitaxially grown on the n-type nitride-based III-V compound semiconductor layer 13 under the condition of preferential growth in the m-plane orientation. The active layer 14 has a sawtooth cross-sectional shape, and the slopes 14a, 14b are m-plane facets.
Next, as shown in FIG. 3B, the p-type nitride-based III-V compound semiconductor layer 15 is epitaxially grown on the active layer 14 under the condition of preferential growth in the a-plane orientation. The p-type nitride-based III-V group compound semiconductor layer 15 has an a-plane upper surface parallel to the main surface of the substrate 11.

The conditions for preferential growth of the n-type nitride III-V compound semiconductor layer 12 and the p-type nitride III-V compound semiconductor layer 15 in the a-plane orientation are, for example, a pressure of 300 Torr and a V / III ratio of the growth material The growth rate is 2000 or less, the growth rate is 4 μm / h or more, and the growth temperature is 1000 ° C. or more. The conditions for preferential growth of the n-type nitride-based III-V group compound semiconductor layer 13 and the active layer 14 in the m-plane orientation are, for example, a growth source having a V / III ratio of 2000 or higher, a growth temperature of 900 ° C. or higher, pressure and The growth rate is not particularly limited.
The growth source of the above-mentioned nitride III-V compound semiconductor layer is, for example, triethylgallium ((C ₂ H ₅ ) ₃ Ga, TEG) or trimethyl gallium ((CH ₃ ) ₃ Ga, TMG as a Ga source. ), Trimethylaluminum ((CH ₃ ) ₃ Al, TMA) as a raw material of Al, triethylindium ((C ₂ H ₅ ) ₃ In, TEI) or trimethylindium ((CH ₃ ) ₃ In, TMI), and ammonia (NH ₃ ) is used as a raw material for N. As for the dopant, for example, silane (SiH ₄ ) is used as the n-type dopant, and bis (methylcyclopentadienyl) magnesium ((CH ₃ C ₅ H ₄ ) ₂ Mg), bis (ethylcyclopenta) is used as the p-type dopant. Dienyl) magnesium ((C ₂ H ₅ C ₅ H ₄ ) ₂ Mg) or bis (cyclopentadienyl) magnesium ((C ₅ H ₅ ) ₂ Mg) is used. For the carrier gas atmosphere during the growth of the nitride-based III-V compound semiconductor layer, eg, H ₂ gas is used.

Next, the substrate 11 on which the nitride III-V compound semiconductor layer is grown in this way is taken out from the MOCVD apparatus.
Next, as shown in FIG. 1, the p-side electrode 16 is formed on the p-type nitride III-V compound semiconductor layer 15 by a lift-off method or the like.
Next, in order to activate the p-type impurity of the p-type nitride III-V compound semiconductor layer 15, for example, a mixed gas of N ₂ and O ₂ (composition is, for example, 99% N ₂ and O ₂ In a 1% atmosphere, heat treatment is performed at a temperature of 550 to 750 ° C. (for example, 650 ° C.) or 580 to 620 ° C. (for example, 600 ° C.). Here, for example, activation is easily caused by mixing O ₂ with N ₂ . Further, for example, nitrogen halide (NF ₃ , NCl _3, etc.) is mixed in a mixed gas atmosphere of N ₂ or N ₂ and O ₂ as a raw material such as F and Cl having high electronegativity as in O and N. You may do it. The time for this heat treatment is, for example, 5 minutes to 2 hours or 40 minutes to 2 hours, generally about 10 to 60 minutes. The reason for the relatively low temperature of the heat treatment is to prevent the active layer 14 and the like from being deteriorated during the heat treatment. This heat treatment may be performed after the p-type nitride-based III-V group compound semiconductor layer 15 is epitaxially grown and before the p-side electrode 16 is formed.
Next, as shown in FIG. 3C, the n-type nitride III-V compound semiconductor layer 13, the active layer 14, and the p-type nitride III-V compound semiconductor layer 15 are subjected to, for example, reactive ion etching ( RIE), powder blasting method, sand blasting method or the like, and patterning into a predetermined mesa shape.

Next, the n-side electrode 17 is formed on the n-type nitride-based III-V group compound semiconductor layer 12 adjacent to the mesa portion thus formed by a lift-off method or the like.
Next, if necessary, the substrate 11 on which the light emitting diode structure is formed as described above is reduced in thickness by grinding or lapping from the back side, and then the substrate 11 is scribed, Form. Thereafter, the bar is scribed to form a chip.
Thus, the target light emitting diode is manufactured.

  A specific structural example of the light emitting diode will be described. That is, for example, the nitride-based III-V group compound semiconductor layer 12 is an n-type GaN layer, and the n-type nitride-based III-V compound semiconductor layer 13 is an n-type GaInN layer, an n-type GaN layer, and an n-type in order from the bottom. A p-type GaInN layer, a p-type nitride III-V compound semiconductor layer 15 are a p-type GaInN layer, a p-type AlInN layer, a p-type GaN layer, and a p-type GaInN layer in order from the bottom. The active layer 14 has, for example, a GaInN-based multiple quantum well (MQW) structure (for example, one in which a GaInN quantum well layer and a GaN barrier layer are alternately stacked). It is selected according to the wavelength. For example, it is ˜11% at an emission wavelength of 405 nm, ˜18% at 450 nm, and ˜24% at 520 nm. As a material of the p-side electrode 16, for example, Ag or Pd / Ag is used. As the n-side electrode 17, for example, a Ti / Pt / Au structure is used.

  In the light emitting diode shown in FIG. 1, light is emitted by applying a forward voltage between the p-side electrode 16 and the n-side electrode 17 to flow current, and light is extracted through the substrate 11 to the outside. By selecting the In composition of the active layer 14, red to ultraviolet light emission can be obtained. In this case, of the light generated from the active layer 14, the light directed to the substrate 11 goes out through the substrate 11, and the light generated from the active layer 14 travels toward the p-side electrode 16. The light is reflected by the p-side electrode 16, travels toward the substrate 11, passes through the substrate 11, and goes outside. Since the slopes 14a and 14b formed of the m-plane facets on the upper surface and the lower surface of the active layer 14 are inclined by 30 ° with respect to both surfaces of the substrate 11, the light generated from the active layer 14 also faces various directions. As compared with the case where the active layer 14 is flat and parallel to the substrate 11, it is possible to efficiently extract light to the outside. This is shown in FIG.

  As described above, according to the first embodiment, the active layer 14 has a sawtooth cross-sectional shape when viewed in a cross section perpendicular to the main surface of the substrate 11, and the slopes 14 a and 14 b of the active layer 14. Is composed of m-plane facets, the piezoelectric field in this active layer 14 is zero, the quantum confined Stark effect in the active layer 14 can be effectively suppressed, and the emission volume is reduced by increasing the area of the active layer 14. It can be increased by a factor of 1.2. For this reason, the light emission output of the light emitting diode using the nitride III-V group compound semiconductor can be greatly improved. This light-emitting diode can be easily obtained by controlling conditions for preferential growth of a nitride III-V group compound semiconductor layer in the a-plane orientation or the m-plane orientation on the substrate 11 whose main surface is an r-plane or a-plane. Can be manufactured.

Next explained is a light emitting diode according to the second embodiment of the invention.
In this light emitting diode, all of the n-type nitride III-V compound semiconductor layer 12, the n-type nitride III-V compound semiconductor layer 13 and the active layer 14 are preferentially grown in the m-plane orientation, The p-type nitride III-V compound semiconductor layer 15 is preferentially grown in the a-plane orientation. Also in this case, the active layer 14 has a sawtooth cross-sectional shape when viewed in a cross section perpendicular to the main surface of the substrate 11, and the slopes 14a and 14b of the active layer 14 are formed by m-plane facets.

Next, a method for manufacturing the light emitting diode will be described.
As shown in FIG. 5A, when manufacturing this light emitting diode, an n-type nitride III-V compound semiconductor layer 12, an n-type nitride III-V compound semiconductor layer 13, and The active layer 14 is sequentially epitaxially grown under the condition of preferential growth in the m-plane orientation. The active layer 14 has a sawtooth cross-sectional shape, and the slopes 14a, 14b are m-plane facets.
Next, as shown in FIG. 5B, a p-type nitride-based III-V compound semiconductor layer 15 is epitaxially grown on the active layer 14 under the condition of preferential growth on the a-plane.
Except for the above, the method is the same as that of the light emitting diode according to the first embodiment.
According to the second embodiment, the same advantages as those of the first embodiment can be obtained.

Next explained is a light emitting diode according to the third embodiment of the invention.
In this light emitting diode, an n-type nitride III-V compound semiconductor layer 12, an n-type nitride III-V compound semiconductor layer 13, an active layer 14, and a p-type nitride III-V compound semiconductor layer The lower part of 15 is preferentially grown in the m-plane orientation, and the upper part of the p-type nitride III-V compound semiconductor layer 15 is preferentially grown in the a-plane orientation. Also in this case, the active layer 14 has a sawtooth cross-sectional shape when viewed in a cross section perpendicular to the main surface of the substrate 11, and the slopes 14a and 14b of the active layer 14 are formed by m-plane facets.

Next, a method for manufacturing the light emitting diode will be described.
As shown in FIG. 6A, when manufacturing this light emitting diode, an n-type nitride III-V compound semiconductor layer 12, an n-type nitride III-V compound semiconductor layer 13, The active layer 14 and the p-type nitride-based III-V group compound semiconductor layer 15 are epitaxially grown sequentially under conditions of preferential growth in the m-plane orientation. The active layer 14 has a sawtooth cross-sectional shape, and the slopes 14a, 14b are m-plane facets.
Next, as shown in FIG. 6B, the p-type nitride III-V compound semiconductor layer 15 is epitaxially grown under the condition of preferential growth in the a-plane orientation, and the p-type nitride III-V compound semiconductor layer 15 is formed. A desired thickness is obtained.
Except for the above, the method is the same as that of the light emitting diode according to the first embodiment.
According to the third embodiment, the same advantages as those of the first embodiment can be obtained.

Next explained is the fourth embodiment of the invention.
In the fourth embodiment, the substrate 11 on which the n-type nitride III-V compound semiconductor layer 12 is grown is as shown in FIG. 7A.
That is, as shown in FIG. 7A, first, it has a hexagonal crystal structure, is made of a material transparent to visible light, and has a principal surface of {10-12} plane (r-plane) or {11-20 } A flat substrate 11 having a plane (a-plane) is prepared, and convex portions 21 having an isosceles triangular cross section are periodically formed in a predetermined plane shape on the substrate 11. A concave portion 22 having an inverted trapezoidal cross-sectional shape is formed between the convex portions 21. As the substrate 11, for example, those already described can be used, and specifically, for example, an r-plane or a-plane sapphire substrate. The planar shape of the convex portion 21 and the concave portion 22 can be the various planar shapes already described. For example, as shown in FIG. 10, both the convex portion 21 and the concave portion 22 have a stripe shape extending in one direction. In other cases, as shown in FIG. 11, the convex portion 21 has a hexagonal planar shape and is two-dimensionally arranged in a honeycomb shape. For example, the direction of the dotted line in FIG. 10 (direction perpendicular to the stripe) is parallel to the c-axis of the n-type nitride III-V compound semiconductor layer 12 described later, and the direction of the dotted line in FIG. 21) is made parallel to the m-axis of an n-type nitride-based III-V compound semiconductor layer 12 described later. The materials described above can be used as the material of the convex portion 21, but from the viewpoint of ease of processing, for example, a SiO ₂ or SiN film is preferably used.

In order to form the convex portion 21 having an isosceles triangular cross section on the substrate 11, a conventionally known method can be used. For example, a film (for example, a SiO ₂ film or a SiN film) used as the material of the convex portion 21 is formed on the entire surface of the substrate 11 by a CVD method, a vacuum evaporation method, a sputtering method, or the like. Next, a resist pattern having a predetermined shape is formed on the film by lithography. Next, this film is etched using this resist pattern as a mask under conditions where taper etching is performed by the RIE method or the like, thereby forming a convex portion 21 having an isosceles triangular cross section.

  Next, the surface of the substrate 11 and the convex portion 21 is cleaned by performing thermal cleaning or the like, and then, for example, a GaN buffer layer or an AlN buffer is formed on the substrate 11 at a growth temperature of, for example, about 550 ° C. A layer (not shown) is grown. Next, the n-type nitride III-V compound semiconductor is epitaxially grown by, for example, MOCVD. At this time, as shown in FIG. 7B, growth is first started from the bottom surface of the recess 22 to generate a plurality of micronuclei 23 made of a nitride III-V compound semiconductor. Next, as shown in FIG. 7C, an isosceles triangular shape having a bottom face of the recess 22 as a base and a facet inclined with respect to the main surface of the substrate 11 on the slope through the growth and coalescence process of the micronuclei 23. The n-type nitride III-V compound semiconductor layer 12 is grown so as to be. In this example, the height of the n-type nitride-based III-V group compound semiconductor layer 12 having an isosceles triangular cross-sectional shape is larger than the height of the convex portion 21. For example, the extending direction of the n-type nitride-based III-V compound semiconductor layer 12 is the [0001] direction, and the inclined surface is formed of a (1-101) plane facet. The growth conditions of the n-type nitride III-V compound semiconductor layer 12 will be described later.

Subsequently, by performing growth of the n-type nitride III-V compound semiconductor layer 12 while maintaining the facet plane orientation of the slope, as shown in FIG. 8A, the n-type nitride III-V compound Both end portions of the semiconductor layer 12 are grown to the lower portion of the side surface of the convex portion 21 so that the cross-sectional shape becomes a pentagonal shape.
Next, when the growth condition is set to a condition in which the lateral growth is dominant and the growth is continued, as shown in FIG. 8B, the n-type nitride-based III-V compound semiconductor layer 12 is indicated by an arrow. It grows laterally and spreads on the convex portion 21 in a state where the cross-sectional shape becomes a hexagonal shape. In FIG. 8B, a dotted line indicates a growth interface in the middle of growth (the same applies hereinafter).
When the lateral growth is further continued, as shown in FIG. 8C, the n-type nitride III-V compound semiconductor layer 12 grows while increasing its thickness, and finally grows from the adjacent recess 22. The physical group III-V compound semiconductor layers 12 come into contact with each other on the convex portion 21 and are associated with each other.
Subsequently, as shown in FIG. 8C, the n-type nitride-based III-V group compound semiconductor layer 12 is grown in the lateral direction until the surface thereof becomes a flat surface parallel to the main surface of the substrate 11. In the n-type nitride III-V compound semiconductor layer 12 grown in this way, the dislocation density in the portion above the recess 22 is extremely low.
In some cases, the state shown in FIG. 7C can be shifted directly to the state shown in FIG. 8B without going through the state shown in FIG. 8A.

Next, as shown in FIG. 9, as in the first embodiment, an n-type nitride III-V group is formed on the n-type nitride III-V compound semiconductor layer 12 by MOCVD, for example. The compound semiconductor layer 13, the active layer 14, and the p-type nitride III-V compound semiconductor layer 15 are epitaxially grown sequentially.
Next, the substrate 11 on which the nitride III-V compound semiconductor layer is grown in this way is taken out from the MOCVD apparatus.
Thereafter, similarly to the first embodiment, the steps after the formation of the p-side electrode 16 are advanced to manufacture the target light emitting diode.

  In the light emitting diode shown in FIG. 9 thus obtained, light is emitted by applying a forward voltage between the p-side electrode 16 and the n-side electrode 17 to flow current, and light is transmitted through the substrate 11 to the outside. Take out. In this case, of the light generated from the active layer 14, the light directed to the substrate 11 is refracted at the interface between the substrate 11 and the n-type nitride-based III-V compound semiconductor layer 12 of the recess 22, and then the substrate 11. Of the light generated from the active layer 14, the light traveling toward the p-side electrode 16 is reflected by the p-side electrode 16, travels toward the substrate 11, and exits through the substrate 11. Go.

In the fourth embodiment, in order to minimize the threading dislocation density of the n-type nitride-based III-V compound semiconductor layer 12, the width W _g of the bottom surface of the concave portion 22, the depth of the concave portion 22, that is, the convexity The height d of the portion 21 and the angle α between the inclined surface of the n-type nitride III-V compound semiconductor layer 12 and the main surface of the substrate 11 in the state shown in FIG. (See FIG. 12).
2d ≧ W _g tan α
For example, when W _g = 2.1 μm and α = 59 °, d ≧ 1.75 μm, W _g = 2 μm, and when α = 59 °, d ≧ 1.66 μm, W _g = 1.5 μm, α When d = 59 °, d ≧ 1.245 μm, W _g = 1.2 μm, and when α = 59 °, d ≧ 0.966 μm. However, in any case, it is desirable that d <5 μm.

During the growth of the n-type nitride-based III-V compound semiconductor layer 12 in the steps shown in FIGS. 7B and C and FIG. 8A, it is preferable to set the growth temperature to a low value so as to increase the V / III ratio of the growth material. Specifically, when the growth of the n-type nitride III-V compound semiconductor layer 12 is performed under a pressure condition of 1 atm, the growth source has a V / III ratio in the range of, for example, 13000 ± 2000, and a growth temperature. For example, it is preferable to set in the range of 1100 ± 50 ° C. Regarding the V / III ratio of the growth raw material, when the growth of the n-type nitride-based III-V compound semiconductor layer 12 is performed under a pressure condition of x atmospheric pressure, Bernoulli's law that defines the relationship between the flow velocity and the pressure is used. It is preferable to set the V / III ratio corresponding to the square of the amount of change in pressure, specifically, approximately (13000 ± 2000) × x ² . For example, when the growth is performed at 0.92 atmospheres (700 Torr), the V / III ratio of the growth raw material is preferably set to a range of 11000 ± 1700 (for example, 10530). x is generally from 0.01 to 2 atmospheres. As for the growth temperature, when growth is performed under a pressure condition of 1 atm or less, the lateral growth of the n-type nitride III-V compound semiconductor layer 12 is suppressed, and the n-type nitride III- In order to facilitate the selective growth of the group V compound semiconductor layer 12, it is preferable to set the growth temperature lower. For example, when growth is performed at 0.92 atmospheres (700 Torr), the growth temperature is preferably set in a range of 1050 ± 50 ° C. (for example, 1050 ° C.). By doing so, the n-type nitride III-V compound semiconductor layer 12 grows as shown in FIGS. 7B and C and FIG. 8A. At this time, the growth of the n-type nitride III-V compound semiconductor layer 12 does not start from above the convex portion 21. The growth rate is generally 0.5 to 5.0 μm / h, preferably about 3.0 μm / h. When the n-type nitride III-V compound semiconductor layer 12 is a GaN layer, for example, the flow rate of the source gas is 20 SCCM for TMG and 20 SLM for NH ₃ , for example. On the other hand, in the growth (lateral growth) of the n-type nitride III-V compound semiconductor layer 12 in the steps shown in FIGS. 8B and 8C, the growth temperature is set high while the V / III ratio of the growth material is low. . Specifically, when the growth of the n-type nitride III-V compound semiconductor layer 12 is performed under a pressure condition of 1 atm, the growth source has a V / III ratio in the range of 5000 ± 2000, for example, and a growth temperature. For example, it is set in the range of 1200 ± 50 ° C. Regarding the V / III ratio of the growth raw material, when the growth of the n-type nitride-based III-V compound semiconductor layer 12 is performed under a pressure condition of x atmospheric pressure, Bernoulli's law that defines the relationship between the flow velocity and the pressure is used. It is preferable to set the V / III ratio corresponding to the square of the amount of change in pressure, specifically, approximately (5000 ± 2000) × x ² . For example, when the growth is performed at 0.92 atmospheres (700 Torr), the V / III ratio of the growth material is preferably set in the range of 4200 ± 1700 (for example, 4232). Regarding the growth temperature, when growth is performed under a pressure condition of 1 atm or less, the surface of the n-type nitride III-V compound semiconductor layer 12 is prevented from being roughened and the lateral growth is favorably performed. It is preferable to set a low growth temperature. For example, when growth is performed at 0.92 atmospheres (700 Torr), the growth temperature is preferably set in the range of 1150 ± 50 ° C. (eg, 1110 ° C.). When the n-type nitride III-V compound semiconductor layer 12 is a GaN layer, for example, the flow rate of the source gas is, for example, 40 SCCM for TMG and 20 SLM for NH ₃ . By doing so, the n-type nitride III-V compound semiconductor layer 12 is laterally grown as shown in FIGS. 8B and 8C. At this time, no gap is generated between the n-type nitride III-V compound semiconductor layer 12 and the substrate 11.

FIG. 13 schematically shows the flow of the source gas during the growth of the GaN layer and the state of diffusion on the substrate 11 as an example of the n-type nitride-based III-V group compound semiconductor layer 12. The most important point in this growth is that GaN does not grow on the convex portion 21 of the substrate 11 and growth of GaN starts in the concave portion 22 in the early stage of growth. In FIG. 13, the cross-sectional shape of the convex portion 21 is triangular, but GaN does not grow on the convex portion 21 even if the cross-sectional shape of the convex portion 21 is trapezoidal. In general, GaN is grown by using TMG as a Ga raw material and NH ₃ as an N raw material. Ga (CH ₃ ) ₃ (g) + 3 / 2H ₂ (g) → Ga (g) + 3CH ₄ ( g)
NH ₃ (g) → (1-α) NH ₃ (g) + α / 2N ₂ (g) + 3α / 2H ₂ (g)
Ga (g) + NH ₃ (g) = GaN (s) + 3 / 2H ₂ (g)
As represented by the following reaction formula, this occurs when NH ₃ and Ga react directly. At this time, H ₂ gas is generated, and this H ₂ gas has an action opposite to crystal growth, that is, an etching action. In the steps shown in FIGS. 7B and C and FIG. 8A, by using conditions that are not performed in the conventional growth of GaN on a flat substrate, that is, conditions that increase the etching action and are difficult to grow (increase the V / III ratio). The growth at the convex portion 21 is suppressed. On the other hand, since the etching action is weakened inside the recess 22, crystal growth occurs. Furthermore, conventionally, in order to improve the flatness of the surface of the grown crystal, the growth is performed under conditions (higher temperatures) in which the degree of lateral growth is increased. In this fourth embodiment, threading dislocations are formed on the main surface of the substrate 11. For the purpose of reducing the thickness of the recess 22 by bending it in a direction parallel to the n-type nitride group III-V compound semiconductor layer 12 at an earlier stage (as already described). For example, it is grown at 1050 ± 50 ° C.

FIG. 14 schematically shows the crystal defect distribution of the n-type nitride-based III-V compound semiconductor layer 12. In FIG. 14, the code | symbol 24 shows a threading dislocation. As can be seen from FIG. 14, although the dislocation density is high in the vicinity of the central portion of the convex portion 21, that is, in the association portion between the n-type nitride III-V compound semiconductor layers 12 grown from the concave portions 22 adjacent to each other. The dislocation density is low in other parts including the part above the recess 22. For example, when the depth d of the concave portion 22 is 1 μm and the width W _{g of} the bottom surface is 2 μm, the dislocation density of this low dislocation density portion is about 6 × 10 ⁷ / cm ^2, and the substrate 11 with the unevenness processed is used. The dislocation density is reduced by 1 to 2 digits as compared with the case of not being present. It can also be seen that the occurrence of dislocations in the vertical direction with respect to the side wall of the recess 22 does not occur.
In FIG. 14, the average thickness of the high dislocation density and poor crystallinity of the n-type nitride III-V compound semiconductor layer 12 in contact with the substrate 11 in the recess 22 is in contact with the substrate 11 in the protrusion 21. The n-type nitride III-V compound semiconductor layer 12 has a high dislocation density and is about 1.5 times the average thickness of a region with poor crystallinity. This is a result reflecting that the n-type nitride III-V compound semiconductor layer 12 grows in the lateral direction on the convex portion 21.
FIG. 15 shows a distribution of threading dislocations 24 when the convex portion 21 has the planar shape shown in FIG. FIG. 16 shows a distribution of threading dislocations 24 when the convex portion 21 has the planar shape shown in FIG.

FIG. 17 shows a simulation (ray tracing simulation) of how much the light extraction efficiency from the light emitting diode to the outside improves when the depth of the unevenness of the substrate 11 is changed compared to a flat case where the unevenness is not formed. An example of the results obtained is shown. The light extraction is performed from the back side of the substrate 11. In FIG. 17, the horizontal axis indicates the depth of the concave portion 22 (height of the convex portion 21), and the vertical axis indicates the degree of improvement in light extraction efficiency η (light extraction magnification) with respect to the case where the convex portion 22 is not formed. However, the convex portion 21 has a stripe shape extending in one direction, the angle θ formed between the side surface of the convex portion 21 and one main surface of the substrate 11 is 135 °, and the length of the bottom side of the concave portion W _g = 2 μm and the length of the bottom side of the convex portion 21 = 3 μm. The refractive index of the substrate 11 was assumed to be 1.77, and the refractive index of the n-type nitride III-V compound semiconductor layer 12 was assumed to be 2.35. From FIG. 17, the light extraction magnification is 1.35 times or more when the depth of the recess 22 is 0.3 μm or more, 1.5 times or more when the depth of 0.5 μm or more and 2.5 μm or less, and 0.7 μm or more and 2.15 μm or less. 1.75 times or more, 1 μm or more and 1.75 μm or less is 1.85 times or more, and about 1.3 μm is the maximum (about 1.95).

According to the fourth embodiment, the same advantages as those of the first embodiment can be obtained, and the following advantages can also be obtained. That is, since no gap is formed between the substrate 11 and the n-type nitride-based III-V compound semiconductor layer 12, it is possible to prevent a decrease in light extraction efficiency due to the gap. Further, the threading dislocations 24 of the n-type nitride III-V compound semiconductor layer 12 are concentrated near the center of the convex portion 21 of the substrate 11, and the dislocation density in other portions is, for example, about 6 × 10 ⁷ / cm ^2. As compared with the case of using a conventional concavo-convex processed substrate, the nitride type III-, such as the n-type nitride group III-V compound semiconductor layer 12 and the active layer 14 grown thereon, is reduced. The crystallinity of the group V compound semiconductor layer is greatly improved, and the non-luminescent center is also greatly reduced. As a result, a nitride III-V compound semiconductor light emitting diode with extremely high luminous efficiency can be obtained.
In addition, the epitaxial growth necessary for manufacturing the nitride-based III-V compound semiconductor light-emitting diode is only required once, and not only a growth mask is not required, but also the convex portion 21 on the substrate 11 is formed on the substrate 11. Since a film that forms the material of the convex portion 21, for example, a film such as a SiO ₂ film or a SiN film, can be formed only by etching, a substrate 11 such as a sapphire substrate that is difficult to process unevenly. Therefore, a nitride-based III-V compound semiconductor light-emitting diode can be manufactured at low cost.

Next explained is the fifth embodiment of the invention.
In the fifth embodiment, as shown in FIG. 18A, convex portions 21 having a trapezoidal cross section are periodically formed in a predetermined plane shape on a substrate 11. A concave portion 22 having an inverted trapezoidal cross-sectional shape is formed between the convex portions 21.
Next, the n-type nitride III-V compound semiconductor layer 12 is grown in the same manner as in the fourth embodiment. Specifically, as shown in FIG. 18B, the n-type having an isosceles triangular cross-section with the bottom surface of the recess 22 as the bottom through the process of generation, growth and coalescence of the micronuclei 23 on the bottom surface of the recess 22 The nitride-based III-V group compound semiconductor layer 12 is grown, and further undergoes lateral growth, and as shown in FIG. 19C, the n-type nitride-based III-V group compound has a flat surface and a low threading dislocation density. The semiconductor layer 12 is grown.
Next, the process proceeds in the same manner as in the fourth embodiment, and the target nitride-based III-V compound semiconductor light-emitting diode is manufactured as shown in FIG.
Other than the above, this is the same as in the first and fourth embodiments.
20A and 20B show transmission electron micrographs of GaN preferentially grown in the m-plane orientation. Here, FIG. 20A is a cross-sectional view, and FIG. 21B is a bird's-eye view.
FIG. 21 schematically shows the crystal defect distribution of the n-type nitride-based III-V compound semiconductor layer 12. FIG. 22 shows a transmission electron micrograph of the n-type nitride-based III-V compound semiconductor layer 12 in the portion above the recess 22 of the substrate 11. From FIG. 22, a direction inclined by 120 to 150 ° with respect to one principal surface of the substrate 11 from the interface between the n-type nitride-based III-V group compound semiconductor layer 12 and the bottom surface of the recess 22 of the substrate 11, and this one principal surface. It can be seen that dislocations are generated in the vertical direction. In FIG. 21, illustration of dislocations generated in the direction perpendicular to one main surface of the substrate 11 is omitted.
According to the fifth embodiment, the same advantages as those of the first and fourth embodiments can be obtained.

FIG. 23 to FIG. 25 show an example of the result of simulation of the change in the light extraction efficiency from the light emitting diode to the outside when the substrate 11 is uneven and when the substrate 11 is flat. In either case, light extraction is performed from the back side of the substrate 11.
In FIG. 23, the horizontal axis indicates the refractive index of the convex portion 21, and the vertical axis indicates the degree of improvement in light extraction efficiency η (light extraction magnification) with respect to the case where the convex portion 21 is not formed. In FIG. 23, the data ▲ is obtained when the convex portion 21 has the one-dimensional stripe shape shown in FIG. 10 (1D), and the data ● indicates that the one-dimensional stripe-shaped convex portions 21 are provided orthogonal to each other. The case of a two-dimensional array (2D) is shown. However, the angle θ formed between the side surface of the convex portion 21 and one main surface of the substrate 11 is 135 °, the length W _g of the bottom side of the concave portion 22 is 2 μm, and the length of the bottom side of the convex portion 21 is 3 μm. The refractive index of the substrate 11 was assumed to be 1.77, and the refractive index of the n-type nitride III-V compound semiconductor layer 12 was assumed to be 2.35. From FIG. 23, the light extraction magnification becomes maximum when the refractive index of the convex portion 21 is 1.4 in both 1D and 2D, and becomes sufficiently large in the range of the refractive index of 1.2 to 1.7. It can be seen that the light extraction magnification is larger than that of 1D.
This result is the same when the cross-sectional shape of the convex portion 21 is triangular as in the fourth embodiment.

In FIG. 24, the horizontal axis indicates the angle θ formed by the side surface of the convex portion 21 and one main surface of the substrate 11, and the vertical axis indicates the light extraction magnification. In FIG. 24, the data ▲ is obtained when the convex portion 21 has the one-dimensional stripe shape shown in FIG. 10 (1D), and the data ● represents that the convex portions 21 having the one-dimensional stripe shape are provided orthogonal to each other. The case of a two-dimensional array (2D) is shown. However, the length W _g of the bottom side of the concave portion 22 is 3 μm, and the length of the bottom side of the convex portion 21 is 2 μm. The refractive index of the substrate 11 was assumed to be 1.77, the refractive index of the convex portion 21 was assumed to be 1.4, and the refractive index of the n-type nitride III-V compound semiconductor layer 12 was assumed to be 2.35. From FIG. 24, the light extraction magnification is as large as 1.55 times or more in the range of 100 ° <θ <160 °, and the angle θ formed by the side surface of the convex portion 21 with one main surface of the substrate 11 in both 1D and 2D is 132 °. In the range of <θ <139 °, it is extremely large as 1.75 times or more, especially, it becomes maximum when θ = 135 °, or even in the range of 147 ° <θ <154 °, it is extremely large as 1.75 times or more, especially θ = 152. It can be seen that the maximum is at °, and the light extraction magnification is larger in 2D than in 1D.
This result is the same when the cross-sectional shape of the convex portion 21 is triangular as in the fourth embodiment.

In FIG. 25, the horizontal axis indicates the depth d of the concave portion 22, and the vertical axis indicates the degree of improvement in light extraction efficiency η (light extraction magnification) with respect to the case where the convex portion 21 is not formed. The convex portion 21 has a one-dimensional stripe shape shown in FIG. However, the ratio between the length W _g of the bottom side of the concave portion 22 and the length of the bottom side of the convex portion 21 is 3: 2. The refractive index of the substrate 11 was assumed to be 1.77, the refractive index of the convex portion 21 was assumed to be 1.4, and the refractive index of the n-type nitride III-V compound semiconductor layer 12 was assumed to be 2.35. From FIG. 25, it can be seen that the light extraction magnification increases as the depth of the recess 22 increases.

Next, a sixth embodiment of the present invention will be described.
In the sixth embodiment, the steps up to the formation of the p-side electrode 16 are the same as those in any of the first to fifth embodiments, but the subsequent steps are different. Here, the p-side electrode 16 is preferably formed by interposing a layer containing Pd in order to prevent diffusion of an electrode material (for example, Ag), and forming stress, heat, and an upper layer thereon. A high melting point such as Ti, W, Cr, or alloys thereof to prevent the occurrence of defects due to diffusion of Au or Sn to the p-side electrode 16 from layers containing Au or Sn (solder layers, bumps, etc.) By forming a metal or a nitride of these metals (TiN, WN, TiWN, CrN, or the like), a technique used as an amorphous barrier metal layer without grain boundaries is applied. Here, a technique for interposing a layer containing Pd is known as a Pd intervening layer in, for example, a metal plating technique, and the barrier metal layer material is well known in an Al wiring technique, an Ag wiring technique, or the like of a Si-based electronic device. It is.

That is, in the sixth embodiment, as shown in FIG. 26A, after the p-side electrode 16 is formed, the Ni film 41 is formed so as to cover the p-side electrode 16 by a lift method or the like. Next, although illustration is omitted, for example, a Pd film is formed so as to cover the Ni film 41, and a metal nitride film such as TiN, WN, TiWN, CrN, etc. is formed so as to cover the Pd film, Further, if necessary, a film of Ti, W, Mo, Cr, or an alloy thereof is formed so as to cover this film. However, the Ni film 41 is not formed, but instead, a Pd film is formed so as to cover the p-side electrode 16, and a film such as TiN, WN, TiWN, CrN is formed so as to cover the Pd film, If necessary, a film of Ti, W, Mo, Cr, or an alloy thereof may be formed so as to cover this film.
Next, as shown in FIG. 26B, a resist pattern 42 having a predetermined shape is formed by lithography to cover layers such as the Ni film 41 and the Pd film thereon.
Next, as shown in FIG. 26C, the mesa portion is formed to have a trapezoidal cross-sectional shape by etching using, for example, the RIE method using the resist pattern 42 as a mask. The angle formed by the slope of the mesa portion and the main surface of the substrate 11 is, for example, about 35 degrees. A λ / 4 dielectric film (λ: emission wavelength) is formed on the slope of the mesa portion as necessary.

Next, as shown in FIG. 26D, the n-side electrode 17 is formed on the n-type nitride-based III-V compound semiconductor layer 12.
Next, as shown in FIG. 26E, an SiO ₂ film 43 is formed as a passivation film on the entire surface of the substrate. In consideration of adhesion to the base, durability, and corrosion resistance in the process, a SiN film or a SiON film may be used instead of the SiO ₂ film 43.
Next, as shown in FIG. 26F, after the SiO ₂ film 43 is etched back and thinned, an Al film 44 is formed as a reflective film on the SiO ₂ film 43 on the slope of the mesa portion. The Al film 44 is for reflecting the light generated from the active layer 14 toward the substrate 11 and improving the light extraction efficiency. One end of the Al film 44 is formed in contact with the n-side electrode 17. This is because reflection of light is increased by preventing a gap from being formed between the Al film 44 and the n-side electrode 17. Thereafter, the SiO ₂ film 43 is formed again to have a thickness necessary for the passivation film.

Next, as shown in FIG. 26G, portions of the SiO ₂ film 43 above the Ni film 41 and the n-side electrode 17 are removed by etching to form openings 45 and 46, and Ni film 41 and The n-side electrode 17 is exposed.
Next, as shown in FIG. 26H, a pad electrode 47 is formed on the Ni film 41 in the opening 45 portion, and a pad electrode 48 is formed on the n-side electrode 17 in the opening 46 portion.
Next, as shown in FIG. 26I, after a bump mask material 49 is formed on the entire surface of the substrate, a portion of the bump mask material 49 above the pad electrode 48 is removed by etching to form an opening 50. The pad electrode 48 is exposed.

Next, as shown in FIG. 26J, Au bumps 51 are formed on the pad electrodes 48 using a bump mask material 49. Next, the bump mask material 49 is removed. Next, after a bump mask material (not shown) is formed again on the entire surface of the substrate, an opening is formed by etching away a portion of the bump mask material above the pad electrode 47, and the pad electrode 47 is formed in this portion. To expose. Next, an Au bump 52 is formed on the pad electrode 47.
Next, if necessary, the substrate 11 on which the light emitting diode structure is formed as described above is reduced in thickness by grinding or lapping from the back side, and then the substrate 11 is scribed, Form. Thereafter, the bar is scribed to form a chip.

Next explained is a light emitting diode according to the seventh embodiment of the invention.
FIG. 27 shows this light emitting diode.
As shown in FIG. 27, in this light emitting diode, a growth mask 25 made of, for example, a SiO ₂ film is formed on the substrate 11, and an n-type is formed on the substrate 11 in a portion not covered with the growth mask 25. The nitride III-V compound semiconductor layer 13 is preferentially grown in the m-plane orientation. The n-type nitride III-V compound semiconductor layer 13 extends, for example, in the c-axis direction, and has a side surface perpendicular to the surface of the substrate 11 and a slope inclined by 30 ° with respect to the surface of the substrate 11. It has a pentagonal cross-sectional shape. An active layer 14 is preferentially grown in the m-plane direction on the surface of the n-type nitride III-V compound semiconductor layer 13. Then, the p-type nitride-based III-V group compound semiconductor layer 15 is preferentially grown on the a-plane so as to cover the active layer 14 and the growth mask 25. A p-side electrode 16 is formed on the p-type nitride III-V compound semiconductor layer 15. Although not shown in FIG. 27, for example, the p-type nitride III-V compound semiconductor layer 15 and the active layer at one end in the longitudinal direction of the n-type nitride III-V compound semiconductor layer 13 14 is removed, and one end of the n-type nitride III-V compound semiconductor layer 13 is exposed at this portion, and an n-side electrode 17 is formed at this one end.
Other than the above are the same as those in the first embodiment unless they are contrary to the properties.

According to the seventh embodiment, the slopes 14a and 14b of the active layer 14 are formed of m-plane facets as viewed in a cross section perpendicular to the main surface of the substrate 11, so that the piezoelectric field in the active layer 14 is zero. In addition, the quantum confined Stark effect in the active layer 14 can be effectively suppressed. Further, since the active layer 14 is formed on the side surface and the slope of the pentagonal n-type nitride-based III-V group compound semiconductor layer 13, the active layer 14 is compared with the case where the active layer 14 is flat. The area of 14 can be increased, for example, by about 1.5 to 2 times, and thus the emission volume can be increased by about 1.5 to 2 times. For this reason, the light emission output of the light emitting diode using the nitride III-V group compound semiconductor can be greatly improved. In addition, this light-emitting diode can be easily obtained by controlling the conditions for preferential growth of a nitride III-V group compound semiconductor layer in the m-plane or a-plane orientation on the substrate 11 whose main surface is an r-plane or a-plane. Can be manufactured.
Next explained is a light emitting diode according to the eighth embodiment of the invention.
In this light-emitting diode, an n-type substrate such as an n-type GaN substrate whose main surface is an r-plane or an a-plane is used as the substrate 11 in the light-emitting diode shown in FIG. An n-side electrode 17 is formed on the back surface of the n-type substrate 11.
Other than the above, the light emitting diode is the same as that of the seventh embodiment.
According to the eighth embodiment, the same advantages as those of the seventh embodiment can be obtained.

Next, a ninth embodiment of the invention will be described.
In the ninth embodiment, in addition to the blue light emitting diode and the green light emitting diode obtained by the method according to any one of the first to eighth embodiments, a separately prepared red light emitting diode (for example, A case where a light emitting diode backlight is manufactured using an AlGaInP light emitting diode) will be described.
For example, a blue light emitting diode structure is formed on the substrate 11 by the method according to the first embodiment, and bumps (not shown) are formed on the p-side electrode 16 and the n-side electrode 17, respectively. Thus, a blue light emitting diode is obtained in the form of a flip chip. Similarly, a green light emitting diode is obtained in the form of a flip chip. On the other hand, as a red light emitting diode, an AlGaInP light emitting diode is formed by stacking an AlGaInP semiconductor layer on an n-type GaAs substrate to form a diode structure and forming a p-side electrode thereon. It shall be used in the form.

Then, after mounting the red light emitting diode chip, the green light emitting diode chip, and the blue light emitting diode chip on a submount made of AlN or the like, each of them is mounted on the submount, for example, an Al substrate or the like. Mount in a predetermined arrangement on the substrate. This state is shown in FIG. 28A. In FIG. 28A, reference numeral 61 denotes a substrate, 62 denotes a submount, 63 denotes a red light emitting diode chip, 64 denotes a green light emitting diode chip, and 65 denotes a blue light emitting diode chip. The chip size of the red light emitting diode chip 63, the green light emitting diode chip 64, and the blue light emitting diode chip 65 is, for example, 350 μm square. Here, the red light emitting diode chip 63 is mounted such that the n-side electrode is on the submount 62, and the green light emitting diode chip 64 and the blue light emitting diode chip 65 are the p side electrode and the n side. The electrode is placed on the submount 62 through the bump. An extraction electrode (not shown) for an n-side electrode is formed in a predetermined pattern shape on the submount 62 on which the red light emitting diode chip 63 is mounted, and a red portion is formed on a predetermined portion on the extraction electrode. The n-side electrode side of the light emitting diode chip 63 for light emission is mounted. A wire 67 is bonded to the p-side electrode of the red light emitting diode chip 63 and a predetermined pad electrode 66 provided on the substrate 61, and the lead electrode A wire (not shown) is bonded to one end and another pad electrode provided on the substrate 61 so as to connect them. On the submount 62 on which the green light emitting diode chip 64 is mounted, a lead electrode for the p-side electrode and a lead electrode for the n-side electrode (both not shown) are respectively formed in a predetermined pattern shape. Bumps in which the p-side electrode and the n-side electrode side of the light emitting diode chip 64 for green light emission are formed on the lead-out electrode for the p-side electrode and the lead-out electrode for the n-side electrode are formed on them. Are each mounted through. A wire (not shown) is bonded to one end of the lead electrode for the p-side electrode of the green light emitting diode chip 64 and a pad electrode provided on the substrate 61 so as to connect them. In addition, a wire (not shown) is bonded to one end of the extraction electrode for the n-side electrode and a pad electrode provided on the substrate 61 so as to connect them. The same applies to the light-emitting diode chip 65 that emits blue light.
However, the submount 62 is omitted, and the red light emitting diode chip 63, the green light emitting diode chip 64, and the blue light emitting diode chip 65 are directly connected to any printed wiring board or printed wiring board having heat dissipation properties. It is also possible to mount directly on a plate having the above function, or on the inner and outer walls of the housing (for example, the inner wall of the chassis), thereby reducing the cost of the light emitting diode backlight or the entire panel.

The red light emitting diode chip 63, the green light emitting diode chip 64, and the blue light emitting diode chip 65 as described above are set as one unit (cell), and a necessary number of them are arranged on the substrate 61 in a predetermined pattern. . An example is shown in FIG. Next, as shown in FIG. 28B, potting of the transparent resin 68 is performed so as to cover this one unit. Thereafter, the transparent resin 68 is cured. By this curing process, the transparent resin 68 is solidified and is slightly reduced accordingly (FIG. 28C). Thus, as shown in FIG. 30, a light emitting diode chip 63 that emits red light, a light emitting diode chip 64 that emits green light, and a light emitting diode chip 65 that emits blue light are arranged as an array on a substrate 61. A diode backlight is obtained. In this case, since the transparent resin 68 is in contact with the back surface of the substrate 11 of the green light emitting diode chip 64 and the blue light emitting diode chip 65, the back surface of the substrate 11 is in direct contact with air. Accordingly, the difference in refractive index is reduced, and therefore the ratio of the light that is transmitted through the substrate 11 and exits to the outside is reflected by the back surface of the substrate 11, thereby improving the light extraction efficiency, thereby improving the light emission efficiency. Will improve.
This light emitting diode backlight is suitable for use in a backlight of a liquid crystal panel, for example.

Next explained is the tenth embodiment of the invention.
In the tenth embodiment, as in the ninth embodiment, a red light emitting diode chip 63, a green light emitting diode chip 64, and a blue light emitting diode chip 65 are arranged on a substrate 61 in a predetermined pattern. Then, as shown in FIG. 31, a transparent resin 69 suitable for the light emitting diode chip 63 is potted so as to cover the red light emitting diode chip 63, and the green light emitting diode chip 64 is mounted. The transparent resin 70 suitable for the light emitting diode chip 64 is potted so as to cover, and the transparent resin 71 suitable for the light emitting diode chip 65 is potted so as to cover the blue light emitting diode chip 65. Thereafter, the curing treatment of the transparent resins 69 to 71 is performed. By this curing process, the transparent resins 69 to 71 are solidified and are slightly reduced accordingly. In this way, a light emitting diode backlight in which the red light emitting diode chip 63, the green light emitting diode chip 64, and the blue light emitting diode chip 65 as a unit are arranged in an array on the substrate 61 is obtained. In this case, since the transparent resins 70 and 71 are in contact with the back surface of the substrate 11 of the green light emitting diode chip 64 and the blue light emitting diode chip 65, respectively, the back surface of the substrate 11 is in direct contact with air. The difference in refractive index is smaller than in the case, and therefore the ratio of the light that is transmitted through the substrate 11 and exits to the outside is reduced by the back surface of the substrate 11, thereby improving the light extraction efficiency. The luminous efficiency is improved.
This light emitting diode backlight is suitable for use in a backlight of a liquid crystal panel, for example.

Next, an eleventh embodiment of the present invention will be described.
In the eleventh embodiment, in addition to the blue light emitting diode and the green light emitting diode obtained by any one of the methods of the first to eighth embodiments, a separately prepared red light emitting diode is used. A case where a light source cell unit is manufactured will be described.
As shown in FIG. 32A, in the eleventh embodiment, as in the ninth or tenth embodiment, a red light emitting diode chip 63, a green light emitting diode chip 64, and a blue light emitting diode are used. A required number of cells 75 each including at least one chip 65 and arranged in a predetermined pattern are arranged on the printed wiring board 76 in a predetermined pattern. In this example, each cell 75 includes a red light emitting diode chip 63, a green light emitting diode chip 64, and a blue light emitting diode chip 65, which are arranged at the apexes of an equilateral triangle. FIG. 32B shows the cell 75 in an enlarged manner. The interval a between the red light emitting diode chip 63, the green light emitting diode chip 64, and the blue light emitting diode chip 65 in each cell 75 is, for example, 4 mm, but is not limited thereto. The interval b of the cells 75 is, for example, 30 mm, but is not limited to this. As the printed wiring board 76, for example, an FR4 (abbreviation of Flame Retardant Type 4) board, a metal core board, a flexible wiring board, or the like can be used. However, it is not limited to these. As in the eighth embodiment, potting of the transparent resin 68 is performed so as to cover each cell 76, or the transparent resin is covered so as to cover the red light emitting diode chip 63 as in the ninth embodiment. 69, potting of the transparent resin 70 is performed so as to cover the green light emitting diode chip 64, and potting of the transparent resin 71 is performed so as to cover the blue light emitting diode chip 65. In this way, a light source cell unit is obtained in which the cells 75 including the red light emitting diode chip 63, the green light emitting diode chip 64, and the blue light emitting diode chip 65 are arranged on the printed wiring board 76.

Although the specific example of arrangement | positioning of the cell 75 on the printed wiring board 76 is shown in FIG.33 and FIG.34, it is not limited to these. The example shown in FIG. 33 has cells 75 arranged in a 4 × 3 two-dimensional array, and the example shown in FIG. 34 has cells 75 arranged in a 6 × 2 two-dimensional array.
FIG. 35 shows another configuration example of the cell 75. In this example, the cell 75 includes one red light emitting diode chip 63, two green light emitting diode chips 64, and one blue light emitting diode chip 65, which are arranged at the apex of a square, for example. Has been. Two green light emitting diode chips 64 are arranged at the apexes of both ends of one diagonal of the square, and a red light emitting diode chip 63 and a blue light emitting diode chip 65 are arranged at both ends of the other diagonal of the square. It is placed at the vertex.
By arranging one or a plurality of the light source cell units, a light emitting diode backlight suitable for use in a backlight of a liquid crystal panel, for example, can be obtained.

As mentioned above, although embodiment of this invention was described concretely, this invention is not limited to the above-mentioned embodiment, The various deformation | transformation based on the technical idea of this invention is possible.
For example, the numerical values, materials, structures, configurations, shapes, substrates, raw materials, processes, orientations of the convex portions 21 and the concave portions 22 and the like given in the first to eleventh embodiments described above are merely examples, and as necessary. Different numerical values, materials, structures, configurations, shapes, substrates, raw materials, processes, and the like may be used.
Specifically, for example, in the first to eighth embodiments described above, the conductivity types of the p-type layer and the n-type layer may be reversed.
Moreover, you may combine 2 or more of the above-mentioned 1st-11th embodiment as needed.

It is sectional drawing which shows the light emitting diode by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 1st Embodiment of this invention. It is a partially expanded sectional view which shows the mode of the light emission from an active layer in the light emitting diode by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 2nd Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 3rd Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 4th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 4th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 4th Embodiment of this invention. It is a top view which shows the example of the planar shape of the convex part formed on a board | substrate in the manufacturing method of the light emitting diode by 4th Embodiment of this invention. It is a top view which shows the example of the planar shape of the convex part formed on a board | substrate in the manufacturing method of the light emitting diode by 4th Embodiment of this invention. It is a basic diagram which shows the board | substrate used in the manufacturing method of the light emitting diode by 4th Embodiment of this invention. It is a basic diagram for demonstrating the mode of growth of the n-type nitride type III-V group compound semiconductor layer on the board | substrate in the manufacturing method of the light emitting diode by 4th Embodiment of this invention. It is a basic diagram for demonstrating the behavior of the dislocation of the n-type nitride group III-V compound semiconductor layer grown on the board | substrate in the manufacturing method of the light emitting diode by the 4th Embodiment of this invention. It is a basic diagram which shows the example of the distribution of the threading dislocation of the n-type nitride type III-V compound semiconductor layer grown on the board | substrate in the manufacturing method of the light emitting diode by 4th Embodiment of this invention. It is a basic diagram which shows the example of distribution of the threading dislocation of the nitride type III-V group compound semiconductor layer grown on the board | substrate in the manufacturing method of the light emitting diode by 4th Embodiment of this invention. It is a basic diagram which shows the result of the ray tracing simulation of the light emitting diode manufactured by 4th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 5th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 5th Embodiment of this invention. FIG. 10 is a drawing-substituting photograph showing GaN preferentially grown in an m-plane orientation on an r-plane sapphire substrate in a light emitting diode manufacturing method according to a fifth embodiment of the present invention. It is a basic diagram for demonstrating the behavior of the dislocation of the nitride type III-V group compound semiconductor layer grown on the board | substrate in the manufacturing method of the light emitting diode by 5th Embodiment of this invention. It is a drawing substitute photograph which shows the distribution of the dislocation | rearrangement which generate | occur | produced in the recessed part of the uneven structure formed on the r surface sapphire substrate in the manufacturing method of the light emitting diode by 5th Embodiment of this invention. It is a basic diagram which shows the result of the ray-tracing simulation of the light emitting diode manufactured by 5th Embodiment of this invention. It is a basic diagram which shows the result of the ray-tracing simulation of the light emitting diode manufactured by 5th Embodiment of this invention. It is a basic diagram which shows the result of the ray-tracing simulation of the light emitting diode manufactured by 5th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 6th Embodiment of this invention. It is sectional drawing which shows the light emitting diode by 7th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode backlight by 9th Embodiment of this invention. It is a perspective view for demonstrating the manufacturing method of the light emitting diode backlight by 9th Embodiment of this invention. It is a perspective view for demonstrating the manufacturing method of the light emitting diode backlight by 9th Embodiment of this invention. It is a perspective view for demonstrating the manufacturing method of the light emitting diode backlight by 10th Embodiment of this invention. It is the top view which shows the light source cell unit by 11th Embodiment of this invention, and the enlarged view of the cell of this light source cell unit. It is a top view which shows one specific example of the light source cell unit by 11th Embodiment of this invention. It is a top view which shows the other specific example of the light source cell unit by 11th Embodiment of this invention. It is a top view which shows the other structural example of the cell of the light source cell unit by 11th Embodiment of this invention. It is sectional drawing which shows the semiconductor light-emitting device proposed by Unexamined-Japanese-Patent No. 11-112029.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Substrate, 12, 13 ... n-type nitride III-V compound semiconductor layer, 14 ... Active layer, 15 ... p-type nitride III-V compound semiconductor layer, 16 ... p-side electrode, 17 ... n-side electrode, 21 ... convex part, 22 ... concave part, 23 ... micronucleus, 24 ... threading dislocation

Claims (12)

A semiconductor light emitting device having a semiconductor layer including an active layer made of a semiconductor having a hexagonal crystal structure on a substrate made of a substance having a hexagonal crystal structure,
The semiconductor light emitting element, wherein the main surface of the substrate is a {10-12} plane or a {11-20} plane, and the active layer has a slope formed of {1-100} facets.   2. The semiconductor light emitting device according to claim 1, wherein the active layer has a sawtooth cross-sectional shape having a slope formed of {1-100} facets.   2. The semiconductor light emitting device according to claim 1, wherein the semiconductor has a wurtzite structure.   2. The semiconductor light emitting device according to claim 1, wherein the semiconductor is a nitride III-V group compound semiconductor or an oxide semiconductor. A method for manufacturing a semiconductor light-emitting device having a semiconductor layer including an active layer made of a semiconductor having a hexagonal crystal structure on a substrate made of a substance having a hexagonal crystal structure,
A substrate whose principal surface is a {10-12} plane or a {11-20} plane is used as the substrate, and the active layer is grown on the substrate so as to have a slope composed of {1-100} facets. A method for manufacturing a semiconductor light emitting device, characterized in that In a light source cell unit in which a plurality of cells each including at least one of a red light emitting semiconductor light emitting element, a green light emitting semiconductor light emitting element, and a blue light emitting semiconductor light emitting element are arranged,
At least one of the red light emitting semiconductor light emitting element, the green light emitting semiconductor light emitting element, and the blue light emitting semiconductor light emitting element,
A semiconductor light emitting device having a semiconductor layer including an active layer made of a semiconductor having a hexagonal crystal structure on a substrate made of a substance having a hexagonal crystal structure,
The main surface of the substrate is a {10-12} plane or a {11-20} plane, and the active layer has a slope formed of {1-100} plane facets. unit. In a backlight in which a plurality of red light emitting semiconductor light emitting elements, green light emitting semiconductor light emitting elements and blue light emitting semiconductor light emitting elements are arranged,
At least one of the red light emitting semiconductor light emitting element, the green light emitting semiconductor light emitting element, and the blue light emitting semiconductor light emitting element,
A semiconductor light emitting device having a semiconductor layer including an active layer made of a semiconductor having a hexagonal crystal structure on a substrate made of a substance having a hexagonal crystal structure,
The main surface of the substrate is a {10-12} plane or a {11-20} plane, and the active layer has a slope formed of {1-100} plane facets. . In a lighting device in which a plurality of red light emitting semiconductor light emitting elements, green light emitting semiconductor light emitting elements and blue light emitting semiconductor light emitting elements are arranged,
At least one of the red light emitting semiconductor light emitting element, the green light emitting semiconductor light emitting element, and the blue light emitting semiconductor light emitting element,
A semiconductor light emitting device having a semiconductor layer including an active layer made of a semiconductor having a hexagonal crystal structure on a substrate made of a substance having a hexagonal crystal structure,
The main surface of the substrate is a {10-12} plane or a {11-20} plane, and the active layer has a slope formed of {1-100} plane facets. . In a display in which a plurality of red light emitting semiconductor light emitting elements, green light emitting semiconductor light emitting elements and blue light emitting semiconductor light emitting elements are arranged,
At least one of the red light emitting semiconductor light emitting element, the green light emitting semiconductor light emitting element, and the blue light emitting semiconductor light emitting element,
A semiconductor light emitting device having a semiconductor layer including an active layer made of a semiconductor having a hexagonal crystal structure on a substrate made of a substance having a hexagonal crystal structure,
The main surface of the substrate is a {10-12} surface or a {11-20} surface, and the active layer has an inclined surface composed of {1-100} surface facets. In an electronic device having one or more semiconductor light emitting elements,
At least one of the semiconductor light emitting elements is
A semiconductor light emitting device having a semiconductor layer including an active layer made of a semiconductor having a hexagonal crystal structure on a substrate made of a substance having a hexagonal crystal structure,
The main surface of the substrate is a {10-12} plane or a {11-20} plane, and the active layer has a slope formed of {1-100} plane facets. . A semiconductor element having a semiconductor layer including an active layer made of a semiconductor having a hexagonal crystal structure on a substrate made of a substance having a hexagonal crystal structure,
A semiconductor element characterized in that a main surface of the substrate is a {10-12} plane or a {11-20} plane, and the active layer has a slope composed of {1-100} plane facets. . A method of manufacturing a semiconductor device having a semiconductor layer including an active layer made of a semiconductor having a hexagonal crystal structure on a substrate made of a substance having a hexagonal crystal structure,
A substrate whose principal surface is a {10-12} plane or a {11-20} plane is used as the substrate, and the active layer is grown on the substrate so as to have a slope composed of {1-100} facets. A method for manufacturing a semiconductor device, characterized in that:

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