JP4462289B2 - Semiconductor layer growth method and semiconductor light emitting device manufacturing method - Google Patents

Description

  The present invention relates to a method for growing a semiconductor layer, a method for manufacturing a semiconductor light emitting element, a semiconductor light emitting element, and an electronic apparatus. For example, a light emitting diode using a nitride III-V compound semiconductor and various devices using the light emitting diode Or it is a thing suitable for applying to an apparatus.

Conventionally, a method of manufacturing a light-emitting diode using a GaN-based semiconductor is based on metalorganic chemical vapor deposition of a GaN-based semiconductor layer including an n-type layer, an active layer, and a p-type layer on a (0001) plane, that is, a C-plane sapphire substrate. A method of growing by C-axis orientation by the (MOCVD) method is the mainstream.
However, as is well known, in a C-axis oriented InGaN strained quantum well layer grown on a (0001) plane (C plane) sapphire substrate, a large piezoelectric field is perpendicular to the well plane (C-axis direction). This causes a quantum confined Stark effect that spatially separates electrons and holes from each other and lowers the probability of electron-hole recombination. For example, in InGaN / GaN light emitting diodes, this reduces the internal quantum efficiency. As a result, there is a problem of lowering the external quantum efficiency, which is one cause of hindering the improvement of the light emission output.

  In order to suppress the quantum confined Stark effect in the active layer, a method of growing a (11-20) plane (A plane) GaN-based semiconductor layer on a (1-102) plane (R plane) sapphire substrate However, in this (11-20) plane GaN-based semiconductor layer, there are many threading dislocations, and it is difficult to obtain a GaN-based semiconductor layer with good crystal quality.

As a method for suppressing the quantum quantum confined Stark effect in the active layer, when manufacturing a semiconductor light emitting device by growing a plurality of GaN-based semiconductor layers including a strained quantum well layer, at least the surface of the growth surface of the strained quantum well layer When the orientation is different from the orientation in which the piezoelectric field is maximum, for example, when the GaN-based semiconductor layer has a wurtzite crystal structure, the plane orientation of the growth surface of the strained quantum well layer is inclined by 1 ° or more from the [0001] direction ( For example, it has been proposed to select to have 40 °, 90 °, 140 °, etc. (see, for example, Patent Document 1). A semiconductor light emitting device manufactured by this method is shown in FIG. According to this method, as shown in FIG. 39, an n-type GaN contact layer 102 and an n-type AlGaN cladding layer 103 are {0001} on a substrate 101 made of SiC, GaN or the like via an AlN buffer layer (not shown). The surface is grown sequentially in the surface direction, and a {2-1-14} plane or a {01-12} plane is formed on the surface of the n-type AlGaN cladding layer 103 by selective growth or selective etching, and GaInN / GaN or GaInN is formed thereon. / GaInN multiple quantum well layer 104 is grown, and a p-type AlGaN cladding layer 105 and a p-type GaN contact layer 106 are sequentially grown thereon. In this case, the growth surfaces 104a and 104b of the multiple quantum well layer 104 are {2-1-14} planes or {01-12} planes. The p-type AlGaN cladding layer 105 and the p-type GaN contact layer 106 are grown by changing the crystal structure from the plane orientation of the multiple quantum well layer 104 to the {0001} plane orientation direction. Reference numeral 107 denotes a p-side electrode, and 108 denotes an n-side electrode.
JP-A-11-112029

  In the conventional semiconductor light emitting device shown in FIG. 39, the piezoelectric field of the multiple quantum well layer 104 as an active layer can be reduced, but the facets of the {2-1-14} plane and the {01-12} plane are inclined. In practice, it is not always easy to grow the multiple quantum well layer 104 with good controllability, and it is difficult to manufacture a semiconductor light emitting device with a high yield.

Therefore, the problem to be solved by the present invention is that the plane orientation and growth facet of the semiconductor layer grown on the substrate can be selected, and the piezoelectric field of the semiconductor layer can be suppressed or the crystal quality can be increased as necessary. It is an object of the present invention to provide a method for growing a semiconductor layer.
Another problem to be solved by the present invention is to increase the crystal quality of the semiconductor layer forming the light emitting device structure by using the above-described growth method of the semiconductor layer for growing the semiconductor layer forming the light emitting device structure. An object of the present invention is to provide a semiconductor light emitting device that can suppress the quantum confined Stark effect in the active layer and that can be easily manufactured, and a method for manufacturing the same.
Another problem to be solved by the present invention is to provide a high-performance electronic device using the above excellent semiconductor light emitting element.

In order to solve the above problems, the first invention
The (1-100) plane of the substrate made of a substance having a hexagonal crystal structure is made of a semiconductor having a hexagonal crystal structure and has a (11-22) or (10-13) plane orientation. A semiconductor layer growth method characterized in that a semiconductor layer is grown.
In the first invention, typically, the semiconductor layer has a (11-20) facet, a (0001) facet and a (11-22} facet, or a (1-100) facet, (0001). It can be grown out with faceted and (10-13) faceted facets.

A semiconductor having a hexagonal crystal structure constituting the semiconductor layer typically has a wurtzite structure. Specific examples of the semiconductor having the wurtzite structure include nitride-based III-V group compound semiconductors, oxide semiconductors, and α-ZnS, but are not limited thereto. Nitride III-V compound semiconductor is _{generally, Al X B y Ga 1-} xyz In z As u N 1-uv P v ( however, 0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ z ≦ 1,0 ≦ u ≦ 1,0 ≦ v ≦ 1,0 ≦ x + y + z <1,0 ≦ u + v consists <1), more _{specifically, Al X B y Ga 1-} xyz in z N ( However, it is composed of 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, 0 ≦ x + y + z <1), and typically, Al _x Ga _1-xz In _z N (where 0 ≦ x ≦ 1, 0 ≦ z ≦ 1), and specific examples include GaN, InN, AlN, AlGaN, InGaN, and AlGaInN. This nitride-based III-V compound semiconductor has an effect of promoting the bending of dislocations when, for example, B or Cr is contained in GaN. Therefore, BGaN, GaN doped with B in GaN: B, Cr in GaN It may be made of doped GaN: Cr or the like. As this nitride-based III-V group compound semiconductor, preferably, GaN, In _x Ga _1-x N (0 <x <0.5), Al _x Ga _1-x N (0 <x <0. 5), Al _x In _y Ga _1-xy N (0 <x <0.5, 0 <y <0.2) or the like is used. In addition, as a so-called low-temperature buffer layer that is first grown on the substrate, a GaN buffer layer, an AlN buffer layer, an AlGaN buffer layer, etc. are generally used, and those doped with Cr or a CrN buffer layer are used. Also good. Examples of the oxide semiconductor include titanium (IV) oxide (TiO ₂ ), vanadium oxide (V) (V ₂ O ₅ ), chromium oxide (III) (Cr ₂ O ₃ ), manganese oxide (II) (MnO), Iron oxide (III) (Fe ₂ O ₃ ), tricobalt tetroxide (II) (Co ₃ O ₄ ), nickel oxide (II) (NiO), copper (I) oxide (Cu ₂ O), zinc oxide (II ) (ZnO), tin oxide (IV) (SnO ₂ ), gallium oxide (III) (Ga ₂ O ₃ ), indium oxide (III) (In ₂ O ₃ ), bismuth oxide (III) (Bi ₂ O ₃ ) In addition to strontium (II) oxide (SrO), strontium titanate (SrTiO ₃ ), barium titanate (BaTiO ₃ ), yttrium oxide (Y ₂ O ₃ ), etc., oxychalcogenide LnCuOCh (Ln = La, Ce, Nd Pr, Ch = S, Se, Te), for example Examples thereof include CuAlO and SrCu ₂ O ₂ , but are not limited thereto.

As the growth method of the semiconductor layer, various epitaxial growth methods such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxial growth, halide vapor phase epitaxial growth (HVPE), molecular beam epitaxy (MBE) can be used. , Selected as needed.
As the substrate made of a substance having a hexagonal crystal structure, for example, a substrate made of sapphire, SiC (including 6H, 4H), α-ZnS, ZnO, or the like can be used. As the substrate, a substrate made of a nitride III-V group compound semiconductor (GaN, AlGaInN, AlN, GaInN, etc.) may be used. Alternatively, a substrate obtained by growing a substance having a hexagonal crystal structure on a substrate made of a substance different from the substance having a hexagonal crystal structure may be used.

As the substrate, one main surface is composed of (1-100) surfaces, or at least one, and typically a plurality of recesses (grooves) on one main surface, and one side surface of this recess is (1 A material having a −100) plane can be used.
In the case of using a substrate having one (1-100) principal surface, it is preferable to provide a plurality of protrusions made of a material different from this substrate or the same material as this substrate on this substrate. In this case, the growth of the semiconductor layer starts from the bottom surface of the concave portion between the convex portions of the substrate. Typically, convex portions and concave portions are alternately and periodically formed on the main surface of the substrate. In this case, although the period of a convex part and a recessed part is 3-5 micrometers, for example, it is not limited to this. Moreover, although the ratio of the length of the base of a convex part and the length of the base of a recessed part is 0.5-3, for example, it is not limited to this. The height of the convex portion as viewed from the main surface of the substrate is preferably 0.3 μm or more, more preferably 1 μm or more, but is not limited thereto. The convex portion preferably has a side surface inclined with respect to the main surface of the substrate (for example, a side surface in contact with one main surface of the substrate), and an angle between the side surface and the main surface of the substrate is θ, From the viewpoint of improving the light extraction efficiency, for example, 120 ° <θ <150 ° is preferable, and about 140 ° is most preferable, but is not limited thereto. The cross-sectional shape of the convex portion may be various shapes, and the side surface may be a curved surface as well as a flat surface. For example, an n-gon (where n is an integer of 3 or more), specifically Triangular, quadrangular, pentagonal, hexagonal, etc., or those with their corners cut off, rounded corners, circular, elliptical, etc. Those having one apex are desirable, and in particular, a triangle or a shape obtained by cutting off the apex or rounded apex is most desirable. Although the cross-sectional shape of the recess may be various shapes, for example, an n-gon (where n is an integer of 3 or more), specifically, a triangle, a quadrangle, a pentagon, a hexagon, or the like, or these corners are cut off. Or rounded, oval, etc. From the viewpoint of improving the light extraction efficiency, preferably, the cross-sectional shape of the recess is an inverted trapezoid. Here, the inverted trapezoidal shape means not only an accurate inverted trapezoid but also includes an object that can be approximately regarded as an inverted trapezoid (the same applies hereinafter). If the height d of the convex portion (depth of the concave portion) is too large, the source gas is not sufficiently supplied to the inside of the concave portion, which hinders the growth of the semiconductor layer from the bottom surface of the concave portion. Since the semiconductor layer grows not only on the concave portion of the substrate but also on the convex portions on both sides thereof, it is generally selected within the range of 0.5 μm <d <5 μm from the viewpoint of preventing these, Is selected within the range of 1.0 ± 0.2 μm, but is not limited thereto. The width W _g of the recess is generally 0.5 to 5 μm and is typically selected within the range of 2 ± 0.5 μm, but is not limited thereto. When the cross-sectional shape of the convex portion is trapezoidal, the width W _{t of the} convex portion is generally in the range of 1 to 1000 μm, typically 4 ± 2 μm, but is not limited thereto.

  For example, the convex portion or the concave portion may extend in a stripe shape in one direction on the substrate, or may extend in a stripe shape in at least a first direction and a second direction intersecting each other. As a result, the convex portion is an n-gon (where n is an integer of 3 or more), specifically, a triangle, a quadrangle, a pentagon, a hexagon, or the like, or those with the corners cut off, rounded, or circular Alternatively, it may be a two-dimensional pattern such as an ellipse or a dot. In a preferred example, the convex portions have a hexagonal planar shape, the convex portions are two-dimensionally arranged in a honeycomb shape, and concave portions are formed so as to surround the convex portions. By doing so, light emitted from the active layer can be efficiently extracted in all directions of 360 °. Alternatively, the recess may have a hexagonal planar shape, the recesses may be two-dimensionally arranged in a honeycomb shape, and a protrusion may be formed so as to surround the recess. The convex portion is, for example, an n-pyramid (where n is an integer of 3 or more), specifically, a triangular pyramid, a quadrangular pyramid, a pentagonal pyramid, a hexagonal pyramid, etc., or a cut or rounded corner. Things, cones, elliptical cones, etc.

The material of the convex part may be various, and may or may not be conductive. For example, a dielectric such as an oxide, nitride or carbide, a conductor such as a metal or alloy (including a transparent conductor) ) Etc. As the oxide, for example, various oxides such as silicon oxide (SiO _x ), titanium oxide (TiO _x ), and tantalum oxide (TaO _x ) can be used, and two or more of these can be mixed or laminated. It can also be used in the form of a membrane. As the nitride, for example, silicon nitride (SiN _x (including Si ₃ N ₄ )), SiON, CrN, CrNO or the like can be used, and a mixture of two or more of these or in the form of a laminated film It can also be used. As the carbide, SiC, HfC, ZrC, WC, TiC, CrC, or the like can be used, and two or more of these can be mixed or used in the form of a laminated film. As the metal or alloy, B, Al, Ga, In, W, Ni, Co, Pd, Pt, Ag, AgNi, AgPd, AuNi, AuPd, and the like can be used. Alternatively, it can be used in the form of a laminated film. As the transparent conductor, ITO (indium-tin composite oxide), IZO (indium-zinc composite oxide), ZO (zinc oxide), FTO (fluorine-doped tin oxide), tin oxide, and the like can be used. Two or more of these may be mixed or used in the form of a laminated film. Further, two or more of the various materials described above can be mixed or used in the form of a laminated film. A convex portion may be formed of metal or the like, and nitride, oxide, or carbide may be formed by nitriding, oxidizing, or carbonizing at least the surface of the convex portion.

The second invention is
A semiconductor layer made of a semiconductor having a hexagonal crystal structure and having a (11-20) plane orientation is formed on the (1-102) plane of a substrate made of a substance having a hexagonal crystal structure (11-22). And at least one facet selected from the group consisting of (1) facet, (0001) facet, (000-1) facet, (33-62) facet and (1-100) facet. This is a method for growing a semiconductor layer.
In the second invention, for example, the (11-22) plane facet, the (0001) plane facet and the (000-1) plane facet are provided as the semiconductor layer, or the (11-20) plane facet, (1- Growing with 100) facet and (33-62) facet, or with (1-100) facet, or with (1-100) and (11-20) facet Let
In the second invention, what has been described in relation to the first invention is valid as far as it is not contrary to the nature thereof.

The third invention is
The (1-100) plane of the substrate made of a substance having a hexagonal crystal structure is made of a semiconductor having a hexagonal crystal structure and has a (11-22) or (10-13) plane orientation. A method of manufacturing a semiconductor light emitting device, characterized by growing a semiconductor layer having the semiconductor layer.
The semiconductor layer constituting this semiconductor light emitting element includes an n-type layer, an active layer, and a p-type layer. Typically, all of the semiconductor layers including the active layer are made of a semiconductor having a hexagonal crystal structure. The semiconductor light emitting element is a light emitting diode or a semiconductor laser.
The substrate may be left as it is in the final semiconductor light emitting device or may be removed.
In the third aspect of the invention, what has been described in relation to the first aspect of the invention other than the above is valid as long as it is not contrary to the nature thereof.

The fourth invention is:
A semiconductor layer made of a semiconductor having a hexagonal crystal structure and having a (11-20) plane orientation is formed on the (1-102) plane of a substrate made of a substance having a hexagonal crystal structure (11-22). And at least one facet selected from the group consisting of (1) facet, (0001) facet, (000-1) facet, (33-62) facet and (1-100) facet. A method of manufacturing a semiconductor light-emitting device characterized by the above.
In the fourth invention, the matters other than those described above are explained in relation to the first to third inventions unless they are contrary to the nature thereof.

The fifth invention is:
The (1-100) plane of the substrate made of a substance having a hexagonal crystal structure is made of a semiconductor having a hexagonal crystal structure and has a (11-22) or (10-13) plane orientation. It is a semiconductor light emitting element characterized by having a semiconductor layer.

The sixth invention is:
A semiconductor light emitting device comprising a semiconductor having a hexagonal crystal structure and having a semiconductor layer having a (11-22) plane orientation or a (10-13) plane orientation.

The seventh invention
In an electronic device having one or more semiconductor light emitting elements,
At least one of the semiconductor light emitting elements is
On the (1-100) plane of the substrate made of a substance having a hexagonal crystal structure, it is made of a semiconductor having a hexagonal crystal structure and has a (11-22) plane orientation or a (10-13} plane orientation. It has the semiconductor layer which has, It is characterized by the above-mentioned.

The eighth invention
In an electronic device having one or more semiconductor light emitting elements,
At least one of the semiconductor light emitting elements is
It is composed of a semiconductor having a hexagonal crystal structure, and has a semiconductor layer having a (11-22) plane orientation or a (10-13) plane orientation.
In the fifth to eighth aspects of the invention, what has been described in relation to the first and third aspects of the invention is valid as long as it is not contrary to the nature thereof.

  Electronic devices include, for example, light emitting diode backlights (such as liquid crystal display backlights), light emitting diode illumination devices, light emitting diode displays, and projectors or rear projection televisions that use light emitting diodes as light sources, grating light bulbs (GLV), and the like. In general, as long as it has at least one semiconductor light-emitting element for display, illumination, optical communication, optical transmission and other purposes, basically, it may be anything, Including both portable and stationary types, but specific examples other than the above, mobile phones, mobile devices, robots, personal computers, in-vehicle devices, various home appliances, light-emitting diode optical communication devices, Portable security such as light-emitting diode optical transmission device and electronic key Over the equipment, and the like. Electronic devices also include light in different wavelength bands, such as far-infrared wavelength band, infrared wavelength band, red wavelength band, yellow wavelength band, green wavelength band, blue wavelength band, purple wavelength band, and ultraviolet wavelength band. A combination of two or more types of semiconductor light emitting devices that emit light is also included. In particular, in a light emitting diode lighting device, a combination of two or more types of light emitting diodes that emit visible light in different wavelength bands among a red wavelength band, a yellow wavelength band, a green wavelength band, a blue wavelength band, a purple wavelength band, and the like, Two or more types of light emitted from these light emitting diodes can be mixed to obtain natural light or white light. In addition, a semiconductor light-emitting element that emits light in at least one of the blue wavelength band, the violet wavelength band, and the ultraviolet wavelength band is used as a light source, and the phosphor is irradiated with light emitted from the semiconductor light-emitting element. Natural light or white light can be obtained by mixing the light obtained by excitation. In addition, these light emitting diodes that emit visible light in different wavelength bands are, for example, cell units, quartet units, cluster units, and other collective units (strictly speaking, the number of light emitting diodes included in one unit of these units is A single unit name when a plurality of light emitting diodes that are not defined and emit light of the same wavelength or different wavelengths are formed in the same group and are mounted on a wiring board, wiring package, wiring housing wall, etc. In particular, for example, a unit composed of three light emitting diodes (for example, one red light emitting diode, one green light emitting diode, and one blue light emitting diode), Or four light emitting diodes (for example, one red light emitting diode, two green light emitting diodes, and blue light emitting diode). 1 unit), or units consisting of five or more light-emitting diodes, etc., and each unit is mounted on a substrate or plate, or on a housing plate in a two-dimensional array or in one or more rows. It may be.

For example, in a backlight, lighting device, display, light source cell unit, etc., in which a plurality of red light emitting semiconductor light emitting elements, green light emitting semiconductor light emitting elements, and blue light emitting semiconductor light emitting elements are arranged on a substrate, etc. The semiconductor light emitting device according to the fifth or sixth invention can be used as at least one of the light emitting semiconductor light emitting device, the green light emitting semiconductor light emitting device, and the blue light emitting semiconductor light emitting device. As the semiconductor light emitting element emitting red light, for example, an element using an AlGaInP-based semiconductor can be used.
In addition, the semiconductor light emitting device or the method for manufacturing the semiconductor light emitting device according to the third to sixth inventions can be generally applied to all semiconductor devices. This semiconductor element includes a light emitting element such as a general light emitting diode, an intersubband transition emission type (quantum cascade type) light emitting diode, an ordinary semiconductor laser, and an intersubband transition emission type (quantum cascade type) semiconductor laser. In addition, electrons represented by transistors such as photodiodes and other light receiving elements or sensors, solar cells, and field effect transistors (FET) such as high electron mobility transistors and bipolar transistors such as heterojunction bipolar transistors (HBT). A running element is included.

  In the present invention configured as described above, when a substrate having a (1-100) plane is used, the semiconductor layer is grown in the (11-22) plane orientation or (10-13) plane orientation. In the case where a substrate having a (1-102) plane is used, the semiconductor layer is grown in the (11-20) plane orientation, and the (11-22) plane facet, (0001) plane is used. It is possible to grow while emitting at least one facet selected from the group consisting of a facet, a (000-1) facet, a (33-62) facet, and a (1-100) facet. Since the plane orientation and the growth plane facet of the semiconductor layer can be selected in this way, the piezoelectric field generated in the semiconductor layer can be suppressed or the crystal quality can be increased as necessary. The semiconductor layer can be easily grown by setting growth conditions.

  According to the present invention, it is possible to select the plane orientation and growth facet of the semiconductor layer grown on the substrate, and it is possible to suppress the piezoelectric field of the semiconductor layer and increase the crystal quality as necessary. Then, by using this semiconductor layer growth method for the growth of the semiconductor layer forming the light emitting element structure, the crystal quality of the semiconductor layer forming the light emitting element structure is improved, or the quantum confined Stark effect in the active layer is suppressed. Can be. Moreover, the semiconductor light emitting device is easier to manufacture than the one described in Patent Document 1. And various electronic devices, such as a high performance backlight, an illuminating device, a display, are realizable using this high performance semiconductor light emitting element.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings of the embodiments, the same or corresponding parts are denoted by the same reference numerals.
FIG. 1 shows a basic growth method of a nitride III-V compound semiconductor layer according to a first embodiment of the present invention.
As shown in FIG. 1, in the first embodiment, a nitride-based III-V having a (11-22) plane orientation on a sapphire substrate 11 whose main surface is a (1-100) plane (M plane). The group compound semiconductor layer 12 is grown. On the sapphire substrate 11, convex portions 13 made of SiO ₂ , SiN, or the like are formed in a stripe shape extending in one direction, for example. The crystal orientations of the sapphire substrate 11 and the nitride-based III-V compound semiconductor layer 12 are shown in FIG. As a method for growing the nitride III-V compound semiconductor layer 12, for example, MOCVD is used.

  FIG. 2 shows the initial growth of the nitride-based III-V compound semiconductor layer 12. The nitride-based III-V compound semiconductor layer 12 can be grown while providing (11-20) plane (A plane) facets, (0001) plane (C plane) facets, and (11-22) plane facets. . In this case, the growth of the nitride III-V compound semiconductor layer 12 is restricted in the C-axis direction.

The growth conditions of the nitride III-V compound semiconductor layer 12 are, for example, as follows. The growth rate is 0.5 to 8 μm / hour, and the flow rate of group III element materials (for example, trimethylgallium ((CH ₃ ) ₃ Ga, TMG), trimethylindium ((CH ₃ ) ₃ In, TMI), etc.) is 10 ˜90 sccm, the flow rate of nitrogen source (for example, NH ₃ ) is 5-30 slm, the growth temperature is 950-1250 ° C., the V / III ratio of the growth source is 1000-15000, and the growth pressure is 0.01-1 atm.

  FIG. 3 shows a cross-sectional transmission electron micrograph of a sample obtained by growing a GaN layer as the nitride III-V compound semiconductor layer 12 on the sapphire substrate 11 by the MOCVD method. This GaN layer is grown to a continuous film through the state shown in FIG. An X-ray diffraction measurement was performed on a sample in which the GaN layer was grown in the shape shown in FIG. 4A and 4B show the diffraction peak due to the (11-20) plane (A plane) and the diffraction peak due to the (11-22) plane of this GaN layer, respectively.

FIG. 5 shows a basic growth method of a nitride-based III-V compound semiconductor layer according to the second embodiment of the present invention.
As shown in FIG. 5, in the second embodiment, a nitride-based III-V having a (10-13) plane orientation on a sapphire substrate 11 whose main surface is a (1-100) plane (M plane). The group compound semiconductor layer 12 is grown. On the sapphire substrate 11, a convex portion 13 is formed as in the first embodiment. The crystal orientations of the sapphire substrate 11 and the nitride-based III-V compound semiconductor layer 12 are shown in FIG. As a growth method of the nitride III-V compound semiconductor layer 12, for example, the MOCVD method is used.

  FIG. 6 shows the initial growth of the nitride-based III-V compound semiconductor layer 12. The nitride-based III-V compound semiconductor layer 12 can be grown while providing (1-100) plane (M plane) facets, (0001) plane (C plane) facets and (10-13) plane facets. . In this case, the growth of the nitride III-V compound semiconductor layer 12 in the A-axis direction is limited.

The growth conditions of the nitride III-V compound semiconductor layer 12 are, for example, as follows. The growth rate is 0.5-8 μm / hour, the flow rate of Group III element raw material (eg, TMG, TMI, etc.) is 10-90 sccm, the flow rate of nitrogen raw material (eg, NH ₃ ) is 5-30 slm, and the growth temperature is 950. ˜1250 ° C., the growth raw material V / III ratio is 1000 to 15000, and the growth pressure is 0.01 to 1 atm.

  FIG. 7 shows a cross-sectional transmission electron micrograph of a sample obtained by growing a GaN layer as the nitride III-V compound semiconductor layer 12 on the sapphire substrate 11 by the MOCVD method. X-ray diffraction measurement was performed on a sample in which the GaN layer was grown in the shape shown in FIG. 8A, 8B and 8C show the diffraction peak due to the (1-100) plane, the diffraction peak due to the (10-13) plane and the diffraction peak due to the (0001) plane (C plane), respectively.

FIG. 9 shows a basic method for growing a nitride III-V compound semiconductor layer according to the third embodiment of the present invention.
As shown in FIG. 9, in the third embodiment, a nitride-based III-V having a (11-20) plane orientation on a sapphire substrate 11 whose main surface is a (1-102) plane (R plane). The group compound semiconductor layer 12 is grown. On the sapphire substrate 11, a convex portion 13 is formed as in the first embodiment. The crystal orientations of the sapphire substrate 11 and the nitride-based III-V compound semiconductor layer 12 are shown in FIG. As a growth method of the nitride III-V compound semiconductor layer 12, for example, the MOCVD method is used.

  FIG. 10 shows a state of initial growth of the nitride-based III-V compound semiconductor layer 12. In the first example, the nitride-based III-V compound semiconductor layer 12 is grown while exhibiting (11-22) plane facets, (0001) plane (C plane) facets, and (000-1) plane facets. In the second example, the nitride-based III-V group compound semiconductor layer 12 is grown while exhibiting (11-20) plane facets, (33-62) plane facets, and (000-1) plane facets. In this case, the growth of the nitride III-V compound semiconductor layer 12 is restricted in the C-axis direction.

In the first example, the growth conditions of the nitride III-V compound semiconductor layer 12 are, for example, as follows. The growth rate is 0.5 to 8 μm / hour, the flow rate of the group III element raw material (for example, TMG, TMI, etc.) is 10 to 90 sccm, the flow rate of the nitrogen raw material (for example, NH ₃ ) is 5 to 30 slm, and the growth temperature is 800. ˜950 ° C., the growth raw material has a V / III ratio of 1000 to 15000, and a growth pressure of 0.01 to 1 atmosphere. In the second example, the growth conditions of the nitride-based III-V compound semiconductor layer 12 are, for example, as follows. The growth rate is 0.5-8 μm / hour, the flow rate of Group III element raw material (eg, TMG, TMI, etc.) is 10-90 sccm, the flow rate of nitrogen raw material (eg, NH ₃ ) is 5-30 slm, and the growth temperature is 950. ˜1250 ° C., the growth raw material V / III ratio is 1000 to 15000, and the growth pressure is 0.01 to 1 atm.

  FIG. 11 shows a cross-sectional transmission electron micrograph of a sample obtained by growing a GaN layer as a nitride III-V group compound semiconductor layer 12 on the sapphire substrate 11 with the facets of the first example taken out by MOCVD. FIG. 12 shows a cross-sectional transmission electron micrograph of a sample obtained by growing a GaN layer on the sapphire substrate 11 as a nitride-based III-V compound semiconductor layer 12 while exposing the facets of the second example by MOCVD. .

  FIG. 13 shows the state of initial growth of the nitride-based III-V compound semiconductor layer 12 according to the third and fourth examples. In the third example, the nitride-based III-V compound semiconductor layer 12 is grown while exposing the (1-100) facet. In the fourth example, the nitride-based III-V compound semiconductor layer 12 grows with a (11-20) facet on the uppermost surface and a (1-100) facet on the other surface. In this case, the growth of the nitride III-V compound semiconductor layer 12 in the A-axis direction is limited.

In the third example, the growth conditions are as follows, for example. The growth rate is 0.5 to 8 μm / hour, the flow rate of the group III element raw material (for example, TMG, TMI, etc.) is 10 to 90 sccm, the flow rate of the nitrogen raw material (for example, NH ₃ ) is 5 to 30 slm, and the growth temperature is 800. ˜950 ° C., the growth raw material has a V / III ratio of 1000 to 15000, and a growth pressure of 0.01 to 1 atmosphere. In the fourth example, the growth conditions of the nitride-based III-V compound semiconductor layer 12 are, for example, as follows. The growth rate is 0.5-8 μm / hour, the flow rate of Group III element raw material (eg, TMG, TMI, etc.) is 10-90 sccm, the flow rate of nitrogen raw material (eg, NH ₃ ) is 5-30 slm, and the growth temperature is 950. ˜1250 ° C., the growth raw material V / III ratio is 1000 to 15000, and the growth pressure is 0.01 to 1 atm.

  FIG. 14 shows a cross-sectional transmission electron micrograph of a sample obtained by growing a GaN layer as a nitride-based III-V group compound semiconductor layer 12 on the sapphire substrate 11 while exposing the facets of the third example by MOCVD. FIG. 15 shows a cross-sectional transmission electron micrograph of a sample obtained by growing a GaN layer as a nitride III-V group compound semiconductor layer 12 on the sapphire substrate 11 with the facets of the fourth example taken out by MOCVD.

Next explained is a method for growing a nitride-based III-V compound semiconductor layer according to the fourth embodiment of the invention.
As shown in FIG. 16, in the fourth embodiment, the main surface of the sapphire substrate 11 whose surface is off by + 60 ° in the C-axis direction from the M surface is processed by etching, and the cross section is inverted trapezoidal. The recess 14 is formed in a stripe shape extending in one direction, for example. One side surface 14a of the recess 14 is an M-plane. Then, a nitride III-V compound semiconductor layer 12 is grown on the sapphire substrate 11 by the method according to the first embodiment. As a result, the nitride-based III-V group compound semiconductor layer 12 grows in the direction indicated by the arrow in FIG. The upper surface of the nitride III-V compound semiconductor layer 12 is a (11-20) face (A face) facet. In this case, since the dislocations 15 generated from the side surface 14a made of the M plane of the recess 14 extend in the growth direction, threading dislocations that escape to the surface do not occur in the nitride-based III-V compound semiconductor layer 12.

Next explained is a method for growing a nitride-based III-V compound semiconductor layer according to the fifth embodiment of the invention.
As shown in FIG. 17, in the fifth embodiment, the main surface of the sapphire substrate 11 whose main surface is a surface off −60 ° in the C-axis direction from the M surface is processed by etching, and the cross section is inverted. The concave portion 14 having a shape is formed, for example, in a stripe shape extending in one direction. One side surface 14a of the recess 14 is an M-plane. Then, a nitride III-V compound semiconductor layer 12 is grown on the sapphire substrate 11 by the method according to the first embodiment. Then, the nitride-based III-V compound semiconductor layer 12 grows from the side surface 14a made of the M surface of the recess 14 in the direction indicated by the arrow in FIG. The upper surface of the nitride III-V compound semiconductor layer 12 is a (0001) plane (C plane) facet. In this case, the dislocations 15 generated from the side surface 14 a made of the M surface of the recess 14 extend in the growth direction, and this direction is inclined with respect to the upper surface of the nitride-based III-V compound semiconductor layer 12. Therefore, threading dislocations that escape to the surface of the nitride-based III-V compound semiconductor layer 12 are less than when a C-plane nitride-based III-V compound semiconductor layer is grown on a C-plane sapphire substrate.

Next explained is a method for growing a nitride-based III-V compound semiconductor layer according to the sixth embodiment of the invention.
As shown in FIG. 18, in the sixth embodiment, the main surface of the sapphire substrate 11, which is a surface whose main surface is off −120 ° in the C-axis direction from the M surface, is processed by etching to have a trapezoidal cross section. The recess 14 is formed in a stripe shape extending in one direction, for example. One side surface 14a of the recess 14 is an M-plane. Then, a nitride III-V compound semiconductor layer 12 is grown on the sapphire substrate 11 by the method according to the first embodiment. Then, the nitride-based III-V compound semiconductor layer 12 grows from the side surface 14a made of the M surface of the recess 14 in the direction indicated by the arrow in FIG. The upper surface of the nitride III-V compound semiconductor layer 12 is a (11-20) face (A face) facet. In this case, since the dislocations 15 generated from the side surface 14a made of the M plane of the recess 14 extend in the growth direction, threading dislocations that escape to the surface do not occur in the nitride-based III-V compound semiconductor layer 12.

Next explained is a method for growing a nitride-based III-V compound semiconductor layer according to the seventh embodiment of the invention.
As shown in FIG. 19, in the seventh embodiment, the main surface of the sapphire substrate 11, which is a surface whose main surface is + 60 ° off from the M surface in the A axis direction, is processed by etching, and the cross section is inverted trapezoid The recess 14 is formed in a stripe shape extending in one direction, for example. One side surface 14a of the recess 14 is an M-plane. Then, a nitride III-V compound semiconductor layer 12 is grown on the sapphire substrate 11 by the method according to the second embodiment. As a result, the nitride-based III-V group compound semiconductor layer 12 grows in the direction indicated by the arrow in FIG. The upper surface of the nitride III-V compound semiconductor layer 12 is a (1-100) plane (M plane) facet. In this case, since the dislocations 15 generated from the side surface 14a made of the M plane of the recess 14 extend in the growth direction, threading dislocations that escape to the surface do not occur in the nitride-based III-V compound semiconductor layer 12.

Next explained is a method for growing a nitride-based III-V compound semiconductor layer according to the eighth embodiment of the invention.
As shown in FIG. 20, in the eighth embodiment, the main surface of the sapphire substrate 11 whose main surface is a surface that is -60 ° off from the M plane in the C-axis direction is processed by etching, and the cross section is inverted. The concave portion 14 having a shape is formed, for example, in a stripe shape extending in one direction. One side surface 14a of the recess 14 is an M-plane. Then, a nitride III-V compound semiconductor layer 12 is grown on the sapphire substrate 11 by the method according to the second embodiment. As a result, the nitride-based III-V group compound semiconductor layer 12 grows in the direction indicated by the arrow in FIG. The upper surface of the nitride III-V compound semiconductor layer 12 is a (0001) plane (C plane) facet. In this case, the dislocations 15 generated from the side surface 14 a made of the M surface of the recess 14 extend in the growth direction, but the threading dislocations that escape to the surface of the nitride III-V compound semiconductor layer 12 are the side surface 14 a of the recess 14. Therefore, the number of dislocations is less than that in the case of growing a C-plane nitride III-V compound semiconductor layer on a C-plane sapphire substrate.

Next explained is a method for growing a nitride-based III-V compound semiconductor layer according to the ninth embodiment of the invention.
As shown in FIG. 21, in the ninth embodiment, the main surface of the sapphire substrate 11, which is a surface whose main surface is off −120 ° in the C-axis direction from the M surface, is processed by etching, and the cross section is trapezoidal. The recess 14 is formed in a stripe shape extending in one direction, for example. One side surface 14a of the recess 14 is an M-plane. Then, a nitride III-V compound semiconductor layer 12 is grown on the sapphire substrate 11 by the method according to the second embodiment. Then, the growth of the nitride-based III-V compound semiconductor layer 12 starts from the side surface 14a made of the M surface of the recess 14 in the direction indicated by the arrow in FIG. The upper surface of the nitride III-V compound semiconductor layer 12 is a (1-100) plane (M plane) facet. In this case, since the dislocations 15 generated from the side surface 14a made of the M plane of the recess 14 extend in the growth direction, threading dislocations that escape to the surface do not occur in the nitride-based III-V compound semiconductor layer 12.

Next explained is a method for growing a nitride-based III-V compound semiconductor layer according to the tenth embodiment of the invention.
As shown in FIG. 22, in the tenth embodiment, the main surface of the sapphire substrate 11, which is a surface whose main surface is off by + 90 ° in the C-axis direction from the R surface, is processed by etching to have a rectangular cross section. For example, the recess 14 is formed in a stripe shape extending in one direction. One side surface 14a of the recess 14 is an R surface. Then, a nitride III-V compound semiconductor layer 12 is grown on the sapphire substrate 11 by the method according to the first example of the third embodiment. Then, the nitride-based III-V compound semiconductor layer 12 grows from the side surface 14a formed of the R surface of the recess 14 in the direction indicated by the arrow in FIG. The upper surface of the nitride III-V compound semiconductor layer 12 is a (000-1) facet. In this case, since the dislocations 15 generated from the side surface 14a made of the R surface of the recess 14 extend in the growth direction, threading dislocations that escape to the surface do not occur in the nitride III-V compound semiconductor layer 12.

Next explained is a method for growing a nitride-based III-V compound semiconductor layer according to the eleventh embodiment of the invention.
As shown in FIG. 23, in the eleventh embodiment, the main surface of the sapphire substrate 11 formed by etching the main surface of the main surface of the R plane that is −90 ° off in the C-axis direction by etching is rectangular in cross section. The recess 14 is formed in a stripe shape extending in one direction, for example. One side surface 14a of the recess 14 is an R surface. Then, a nitride III-V compound semiconductor layer 12 is grown on the sapphire substrate 11 by the method according to the first example of the third embodiment. Then, the nitride-based III-V compound semiconductor layer 12 grows in the direction indicated by the arrow in FIG. The upper surface of the nitride III-V compound semiconductor layer 12 is a (0001) plane (C plane) facet. In this case, since the dislocations 15 generated from the side surface 14a made of the R surface of the recess 14 extend in the growth direction, threading dislocations that escape to the surface do not occur in the nitride III-V compound semiconductor layer 12.

Next explained is a method for growing a nitride-based III-V compound semiconductor layer according to the twelfth embodiment of the invention.
As shown in FIG. 24, in the twelfth embodiment, the main surface of the sapphire substrate 11 whose main surface is a surface off −80 ° from the R surface in the C-axis direction is processed by etching, and the cross section is trapezoidal. The recess 14 is formed in a stripe shape extending in one direction, for example. One side surface 14a of the recess 14 is an R surface. Then, a nitride III-V compound semiconductor layer 12 is grown on the sapphire substrate 11 by the method according to the second example of the third embodiment. As a result, the nitride-based III-V group compound semiconductor layer 12 grows in the direction indicated by the arrow in FIG. The upper surface of the nitride III-V compound semiconductor layer 12 is a (33-62) facet. In this case, since the dislocations 15 generated from the side surface 14a made of the R surface of the recess 14 extend in the growth direction, threading dislocations that escape to the surface of the nitride-based III-V compound semiconductor layer 12 are greatly reduced.

Next explained is a method for growing a nitride-based III-V compound semiconductor layer according to the thirteenth embodiment of the invention.
As shown in FIG. 25, in the thirteenth embodiment, the main surface of the sapphire substrate 11 whose main surface is a surface off −30 ° in the C-axis direction from the R surface is processed by etching and the cross section is inverted. The concave portion 14 having a shape is formed, for example, in a stripe shape extending in one direction. One side surface 14a of the recess 14 is an R surface. Then, a nitride III-V compound semiconductor layer 12 is grown on the sapphire substrate 11 by the method according to the first example of the third embodiment. Then, as shown by the arrow in FIG. 25, the nitride-based III-V group compound semiconductor layer 12 grows from the side surface 14a made of the R surface of the recess 14. The upper surface of the nitride III-V compound semiconductor layer 12 is a (11-22) facet. In this case, the dislocations 15 generated from the side surface 14 a made of the R surface of the recess 14 extend in the growth direction, but this direction is inclined with respect to the upper surface of the nitride-based III-V compound semiconductor layer 12. Therefore, threading dislocations that escape to the surface of the nitride III-V compound semiconductor layer 12 are greatly reduced.

Next explained is a method for growing a nitride-based III-V compound semiconductor layer according to the fourteenth embodiment of the invention.
As shown in FIG. 26, in the fourteenth embodiment, the main surface of the sapphire substrate 11 whose surface is off by ± 30 ° in the A-axis direction from the R surface is processed by etching and the cross section is inverted. The concave portion 14 having a shape is formed, for example, in a stripe shape extending in one direction. One side surface 14a of the recess 14 is an R surface. Then, a nitride III-V compound semiconductor layer 12 is grown on the sapphire substrate 11 by the method according to the third example of the third embodiment. Then, the nitride-based III-V compound semiconductor layer 12 grows from the side surface 14a formed of the R surface of the recess 14 in the direction indicated by the arrow in FIG. The upper surface of the nitride III-V compound semiconductor layer 12 is a (1-100) facet. In this case, the dislocations 15 generated from the side surface 14 a made of the R surface of the recess 14 extend in the growth direction, but this direction is inclined with respect to the upper surface of the nitride-based III-V compound semiconductor layer 12. Therefore, threading dislocations that escape to the surface of the nitride-based III-V compound semiconductor layer 12 do not occur.

Next explained is a method for growing a nitride-based III-V compound semiconductor layer according to the fifteenth embodiment of the invention.
As shown in FIG. 27, in the fifteenth embodiment, the main surface of the sapphire substrate 11 whose main surface is a surface off ± 90 ° in the A-axis direction from the R surface is processed by etching, and the cross section is inverted. The concave portion 14 having a shape is formed, for example, in a stripe shape extending in one direction. One side surface 14a of the recess 14 is an R surface. Then, a nitride III-V compound semiconductor layer 12 is grown on the sapphire substrate 11 by the method according to the third example of the third embodiment. As a result, the nitride-based III-V group compound semiconductor layer 12 grows in the direction indicated by the arrow in FIG. The upper surface of the nitride III-V compound semiconductor layer 12 is a (33-62) facet. In this case, since the dislocation 15 generated from the side surface 14 a made of the R surface of the recess 14 extends in the growth direction, there is no threading dislocation that escapes to the surface of the nitride III-V compound semiconductor layer 12.

Next explained is a manufacturing method for the light emitting diode according to the sixteenth embodiment of the invention.
In the sixteenth embodiment, first, similarly to the first embodiment, a nitride-based III-V group compound semiconductor having a (11-22) plane orientation on a sapphire substrate 11 whose main surface is an M-plane. Layer 12 is grown.
Specifically, as shown in FIG. 28A, first, a convex portion 13 having a trapezoidal cross section is periodically formed in a predetermined planar shape on a sapphire substrate 11 whose main surface is an M plane. A concave portion 14 having an inverted trapezoidal cross-sectional shape is formed between the convex portions 13. The planar shape of the convex portion 13 and the concave portion 14 has, for example, a stripe shape extending in one direction. The convex portion 13 is made of, for example, SiN (Si ₃ N ₄ or the like), SiO ₂ or the like. In order to form the convex portion 13, a conventionally known method can be used. For example, a film serving as the material of the convex portion 13 is formed on the entire surface of the sapphire substrate 11 by CVD, vacuum vapor deposition, sputtering, or the like. Next, a resist pattern having a predetermined shape is formed on the film by lithography. Next, this film is etched using the resist pattern as a mask under conditions where taper etching is performed by a reactive ion etching (RIE) method or the like, thereby forming a convex portion 13 having a trapezoidal cross section.

  Next, after cleaning the surfaces of the sapphire substrate 11 and the convex portion 13 by performing thermal cleaning or the like, for example, a GaN buffer layer, for example, is grown on the sapphire substrate 11 at a growth temperature of, for example, about 550 ° C. An AlN buffer layer, a CrN buffer layer, a Cr-doped GaN buffer layer, or a Cr-doped AlN buffer layer (not shown) is grown. Next, as shown in FIG. 28B, the nitride III-V compound semiconductor layer 12 is grown on the bottom surface of the recess 14 by, for example, the MOCVD method, as in the first embodiment. The nitride III-V compound semiconductor layer 12 may be undoped, or may be doped with an n-type impurity or a p-type impurity. The nitride III-V compound semiconductor layer 12 is, for example, a GaN layer.

Next, when the growth is continued by setting growth conditions in which the (11-22) facet is preferentially emitted, the nitride-based III-V compound semiconductor layer 12 increases in thickness as shown in FIG. 28C. Grows and becomes a continuous film.
Next, as shown in FIG. 29, the n-type nitride III-V compound semiconductor layer 16 and the nitride III-V group semiconductor layer 16 are formed on the nitride III-V compound semiconductor layer 12, for example, by MOCVD. An active layer 17 using a compound semiconductor and a p-type nitride-based III-V compound semiconductor layer 18 are sequentially grown. These n-type nitride III-V compound semiconductor layer 16, active layer 17, and p-type nitride III-V compound semiconductor layer 18 have a (11-22) plane orientation. In this case, it is assumed that the nitride III-V compound semiconductor layer 15 is n-type.

Next, the sapphire substrate 11 on which the nitride III-V compound semiconductor layer is grown in this way is taken out from the MOCVD apparatus.
Next, the p-side electrode 19 is formed on the p-type nitride III-V compound semiconductor layer 18. As a material for the p-side electrode 19, it is preferable to use an ohmic metal having a high reflectance with respect to light having an emission wavelength.
Thereafter, in order to activate the p-type impurity of the p-type nitride III-V compound semiconductor layer 18, for example, a mixed gas of N ₂ and O ₂ (composition is, for example, 99% N ₂ and O ₂ In a 1% atmosphere, heat treatment is performed at a temperature of 550 to 750 ° C. (for example, 650 ° C.) or 580 to 620 ° C. (for example, 600 ° C.). Here, for example, activation is easily caused by mixing O ₂ with N ₂ . Further, for example, nitrogen halide (NF ₃ , NCl _3, etc.) is mixed in a mixed gas atmosphere of N ₂ or N ₂ and O ₂ as a raw material such as F and Cl having high electronegativity as in O and N. You may do it. The time for this heat treatment is, for example, 5 minutes to 2 hours or 40 minutes to 2 hours, generally about 10 to 60 minutes. The reason why the temperature of the heat treatment is relatively low is to prevent the active layer 16 and the like from being deteriorated during the heat treatment. This heat treatment may be performed after the p-type nitride-based III-V group compound semiconductor layer 18 is epitaxially grown and before the p-side electrode 19 is formed.
Next, the n-type nitride III-V compound semiconductor layer 16, the active layer 17, and the p-type nitride III-V compound semiconductor layer 18 are formed in a predetermined shape by, for example, the RIE method, the powder blast method, the sand blast method, or the like. To form a mesa portion.

Next, the n-side electrode 21 is formed on the n-type nitride-based III-V compound semiconductor layer 12 in a portion adjacent to the mesa portion.
Next, if necessary, the substrate 11 on which the light emitting diode structure is formed as described above is reduced in thickness by grinding or lapping from the back side, and then the substrate 11 is scribed, Form. Thereafter, the bar is scribed to form a chip.
Thus, the target light emitting diode is manufactured.

  A specific structural example of the light emitting diode will be described. That is, for example, the nitride III-V compound semiconductor layer 12 is an n-type GaN layer, the n-type nitride III-V compound semiconductor layer 16 is an n-type GaN layer and an n-type GaInN layer in order from the bottom, The p-type nitride III-V compound semiconductor layer 18 is a p-type AlInN layer, a p-type GaN layer, and a p-type GaInN layer in order from the bottom. The active layer 17 has, for example, a GaInN-based multiple quantum well (MQW) structure (for example, one in which GaInN quantum well layers and GaN barrier layers are alternately stacked), and the In composition of the active layer 17 is the light emission of the light emitting diode. It is selected according to the wavelength. For example, it is ˜11% at an emission wavelength of 405 nm, ˜18% at 450 nm, and ˜24% at 520 nm. As a material of the p-side electrode 19, for example, Ag, Pd / Ag, or the like is used, or a barrier metal made of Ti, W, Cr, WN, CrN, or the like is used in addition to this, if necessary. As the n-side electrode 21, for example, a Ti / Pt / Au structure is used.

  According to the sixteenth embodiment, since the active layer 14 has a (11-22) plane orientation and the generation of a piezoelectric field can be suppressed, the quantum confined Stark effect in the active layer 14 can be effectively suppressed. it can. For this reason, the luminous efficiency of the light emitting diode using the nitride III-V group compound semiconductor can be greatly improved. Further, the n-type nitride III-V compound semiconductor layer 16, the active layer 17, and the p-type nitride III-V compound semiconductor layer 18 having the (11-22) plane orientation can be easily grown. Therefore, the semiconductor light emitting device can be easily manufactured.

Next explained is a manufacturing method of the light emitting diode according to the seventeenth embodiment of the invention.
In the seventeenth embodiment, as shown in FIG. 30A, first, as in the fourth embodiment, the main surface of the sapphire substrate 11 having a main surface that is off by + 60 ° in the C-axis direction from the M plane. The surface is processed by etching to form a recess 14 in which one side surface 14a is an M surface. Then, as shown in FIG. 30B, the nitride-based III-V group compound semiconductor layer 12 having the (11-22) plane orientation is grown on the sapphire substrate 11 in the same manner as the fourth embodiment until the recesses 14 are filled. Let
Next, when the growth is continued by setting growth conditions in which the (11-20) facet is preferentially emitted, the nitride III-V compound semiconductor layer 12 increases in thickness as shown in FIG. 30C. Grows and becomes a continuous film.
Next, the process proceeds in the same manner as in the sixteenth embodiment to manufacture a target light emitting diode. The n-type nitride III-V compound semiconductor layer 16, the active layer 17, and the p-type nitride III-V compound semiconductor layer 18 have a (11-20) plane (A plane) orientation.

  According to the seventeenth embodiment, since the active layer 14 has the (11-20) plane (A plane) orientation and the generation of the piezoelectric field can be suppressed, the quantum confined Stark effect in the active layer 14 is effective. Can be suppressed. Further, since threading dislocations in the nitride-based III-V compound semiconductor layer 12 can be eliminated, the n-type nitride-based III-V compound semiconductor layer 16, the active layer 17, and the p-type nitride grown thereon The threading dislocation of the III-V compound semiconductor layer 18 can be eliminated, and the n-type nitride III-V compound semiconductor layer 16, the active layer 17 and the p-type nitride III-V compound semiconductor layer can be eliminated. The crystal quality of 18 can be increased. For this reason, the luminous efficiency of the light emitting diode using the nitride III-V group compound semiconductor can be greatly improved. The n-type nitride III-V compound semiconductor layer 16, the active layer 17, and the p-type nitride III-V compound semiconductor layer 18 having a (11-20) plane orientation can be easily grown. Therefore, the semiconductor light emitting device can be easily manufactured.

Next, an eighteenth embodiment of the invention is described.
In the eighteenth embodiment, in addition to the blue light emitting diode and the green light emitting diode obtained by the method according to any of the sixteenth or seventeenth embodiments, a separately prepared red light emitting diode (for example, A case where a light emitting diode backlight is manufactured using an AlGaInP light emitting diode) will be described.
For example, a blue light emitting diode structure is formed on the sapphire substrate 11 by the method according to the sixteenth or seventeenth embodiment, and bumps (not shown) are formed on the p-side electrode 19 and the n-side electrode 21, respectively. Thereafter, this is chipped to obtain a blue light emitting diode in the form of a flip chip. Similarly, a green light emitting diode is obtained in the form of a flip chip. On the other hand, as a red light emitting diode, an AlGaInP light emitting diode is formed by stacking an AlGaInP semiconductor layer on an n-type GaAs substrate to form a diode structure and forming a p-side electrode thereon. It shall be used in the form.

Then, after mounting the red light emitting diode chip, the green light emitting diode chip, and the blue light emitting diode chip on a submount made of AlN or the like, each of them is mounted on the submount, for example, an Al substrate or the like. Mount in a predetermined arrangement on the substrate. This state is shown in FIG. 31A. In FIG. 31A, reference numeral 61 denotes a substrate, 62 denotes a submount, 63 denotes a red light emitting diode chip, 64 denotes a green light emitting diode chip, and 65 denotes a blue light emitting diode chip. The chip size of the red light emitting diode chip 63, the green light emitting diode chip 64, and the blue light emitting diode chip 65 is, for example, 350 μm square. Here, the red light emitting diode chip 63 is mounted such that the n-side electrode is on the submount 62, and the green light emitting diode chip 64 and the blue light emitting diode chip 65 are the p side electrode and the n side. The electrode is placed on the submount 62 through the bump. An extraction electrode (not shown) for an n-side electrode is formed in a predetermined pattern shape on the submount 62 on which the red light emitting diode chip 63 is mounted, and a red portion is formed on a predetermined portion on the extraction electrode. The n-side electrode side of the light emitting diode chip 63 for light emission is mounted. A wire 67 is bonded to the p-side electrode of the red light emitting diode chip 63 and a predetermined pad electrode 66 provided on the substrate 61, and the lead electrode A wire (not shown) is bonded to one end and another pad electrode provided on the substrate 61 so as to connect them. On the submount 62 on which the green light emitting diode chip 64 is mounted, a lead electrode for the p-side electrode and a lead electrode for the n-side electrode (both not shown) are respectively formed in a predetermined pattern shape. Bumps in which the p-side electrode and the n-side electrode side of the light emitting diode chip 64 for green light emission are formed on the lead-out electrode for the p-side electrode and the lead-out electrode for the n-side electrode are formed on them. Each is mounted through. A wire (not shown) is bonded to one end of the lead electrode for the p-side electrode of the green light emitting diode chip 64 and a pad electrode provided on the substrate 61 so as to connect them. In addition, a wire (not shown) is bonded to one end of the extraction electrode for the n-side electrode and a pad electrode provided on the substrate 61 so as to connect them. The same applies to the light-emitting diode chip 65 emitting blue light.
However, the submount 62 is omitted, and the red light emitting diode chip 63, the green light emitting diode chip 64, and the blue light emitting diode chip 65 are directly connected to any printed wiring board or printed wiring board having heat dissipation properties. It is also possible to mount directly on a plate having the above function, or on the inner and outer walls of the housing (for example, the inner wall of the chassis), thereby reducing the cost of the light emitting diode backlight or the entire panel.

The red light emitting diode chip 63, the green light emitting diode chip 64, and the blue light emitting diode chip 65 as described above are set as one unit (cell), and a necessary number of them are arranged on the substrate 61 in a predetermined pattern. . An example is shown in FIG. Next, as shown in FIG. 31B, the transparent resin 68 is potted so as to cover this one unit. Thereafter, the transparent resin 68 is cured. By this curing process, the transparent resin 68 is solidified and is slightly reduced accordingly (FIG. 31C). Thus, as shown in FIG. 33, the light emitting diode chip 63 that emits red light, the light emitting diode chip 64 that emits green light, and the light emitting diode chip 65 that emits blue light are arranged on the substrate 61 as an array. A diode backlight is obtained. In this case, since the transparent resin 68 is in contact with the back surface of the sapphire substrate 11 of the green light emitting diode chip 64 and the blue light emitting diode chip 65, the back surface of the sapphire substrate 11 is in direct contact with air. Accordingly, the difference in refractive index is smaller, and therefore the ratio of the light that is transmitted through the sapphire substrate 11 and reflected outside is reduced by the back surface of the sapphire substrate 11, thereby improving the light extraction efficiency. This improves luminous efficiency.
This light emitting diode backlight is suitable for use in a backlight of a liquid crystal panel, for example.

Next, a nineteenth embodiment of the present invention is described.
In the nineteenth embodiment, as in the eighteenth embodiment, a red light emitting diode chip 63, a green light emitting diode chip 64, and a blue light emitting diode chip 65 are arranged on a substrate 61 in a predetermined pattern. 34, after placing the required number of the transparent resin 69 suitable for the light emitting diode chip 63 so as to cover the red light emitting diode chip 63, as shown in FIG. The transparent resin 70 suitable for the light emitting diode chip 64 is potted so as to cover, and the transparent resin 71 suitable for the light emitting diode chip 65 is potted so as to cover the blue light emitting diode chip 65. Thereafter, the curing treatment of the transparent resins 69 to 71 is performed. By this curing process, the transparent resins 69 to 71 are solidified and are slightly reduced accordingly. In this way, a light emitting diode backlight in which the red light emitting diode chip 63, the green light emitting diode chip 64, and the blue light emitting diode chip 65 as a unit are arranged in an array on the substrate 61 is obtained. In this case, since the transparent resins 70 and 71 are in contact with the back surface of the sapphire substrate 11 of the green light emitting diode chip 64 and the blue light emitting diode chip 65, respectively, the back surface of the sapphire substrate 11 is in direct contact with air. Accordingly, the difference in refractive index is smaller than that in the case where the light is transmitted through the sapphire substrate 11, and the ratio of the light that is about to go out to the outside is reflected by the back surface of the sapphire substrate 11. As a result, the luminous efficiency is improved.
This light emitting diode backlight is suitable for use in a backlight of a liquid crystal panel, for example.

Next, a twentieth embodiment of the invention is described.
In the twentieth embodiment, a separately prepared red light emitting diode is used in addition to the blue light emitting diode and the green light emitting diode obtained by the method of the sixteenth or seventeenth embodiment. The case where a light source cell unit is manufactured will be described.
As shown in FIG. 35A, in the twentieth embodiment, as in the eighteenth or nineteenth embodiment, a red light emitting diode chip 63, a green light emitting diode chip 64, and a blue light emitting diode. At least one chip 65 is included, and a required number of cells 75 each having a predetermined pattern are arranged on the printed wiring board 76 in a predetermined pattern. In this example, each cell 75 includes a red light emitting diode chip 63, a green light emitting diode chip 64, and a blue light emitting diode chip 65, which are arranged at the apexes of an equilateral triangle. FIG. 35B shows the cell 75 in an enlarged manner. The interval a between the red light emitting diode chip 63, the green light emitting diode chip 64, and the blue light emitting diode chip 65 in each cell 75 is, for example, 4 mm, but is not limited thereto. The interval b of the cells 75 is, for example, 30 mm, but is not limited to this. As the printed wiring board 76, for example, an FR4 (abbreviation of Flame Retardant Type 4) board, a metal core board, a flexible wiring board, or the like can be used, but any other printed wiring board having heat dissipation can be used. However, it is not limited to these. As in the eighth embodiment, potting of the transparent resin 68 is performed so as to cover each cell 76, or, as in the ninth embodiment, the transparent resin 68 is covered so as to cover the red light emitting diode chip 63. 69, potting of the transparent resin 70 is performed so as to cover the green light emitting diode chip 64, and potting of the transparent resin 71 is performed so as to cover the blue light emitting diode chip 65. In this way, a light source cell unit is obtained in which the cells 75 including the red light emitting diode chip 63, the green light emitting diode chip 64, and the blue light emitting diode chip 65 are arranged on the printed wiring board 76.

Specific examples of the arrangement of the cells 75 on the printed wiring board 76 are shown in FIGS. 36 and 37, but are not limited thereto. The example shown in FIG. 36 has cells 75 arranged in a 4 × 3 two-dimensional array, and the example shown in FIG. 37 has cells 75 arranged in a 6 × 2 two-dimensional array.
FIG. 38 shows another configuration example of the cell 75. In this example, the cell 75 includes one red light emitting diode chip 63, two green light emitting diode chips 64, and one blue light emitting diode chip 65, which are arranged at the apex of a square, for example. Has been. Two green light emitting diode chips 64 are arranged at the apexes of both ends of one diagonal of the square, and a red light emitting diode chip 63 and a blue light emitting diode chip 65 are arranged at both ends of the other diagonal of the square. It is placed at the vertex.
By arranging one or a plurality of the light source cell units, a light emitting diode backlight suitable for use in a backlight of a liquid crystal panel, for example, can be obtained.

As mentioned above, although embodiment of this invention was described concretely, this invention is not limited to the above-mentioned embodiment, The various deformation | transformation based on the technical idea of this invention is possible.
For example, the numerical values, materials, structures, configurations, shapes, substrates, raw materials, processes, and the like given in the first to twentieth embodiments are merely examples, and if necessary, numerical values, materials, Structures, configurations, shapes, substrates, raw materials, processes, and the like may be used.

It is a basic diagram for demonstrating the growth method of the nitride type III-V compound semiconductor layer by 1st Embodiment of this invention. It is a basic diagram for demonstrating the growth method of the nitride type III-V compound semiconductor layer by 1st Embodiment of this invention. It is a drawing substitute photograph which shows the sample which grew the GaN layer with the growth method of the nitride type | system | group III-V compound semiconductor layer by 1st Embodiment of this invention. It is a basic diagram which shows the result of the X-ray-diffraction measurement of the GaN layer grown with the growth method of the nitride type III-V compound semiconductor layer by 1st Embodiment of this invention. It is a basic diagram for demonstrating the growth method of the nitride type III-V group compound semiconductor layer by 2nd Embodiment of this invention. It is a basic diagram for demonstrating the growth method of the nitride type III-V group compound semiconductor layer by 2nd Embodiment of this invention. It is a drawing substitute photograph which shows the sample which grew the GaN layer with the growth method of the nitride type | system | group III-V compound semiconductor layer by 1st Embodiment of this invention. It is a basic diagram which shows the result of the X-ray-diffraction measurement of the GaN layer grown with the growth method of the nitride type III-V compound semiconductor layer by 1st Embodiment of this invention. It is a basic diagram for demonstrating the growth method of the nitride type III-V compound semiconductor layer by 3rd Embodiment of this invention. It is a basic diagram for demonstrating the growth method of the nitride type III-V compound semiconductor layer by 3rd Embodiment of this invention. It is a drawing substitute photograph which shows the sample which grew the GaN layer with the growth method of the nitride type | system | group III-V compound semiconductor layer by 3rd Embodiment of this invention. It is a drawing substitute photograph which shows the sample which grew the GaN layer with the growth method of the nitride type | system | group III-V compound semiconductor layer by 3rd Embodiment of this invention. It is a basic diagram for demonstrating the growth method of the nitride type III-V compound semiconductor layer by 3rd Embodiment of this invention. It is a drawing substitute photograph which shows the sample which grew the GaN layer with the growth method of the nitride type | system | group III-V compound semiconductor layer by 3rd Embodiment of this invention. It is a drawing substitute photograph which shows the sample which grew the GaN layer with the growth method of the nitride type | system | group III-V compound semiconductor layer by 3rd Embodiment of this invention. It is a basic diagram for demonstrating the growth method of the nitride type III-V compound semiconductor layer by 4th Embodiment of this invention. It is a basic diagram for demonstrating the growth method of the nitride type III-V compound semiconductor layer by 5th Embodiment of this invention. It is a basic diagram for demonstrating the growth method of the nitride type III-V compound semiconductor layer by 6th Embodiment of this invention. It is a basic diagram for demonstrating the growth method of the nitride type III-V compound semiconductor layer by 7th Embodiment of this invention. It is a basic diagram for demonstrating the growth method of the nitride type III-V compound semiconductor layer by 8th Embodiment of this invention. It is a basic diagram for demonstrating the growth method of the nitride type III-V compound semiconductor layer by 9th Embodiment of this invention. It is a basic diagram for demonstrating the growth method of the nitride type III-V compound semiconductor layer by 10th Embodiment of this invention. It is a basic diagram for demonstrating the growth method of the nitride type III-V compound semiconductor layer by 11th Embodiment of this invention. It is a basic diagram for demonstrating the growth method of the nitride type III-V compound semiconductor layer by 12th Embodiment of this invention. It is a basic diagram for demonstrating the growth method of the nitride type III-V compound semiconductor layer by 13th Embodiment of this invention. It is a basic diagram for demonstrating the growth method of the nitride type III-V compound semiconductor layer by 14th Embodiment of this invention. It is a basic diagram for demonstrating the growth method of the nitride type III-V compound semiconductor layer by 15th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 16th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 16th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 17th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode backlight by 18th Embodiment of this invention. It is a perspective view for demonstrating the manufacturing method of the light emitting diode backlight by 18th Embodiment of this invention. It is a perspective view for demonstrating the manufacturing method of the light emitting diode backlight by 18th Embodiment of this invention. It is a perspective view for demonstrating the manufacturing method of the light emitting diode backlight by 19th Embodiment of this invention. It is the top view which shows the light source cell unit by 20th Embodiment of this invention, and the enlarged view of the cell of this light source cell unit. It is a top view which shows one specific example of the light source cell unit by 20th Embodiment of this invention. It is a top view which shows the other specific example of the light source cell unit by 20th Embodiment of this invention. It is a top view which shows the other structural example of the cell of the light source cell unit by 20th Embodiment of this invention. It is sectional drawing which shows the semiconductor light-emitting device proposed by Unexamined-Japanese-Patent No. 11-112029.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Sapphire substrate, 12 ... Nitride type III-V group compound semiconductor layer, 13 ... Convex part, 14 ... Concave part, 15 ... Dislocation, 16 ... N-type nitride type III-V group compound semiconductor layer, 17 ... Active layer 18 ... p-type nitride III-V compound semiconductor layer, 19 ... p-side electrode, 21 ... n-side electrode

Claims (10)

The (1-100) plane of the substrate made of a substance having a hexagonal crystal structure is made of a semiconductor having a hexagonal crystal structure and has a (11-22) or (10-13) plane orientation. A method for growing a semiconductor layer, comprising: growing a semiconductor layer having a (11-20) facet, a (0001) facet and a (11-22) facet . 2. The method for growing a semiconductor layer according to claim 1, wherein the semiconductor layer is made of a semiconductor having a wurtzite structure. 2. The method of growing a semiconductor layer according to claim 1, wherein the semiconductor layer is made of a nitride III-V compound semiconductor, an oxide semiconductor, or oxychalcogenide. 2. The method for growing a semiconductor layer according to claim 1, wherein one main surface of the substrate is a (1-100) plane. 2. The method for growing a semiconductor layer according to claim 1, wherein at least one recess is formed on one main surface of the substrate, and one side surface of the recess is a (1-100) plane. The (1-100) plane of the substrate made of a substance having a hexagonal crystal structure is made of a semiconductor having a hexagonal crystal structure and has a (11-22) or (10-13) plane orientation. A method for manufacturing a semiconductor light emitting device, comprising: growing a semiconductor layer having a (11-20) plane facet, a (0001) plane facet, and a (11-22) plane facet. The method for manufacturing a semiconductor light emitting device according to claim 6, wherein the semiconductor layer is made of a semiconductor having a wurtzite structure. 7. The method of manufacturing a semiconductor light emitting device according to claim 6, wherein the semiconductor layer is made of a nitride III-V compound semiconductor, an oxide semiconductor, or oxychalcogenide. The method for manufacturing a semiconductor light emitting element according to claim 6, wherein one main surface of the substrate is a (1-100) plane. 7. The method of manufacturing a semiconductor light emitting element according to claim 6, wherein at least one recess is formed on one main surface of the substrate, and one side surface of the recess is a (1-100) plane.

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