JP4915218B2 - Manufacturing method of light emitting diode - Google Patents

Description

  The present invention relates to a light emitting diode, a method for manufacturing the same, a light source cell unit, a light emitting diode backlight, a light emitting diode illuminating device, a light emitting diode display, and an electronic device. The present invention is suitable for application to various devices or equipment using the light emitting diode.

When a GaN-based semiconductor is epitaxially grown on a heterogeneous substrate such as a sapphire substrate, crystal defects, particularly threading dislocations, occur at a high density because of a large difference in lattice constant and thermal expansion coefficient between the two.
In order to avoid this problem, a technique for reducing dislocation density by selective lateral growth has been widely used. In this technology, after a GaN-based semiconductor is first epitaxially grown on a sapphire substrate or the like, the substrate is taken out from the crystal growth apparatus, and a growth mask made of a SiO ₂ film or the like is formed on the GaN-based semiconductor layer, and then this substrate Is returned to the crystal growth apparatus, and a GaN-based semiconductor is epitaxially grown again using this growth mask.
According to this technique, the dislocation density of the upper GaN-based semiconductor layer can be reduced, but the cost is high because two epitaxial growths are required.

  Therefore, a method has been proposed in which uneven processing is performed on a different substrate in advance and a GaN-based semiconductor is epitaxially grown on the processed substrate (for example, see Non-Patent Document 1, Patent Documents 1 and 2). An overview of this method is shown in FIGS. According to this method, first, as shown in FIG. 83A, an uneven surface is applied to one principal surface of the c-plane sapphire substrate 101. The code | symbol 101a shows a recessed part and 101b shows a convex part. These concave portions 101 a and convex portions 101 b extend in the <1-100> direction of the sapphire substrate 101. Next, the GaN-based semiconductor layer 102 is grown on the sapphire substrate 101 through the process shown in FIGS. 83B and 83C. In FIG. 83C, a dotted line indicates a growth interface in the middle of growth. What is characteristic here is that a gap 103 is formed between the sapphire substrate 101 and the GaN-based semiconductor layer 102 in the recess 101a as shown in FIG. 83C. FIG. 84 schematically shows the crystal defect distribution of the GaN-based semiconductor layer 102 grown by this method. As shown in FIG. 84, threading dislocations 104 are generated in the vertical direction from the interface with the upper surface of the convex portion 101b in the portion of the GaN-based semiconductor layer 102 on the convex portion 101b to form a high defect density region 105. Thus, the portion between the high defect density regions 105 above the recesses 101 a is a low defect density region 106.

For reference, in FIGS. 85A to 85D, the GaN-based semiconductor layer 102 in the case where the extending direction of the concave portion 101a and the convex portion 101b is the <11-20> direction orthogonal to the <1-100> direction of the sapphire substrate 101. Shows the growth of
86A to 86F show another conventional growth method different from the above (see, for example, Patent Document 3). In this method, as shown in FIG. 86A, a sapphire substrate 101 subjected to unevenness processing is used, and a GaN-based semiconductor layer 102 is grown thereon through the processes shown in FIGS. According to this method, the GaN-based semiconductor layer 102 can be grown without forming a gap with the sapphire substrate 101.

A growth method has been proposed in which a convex portion is formed on a substrate using a material different from that of the substrate and growth of a nitride III-V group compound semiconductor is started from a concave portion between the convex portions (for example, Patent Document 4). 5), and these growth modes differ greatly from the present invention.
Mitsubishi Cable Industrial Time Report No. 98 October 2001: Development of high power ultraviolet LED using LEPS method JP 2004-6931 A JP 2004-6937 A JP 2003-318441 A Japanese Patent Laid-Open No. 2003-324069 Japanese Patent No. 2830814

  In the conventional growth method shown in FIG. 83, the gap 103 is formed between the sapphire substrate 101 and the GaN-based semiconductor layer 102 as described above. According to the knowledge of the present inventor, the GaN-based semiconductor is formed. When a light emitting diode structure is formed by growing a GaN-based semiconductor layer on the layer 102, there is a problem that the light emitting diode has low light emission efficiency. This is presumably because the light generated from the active layer during the operation of the light emitting diode is repeatedly reflected inside the gap 103 and absorbed as a result, resulting in poor light extraction efficiency.

  On the other hand, in the conventional growth method shown in FIG. 86, although no void is formed between the sapphire substrate 101 and the GaN-based semiconductor layer 102, the dislocation density of the GaN-based semiconductor layer 102 is shown in FIG. It is considered difficult to reduce the level to the same level as the growth method. Therefore, when a GaN-based semiconductor layer is grown on the GaN-based semiconductor layer 102 having a high dislocation density to form a light-emitting diode structure, the dislocation density of these GaN-based semiconductor layers also increases, which reduces the light emission efficiency. I was invited.

Therefore, the problem to be solved by the present invention is that the light emission efficiency is extremely high due to the significant improvement in light extraction efficiency and the crystallinity of the nitride III-V compound semiconductor layer constituting the light emitting diode, Moreover, it is an object of the present invention to provide a light emitting diode that can be manufactured at a low cost by one epitaxial growth and a manufacturing method thereof.
Another problem to be solved by the present invention is to provide a high-performance light source cell unit, a light-emitting diode backlight, a light-emitting diode illuminating device, a light-emitting diode display, and an electronic device using the light-emitting diode as described above. .
Still another problem to be solved by the present invention is that the light extraction efficiency is greatly improved and the crystallinity of the nitride III-V compound semiconductor layer and other various semiconductor layers constituting the light emitting diode structure is greatly increased. It is an object of the present invention to provide a light emitting diode which can be manufactured at a low cost by an epitaxial growth at a low cost and a manufacturing method thereof.
The above and other problems will become apparent from the description of this specification with reference to the accompanying drawings.

In order to solve the above problem, the first invention is:
Using a substrate having a plurality of convex portions on one main surface, the first nitride-based III-V group compound semiconductor layer is formed in the concave portion of the substrate through a triangular cross-sectional shape with the bottom surface as the base. A growing process;
Laterally growing a second nitride III-V compound semiconductor layer on the substrate from the first nitride III-V compound semiconductor layer;
On the second nitride III-V compound semiconductor layer, the third conductivity type third nitride III-V compound semiconductor layer, the active layer, and the second conductivity type fourth nitride. Sequentially growing a III-V compound semiconductor layer,
The first nitride III-V compound semiconductor layer, the second nitride III-V compound semiconductor layer, the third nitride III-V compound semiconductor layer, the active layer, and the above Of the fourth nitride-based III-V compound semiconductor layer, a portion corresponding to the central portion between the recess and / or the recesses adjacent to each other is used as the fourth nitride-based III-V compound semiconductor layer. Forming a groove by removing from the surface of the layer in a depth direction until at least the third nitride III-V compound semiconductor layer is exposed;
The groove is filled with a dielectric that is transparent to the light having the emission wavelength from the active layer. At this time, the surface of the dielectric has a recess and / or a protrusion, and / or the dielectric A method for producing a light emitting diode, comprising the step of containing scattering particles.

The convex portion of the substrate is made of a material different from the substrate or the same material as the substrate.
The conductivity type of the first nitride III-V compound semiconductor layer and the second nitride III-V compound semiconductor layer may be any of p-type, n-type, and i-type, The conductivity types may or may not be the same conductivity type, and the conductivity types may be within the first nitride III-V compound semiconductor layer or the second nitride III-V compound semiconductor layer. Two or more different parts may be mixed.

  Typically, when the first nitride-based III-V compound semiconductor layer is grown, dislocations are generated in a direction perpendicular to the principal surface of the substrate from the interface with the bottom surface of the recess of the substrate. When the dislocation reaches the slope of the first nitride-based III-V compound semiconductor layer in the state of having a triangular cross-sectional shape or the vicinity thereof, a triangular portion is formed in a direction parallel to the one principal surface. Bend away from the camera. Here, the triangular cross-sectional shape or the triangular shape in the triangular portion means not only an accurate triangle, but also includes what can be regarded as an approximate triangle, such as a rounded top (for example) ( The same applies below). Preferably, in the initial stage of growth of the first nitride-based III-V group compound semiconductor layer, a plurality of micronuclei are formed on the bottom surface of the concave portion of the substrate, and these micronuclei grow and coalesce. Thus, dislocations generated from the interface with the bottom surface of the concave portion of the substrate in a direction perpendicular to one main surface of the substrate are repeatedly bent in a direction parallel to the one main surface. By doing so, dislocations that escape to the top during the growth of the first nitride-based III-V compound semiconductor layer can be reduced.

  As described above, the number of dislocations that escape to the top during the growth of the first nitride-based III-V compound semiconductor layer can be reduced, but the dislocations that escape to the top are the second nitride-based III-V in the upper layer. It propagates to the group compound semiconductor layer, the third nitride-based III-V group compound semiconductor layer, the active layer, and the fourth nitride-based group III-V compound semiconductor layer to form threading dislocations. This threading dislocation includes a first nitride-based III-V compound semiconductor layer, a second nitride-based III-V compound semiconductor layer, a third nitride-based III-V compound semiconductor layer, an active layer, and The fourth nitride-based III-V group compound semiconductor layer concentrates on a portion corresponding to the recess (portion above the recess). The threading dislocations and the vicinity thereof have poor crystallinity and a large number of non-emissive centers exist, so that the luminous efficiency is lowered. In particular, the non-radiative centers present in the active layer have a great adverse effect on the luminous efficiency. Therefore, the first nitride III-V compound semiconductor layer, the second nitride III-V compound semiconductor layer, the third nitride III-V compound semiconductor layer, the active layer, and the fourth A portion of the nitride-based III-V compound semiconductor layer that corresponds to the recess is at least a third nitride-based III- in the depth direction from the surface of the fourth nitride-based III-V compound semiconductor layer. If the groove is formed by removing the V group compound semiconductor layer until it is exposed, at least the active layer and those generated in the upper layer of the threading dislocations can be removed, so that the non-luminescent center is greatly reduced. be able to. The width of the portion to be removed may be, for example, a width capable of removing all or most of the threading dislocations, and may be the same as the width of the recess, smaller than the width of the recess, or larger than the width of the recess. . This removal can be performed by various methods such as a reactive ion etching (RIE) method, a powder blast method, and a sand blast method. On the other hand, when the second nitride-based III-V compound semiconductor layer is grown in the lateral direction, threading dislocations are present at the association portion of the second nitride-based III-V compound semiconductor layer above the convex portion. The threading dislocations of the second nitride-based III-V compound semiconductor layer are concentrated, and the third nitride-based III-V compound semiconductor layer, the active layer, and the fourth nitride-based III-V group of the upper layer are concentrated. Propagates to the compound semiconductor layer. This threading dislocation is caused by the second nitride III-V compound semiconductor layer, the third nitride III-V compound semiconductor layer, the active layer, and the fourth nitride III-V compound semiconductor layer. It concentrates on the part corresponding to the center part between the mutually adjacent recessed parts (part on the center part between recessed parts). Therefore, the second nitride III-V compound semiconductor layer, the third nitride III-V compound semiconductor layer, the active layer, and the fourth nitride III-V compound semiconductor layer are mutually connected. At least a third nitride-based III-V compound semiconductor layer is formed in the depth direction from the surface of the fourth nitride-based III-V compound semiconductor layer at a portion corresponding to the central portion between adjacent recesses. When the groove is formed by removing it until it is exposed, at least the active layer of the threading dislocations and those generated in the upper layer can be removed, so that the non-luminescent center can be greatly reduced. The width of the part to be removed may be a width that can remove all or most of the threading dislocations, for example. This removal can also be performed by various methods such as RIE, powder blasting, and sand blasting.

  As described above, the first nitride-based III-V compound semiconductor layer, the second nitride-based III-V compound semiconductor layer, the third nitride-based III-V compound semiconductor layer, the active layer, and After forming a groove in a portion corresponding to the central portion between the recesses and / or the recesses adjacent to each other in the fourth nitride-based III-V group compound semiconductor layer, the light of the emission wavelength from the active layer The groove is filled with a transparent dielectric, the surface of the dielectric having recesses and / or protrusions and / or the dielectric containing light scattering particles. This dielectric is preferably a first nitride-based III-V compound semiconductor layer, a second nitride-based III-V compound semiconductor layer, and a third nitride-based III-V compound semiconductor layer. The refractive index is smaller than that of the active layer and the fourth nitride-based III-V compound semiconductor layer, but is not limited thereto. After that, typically, an electrode on the second conductivity type side is formed on the fourth nitride-based III-V compound semiconductor layer so as to cover the surface of the dielectric filling the groove. On the surface of the dielectric, a reflection film made of a highly reflective material having a high reflectance of light having an emission wavelength from the active layer is formed as necessary. As the material of the electrode on the second conductivity type side, a highly reflective material having a high reflectance of light having an emission wavelength from the active layer is preferably used.

When the surface of the dielectric filling the groove has a recess and / or a protrusion, the recess at the interface between the electrode on the second conductivity type side and the dielectric filling the groove out of the light generated from the active layer And / or the light incident on the convex part is reflected by the surface of the concave part and / or the convex part. Here, assuming that the angle between the normal of the main surface of the substrate passing through the incident point of the light and the incident light is θ ₁ , and the angle between the normal and the reflected light is θ ₂ , θ ₁ > θ ₂ It is desirable to select the inclination angle of the concave and / or convex surfaces so that the amount of light to be as large as possible. No recesses and / or protrusions are formed, the surface of the fourth nitride III-V compound semiconductor layer is flat, and the substrate and the fourth nitride III-V compound semiconductor layer are parallel to each other In some cases, when light generated from the active layer is incident on the interface between the fourth nitride-based III-V compound semiconductor layer and the second conductivity type electrode formed thereon at a large incident angle. In this interface, the light is reflected at a reflection angle substantially equal to the incident angle and is directed toward the substrate side. When the incident angle of light with respect to the main surface of the substrate is larger than the critical angle, total reflection is performed on the main surface of the substrate, The reflection is repeated inside the fourth nitride-based III-V compound semiconductor layer and the active layer, and is absorbed by the active layer in the process and gradually attenuates. Invitation to fill the ditch while the amount is less If the surface of the body has a recess and / or projections, by which may be θ _1> θ ₂ as described above, eliminates this problem, the final amount of the light can be taken out to the outside Can do a lot. The dielectric that fills the groove may be an inorganic material or an organic material, and an optimum material is appropriately used according to the temperature of the process after filling the groove. Specifically, the dielectric is, for example, silicon dioxide (SiO ₂ ), polyimide, or water glass that is solidified into glass, but is not limited thereto. In addition, in order to fill the groove with a dielectric and form a concave portion and / or a convex portion on the surface thereof, for example, when SiO ₂ is used as the dielectric, the _{first step} is performed using a vacuum process such as vacuum deposition or sputtering. After depositing SiO ₂ on the nitride-based group III-V compound semiconductor layer 4 to fill the groove, the dielectric is patterned using a lithography technique and an etching technique. Alternatively, when polyimide is used as the dielectric, for example, a hydrophilic photoresist film made of polyethylene glycol dimethacrylate or the like is formed on the fourth nitride-based III-V group compound semiconductor layer other than the groove. After that, a hydrophobic polyimide precursor solution is formed by spin coating or the like to fill the groove, and after removing the photoresist film, firing is performed to solidify the film made of this polyimide precursor solution to form the groove. The surface of the polyimide to be filled can be made convex.

On the other hand, when the dielectric filling the grooves contains light scattering particles, light generated from the active layer is scattered when incident on the light scattering particles, so that the amount of light satisfying θ ₁ > θ ₂ is reduced. Become more. The size (particle size), material, and the like of the light scattering particles are selected so that light having an emission wavelength from the active layer can be efficiently scattered. Specifically, the light scattering particles can be formed of, for example, aluminum oxide, titanium oxide, zirconium oxide, silicon nitride, boron nitride, barium titanate, silicon carbide, and the like, but are not limited thereto. Absent. The particle diameter of the light scattering particles is generally selected to be equal to or less than the wavelength of light from the active layer (emission wavelength) in order to reduce light absorption loss due to the light scattering particles. Specifically, it is selected to be 20 to 1000 nm, for example. In order to fill the groove with a dielectric containing the light scattering particles, for example, a water glass or polyimide precursor solution in which the light scattering particles are dispersed is formed by spin coating or the like to fill the groove and perform firing. Use glass or polyimide.
Preferably, the surface of the dielectric filling the groove has a concave portion and / or a convex portion, and the dielectric includes light scattering particles. By doing so, the amount of light satisfying θ ₁ > θ ₂ is further increased.

  The first nitride III-V compound semiconductor layer, the second nitride III-V compound semiconductor layer, the third nitride III-V compound semiconductor layer, the active layer, and the fourth Of the nitride-based III-V group compound semiconductor layer, a portion corresponding to the central portion between the recesses and / or the recesses adjacent to each other is deepened from the surface of the fourth nitride-based III-V group compound semiconductor layer. By forming the groove by removing in the direction until the substrate is exposed, almost all threading dislocations can be removed. In particular, when the convex portion is made of a material different from that of the substrate, the convex portion, the first nitride III-V compound semiconductor layer, the second nitride III-V compound semiconductor layer, and the third nitride III The portion corresponding to the central portion between the recesses and / or the recesses adjacent to each other in the group V compound semiconductor layer, the active layer, and the fourth nitride-based III-V group compound semiconductor layer is the fourth nitride. Grooves are formed by removing the substrate from the surface of the III-V compound semiconductor layer in the depth direction until the substrate is exposed. After the substrate is thus exposed, the remaining convex portions are removed by wet etching or the like. Thus, the first nitride III-V compound semiconductor layer, the second nitride III-V compound semiconductor layer, the third nitride III-V compound semiconductor layer, the active layer, and the fourth Nitride system III V compound semiconductor layer can be peeled from the substrate. As a material for the convex portion in this case, an amorphous material that can be easily removed by etching is preferably used. However, this peeling may be performed by other methods such as peeling by laser light irradiation (so-called laser peeling). The peeled substrate can be reused after being subjected to a treatment such as surface polishing as necessary.

Typically, convex portions and concave portions are alternately and periodically formed on one main surface of the substrate. In this case, the period of a convex part and a recessed part is 3-5 micrometers suitably. Further, the ratio of the length of the bottom of the convex portion to the length of the bottom of the concave portion is preferably 0.5 to 3, and most preferably around 0.5. The height of the convex portion viewed from one main surface of the substrate is preferably 0.3 μm or more, more preferably 1 μm or more. The convex portion preferably has a side surface inclined with respect to one main surface of the substrate (for example, a side surface in contact with one main surface of the substrate), and an angle between the side surface and one main surface of the substrate is θ. Then, from the viewpoint of improving the light extraction efficiency, for example, preferably 100 ° <θ <160 °, more preferably 132 ° <θ <139 ° or 147 ° <θ <154 °, which is most preferable. Is 135 ° or 152 °. The cross-sectional shape of the convex portion may be various shapes, and the side surface may be a curved surface as well as a flat surface. For example, an n-gon (where n is an integer of 3 or more), specifically Triangular, quadrangular, pentagonal, hexagonal, etc., or those with their corners cut off, rounded corners, circular, oval, etc. Of these, the highest position when viewed from one main surface of the board Those having one apex are desirable, and in particular, a triangle or a shape obtained by cutting off the apex or a rounded apex is most desirable. Although the cross-sectional shape of the recess may be various shapes, for example, an n-gon (where n is an integer of 3 or more), specifically, a triangle, a quadrangle, a pentagon, a hexagon, or the like, or these corners are cut off. Or rounded, oval, etc. From the viewpoint of improving the light extraction efficiency, preferably, the cross-sectional shape of the recess is an inverted trapezoid. Here, the inverted trapezoidal shape means not only an accurate inverted trapezoid but also includes an object that can be approximately regarded as an inverted trapezoid (the same applies hereinafter). In this case, from the viewpoint of minimizing the dislocation density of the second nitride-based III-V compound semiconductor layer, it is preferable that the depth of the concave portion (same as the height of the convex portion) be d and the width of the bottom surface of the concave portion. when a you a W _g, the angle between the inclined surface and the main surface of the substrate of the first nitride III-V compound semiconductor layer in a state where a triangular cross-sectional shape is alpha, the 2d ≧ W _g tan [alpha D, W _g , and α are determined so as to hold. Since α is normally constant, d and W _g are determined so that this equation is satisfied. If d is too large, the source gas is not sufficiently supplied to the inside of the recess, which hinders the growth of the first nitride-based III-V compound semiconductor layer from the bottom of the recess, and conversely if d is too small. The first nitride-based III-V compound semiconductor layer grows not only on the concave portion of the substrate but also on the convex portions on both sides thereof. From the viewpoint of preventing these, generally, 0.5 μm <d It is selected within the range of <5 μm, and typically selected within the range of 1.0 ± 0.2 μm. W _g is generally 0.5 to 5 μm, and is typically selected within a range of 2 ± 0.5 μm. Further, the width W _t of the top surface of the convex portion is 0 when the cross-sectional shape of the convex portion is triangular, but when the cross-sectional shape of the convex portion is trapezoidal, this convex portion is the second nitride system. Since it is a region used for the lateral growth of the III-V compound semiconductor layer, the longer the area, the larger the area of the portion having a lower dislocation density. When the cross-sectional shape of the convex portion is trapezoidal, W _t is generally 1 to 1000 μm.

  For example, the convex portion or the concave portion may extend in a stripe shape in one direction on the substrate, or may extend in a stripe shape in at least a first direction and a second direction intersecting each other. As a result, the convex portion is an n-gon (where n is an integer of 3 or more), specifically, a triangle, a quadrangle, a pentagon, a hexagon, or the like, or those with the corners cut off, rounded, or circular Alternatively, it may be a two-dimensional pattern such as an ellipse or a dot. In a preferred example, the convex portions have a hexagonal planar shape, the convex portions are two-dimensionally arranged in a honeycomb shape, and concave portions are formed so as to surround the convex portions. By doing so, light emitted from the active layer can be efficiently extracted in all directions of 360 °. Alternatively, the recess may have a hexagonal planar shape, the recesses may be two-dimensionally arranged in a honeycomb shape, and a protrusion may be formed so as to surround the recess. When the concave portion of the substrate has a stripe shape, the concave portion extends, for example, in the <1-100> direction of the first nitride-based III-V compound semiconductor layer, or a sapphire substrate is used as the substrate, for example. In some cases, the sapphire substrate may extend in the <11-20> direction. The convex portion is, for example, an n-pyramid (where n is an integer of 3 or more), specifically, a triangular pyramid, a quadrangular pyramid, a pentagonal pyramid, a hexagonal pyramid, etc., or a cut or rounded corner. Things, cones, elliptical cones, etc.

When the convex portion is made of a material different from that of the substrate, the material of the convex portion may be various, and may or may not be conductive. For example, a dielectric such as an oxide, nitride or carbide, metal Or a conductor such as an alloy (including a transparent conductor). As the oxide, for example, various oxides such as silicon oxide (SiO _x ), titanium oxide (TiO _x ), and tantalum oxide (TaO _x ) can be used, and two or more of these can be mixed or laminated. It can also be used in the form of a membrane. As the nitride, for example, silicon nitride (SiN _x ), SiON, CrN, CrNO or the like can be used, and two or more of these can be mixed or used in the form of a laminated film. As the carbide, SiC, HfC, ZrC, WC, TiC, CrC or the like can be used, and two or more of these can be mixed or used in the form of a laminated film. As the metal or alloy, B, Al, Ga, In, W, Ni, Co, Pd, Pt, Ag, AgNi, AgPd, AuNi, AuPd, and the like can be used. Alternatively, it can be used in the form of a laminated film. As the transparent conductor, ITO (indium-tin composite oxide), IZO (indium-zinc composite oxide), ZO (zinc oxide), FTO (fluorine-doped tin oxide), tin oxide, and the like can be used. Two or more of these may be mixed or used in the form of a laminated film. Further, two or more of the various materials described above can be mixed or used in the form of a laminated film. A convex portion may be formed of metal or the like, and nitride, oxide, or carbide may be formed by nitriding, oxidizing, or carbonizing at least the surface of the convex portion.

The refractive index of the convex portion is determined by design as necessary, but in general, the refractive index is different from the refractive index of the substrate and the refractive index of the nitride III-V compound semiconductor layer grown on the substrate. Typically, it is selected to be equal to or lower than the refractive index of the substrate.
If necessary, the projections may scatter light emitted from the active layer, improve light extraction efficiency, and introduce a scattering center for the purpose of increasing the output of the light emitting diode. . As such a scattering center, for example, silicon fine particles such as silicon nanocrystals can be used. In order to form the convex portion into which such silicon fine particles are introduced, for example, the convex portion may be formed on the substrate with silicon oxide and then heat treatment may be performed.

From the viewpoint of growing the first nitride-based III-V compound semiconductor layer only in the concave portion of the substrate, for example, at least the surface of the convex portion may be formed of an amorphous layer. This amorphous layer serves as a growth mask. This utilizes the fact that nucleation hardly occurs during growth on an amorphous layer. This amorphous layer may be formed on the substrate by various film forming methods, or may be formed by forming a convex portion with metal or the like and oxidizing the surface of the convex portion. This amorphous layer is, for example, a SiO _x film, a SiN _x film, an amorphous Si (a-Si) film, an amorphous CrN film, or a laminated film of two or more of these, and is generally It is an insulating film. In some cases, the convex portion may be formed of a first amorphous layer, a second amorphous layer, and a third amorphous layer formed on the substrate. In this case, for example, the second amorphous layer may be selectively etched with respect to the first amorphous layer and the third amorphous layer.
In the third nitride-based III-V compound semiconductor layer, an electrode on the first conductivity type side is formed in a state of being electrically connected thereto. Similarly, an electrode on the second conductivity type side is formed on the fourth nitride-based III-V compound semiconductor layer in a state of being electrically connected thereto.

Various substrates can be used as the substrate. Specifically, the substrate made of a material different from the nitride III-V compound semiconductor includes, for example, sapphire (including a c-plane, a-plane, r-plane, etc., and a plane off from these planes). ), SiC (including 6H, 4H, 3C), Si, ZnS, ZnO, LiMgO, GaAs, spinel (MgAl ₂ O ₄ , ScAlMgO ₄ ), garnet, CrN (for example, CrN (111)), etc. Preferably, a hexagonal or cubic substrate made of these materials, more preferably a hexagonal substrate is used. As the substrate, a substrate made of a nitride III-V group compound semiconductor (GaN, AlGaInN, AlN, GaInN, etc.) may be used. Alternatively, a nitride III-V compound semiconductor layer is grown as a substrate on a substrate made of a material different from the nitride III-V compound semiconductor, and the nitride III-V compound semiconductor layer is formed on the nitride III-V compound semiconductor layer. What formed the convex part may be sufficient.
For example, when a substrate such as a nitride III-V group compound semiconductor layer grown on a substrate is used as the substrate, the material of the convex portion is different from that of the layer immediately below the convex portion. It is done.
The substrate may be removed as necessary.

The first to fourth nitride III-V compound semiconductor layer and the nitride constituting the active layer based III-V compound semiconductor layer, most _{commonly, Al X B y Ga 1-} xyz In z As _u N _1-uv P _v (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, 0 ≦ u ≦ 1, 0 ≦ v ≦ 1, 0 ≦ x + y + z <1, 0 ≦ u + v <consists 1), more _{specifically, Al X B y Ga 1-} xyz in z N ( However, 0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ z ≦ 1,0 ≦ x + y + z <1) Typically, it consists of Al _x Ga _{1 -xz} In _z N (where 0 ≦ x ≦ 1, 0 ≦ z ≦ 1). Specific examples are GaN, InN, AlN, AlGaN, InGaN. And AlGaInN. The nitride III-V compound semiconductor layer constituting the first to fourth nitride III-V compound semiconductor layers and the active layer promotes the bending of dislocations when, for example, B or Cr is contained in GaN. Therefore, it may be made of BGaN, GaN: B doped GaN: B, GaN: Cr doped GaN: Cr, or the like. Particularly first first nitride III-V compound semiconductor layer grown on the recessed portions of the substrate, _{preferably, GaN, In X Ga 1-} x N (0 <x <0.5), Al X A material consisting of Ga _1-x N (0 <x <0.5) and Al _x In _y Ga _1-xy N (0 <x <0.5, 0 <y <0.2) is used. The first conductivity type may be n-type or p-type, and the second conductivity type is p-type or n-type accordingly. In addition, as a so-called low-temperature buffer layer that is first grown on the substrate, a GaN buffer layer, an AlN buffer layer, an AlGaN buffer layer, etc. are generally used, and those doped with Cr or CrN buffer layers are used. Also good.

The thickness of the second nitride-based III-V compound semiconductor layer is selected as necessary, and is typically about several μm or less, but is thicker depending on the application, for example, about several tens to 300 μm. It may be.
Examples of a method for growing the nitride III-V compound semiconductor layers constituting the first to fourth nitride III-V compound semiconductor layers and the active layer include, for example, metal organic chemical vapor deposition (MOCVD), Various epitaxial growth methods such as hydride vapor phase epitaxial growth, halide vapor phase epitaxial growth (HVPE), and molecular beam epitaxy (MBE) can be used.

The second invention is
A substrate having a plurality of convex portions on one main surface;
A fifth nitride-based III-V compound semiconductor layer grown on the substrate without forming a void in the recess of the substrate;
The third nitride III-V compound semiconductor layer of the first conductivity type on the fifth nitride III-V compound semiconductor layer, the active layer, and the fourth nitride of the second conductivity type A system III-V compound semiconductor layer,
In the fifth nitride-based III-V compound semiconductor layer, a dislocation generated in a direction perpendicular to the one main surface from the interface with the bottom surface of the recess is a triangular portion having the bottom surface of the recess as a base. Is bent in a direction parallel to the one principal surface,
Of the fifth nitride III-V compound semiconductor layer, the third nitride III-V compound semiconductor layer, the active layer, and the fourth nitride III-V compound semiconductor layer At least the third nitridation in a depth direction from the surface of the fourth nitride-based III-V compound semiconductor layer. The physical group III-V compound semiconductor layer is removed until it is exposed to form a groove, and the groove is filled with a dielectric transparent to the light having the emission wavelength from the active layer, and the surface of the dielectric is It is a light emitting diode which has a recessed part and / or a convex part, and / or the said dielectric material contains light-scattering particle | grains.

In the second invention and the third to seventh inventions described later, the fifth nitride-based III-V compound semiconductor layer is the first nitride-based III-V compound semiconductor layer in the first invention and This corresponds to the second nitride-based III-V compound semiconductor layer. The dielectric filling the trench is preferably a fifth nitride III-V compound semiconductor layer, a third nitride III-V compound semiconductor layer, an active layer, and a fourth nitride III- Although it has a refractive index smaller than the refractive index of a V group compound semiconductor layer, it is not limited to this.
The substrate may be removed as necessary.
In the second invention and the third to thirteenth inventions to be described later, what has been described in relation to the first invention is valid as long as it is not contrary to the nature thereof.

The third invention is
In a light source cell unit in which a plurality of cells each including at least one red light emitting diode, green light emitting diode and blue light emitting diode are arranged,
At least one of the red light emitting diode, the green light emitting diode, and the blue light emitting diode,
A substrate having a plurality of convex portions on one main surface;
A fifth nitride-based III-V compound semiconductor layer grown on the substrate without forming a void in the recess of the substrate;
The third nitride III-V compound semiconductor layer of the first conductivity type on the fifth nitride III-V compound semiconductor layer, the active layer, and the fourth nitride of the second conductivity type A system III-V compound semiconductor layer,
In the fifth nitride-based III-V compound semiconductor layer, a dislocation generated in a direction perpendicular to the one main surface from the interface with the bottom surface of the recess is a triangular portion having the bottom surface of the recess as a base. Is bent in a direction parallel to the one principal surface,
Of the fifth nitride III-V compound semiconductor layer, the third nitride III-V compound semiconductor layer, the active layer, and the fourth nitride III-V compound semiconductor layer At least the third nitridation in a depth direction from the surface of the fourth nitride-based III-V compound semiconductor layer. The physical group III-V compound semiconductor layer is removed until it is exposed to form a groove, and the groove is filled with a dielectric transparent to the light having the emission wavelength from the active layer, and the surface of the dielectric is It has a recessed part and / or a convex part, and / or the said dielectric material is what contains a light-scattering particle, It is characterized by the above-mentioned.

The fourth invention is:
In a light emitting diode backlight in which a plurality of red light emitting diodes, green light emitting diodes and blue light emitting diodes are arranged,
At least one of the red light emitting diode, the green light emitting diode, and the blue light emitting diode,
A substrate having a plurality of convex portions on one main surface;
A fifth nitride-based III-V compound semiconductor layer grown on the substrate without forming a void in the recess of the substrate;
The third nitride III-V compound semiconductor layer of the first conductivity type on the fifth nitride III-V compound semiconductor layer, the active layer, and the fourth nitride of the second conductivity type A system III-V compound semiconductor layer,
In the fifth nitride-based III-V compound semiconductor layer, a dislocation generated in a direction perpendicular to the one main surface from the interface with the bottom surface of the recess is a triangular portion having the bottom surface of the recess as a base. Is bent in a direction parallel to the one principal surface,
Of the fifth nitride III-V compound semiconductor layer, the third nitride III-V compound semiconductor layer, the active layer, and the fourth nitride III-V compound semiconductor layer At least the third nitridation in a depth direction from the surface of the fourth nitride-based III-V compound semiconductor layer. The physical group III-V compound semiconductor layer is removed until it is exposed to form a groove, and the groove is filled with a dielectric transparent to the light having the emission wavelength from the active layer, and the surface of the dielectric is It has a recessed part and / or a convex part, and / or the said dielectric material is what contains a light-scattering particle, It is characterized by the above-mentioned.

The fifth invention is:
In a light emitting diode illuminating device in which a plurality of red light emitting diodes, green light emitting diodes and blue light emitting diodes are arranged,
At least one of the red light emitting diode, the green light emitting diode, and the blue light emitting diode,
A substrate having a plurality of convex portions on one main surface;
A fifth nitride-based III-V compound semiconductor layer grown on the substrate without forming a void in the recess of the substrate;
The third nitride III-V compound semiconductor layer of the first conductivity type on the fifth nitride III-V compound semiconductor layer, the active layer, and the fourth nitride of the second conductivity type A system III-V compound semiconductor layer,
In the fifth nitride-based III-V compound semiconductor layer, a dislocation generated in a direction perpendicular to the one main surface from the interface with the bottom surface of the recess is a triangular portion having the bottom surface of the recess as a base. Is bent in a direction parallel to the one principal surface,
Of the fifth nitride III-V compound semiconductor layer, the third nitride III-V compound semiconductor layer, the active layer, and the fourth nitride III-V compound semiconductor layer At least the third nitridation in a depth direction from the surface of the fourth nitride-based III-V compound semiconductor layer. The physical group III-V compound semiconductor layer is removed until it is exposed to form a groove, and the groove is filled with a dielectric transparent to the light having the emission wavelength from the active layer, and the surface of the dielectric is It has a recessed part and / or a convex part, and / or the said dielectric material is what contains a light-scattering particle, It is characterized by the above-mentioned.

The sixth invention is:
In a light emitting diode display in which a plurality of red light emitting diodes, green light emitting diodes and blue light emitting diodes are arranged,
At least one of the red light emitting diode, the green light emitting diode, and the blue light emitting diode,
A substrate having a plurality of convex portions on one main surface;
A fifth nitride-based III-V compound semiconductor layer grown on the substrate without forming a void in the recess of the substrate;
The third nitride III-V compound semiconductor layer of the first conductivity type on the fifth nitride III-V compound semiconductor layer, the active layer, and the fourth nitride of the second conductivity type A system III-V compound semiconductor layer,
In the fifth nitride-based III-V compound semiconductor layer, a dislocation generated in a direction perpendicular to the one main surface from the interface with the bottom surface of the recess is a triangular portion having the bottom surface of the recess as a base. Is bent in a direction parallel to the one principal surface,
Of the fifth nitride III-V compound semiconductor layer, the third nitride III-V compound semiconductor layer, the active layer, and the fourth nitride III-V compound semiconductor layer At least the third nitridation in a depth direction from the surface of the fourth nitride-based III-V compound semiconductor layer. The physical group III-V compound semiconductor layer is removed until it is exposed to form a groove, and the groove is filled with a dielectric transparent to the light having the emission wavelength from the active layer, and the surface of the dielectric is It has a recessed part and / or a convex part, and / or the said dielectric material is what contains a light-scattering particle, It is characterized by the above-mentioned.
In the third to sixth inventions, for example, a red light emitting diode using an AlGaInP-based semiconductor can be used.

The seventh invention
In an electronic device having one or more light emitting diodes,
At least one of the light emitting diodes,
A substrate having a plurality of convex portions on one main surface;
A fifth nitride-based III-V compound semiconductor layer grown on the substrate without forming a void in the recess of the substrate;
The third nitride III-V compound semiconductor layer of the first conductivity type on the fifth nitride III-V compound semiconductor layer, the active layer, and the fourth nitride of the second conductivity type A system III-V compound semiconductor layer,
In the fifth nitride-based III-V compound semiconductor layer, a dislocation generated in a direction perpendicular to the one main surface from the interface with the bottom surface of the recess is a triangular portion having the bottom surface of the recess as a base. Is bent in a direction parallel to the one principal surface,
Of the fifth nitride III-V compound semiconductor layer, the third nitride III-V compound semiconductor layer, the active layer, and the fourth nitride III-V compound semiconductor layer At least the third nitridation in a depth direction from the surface of the fourth nitride-based III-V compound semiconductor layer. The physical group III-V compound semiconductor layer is removed until it is exposed to form a groove, and the groove is filled with a dielectric transparent to the light having the emission wavelength from the active layer, and the surface of the dielectric is It has a recessed part and / or a convex part, and / or the said dielectric material is what contains a light-scattering particle, It is characterized by the above-mentioned.

  In the seventh invention, the electronic device includes a light-emitting diode backlight (such as a backlight of a liquid crystal display), a light-emitting diode illuminating device, a light-emitting diode display, and the like. (GLV), etc., but in general, anything that has at least one light emitting diode for display, illumination, optical communication, optical transmission and other purposes is basically Well, including both portable and stationary types, but specific examples other than the above include mobile phones, mobile devices, robots, personal computers, in-vehicle devices, various household electrical appliances, light-emitting diode light Portable devices such as communication devices, light-emitting diode optical transmission devices, and electronic keys Security equipment, and the like. Electronic devices also include light in different wavelength bands, such as far-infrared wavelength band, infrared wavelength band, red wavelength band, yellow wavelength band, green wavelength band, blue wavelength band, purple wavelength band, and ultraviolet wavelength band. A combination of two or more types of light emitting diodes that emit light is also included. In particular, in a light emitting diode lighting device, a combination of two or more types of light emitting diodes that emit visible light in different wavelength bands among a red wavelength band, a yellow wavelength band, a green wavelength band, a blue wavelength band, a purple wavelength band, and the like, Two or more types of light emitted from these light emitting diodes can be mixed to obtain natural light or white light. Also, a light emitting diode that emits light in at least one of the blue wavelength band, purple wavelength band, and ultraviolet wavelength band is used as a light source, and the phosphor is irradiated with light emitted from the light emitting diode for excitation. By mixing the light obtained by doing so, natural light or white light can be obtained. Further, light emitting diodes that emit visible light having different wavelength bands are defined as, for example, cell units, quartet units, cluster units (a strict definition is the number of light emitting diodes included in one unit). A single unit name when a plurality of light emitting diodes that emit light of the same wavelength or different wavelengths are formed in the same group and are mounted on a wiring board, wiring package, wiring housing wall, or the like. Specifically, for example, a unit composed of three light emitting diodes (for example, one red light emitting diode, one green light emitting diode, and one blue light emitting diode), or Four light emitting diodes (eg, one red light emitting diode, two green light emitting diodes, blue light emitting diode) 1 unit), or units consisting of five or more light emitting diodes, etc., and each unit is mounted on a substrate or plate, or on a housing plate in a two-dimensional array or in one or more rows. May be.

The eighth invention
Using a substrate having a plurality of convex portions on one principal surface, and growing a first semiconductor layer in a concave portion of the substrate through a triangular cross-sectional shape having a bottom surface as a base;
Laterally growing a second semiconductor layer on the substrate from the first semiconductor layer;
Growing a third semiconductor layer of the first conductivity type, an active layer and a fourth semiconductor layer of the second conductivity type on the second semiconductor layer;
Of the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the active layer, and the fourth semiconductor layer, in the central portion between the concave portions and / or the concave portions adjacent to each other. Forming a groove by removing a corresponding portion in a depth direction from the surface of the fourth semiconductor layer until at least the third semiconductor layer is exposed; and
The groove is filled with a dielectric that is transparent to the light having the emission wavelength from the active layer. At this time, the surface of the dielectric has a recess and / or a protrusion, and / or the dielectric A method for producing a light emitting diode, comprising the step of containing scattering particles.

The ninth invention
A substrate having a plurality of convex portions on one main surface;
A fifth semiconductor layer grown on the substrate without forming a void in the recess of the substrate;
A third semiconductor layer of a first conductivity type on the fifth semiconductor layer, an active layer and a fourth semiconductor layer of a second conductivity type;
In the fifth semiconductor layer, dislocations generated from the interface with the bottom surface of the recess in a direction perpendicular to the one principal surface reach the slope of the triangular portion having the bottom surface of the recess as a base or the vicinity thereof. From there, it is bent in a direction parallel to the one principal surface,
Of the fifth semiconductor layer, the third semiconductor layer, the active layer, and the fourth semiconductor layer, a portion corresponding to a central portion between the recesses and / or the recesses adjacent to each other is the first semiconductor layer. 4 is removed from the surface of the semiconductor layer 4 in the depth direction until at least the third semiconductor layer is exposed to form a groove, and the groove is formed by a dielectric that is transparent to light having an emission wavelength from the active layer. Is a light emitting diode, wherein the dielectric has a concave portion and / or a convex portion, and / or the dielectric contains light scattering particles.
In the ninth invention, the fifth semiconductor layer corresponds to the first semiconductor layer and the second semiconductor layer in the eighth invention.

In the eighth and ninth inventions, the first to fifth semiconductor layers include a nitride III-V compound semiconductor, a wurtzit structure, and more generally a hexagonal crystal structure. From other semiconductors having other crystal structures such as oxide semiconductors such as ZnO, α-ZnS, α-CdS, α-CdSe, and also CrN (111) and oxychalcogenide semiconductors It may be. Here, the oxychalcogenide-based semiconductor means oxychalcogenide LnMOCh (where Ln is at least one lanthanoid, M is Cu or Cd, and Ch is at least one chalcogen) or a part of the constituent elements of the oxychalcogenide is another element. In particular, Ln is selected from the group consisting of La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. At least one kind.
The eighth and ninth inventions can be applied in the same way as the first and second inventions.

The tenth invention is
Using a substrate having a plurality of convex portions on one principal surface, and growing a first semiconductor layer in a concave portion of the substrate through a triangular cross-sectional shape having a bottom surface as a base;
Laterally growing a second semiconductor layer on the substrate from the first semiconductor layer;
Growing a third semiconductor layer of the first conductivity type, an active layer and a fourth semiconductor layer of the second conductivity type on the second semiconductor layer;
Of the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the active layer, and the fourth semiconductor layer, in the central portion between the concave portions and / or the concave portions adjacent to each other. Forming a groove by removing a corresponding portion in a depth direction from the surface of the fourth semiconductor layer until at least the third semiconductor layer is exposed; and
Forming a protective element for the light emitting diode in at least one of the grooves.

The eleventh invention is
A substrate having a plurality of convex portions on one main surface;
A fifth semiconductor layer grown on the substrate without forming a void in the recess of the substrate;
A third semiconductor layer of a first conductivity type on the fifth semiconductor layer, an active layer and a fourth semiconductor layer of a second conductivity type;
In the fifth semiconductor layer, dislocations generated from the interface with the bottom surface of the recess in a direction perpendicular to the one principal surface reach the slope of the triangular portion having the bottom surface of the recess as a base or the vicinity thereof. From there, it is bent in a direction parallel to the one principal surface,
Of the fifth semiconductor layer, the third semiconductor layer, the active layer, and the fourth semiconductor layer, a portion corresponding to a central portion between the recesses and / or the recesses adjacent to each other is the first semiconductor layer. 4 is removed from the surface of the semiconductor layer 4 in the depth direction until at least the third semiconductor layer is exposed to form a groove,
A light emitting diode is characterized in that a protection element for the light emitting diode is formed in at least one of the grooves.

  In the tenth and eleventh inventions, the same semiconductors as those in the eighth and ninth inventions can be used as semiconductors constituting the first to fifth semiconductor layers and the active layer. As the light-emitting diode protection element, various elements can be used as long as the light-emitting diode can be electrostatically protected. Specifically, for example, a Schottky provided in reverse parallel to the light-emitting diode is used. A barrier diode, a pn junction diode, or the like, an npn junction diode (back-to-back diode) provided in parallel with the light emitting diode, a capacitor, a varistor element, or the like can be used. Typically, a convex portion, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, an active layer, and / or a central portion between concave portions adjacent to each other and / or a concave portion among the fourth semiconductor layers. A portion corresponding to is removed from the surface of the fourth semiconductor layer in the depth direction until the substrate is exposed to form a groove, and this protective element is formed in at least one groove. The protective element is formed in at least one groove of one light emitting diode, but may be formed in two or more grooves depending on circumstances. In this case, since the protective element is formed in a groove formed to remove threading dislocations, the effective light emitting area of the light emitting diode is hardly reduced by forming the protective element. Typically, both terminals of the protective element are provided above and below the groove. Then, an electrode on the second conductivity type side is provided on the fourth semiconductor layer and connected to one terminal of this protection element. Thereafter, the remaining protrusions are removed by wet etching or the like, so that the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the active layer, and the fourth semiconductor layer are separated from the substrate. Since the other terminal of the protective element is exposed on the peeled surface of the light emitting diode structure thus peeled, an electrode on the first conductivity type side is provided on this peeled surface and connected to this terminal. This eliminates the need for wiring between the light emitting diode and the protective element.

The twelfth invention
Using a substrate having a plurality of convex portions on one principal surface, and growing a first semiconductor layer in a concave portion of the substrate through a triangular cross-sectional shape having a bottom surface as a base;
Laterally growing a second semiconductor layer on the substrate from the first semiconductor layer;
Growing a third semiconductor layer of the first conductivity type, an active layer and a fourth semiconductor layer of the second conductivity type on the second semiconductor layer;
Of the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the active layer, and the fourth semiconductor layer, in the central portion between the concave portions and / or the concave portions adjacent to each other. Forming a groove by removing a corresponding portion in a depth direction from the surface of the fourth semiconductor layer until at least the third semiconductor layer is exposed; and
Forming a second conductivity type side electrode on the fourth semiconductor layer;
Bonding the wiring board on which the light emitting diode driving circuit is formed to the fourth semiconductor layer side so that the electrode of the wiring board and the electrode on the second conductivity type side are electrically connected to each other. It is a manufacturing method of the light emitting diode array characterized by having.

The thirteenth invention
A substrate having a plurality of convex portions on one main surface;
A fifth semiconductor layer grown on the substrate without forming a void in the recess of the substrate;
A third semiconductor layer of a first conductivity type on the fifth semiconductor layer, an active layer and a fourth semiconductor layer of a second conductivity type;
In the fifth semiconductor layer, dislocations generated from the interface with the bottom surface of the recess in a direction perpendicular to the one principal surface reach the slope of the triangular portion having the bottom surface of the recess as a base or the vicinity thereof. From there, it is bent in a direction parallel to the one principal surface,
Of the fifth semiconductor layer, the third semiconductor layer, the active layer, and the fourth semiconductor layer, a portion corresponding to a central portion between the recesses and / or the recesses adjacent to each other is the first semiconductor layer. 4 is removed from the surface of the semiconductor layer 4 in the depth direction until at least the third semiconductor layer is exposed to form a groove,
An electrode on the second conductivity type side is formed on the fourth semiconductor layer,
The wiring board on which the light emitting diode driving circuit is formed is bonded to the fourth semiconductor layer side so that the electrode of the wiring board and the electrode on the second conductivity type side are electrically connected to each other. The light emitting diode array characterized by the above.

In the twelfth and thirteenth inventions, the same semiconductors as those in the eighth and ninth inventions can be used as semiconductors constituting the first to fifth semiconductor layers and the active layer. In one example, an electrode on the first conductivity type side is formed on the third semiconductor layer exposed on the bottom surface of at least one groove, and the electrode on the first conductivity type side is formed on the fourth semiconductor layer. When pulling out and bonding the wiring substrate to the fourth semiconductor layer side, the electrode on the first conductivity type side and the electrode connected to the electrode on the second conductivity type side of the wiring substrate and another electrode are mutually connected Connect electrically. In another example, the convex portion, the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the active layer, and the central portion between the concave portions and / or the concave portions adjacent to each other among the fourth semiconductor layers. A portion corresponding to is removed from the surface of the fourth semiconductor layer in the depth direction until the substrate is exposed to form a groove, and then the remaining convex portions are removed by etching by wet etching or the like. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the active layer, and the fourth semiconductor layer are peeled from the substrate. An electrode on the first conductivity type side made of a transparent electrode is formed on the peeled surface of the light emitting diode structure thus peeled.
The light emitting diode arrays according to the twelfth and thirteenth inventions can be used as light emitting diode displays, light emitting diode backlights, light emitting diode illumination devices, light source cell units, and the like.

In the present invention configured as described above, the growth of the first nitride-based III-V group compound semiconductor layer is started from the bottom surface of the concave portion of the substrate, and the triangular cross-sectional shape having the bottom surface in the middle of the growth is started. By growing the first nitride-based III-V compound semiconductor layer through this state, the recess can be filled without a gap. Then, a second nitride III-V compound semiconductor layer is laterally grown from the first nitride III-V compound semiconductor layer thus grown. At this time, in the first nitride-based III-V group compound semiconductor layer, dislocations are generated in a direction perpendicular to the main surface of the substrate from the interface with the bottom surface of the recess of the substrate. The dislocation reaches a slope of the compound III-V compound semiconductor layer or the vicinity thereof, and with the growth of the second nitride III-V compound semiconductor layer, this dislocation is parallel to one main surface of the substrate. Bend to. When the second nitride-based III-V compound semiconductor layer is grown sufficiently thick, the portion above the dislocation parallel to one main surface of the substrate becomes a region having a very low dislocation density. In the second nitride-based III-V compound semiconductor layer, threading dislocations are generated in a portion corresponding to the recess and / or a portion corresponding to the central portion between the recesses adjacent to each other. Nitride-based III-V compound semiconductor layer, second nitride-based III-V compound semiconductor layer, third nitride-based III-V compound semiconductor layer, active layer, and fourth nitride-based III- A portion of the group V compound semiconductor layer corresponding to the recess and / or the central portion between the recesses adjacent to each other is removed until at least the third nitride-based III-V group compound semiconductor layer is exposed. By forming the threading dislocation, at least the active layer and the upper layer thereof can be removed. Then, the groove is filled with a dielectric that is transparent to the light having the emission wavelength from the active layer, the surface of the dielectric has a concave portion and / or a convex portion, and the fourth nitride III-V When an electrode on the second conductivity type side is formed on the group compound semiconductor layer, light or the like generated from the active layer is incident on a recess and / or a protrusion on the interface between the electrode on the second conductivity type and the dielectric When it does, it can be made to reflect in the direction of the angle which becomes easy to be taken out finally. When the dielectric includes light scattering particles, the light generated from the active layer is scattered when incident on the light scattering particles. Will go on. In this method, the first to fourth nitride III-V compound semiconductor layers can be grown by one epitaxial growth.
More generally, the first nitride-based group III-V compound semiconductor layer is the first semiconductor layer, the second nitride-based group III-V compound semiconductor layer is the second semiconductor layer, and the third nitride is used. By replacing the physical III-V compound semiconductor layer with the third semiconductor layer and the fourth nitride III-V compound semiconductor layer with the fourth semiconductor layer, the same is true.

According to the present invention, since no gap is formed between the first nitride-based III-V group compound semiconductor layer and the second nitride-based III-V group compound semiconductor layer and the substrate, light extraction efficiency is achieved. In addition, since the crystallinity of the second nitride III-V compound semiconductor layer is improved, a third nitride III-V compound semiconductor grown on the second nitride III-V compound semiconductor layer can be obtained. The crystallinity of the layer, the active layer, and the fourth nitride-based III-V compound semiconductor layer is also greatly improved, and in addition to this, the removal of threading dislocations can greatly reduce the non-luminescent center. A light-emitting diode with extremely high efficiency can be obtained. Then, the groove formed for removing the threading dislocation is filled with a dielectric, the surface of the dielectric has a concave portion and / or a convex portion, and / or the dielectric includes light scattering particles. As a result, the light generated from the active layer is finally easily extracted to the outside, whereby the light extraction efficiency can be further improved, and the light emission efficiency of the light emitting diode is further increased. Moreover, since the light emitting diode can be manufactured by one epitaxial growth, the cost is low. And using this light emitting diode with high luminous efficiency, high performance light source cell unit, light emitting diode backlight, light emitting diode lighting device, light emitting diode display, light emitting diode optical communication device, space optical transmission device, various electronic devices etc. Can be realized.
More generally, the first nitride-based group III-V compound semiconductor layer is the first semiconductor layer, the second nitride-based group III-V compound semiconductor layer is the second semiconductor layer, and the third nitride is used. The same effect as above can be obtained by replacing the physical III-V compound semiconductor layer with the third semiconductor layer and the fourth nitride III-V compound semiconductor layer with the third semiconductor layer.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings of the embodiments, the same or corresponding parts are denoted by the same reference numerals.
1 to 7 show a light emitting diode manufacturing method according to the first embodiment of the present invention in the order of steps. This light-emitting diode uses a nitride III-V compound semiconductor such as GaN.

In the first embodiment, as shown in FIG. 1A, first, a substrate 11 having a flat main surface and made of a material different from that of a nitride III-V compound semiconductor is prepared. The convex part 12 whose cross-sectional shape is an isosceles triangle shape is periodically formed in a predetermined planar shape. A concave portion 13 having an inverted trapezoidal cross-sectional shape is formed between the convex portions 12. As this substrate 11, for example, those already described can be used. Specifically, for example, a sapphire substrate is used, and its main surface is, for example, a c-plane. The planar shape of the convex portion 12 and the concave portion 13 can be the various planar shapes already described. For example, as shown in FIG. 9, both the convex portion 12 and the concave portion 13 have a stripe shape extending in one direction. In other cases, as shown in FIG. 10, the convex portion 12 has a hexagonal planar shape and is arranged two-dimensionally in a honeycomb shape. Typically, the direction of the dotted line in FIG. 9 (direction orthogonal to the stripe) is parallel to the a-axis of the nitride III-V compound semiconductor layer 15 described later, and the direction of the dotted line in FIG. The direction connecting the portions 12) is made parallel to the m-axis of the nitride III-V compound semiconductor layer 15 described later. For example, when the substrate 11 is a sapphire substrate, the extending direction of the stripe-shaped convex portion 12 and the concave portion 13 in FIG. 9 is the <1-100> direction of the sapphire substrate, and the extending direction of the concave portion 13 in FIG. Similarly, it is the <1-100> direction of the sapphire substrate. These extending directions may be the <11-20> direction of the sapphire substrate. The materials described above can be used as the material of the convex portion 12; however, from the viewpoint of easiness of processing, preferably, for example, SiO ₂ and SiN (not only Si ₃ N ₄ but also a plasma CVD method is used. CrN, SiON, CrON, etc. are also used.

In order to form the convex part 12 having a cross-sectional shape of an isosceles triangle on the substrate 11, a conventionally known method can be used. For example, a film (for example, a SiN film, a SiO ₂ film, or the like) that is a material of the convex portion 12 is formed on the entire surface of the substrate 11 by CVD, vacuum deposition, sputtering, or the like. Next, a resist pattern having a predetermined shape is formed on the film by lithography. Next, this film is etched using this resist pattern as a mask under conditions where taper etching is performed by the RIE method or the like, thereby forming a convex portion 12 having an isosceles triangular cross section.

  Next, after the surfaces of the substrate 11 and the convex portion 12 are cleaned by performing thermal cleaning or the like, for example, a GaN buffer layer, an AlN buffer, or the like is grown on the substrate 11 at a growth temperature of, for example, about 550 ° C. A layer, a CrN buffer layer, a Cr-doped GaN buffer layer, or a Cr-doped AlN buffer layer (not shown) is grown. Next, epitaxial growth of a nitride III-V compound semiconductor is performed by, for example, MOCVD. This nitride-based III-V group compound semiconductor is, for example, GaN. At this time, as shown in FIG. 1B, growth is first started from the bottom surface of the recess 13 to generate a plurality of micronuclei 14 made of a nitride III-V compound semiconductor. Next, as shown in FIG. 1C, an isosceles triangular shape having a bottom surface of the recess 13 as a bottom and a facet inclined with respect to the main surface of the substrate 11 on the inclined surface through the growth and coalescence process of the micronuclei 14. The nitride III-V compound semiconductor layer 15 is grown so as to have a cross-sectional shape. In this example, the height of the nitride-based III-V group compound semiconductor layer 15 having an isosceles triangular cross-sectional shape is larger than the height of the convex portion 12. For example, the extending direction of the nitride III-V compound semiconductor layer 15 is the <1-100> direction, and the facet of the inclined surface is the (1-101) plane. The nitride III-V compound semiconductor layer 15 may be undoped or doped with n-type impurities or p-type impurities. The growth conditions for the nitride III-V compound semiconductor layer 15 will be described later. The extending direction of the nitride-based III-V compound semiconductor layer 15 may be the <11-20> direction.

Subsequently, by performing growth of the nitride III-V compound semiconductor layer 15 while maintaining the facet plane orientation of the inclined surface, as shown in FIG. 2A, the nitride III-V compound semiconductor layer 15 Both end portions grow to the lower portion of the side surface of the convex portion 12 and the cross-sectional shape becomes a pentagonal shape.
Next, when the growth condition is set to a condition in which the lateral growth is dominant, and the growth is continued, as shown in FIG. It grows in the direction and spreads on the convex portion 12 in a state where the cross-sectional shape becomes a hexagonal shape. In FIG. 2B, a dotted line indicates a growth interface during the growth (the same applies hereinafter).
When the lateral growth is further continued, as shown in FIG. 2C, the nitride-based III-V compound semiconductor layer 15 grows while increasing its thickness, and finally the nitride-based III-III grown from the adjacent recess 13. The group V compound semiconductor layers 15 come into contact with each other on the convex portion 12 and are associated with each other.
Subsequently, the nitride-based III-V compound semiconductor layer 15 is laterally grown until the surface thereof becomes a flat surface parallel to the main surface of the substrate 11. The nitride-based III-V group compound semiconductor layer 15 thus grown has a very low dislocation density in the portion above the recess 13.
In some cases, the state shown in FIG. 1C can be shifted directly to the state shown in FIG. 2B without going through the state shown in FIG. 2A.

Next, as shown in FIG. 3, the n-type nitride III-V compound semiconductor layer 16 and the nitride III-V group semiconductor layer 16 are formed on the nitride III-V compound semiconductor layer 15 by MOCVD, for example. An active layer 17 using a compound semiconductor and a p-type nitride-based III-V group compound semiconductor layer 18 are sequentially epitaxially grown. In this case, it is assumed that the nitride III-V compound semiconductor layer 15 is n-type. In these nitride III-V compound semiconductor layer 15, n-type nitride III-V compound semiconductor layer 16, active layer 17 and p-type nitride III-V compound semiconductor layer 18, convex portions 12, threading dislocations 19 occur at a high density (for example, about 10 ⁸ / cm ² or more) in the vicinity of the central portion of 12, that is, at the meeting portion between the nitride-based III-V group compound semiconductor layers 15 growing from the recesses 13 adjacent to each other. However, threading dislocations 19 are generated in the upper part of the recess 13 although the density is low, and the other parts have a low dislocation density. For example, when the depth d of the recess 13 is 1 μm and the width W _{g of} the bottom surface is 2 μm, the dislocation density of the low dislocation density portion is 6 × 10 ⁷ / cm ² , and the substrate 11 subjected to the uneven processing is used. The dislocation density is reduced by 1 to 2 orders of magnitude compared to the case where there is no dislocation. No dislocation occurs in the direction perpendicular to the side wall of the recess 13. FIG. 11 shows a distribution of threading dislocations 19 when the convex portion 12 has the planar shape shown in FIG. FIG. 12 shows the distribution of threading dislocations 19 when the convex portion 12 has the planar shape shown in FIG.

Next, the substrate 11 on which the nitride-based III-V compound semiconductor layer is grown in this way is taken out from the MOCVD apparatus.
Next, a resist pattern (not shown) having a predetermined shape with an opening corresponding to the predetermined portion including the threading dislocation 19 is formed on the p-type nitride-based III-V compound semiconductor layer 18 by lithography. Using this resist pattern as a mask, the n-type nitride III-V compound semiconductor layer 16 is etched to a depth in the thickness direction by, for example, RIE. By this etching, a groove 20 is formed as shown in FIG. 4, and threading dislocations 19 in the groove 20 are removed.
Next, as shown in FIG. 5, the inside of the groove 20 thus formed is filled with a dielectric 21. At this time, the surface of the dielectric 21 is made concave. The dielectric 21 includes a nitride III-V compound semiconductor layer 15, an n-type nitride III-V compound semiconductor layer 16, an active layer 17, and a p-type nitride III-V compound semiconductor layer 18. A material having a refractive index smaller than the refractive index of the active layer 17 and transparent to light having an emission wavelength from the active layer 17 is used. Specifically, for example, SiO ₂ is used.
Next, as shown in FIG. 6, the p-side electrode 22 is formed on the p-type nitride III-V compound semiconductor layer 18. As a material of the p-side electrode 22, for example, it is preferable to use an ohmic metal having high reflectivity such as Ag or an Ag alloy containing Ag as a main component.

Thereafter, in order to activate the p-type impurity of the p-type nitride III-V compound semiconductor layer 18, for example, a mixed gas of N ₂ and O ₂ (composition is, for example, 99% N ₂ and O ₂ In a 1% atmosphere, heat treatment is performed at a temperature of 550 to 750 ° C. (for example, 650 ° C.) or 580 to 620 ° C. (for example, 600 ° C.). Here, for example, activation is easily caused by mixing O ₂ with N ₂ . Further, for example, nitrogen halide (NF ₃ , NCl _3, etc.) is mixed in a mixed gas atmosphere of N ₂ or N ₂ and O ₂ as a raw material such as F and Cl having high electronegativity as in O and N. You may do it. The time for this heat treatment is, for example, 5 minutes to 2 hours or 40 minutes to 2 hours, generally about 10 to 60 minutes. The reason for the relatively low temperature of the heat treatment is to prevent deterioration of the active layer 17 and the like during the heat treatment. This heat treatment may be performed after the p-type nitride III-V compound semiconductor layer 18 is epitaxially grown and before the p-side electrode 22 is formed.
Next, as shown in FIG. 7, the n-type nitride III-V compound semiconductor layer 16, the active layer 17, and the p-type nitride III-V compound semiconductor layer 18 are formed by, for example, RIE or powder blasting. Then, the mesa portion 23 is formed by patterning into a predetermined shape by a sandblast method or the like.

Next, the n-side electrode 24 is formed on the n-type nitride III-V compound semiconductor layer 15 adjacent to the mesa portion 23.
Next, if necessary, the substrate 11 on which the light emitting diode structure is formed as described above is reduced in thickness by grinding or lapping from the back side, and then the substrate 11 is scribed, Form. Thereafter, the bar is scribed to form a chip.
Thus, the target light emitting diode is manufactured.
FIG. 8 shows an enlarged view of the vicinity of the groove 20 in which the dielectric 21 is embedded and the p-side electrode 22 in this light emitting diode.
FIG. 13 shows an example of the planar shape of the p-side electrode 22 and the n-side electrode 24 when the convex portion 12 has a stripe shape extending in one direction.

The growth source of the above-mentioned nitride III-V compound semiconductor layer is, for example, triethylgallium ((C ₂ H ₅ ) ₃ Ga, TEG) or trimethyl gallium ((CH ₃ ) ₃ Ga, TMG as a Ga source. ), Trimethylaluminum ((CH ₃ ) ₃ Al, TMA) as a raw material of Al, triethylindium ((C ₂ H ₅ ) ₃ In, TEI) or trimethylindium ((CH ₃ ) ₃ In, TMI), and ammonia (NH ₃ ) is used as a raw material for N. As for the dopant, for example, silane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used as the n-type dopant, and bis (methylcyclopentadienyl) magnesium ((CH ₃ C ₅ H ₄ ) ₂ is used as the p-type dopant. Mg), bis (ethylcyclopentadienyl) magnesium ((C ₂ H ₅ C ₅ H ₄ ) ₂ Mg) or bis (cyclopentadienyl) magnesium ((C ₅ H ₅ ) ₂ Mg) is used. For the carrier gas atmosphere during the growth of the nitride-based III-V compound semiconductor layer, eg, H ₂ gas is used.

  A specific structural example of the light emitting diode will be described. That is, for example, the nitride III-V compound semiconductor layer 15 is an n-type GaN layer, the n-type nitride III-V compound semiconductor layer 16 is an n-type GaN layer and an n-type GaInN layer in order from the bottom, The p-type nitride III-V compound semiconductor layer 18 is a p-type AlInN layer, a p-type GaN layer, and a p-type GaInN layer in order from the bottom. The active layer 17 has, for example, a GaInN-based multiple quantum well (MQW) structure (for example, one in which GaInN quantum well layers and GaN barrier layers are alternately stacked), and the In composition of the active layer 17 is the light emission of the light emitting diode. It is selected according to the wavelength. For example, it is ˜11% at an emission wavelength of 405 nm, ˜18% at 450 nm, and ˜24% at 520 nm. As a material of the p-side electrode 22, for example, Ag, Pd / Ag, or the like is used, or a barrier metal made of Ti, W, Cr, WN, CrN, or the like is used in addition to this, if necessary. As the n-side electrode 24, for example, a Ti / Pt / Au structure is used.

In the light-emitting diode shown in FIG. 7 thus obtained, light is emitted by applying a forward voltage between the p-side electrode 22 and the n-side electrode 24 and flowing current, for example, through the substrate 11 to the outside. Take out the light. By selecting the In composition of the active layer 17, red to ultraviolet light emission, particularly blue light emission, green light emission, or red light emission can be obtained. In this case, of the light generated from the active layer 17, the light directed to the substrate 11 is refracted at the interface between the substrate 11 and the nitride-based III-V compound semiconductor layer 15 of the recess 13 and then passes through the substrate 11. And go outside. On the other hand, of the light generated from the active layer 17, the light traveling toward the p-side electrode 22 is reflected by the p-side electrode 22, travels toward the substrate 11, and exits through the substrate 11. At this time, as shown in FIG. 8, light incident on the interface between the dielectric 21 embedded in the groove 20 and the p-side electrode 22 at an angle θ ₁ with respect to the normal of the main surface of the substrate 11 is dielectric Since the surface of the body 21 is concave, and the interface between the dielectric 21 and the p-side electrode 22 is concave, the angle θ is smaller than θ _{1 with} respect to the normal of the main surface of the substrate 11. ₂ (ie, θ ₁ > θ ₂ ). As a result, compared to the case where the main surface of the substrate 11 and the lower surface of the p-side electrode 22 are parallel to each other, the proportion of light incident on the main surface of the substrate 11 with a smaller incident angle increases. In particular, the amount of light that goes out through the substrate 11 increases.

In the first embodiment, in order to minimize the threading dislocation density of the nitride-based III-V compound semiconductor layer 15, the width W _g of the bottom surface of the concave portion 13, the depth of the concave portion 13, that is, the convex portion 12. And the angle α formed by the slope of the nitride-based III-V compound semiconductor layer 15 in the state shown in FIG. 1C and the main surface of the substrate 11 are determined so as to satisfy the following formula ( (See FIG. 14).
2d ≧ W _g tan α
For example, when W _g = 2.1 μm and α = 59 °, d ≧ 1.75 μm, W _g = 2 μm, and when α = 59 °, d ≧ 1.66 μm, W _g = 1.5 μm, α When d = 59 °, d ≧ 1.245 μm, W _g = 1.2 μm, and when α = 59 °, d ≧ 0.966 μm. However, in any case, it is desirable that d <5 μm.

During the growth of the nitride-based III-V group compound semiconductor layer 15 in the steps shown in FIGS. 1B and 1C and FIG. 2A, it is preferable to set the growth temperature low so as to increase the V / III ratio of the growth material. Specifically, when the growth of the nitride III-V compound semiconductor layer 15 is performed under a pressure condition of 1 atm, the V / III ratio of the growth material is in the range of, for example, 13000 ± 2000, and the growth temperature is, for example, 1100. It is preferable to set in the range of ± 50 ° C. Regarding the V / III ratio of the growth raw material, when the growth of the nitride-based III-V compound semiconductor layer 15 is performed under a pressure condition of x atmospheric pressure, the pressure is determined from Bernoulli's law that defines the relationship between the flow velocity and the pressure. It is preferable to set the V / III ratio corresponding to the square of the amount of change, specifically (13000 ± 2000) × x ² . For example, when the growth is performed at 0.92 atmospheres (700 Torr), the V / III ratio of the growth raw material is preferably set to a range of 11000 ± 1700 (for example, 10530). x is generally from 0.01 to 2 atmospheres. When the growth is performed under a pressure condition of 1 atm or less, the lateral growth of the nitride-based III-V compound semiconductor layer 15 is suppressed, and the nitride-based III-V compound semiconductor in the recess 13 is suppressed. In order to facilitate the selective growth of the layer 15, it is preferable to set it to a lower growth temperature. For example, when growth is performed at 0.92 atmospheres (700 Torr), the growth temperature is preferably set in a range of 1050 ± 50 ° C. (for example, 1050 ° C.). By doing so, the nitride III-V compound semiconductor layer 15 grows as shown in FIGS. 1B and 1C and FIG. 2A. At this time, the nitride-based III-V compound semiconductor layer 15 does not start to grow from above the convex portion 12. The growth rate is generally 0.5 to 5.0 μm / h, preferably about 3.0 μm / h. When the nitride III-V compound semiconductor layer 15 is a GaN layer, for example, the flow rate of the source gas is, for example, 20 SCCM for TMG and 20 SLM for NH ₃ . On the other hand, the growth (lateral growth) of the nitride-based III-V compound semiconductor layer 15 in the steps shown in FIGS. 2B and 2C is performed by setting the growth temperature high while lowering the V / III ratio of the growth material. Specifically, when the growth of the nitride-based III-V compound semiconductor layer 15 is performed under a pressure condition of 1 atm, the V / III ratio of the growth material is in the range of 5000 ± 2000, for example, and the growth temperature is, for example, 1200. Set in the range of ± 50 ° C. Regarding the V / III ratio of the growth raw material, when the growth of the nitride-based III-V compound semiconductor layer 15 is performed under a pressure condition of x atmospheric pressure, the pressure is determined from Bernoulli's law that defines the relationship between the flow velocity and the pressure. It is preferable to set the V / III ratio corresponding to the square of the amount of change, specifically (5000 ± 2000) × x ² . For example, when the growth is performed at 0.92 atmospheres (700 Torr), the V / III ratio of the growth material is preferably set in the range of 4200 ± 1700 (for example, 4232). As for the growth temperature, when growth is performed under a pressure condition of 1 atm or less, the surface of the nitride III-V compound semiconductor layer 15 is prevented from being roughened, and the lateral growth is favorably performed. It is preferable to set the temperature. For example, when growth is performed at 0.92 atmospheres (700 Torr), the growth temperature is preferably set in the range of 1150 ± 50 ° C. (eg, 1110 ° C.). When the nitride-based III-V group compound semiconductor layer 15 is, for example, a GaN layer, the flow rate of the source gas is, for example, 40 SCCM for TMG and 20 SLM for NH ₃ . By doing so, as shown in FIGS. 2B and 2C, the nitride-based III-V compound semiconductor layer 15 grows laterally.

FIG. 15 schematically shows the flow of the source gas during the growth of the GaN layer and the state of diffusion on the substrate 11 as an example of the nitride-based III-V group compound semiconductor layer 15. The most important point in this growth is that GaN does not grow on the convex portion 12 of the substrate 11 and growth of GaN starts in the concave portion 13 in the early stage of growth. In FIG. 15, the cross-sectional shape of the convex portion 12 is triangular, but GaN does not grow on the convex portion 12 even if the cross-sectional shape of the convex portion 12 is trapezoidal. In general, GaN is grown by using TMG as a Ga raw material and NH ₃ as an N raw material. Ga (CH ₃ ) ₃ (g) + 3 / 2H ₂ (g) → Ga (g) + 3CH ₄ ( g)
NH ₃ (g) → (1-α) NH ₃ (g) + α / 2N ₂ (g) + 3α / 2H ₂ (g)
Ga (g) + NH ₃ (g) = GaN (s) + 3 / 2H ₂ (g)
As represented by the following reaction formula, this occurs when NH ₃ and Ga react directly. At this time, H ₂ gas is generated, and this H ₂ gas has an action opposite to crystal growth, that is, an etching action. In the steps shown in FIGS. 1B and 1C and FIG. 2A, by using conditions that are not performed in the conventional GaN growth on a flat substrate, that is, conditions that increase the etching action and are difficult to grow (increase the V / III ratio). The growth at the convex portion 12 is suppressed. On the other hand, since the etching action is weakened inside the recess 13, crystal growth occurs. Further, conventionally, in order to improve the flatness of the surface of the grown crystal, the growth is performed under conditions (higher temperatures) in which the degree of lateral growth is increased. In this first embodiment, threading dislocations are formed on the main surface of the substrate 11. For the purpose of reducing the thickness of the recess 13 by bending it in a direction parallel to the front surface, or filling the inside of the recess 13 with the nitride-based III-V group compound semiconductor layer 15 at an earlier stage (for example, 1050 ± 50 ° C.).

Next, the growth mode of the nitride-based III-V compound semiconductor layer 15 and the state of dislocation propagation from the initial growth will be described with reference to FIGS.
When the growth is started, as shown in FIG. 16A, first, a plurality of micronuclei 14 made of a nitride III-V compound semiconductor are generated on the bottom surface of the recess 13. In these micronuclei 14, dislocations (shown by dotted lines) propagate in the vertical direction from the interface with the substrate 11, and the dislocations escape from the side surfaces of the micronuclei 14. When the growth is continued, as shown in FIGS. 16B and 16C, the nitride-based III-V group compound semiconductor layer 15 grows through the growth and coalescence process of the micronuclei 14. In the process of growth and coalescence of these micronuclei 14, dislocation bending occurs in a direction parallel to the main surface of the substrate 11. As the growth continues further, as shown in FIG. 16D, the nitride-based III-V compound semiconductor layer 15 has an isosceles triangular cross-sectional shape with the bottom surface of the recess 13 as a base. At this point, the dislocations that escape from the nitride-based III-V compound semiconductor layer 15 to the upper part are greatly reduced. Next, as shown in FIG. 16E, the nitride III-V compound semiconductor layer 15 is grown in the lateral direction. In this process, the dislocations that have escaped to the side surface of the nitride-based III-V compound semiconductor layer 15 having an isosceles triangular cross-section with the bottom surface of the concave portion 13 as the base are located at a position lower than the convex portion 12. The nitride system III that has been stretched parallel to the main surface of the substrate 11 and disappeared while continuing to extend to the side surface of the convex portion 12 and that is located higher than the convex portion 12 extends parallel to the main surface of the substrate 11 and laterally grown. -It escapes to the side surface of the group V compound semiconductor layer 15. When the lateral growth of the nitride-based III-V compound semiconductor layer 15 is further continued, as shown in FIG. 16F, the nitride-based III-V group compound semiconductor layers 15 grown on both sides of the convex portion 12 are formed. Eventually, the surface of the nitride III-V compound semiconductor layer 15 becomes a flat surface parallel to the main surface of the substrate 11. The dislocations in the nitride-based III-V compound semiconductor layer 15 are bent upward (in the direction perpendicular to the main surface of the substrate 11) when meeting on the convex portion 12, and become threading dislocations.

With reference to FIGS. 17A and 17B, the behavior of the dislocation from the generation of the micronucleus 14 to after the lateral growth of the nitride III-V compound semiconductor layer 15 will be described again. As shown in FIGS. 17A and 17B, dislocations generated from the interface with the substrate 11 in the process of generation, growth, and coalescence of the micronuclei 14 are bundled by repeatedly bending in the horizontal direction (dislocation (1)). In addition, the dislocations bent in the horizontal direction extend to the side surface of the convex portion 12 and disappear (dislocation (2)). Furthermore, dislocations generated from the interface with the substrate 11 are bent only once and escape to the surface of the nitride III-V compound semiconductor layer 15 (dislocation (3)). Nitride system III with fewer threading dislocations compared to the case where the above-mentioned dislocations are bundled and the dislocations bent in the horizontal direction extend to the side surfaces of the protrusions 12 and disappear, so that the micronucleus 14 is not generated. The −V group compound semiconductor layer 15 can be obtained.
FIGS. 18A to 18C show cross-sectional TEM photographs in a state where the micronuclei 14 are generated on the bottom surface of the recess 13 as shown in FIG. 16A. 18B and 18C are cross-sectional TEM photographs in which a portion surrounded by an ellipse in FIG. 18A is enlarged. 18A to C clearly show that the micronuclei 14 are generated in the early stage of growth.

Next, how the behavior of dislocations generated in the nitride-based III-V compound semiconductor layer 15 differs depending on whether or not the micronucleus 14 is generated at the initial stage of growth will be described.
FIGS. 19A to 19C show states corresponding to FIGS. 16D to 16F in the case where the micronuclei 14 are not generated at the initial growth stage of the nitride-based III-V compound semiconductor layer 15. As shown in FIG. 19A, when the micronuclei 14 are not generated at the initial stage of growth, the nitride-based III-V compound semiconductor layer 15 has an isosceles triangular cross-sectional shape with the bottom surface of the recess 13 as a base. At the time of growth, only dislocations extending upward from the interface with the bottom surface of the recess 13 exist, but this dislocation density is generally higher than that in the case of FIG. 16D. When the growth is continued, as shown in FIG. 19B, the dislocations that have escaped to the side surface of the nitride-based III-V group compound semiconductor layer 15 having an isosceles triangular cross-section with the bottom surface of the recess 13 as a base are Those lower than 12 continue to extend to the side surface of the convex portion 12 in parallel to the main surface of the substrate 11 and disappear, and those higher than the convex portion 12 extend in parallel to the main surface of the substrate 11. The nitride-based group III-V compound semiconductor layer 15 grown in the lateral direction passes through the side surface. When the lateral growth of the nitride-based III-V compound semiconductor layer 15 is further continued, as shown in FIG. 19C, the nitride-based III-V group compound semiconductor layers 15 grown on both sides of the convex portion 12 are formed. As a result, the surface of the nitride III-V compound semiconductor layer 15 becomes a flat surface parallel to the main surface of the substrate 11. The dislocations in the nitride-based III-V compound semiconductor layer 15 are bent upward when meeting on the convex portion 12 to become threading dislocations 19. Although the density of the threading dislocations 19 is sufficiently low, it is higher than that in the case where the micronuclei 14 are generated on the bottom surface of the recess 13 in the early stage of growth. As shown in FIGS. 20A and 20B, when the micronucleus 14 is not generated, the dislocation generated from the interface with the substrate 11 reaches the slope of the isosceles triangular portion with the bottom surface of the recess 13 as the bottom. This is because it bends in the horizontal direction only once. That is, in this case, the effect of bundling dislocations in the process of generating, growing and coalescing the micronuclei 14 cannot be obtained.

FIG. 21 shows a simulation (ray tracing simulation) of how much the light extraction efficiency from the light emitting diode to the outside improves when the depth of the unevenness of the substrate 11 is changed compared to a flat case where the unevenness is not formed. An example of the results obtained is shown. The light extraction is performed from the back side of the substrate 11. In FIG. 21, the horizontal axis indicates the depth of the concave portion 13 (height of the convex portion 12), and the vertical axis indicates the degree of improvement in light extraction efficiency η (light extraction magnification) with respect to the case where the convex portion 12 is not formed. However, the convex portion 12 has a stripe shape extending in one direction, the angle θ formed between the side surface of the convex portion 12 and one main surface of the substrate 11 is 135 °, and the length of the bottom side of the concave portion W _g = 2 μm and the length of the bottom side of the convex portion 12 = 3 μm. The refractive index of the substrate 11 was assumed to be 1.77, and the refractive index of the nitride III-V compound semiconductor layer 15 was assumed to be 2.35. From FIG. 21, the light extraction magnification is 1.35 times or more when the depth of the recess 13 is 0.3 μm or more, 1.5 times or more when the depth of 0.5 μm or more and 2.5 μm or less, and 0.7 μm or more and 2.15 μm or less. 1.75 times or more, 1 μm or more and 1.75 μm or less is 1.85 times or more, and about 1.3 μm is the maximum (about 1.95).

As described above, according to the first embodiment, since no gap is formed between the substrate 11 and the nitride-based III-V compound semiconductor layer 15, the light extraction efficiency is reduced due to the gap. Can be prevented. Further, the threading dislocations in the nitride III-V compound semiconductor layer 15 are concentrated near the center of the convex portion 12 of the substrate 11, and the dislocation density in other portions is, for example, about 6 × 10 ⁷ / cm ² . Since it is greatly reduced as compared with the case of using the concavo-convex processed substrate, the nitride III-V compound semiconductor layer such as the nitride III-V compound semiconductor layer 15 and the active layer 17 grown thereon is used. The crystallinity of this material is greatly improved, and the non-luminescent center and the like are also greatly reduced. Further, threading dislocations generated in the nitride-based III-V compound semiconductor layer 15, the n-type nitride-based III-V compound semiconductor layer 16, the active layer 17, and the p-type nitride-based III-V compound semiconductor layer 18. 19 of the n-type nitride III-V group compound semiconductor layer 16 is removed by forming a groove 20 in this portion up to a depth in the middle of the thickness direction. It is possible to remove the non-luminescent center that is concentrated in the threading dislocation 19 in the removed portion and the portion in the vicinity thereof. For this reason, a significant reduction in non-radiative recombination can be achieved. Then, a dielectric 21 is embedded in the groove 20, and at this time, the surface of the dielectric 21 is concave, and the p-type nitride III-V compound semiconductor layer 18 is formed so as to cover the dielectric 21. By forming the p-side electrode 22 thereon, the amount of light that finally goes out through the substrate 11 increases. As a result, a nitride III-V compound semiconductor light emitting diode with extremely high luminous efficiency can be obtained.
In addition, the epitaxial growth necessary for manufacturing the nitride-based III-V compound semiconductor light-emitting diode is only required once, and not only a growth mask is not required, but also the protrusion 12 on the substrate 11 is formed on the substrate 11. A film that forms the material of the convex portion 12, for example, a film such as a SiO ₂ film, a SiON film, a SiN film, a CrN film, or a CrON film is formed, and this is formed only by processing by etching, powder blasting, sand blasting, etc Therefore, it is not necessary to process the substrate 11 such as a sapphire substrate, which is difficult to process, so that the manufacturing process is simple and the nitride III-V compound semiconductor light emitting diode is manufactured at low cost. be able to.

Next explained is the second embodiment of the invention.
In the second embodiment, as shown in FIG. 22, after the dielectric 21 is embedded in the groove 20 as in the first embodiment, a reflective film 25 is formed on the surface of the dielectric 21, A p-side electrode 22 is formed on the p-type nitride III-V compound semiconductor layer 18 so as to cover these reflective films 25.
Thereafter, the process proceeds in the same manner as in the first embodiment, and the target nitride-based III-V compound semiconductor light-emitting diode is manufactured as shown in FIG.
Other than the above are the same as in the first embodiment.
FIG. 24 shows an enlarged view of the vicinity of the groove 20 in which the dielectric 21 is embedded and the p-side electrode 22 in this light emitting diode.
According to the second embodiment, the same advantages as those of the first embodiment can be obtained, and the following advantages can be obtained. That is, since the reflective film 25 is formed on the surface of the dielectric 21 embedded in the groove 20, even if a material having a slightly lower reflectivity than the first embodiment is used as the material of the p-side electrode 22, A nitride-based III-V compound semiconductor light emitting diode having a luminous efficiency equivalent to that of the first embodiment can be obtained.

Next explained is the third embodiment of the invention.
In the third embodiment, as shown in FIG. 25, after forming the groove 20 as in the first embodiment, a dielectric 21 is embedded in the groove 20. At this time, the surface of the dielectric 21 is made convex.
Thereafter, the process proceeds in the same manner as in the first embodiment, and the target nitride-based III-V compound semiconductor light-emitting diode is manufactured as shown in FIG.
Other than the above are the same as in the first embodiment.
FIG. 27 shows an enlarged view of the vicinity of the groove 20 in which the dielectric 21 is embedded and the p-side electrode 22 in this light emitting diode.
According to the third embodiment, the same advantages as those of the first embodiment can be obtained.

Next explained is the fourth embodiment of the invention.
In the fourth embodiment, after the dielectric 21 is embedded in the groove 20 as in the third embodiment, the reflective film 25 is formed on the surface of the dielectric 21 in the same manner as in the second embodiment. Then, the p-side electrode 22 is formed on the p-type nitride-based III-V compound semiconductor layer 18 so as to cover these reflective films 25.
Thereafter, the process proceeds in the same manner as in the first embodiment, and the target nitride III-V compound semiconductor light emitting diode is manufactured.
Other than the above are the same as in the first embodiment.
FIG. 28 shows an enlarged view of the vicinity of the groove 20 in which the dielectric 21 is embedded and the p-side electrode 22 in this light emitting diode.
According to the fourth embodiment, the same advantages as those of the first and second embodiments can be obtained.

Next explained is the fifth embodiment of the invention.
In the fifth embodiment, as shown in FIG. 29, after forming the groove 20 as in the first embodiment, a dielectric 21 is embedded in the groove 20. At this time, the surface of the dielectric 21 is a left-right symmetrical convex surface composed of two inclined surfaces.
Thereafter, the process proceeds in the same manner as in the first embodiment, and the target nitride-based III-V compound semiconductor light-emitting diode is manufactured as shown in FIG.
Other than the above are the same as in the first embodiment.
FIG. 31 shows an enlarged view of the vicinity of the groove 20 in which the dielectric 21 is embedded and the p-side electrode 22 in this light emitting diode.
According to the fifth embodiment, advantages similar to those of the first embodiment can be obtained.

Next explained is the sixth embodiment of the invention.
In the sixth embodiment, after the dielectric 21 is embedded in the groove 20 as in the fifth embodiment, the reflective film 25 is formed on the surface of the dielectric 21 in the same manner as in the second embodiment. Then, the p-side electrode 22 is formed on the p-type nitride-based III-V compound semiconductor layer 18 so as to cover these reflective films 25.
Thereafter, the process proceeds in the same manner as in the first embodiment, and the target nitride III-V compound semiconductor light emitting diode is manufactured.
Other than the above are the same as in the first embodiment.
FIG. 32 shows an enlarged view of the vicinity of the groove 20 in which the dielectric 21 is buried and the p-side electrode 22 in this light emitting diode.
According to the sixth embodiment, the same advantages as those of the first and second embodiments can be obtained.

Next explained is the seventh embodiment of the invention.
In the seventh embodiment, as shown in FIG. 33, after forming the groove 20 as in the first embodiment, a dielectric 21 is embedded in the groove 20. At this time, the surface of the dielectric 21 is made to be an uneven surface.
Thereafter, the process proceeds in the same manner as in the first embodiment, and the target nitride-based III-V compound semiconductor light-emitting diode is manufactured as shown in FIG.
Other than the above are the same as in the first embodiment.
FIG. 35 shows an enlarged view of the vicinity of the groove 20 in which the dielectric 21 is buried and the p-side electrode 22 in this light emitting diode.
According to the seventh embodiment, the same advantages as those of the first embodiment can be obtained.

Next, an eighth embodiment of the invention will be described.
In the eighth embodiment, after the dielectric 21 is embedded in the groove 20 as in the seventh embodiment, the reflective film 25 is formed on the surface of the dielectric 21 in the same manner as in the second embodiment. Then, the p-side electrode 22 is formed on the p-type nitride-based III-V compound semiconductor layer 18 so as to cover these reflective films 25.
Thereafter, the process proceeds in the same manner as in the first embodiment, and the target nitride III-V compound semiconductor light emitting diode is manufactured.
Other than the above are the same as in the first embodiment.
FIG. 36 shows an enlarged view of the vicinity of the groove 20 in which the dielectric 21 is embedded and the p-side electrode 22 in this light emitting diode.
According to the eighth embodiment, the same advantages as those of the first and second embodiments can be obtained.

Next, a ninth embodiment of the invention will be described.
In the ninth embodiment, after forming the groove 20 in the same manner as in the first embodiment, as shown in FIG. 37, the groove 20 is embedded with the dielectric 21 in which the light scattering particles 26 are dispersed. Then, the entire surface of the p-type nitride III-V compound semiconductor layer 18 is planarized.
Next, as shown in FIG. 38, the p-side electrode 22 is formed on the p-type nitride III-V compound semiconductor layer 18.
Thereafter, the process proceeds in the same manner as in the first embodiment, and the target nitride-based III-V compound semiconductor light-emitting diode is manufactured as shown in FIG.
Other than the above are the same as in the first embodiment.
FIG. 40 shows an enlarged view of the vicinity of the groove 20 in which the dielectric 21 in which the light scattering particles 26 are dispersed and the p-side electrode 22 are embedded in this light emitting diode. Also in this case, light incident on the interface between the dielectric 21 embedded in the groove 20 and the p-side electrode 22 at an angle θ ₁ with respect to the normal of the main surface of the substrate 11 is light included in the dielectric 21. The scattering particles 26 scatter in the direction of an angle θ ₂ smaller than θ ₁ (that is, θ ₁ > θ ₂ ) with respect to the normal line of the main surface of the substrate 11. As a result, compared to the case where the main surface of the substrate 11 and the lower surface of the p-side electrode 22 are parallel to each other, the proportion of light incident on the main surface of the substrate 11 with a smaller incident angle increases. In particular, the amount of light that goes out through the substrate 11 increases.
According to the ninth embodiment, the same advantages as those of the first embodiment can be obtained.

Next explained is the tenth embodiment of the invention.
In the tenth embodiment, unlike the first embodiment, the n-type nitride III-V compound semiconductor layer 16, the active layer 17, and the p-type nitride III-V compound semiconductor layer 18 are not mesa. The part 23 is not formed. Then, the process proceeds in the same manner as in the first embodiment to form the p-side electrode 22 on the p-type nitride-based III-V compound semiconductor layer 18, and then the substrate 11 is removed, and the n-type nitride-based material is removed. The back surface of the III-V compound semiconductor layer 15 is exposed. Then, as shown in FIG. 41, the n-side electrode 24 is formed on the back surface of the nitride-based III-V compound semiconductor layer 15.
Here, by using the p-side electrode 22 and the n-side electrode 24 as a highly reflective electrode and a transparent electrode, respectively, light can be extracted to the outside through the n-side electrode 24.
Further, since the entire thickness of the light emitting diode becomes extremely small by removing the substrate 11, in order to improve the mechanical strength, as shown in FIG. 42, a support substrate 27 is placed on the p-side electrode 22 thereon. It may be bonded and bonded via the metal electrode 28. The support substrate 27 may be either conductive or non-conductive, and the support substrate 27 may have a structure that allows current to flow to the light emitting diode through the metal electrode 28.
Other than the above are the same as in the first embodiment.
According to the tenth embodiment, the same advantages as those of the first embodiment can be obtained. Here, the light generated in the active layer 17 spreads to the p-side electrode 22 side and the n-side electrode 24 side, but the material of the substrate 11 and the convex portion 12, the configuration of the convex portion 12, the p-side electrode 22 and the n-side electrode. The light extraction direction can be controlled by selectively using a highly reflective electrode or a transparent electrode as 24. The p-side electrode 22 is formed on almost the entire surface of the p-type nitride III-V compound semiconductor layer 18, and the n-side electrode 24 is also formed on the almost entire surface of the n-type nitride III-V compound semiconductor layer 15. Because it is formed, it is possible to prevent the occurrence of current crowding phenomenon, which is a cause of concern such as lowering of luminous efficiency and lowering reliability during the operation of the light emitting diode. The light emitting efficiency and reliability of the diode can be improved, and this is particularly effective when the output of the light emitting diode is increased.

Next, an eleventh embodiment of the present invention will be described.
In the eleventh embodiment, as shown in FIG. 43A, convex portions 12 having a trapezoidal cross section are periodically formed on a substrate 11 in a predetermined plane shape. A concave portion 13 having an inverted trapezoidal cross-sectional shape is formed between the convex portions 12.
Next, the nitride III-V compound semiconductor layer 15 is grown in the same manner as in the first embodiment. Specifically, as shown in FIG. 43B through the process of generating, growing and coalescing the micronuclei 14 on the bottom surface of the recess 13, the nitride having an isosceles triangular cross-section with the bottom surface of the recess 13 as the base As shown in FIG. 43C, a III-V group compound semiconductor layer 15 having a flat surface and a low threading dislocation density is grown through lateral growth. Grow.
Next, the process proceeds in the same manner as in the first embodiment, and the target nitride-based III-V compound semiconductor light-emitting diode is manufactured as shown in FIG.
Other than the above are the same as in the first embodiment.
According to the eleventh embodiment, advantages similar to those of the first embodiment can be obtained.

FIGS. 45 to 47 show an example of a result of a simulation of a change in light extraction efficiency from the light emitting diode to the outside when the substrate 11 is uneven and when the substrate 11 is flat. In any case, light extraction is performed from the back side of the substrate 11.
In FIG. 45, the horizontal axis indicates the refractive index of the convex portion 12, and the vertical axis indicates the degree of improvement in light extraction efficiency η (light extraction magnification) with respect to the case where the convex portion 12 is not formed. In FIG. 45, the data ▲ is obtained when the convex portions 12 are in the one-dimensional stripe shape shown in FIG. 9 (1D), and the data ● is obtained by providing the one-dimensional stripe-shaped convex portions 12 orthogonal to each other. The case of a two-dimensional array (2D) is shown. However, the angle θ formed between the side surface of the convex portion 12 and one main surface of the substrate 11 is 135 °, the length W _g of the bottom side of the concave portion 13 is 2 μm, and the length of the bottom side of the convex portion 12 is 3 μm. The refractive index of the substrate 11 was assumed to be 1.77, and the refractive index of the nitride III-V compound semiconductor layer 15 was assumed to be 2.35. From FIG. 45, the light extraction magnification becomes maximum when the refractive index of the convex portion 12 is 1.4 for both 1D and 2D, and becomes sufficiently large when the refractive index is in the range of 1.2 to 1.7. It can be seen that the light extraction magnification is larger than that of 1D.
This result is the same when the cross-sectional shape of the convex portion 12 is triangular as in the first embodiment.

In FIG. 46, the horizontal axis represents the angle θ formed by the side surface of the convex portion 12 and one main surface of the substrate 11, and the vertical axis represents the light extraction magnification. In FIG. 46, the data ▲ is obtained when the convex portion 12 has the one-dimensional stripe shape shown in FIG. 9 (1D), and the data ● represents that the convex portions 12 having the one-dimensional stripe shape are provided orthogonal to each other. The case of a two-dimensional array (2D) is shown. However, the length W _g of the bottom side of the recess 13 is 3 μm, and the length of the bottom side of the projection 12 is 2 μm. It is assumed that the refractive index of the substrate 11 is 1.77, the refractive index of the convex portion 12 is 1.4, and the refractive index of the nitride III-V compound semiconductor layer 15 is 2.35. From FIG. 46, the light extraction magnification is as large as 1.55 times or more in the range of 100 ° <θ <160 °, and the angle θ formed by the side surface of the convex portion 12 with one main surface of the substrate 11 is 132 ° in both 1D and 2D. In the range of <θ <139 °, it is extremely large as 1.75 times or more, especially, it becomes maximum when θ = 135 °, or even in the range of 147 ° <θ <154 °, it is extremely large as 1.75 times or more, especially θ = 152. It can be seen that the maximum is at °, and the light extraction magnification is larger in 2D than in 1D.
This result is the same when the cross-sectional shape of the convex portion 12 is triangular as in the first embodiment.

In FIG. 47, the horizontal axis indicates the depth d of the concave portion 13, and the vertical axis indicates the degree of improvement in the light extraction efficiency η (light extraction magnification) with respect to the case where the convex portion 12 is not formed. The convex portion 12 has a one-dimensional stripe shape shown in FIG. However, the ratio between the length W _g of the bottom side of the concave portion 13 and the length of the bottom side of the convex portion 12 is 3: 2. It is assumed that the refractive index of the substrate 11 is 1.77, the refractive index of the convex portion 12 is 1.4, and the refractive index of the nitride III-V compound semiconductor layer 15 is 2.35. FIG. 47 shows that the light extraction magnification increases as the depth of the recess 13 increases.

48A, a sapphire substrate is used as the substrate 11, a concavo-convex substrate having a trapezoidal cross section formed thereon is used, and an n-type GaN is used as the nitride III-V compound semiconductor layer 15 thereon. N-type nitride III-V group compound semiconductor layer 16 as n-type GaN layer and n-type GaInN layer, active layer 17 as In composition corresponding to green emission wavelength, GaInN / GaN MQW structure, p-type nitride Atomic force microscope (AFM) on the surface of the p-type GaInN layer of a green light-emitting diode produced by growing a p-type AlInN layer, a p-type GaN layer, and a p-type GaInN layer as the III-V compound semiconductor layer 18 An example of an image (20 μm □) is shown. FIG. 48B shows an example of an AFM image (20 μm □) of the surface of the p-type GaInN layer of a green light emitting diode manufactured in the same manner as described above except that a normal flat sapphire substrate is used. As shown in FIG. 48B, high-density pits exceeding 1 × 10 ⁸ / cm ² are randomly dispersed in the surface of the p-type GaInN layer of the light emitting diode using a normal flat sapphire substrate. Yes. On the other hand, as shown in FIG. 48A, pits are unevenly distributed on the surface of the p-type GaInN layer of the light emitting diode using the concavo-convex substrate, and grow from the vicinity of the central portion of the convex portion 12, that is, from the concave portions 13 adjacent to each other. The pit density of the portion considered to correspond to the meeting portion between the layers is as high as about 1 × 10 ⁸ / cm ^2, and the pit density of the portion considered to correspond to the recess 13 is about 1 × 10 ⁷ / cm ^2. 44, which is in good agreement with the distribution of threading dislocations 19 shown in FIG.

Next, a twelfth embodiment of the invention is described.
In the twelfth embodiment, as shown in FIG. 49, convex portions 12 having a trapezoidal cross section are periodically formed on the substrate 11, and an inverted trapezoidal cross sectional shape is formed between the convex portions 12. The formation of the recess 13 is the same as in the eleventh embodiment. In this case, the width W _t of the top surface of the projection 12 is selected to be sufficiently larger than the width W _g of the bottom surface of the recess 13. Then, on the substrate 11, the nitride III-V compound semiconductor layer 15, the n-type nitride III-V compound semiconductor layer 16, the active layer 17, and the p-type nitride are formed in the same manner as the eleventh embodiment. The physical group III-V compound semiconductor layer 18 is grown sequentially.
Thereafter, the process proceeds in the same manner as in the first embodiment, and the target nitride-based III-V compound semiconductor light-emitting diode is manufactured as shown in FIG.
Other than the above are the same as in the first embodiment.
According to the twelfth embodiment, the same advantages as those of the first embodiment can be obtained.

Next, a thirteenth embodiment of the invention is described.
In the thirteenth embodiment, a groove 20 is formed in the threading dislocation 19 as in the twelfth embodiment. In this case, the substrate 11 is exposed in the groove 20 as shown in FIG. Form to depth. The material of the convex portion 12 is preferably an amorphous material such as SiO ₂ so that it can be easily removed by wet etching later. However, the material is not limited to this. Absent. As will be described later, at least one groove 20 that forms the protective element is formed to have a larger width than the other grooves 20 as necessary, and is used here.
Next, as shown in FIG. 52, the grooves 20 other than the wide groove 20 are filled with the dielectric 21, and an insulating film 29 such as a SiO ₂ film is formed on the inner wall of the wide groove 20 to emit light therebetween. A diode protection element 30 is formed. The protective element 30 is for preventing destruction of the light emitting diode when an overvoltage is applied to the light emitting diode.
Next, the p-side electrode 22 is formed on the p-type nitride III-V compound semiconductor layer 18.
Next, the protrusions 12 and the like are removed by etching, and the substrate 11 is further removed to expose and flatten the back surface of the n-type nitride III-V compound semiconductor layer 15. Then, as shown in FIG. 53, the n-side electrode 24 is formed on the back surface of the nitride III-V compound semiconductor layer 15.
Here, by using the p-side electrode 22 and the n-side electrode 24 as a highly reflective electrode and a transparent electrode, respectively, light can be extracted to the outside through the n-side electrode 24.
Further, since the entire thickness of the light emitting diode becomes extremely small by removing the substrate 11, in order to improve the mechanical strength, the support substrate 27 is placed on the p-side electrode 22 as shown in FIG. The metal electrode 28 may be attached and bonded.
Other than the above are the same as in the first embodiment.

In this light emitting diode, the protection element 30 is connected in parallel between the p-side electrode 22 and the n-side electrode 24. An equivalent circuit is shown in FIG.
Various elements can be used as the protective element 30, and specific examples are as follows.
FIG. 55 shows a case where a Schottky barrier diode 31 connected in reverse parallel to the light emitting diode is used as the protection element 30. An equivalent circuit is shown in FIG. As shown in FIG. 55, the Schottky barrier diode 31 includes an n-type semiconductor layer 31a and a Schottky electrode 31b in Schottky contact with the n-type semiconductor layer 31a. The p-side electrode 22 is in ohmic contact with the n-type semiconductor layer 31a, and the n-side electrode 24 is connected to the Schottky electrode 31b. Examples of the material of the n-type semiconductor layer 31a include n-type amorphous silicon, ITO, ZnO, SnO ₂ , In ₂ O ₃ , ZnS, ZnSe, ZnSb ₂ O ₆ , CdO, CdIn ₂ O ₄ , MgIn ₂ O ₄ , ZnGa ₂ O ₄ , CdGa ₂ O ₄ , Ga ₂ O ₃ , GaSnO ₃ , CdSnO ₄ , InGaMgO ₄ , InGaZnO ₄ , Zn ₂ In ₂ O ₅ , AgSbO ₃ , Cd ₃ Sb ₂ O ₇ , Cd ₂ GeO ₄ , AgInO _2. Known materials such as CdS and CdSe can be used. As a material of the Schottky electrode 31b, for example, a known Schottky material such as Ti, Pt, Cr, Al, Sm, PtSi, and Pd ₂ Si can be used.

  The Schottky barrier diode 31 becomes conductive when a reverse overvoltage (surge voltage) of a predetermined value or more is applied to the light emitting diode. For this reason, since the voltage between both terminals of the light emitting diode is limited to the forward voltage of the Schottky barrier diode 31, the light emitting diode is protected from a reverse overvoltage due to static electricity or the like. The conduction start voltage of the Schottky barrier diode 31 is set to be equal to or lower than the allowable maximum reverse voltage of the light emitting diode. That is, the forward conduction start voltage of the Schottky barrier diode 31 is set to a value lower than the voltage at which the light emitting diode may be destroyed. Note that the forward conduction start voltage of the Schottky barrier diode 31 is preferably higher than the reverse voltage applied to the light emitting diode during normal operation and lower than the voltage at which the light emitting diode may be destroyed.

FIG. 57 shows a case where a Schottky barrier diode 31 that is also connected in reverse parallel to the light emitting diode is used as the protection element 30, and an equivalent circuit is as shown in FIG. As shown in FIG. 57, the Schottky barrier diode 31 includes a p-type semiconductor layer 31c and a Schottky electrode 31b in Schottky contact with the p-type semiconductor layer 31c. The n-side electrode 24 is in ohmic contact with the p-type semiconductor layer 31c, and the p-side electrode 22 is connected to the Schottky electrode 31b. As a material of the p-type semiconductor layer 31c, p-type amorphous silicon, NiO, Cu ₂ O, FeO, CuAlO ₂ , SrCu ₂ O ₂ or the like can be used.
The forward conduction start voltage of the Schottky barrier diode 31 is the same as that of the Schottky barrier diode 31 shown in FIG.

  FIG. 58 shows a case where a pn junction diode 32 connected in reverse parallel to the light emitting diode is used as the protection element 30. An equivalent circuit is shown in FIG. As shown in FIG. 58, the pn junction diode 32 includes a p-type semiconductor layer 32a and an n-type semiconductor layer 32b. The p-side electrode 22 is in ohmic contact with the n-type semiconductor layer 32b, and the n-side electrode 24 is in ohmic contact with the p-type semiconductor layer 32a. If necessary, a metal layer for improving ohmic contact characteristics may be provided between the p-side electrode 22 and the n-type semiconductor layer 32b and between the n-side electrode 24 and the p-type semiconductor layer 32a. .

  The pn junction diode 32 is configured as a rectifier diode or a constant voltage diode. When the pn junction diode 32 is configured as a rectifier diode, the pn junction diode 32 is turned on when an overvoltage in a reverse direction equal to or greater than a predetermined value is applied to the light emitting diode. As a result, the voltage applied to the light emitting diode is limited to the forward voltage of the pn junction diode 32. Therefore, the light emitting diode can be protected from reverse overvoltage such as surge voltage due to static electricity. The forward conduction start voltage of the pn junction diode 32 is set to be equal to or lower than the maximum allowable reverse voltage of the light emitting diode. The forward conduction start voltage of the pn junction diode 32 is preferably higher than the voltage applied in the reverse direction to the light emitting diode during normal operation and lower than the voltage at which the light emitting diode may be destroyed.

  When the pn junction diode 32 is configured as a constant voltage diode such as a Zener diode, the reverse breakdown voltage of the pn junction diode 32 is between the forward voltage in the normal operating range of the light emitting diode and the allowable maximum forward voltage. Is set. Thus, the pn junction diode 32 protects the light emitting diode from forward overvoltage such as surge voltage. The forward conduction start voltage of the pn junction diode 32 is preferably higher than the voltage applied in the reverse direction to the light emitting diode during normal operation and lower than the voltage at which the light emitting diode may be destroyed.

FIG. 60 shows a case where an npn junction diode 33 connected in parallel to the light emitting diode is used as the protection element 30. An equivalent circuit is shown in FIG. As shown in FIG. 60, the npn junction diode 33 includes an n-type semiconductor layer 33a, a p-type semiconductor layer 33b, and an n-type semiconductor layer 33c. The p-side electrode 22 is in ohmic contact with the n-type semiconductor layer 33a, and the n-side electrode 24 is in ohmic contact with the n-type semiconductor layer 33c. If necessary, a metal layer for improving ohmic contact characteristics may be provided between the p-side electrode 22 and the n-type semiconductor layer 33a and between the n-side electrode 24 and the n-type semiconductor layer 33c. .
The breakdown voltage in the forward direction and the reverse direction of the npn junction diode 33 is preferably between the voltage in the normal operating range of the light emitting diode and the allowable maximum voltage. Thereby, the back-to-back diode 33 as a constant voltage diode protects the light emitting diode from an overvoltage such as a surge voltage higher than the allowable maximum voltage.

FIG. 62 shows a case where the capacitor 34 connected in parallel to the light emitting diode is used as the protection element 30. An equivalent circuit is shown in FIG. As shown in FIG. 62, the capacitor 34 is formed by sandwiching a dielectric 35 between the p-side electrode 22 and the n-side electrode 24. The dielectric 35 is made of a dielectric material having a relative dielectric constant larger than that of the insulating film 29 formed on the inner wall of the groove 20. Examples of the dielectric material include barium titanate and strontium titanate, but are not limited thereto, and other known dielectric materials can be used.
The capacitor 34 protects the light emitting diode from an overvoltage such as a surge voltage higher than the voltage in the normal operating range of the light emitting diode.

According to the thirteenth embodiment, since the protective element 30 is connected in parallel to the light emitting diode, the protective element 30 works when an overvoltage is applied to the light emitting diode for some reason. This destruction of the light emitting diode can be effectively prevented. Further, since the protective element 30 is formed in the groove 20 formed for the removal of the threading dislocation 19, there is almost no decrease in the effective light emitting area. Further, the wiring between the light emitting diode and the protection element 30 is not necessary. In addition, the same advantages as those of the first embodiment can be obtained. That is, the threading dislocations in the nitride-based III-V compound semiconductor layer 15 are concentrated in the vicinity of the central portion of the convex portion 12 of the substrate 11, and the dislocation density in other portions is, for example, about 6 × 10 ⁷ / cm ² . Since it is greatly reduced as compared with the case of using the concavo-convex processed substrate, the nitride III-V compound semiconductor layer such as the nitride III-V compound semiconductor layer 15 and the active layer 17 grown thereon is used. The crystallinity of this material is greatly improved, and the non-luminescent center and the like are also greatly reduced. Further, threading dislocations generated in the nitride-based III-V compound semiconductor layer 15, the n-type nitride-based III-V compound semiconductor layer 16, the active layer 17, and the p-type nitride-based III-V compound semiconductor layer 18. 19 of the n-type nitride III-V group compound semiconductor layer 16 is removed by forming a groove 20 in this portion up to a depth in the middle of the thickness direction. It is possible to remove the non-luminescent center that is concentrated in the threading dislocation 19 in the removed portion and the portion in the vicinity thereof. For this reason, a significant reduction in non-radiative recombination can be achieved. As a result, a nitride III-V compound semiconductor light emitting diode with extremely high luminous efficiency can be obtained. In addition, the epitaxial growth necessary for manufacturing the nitride-based III-V compound semiconductor light-emitting diode is only required once, and not only a growth mask is not required, but also the protrusion 12 on the substrate 11 is formed on the substrate 11. Since a film such as a SiO ₂ film, for example, that forms the material of the convex portion 12 can be formed by etching and processed by etching or the like, the processing of the substrate 11 such as a sapphire substrate that is difficult to process unevenly. Therefore, the manufacturing process is simple, and a nitride III-V compound semiconductor light emitting diode can be manufactured at low cost.

Next, a fourteenth embodiment of the invention is described.
In the fourteenth embodiment, the steps up to the formation of the p-side electrode 22 are the same as those in the first embodiment, but the subsequent steps are different. Here, the p-side electrode 22 is preferably formed by interposing a layer containing Pd in order to prevent diffusion of an electrode material (for example, Ag) or the like, and forming stress, heat, or an upper layer thereon. A high melting point such as Ti, W, Cr, or an alloy thereof, for example, to prevent the occurrence of defects due to diffusion of Au or Sn to the p-side electrode 22 from a layer containing Au or Sn (such as a solder layer or a bump) By forming a metal or a nitride of these metals (TiN, WN, TiWN, CrN, etc.), a technique for applying an amorphous barrier metal layer without grain boundaries is applied. The description and illustration of the groove 20 and the dielectric 21 filling the groove 20 are omitted.

That is, in the fourteenth embodiment, as shown in FIG. 64A, after the p-side electrode 22 is formed, the Ni film 41 is formed so as to cover the p-side electrode 22 by a lift method or the like. Next, although illustration is omitted, for example, a Pd film is formed so as to cover the Ni film 41, and a metal nitride film such as TiN, WN, TiWN, CrN, etc. is formed so as to cover the Pd film, Further, if necessary, a film of Ti, W, Mo, Cr, or an alloy thereof is formed so as to cover this film. However, the Ni film 41 is not formed, but instead, a Pd film is formed so as to cover the p-side electrode 22, and a film such as TiN, WN, TiWN, CrN is formed so as to cover the Pd film, A film of Ti, W, Mo, Cr, or an alloy thereof may be formed so as to cover this film as necessary.
Next, as shown in FIG. 64B, a resist pattern 42 having a predetermined shape is formed by lithography to cover layers such as the Ni film 41 and the Pd film thereon.
Next, as shown in FIG. 64C, the mesa portion 23 is formed to have a trapezoidal cross section by etching, for example, by the RIE method using the resist pattern 42 as a mask. The angle formed by the slope of the mesa portion 23 and the main surface of the substrate 11 is, for example, about 35 degrees. A λ / 4 dielectric film (λ: emission wavelength) is formed on the slope of the mesa portion 23 as necessary.

Next, as shown in FIG. 64D, the n-side electrode 24 is formed on the n-type nitride-based III-V group compound semiconductor layer 15.
Next, as shown in FIG. 64E, a SiO ₂ film 43 is formed as a passivation film on the entire surface of the substrate. In consideration of adhesion to the base, durability, and corrosion resistance in the process, a SiN film or a SiON film may be used instead of the SiO ₂ film 43.
Next, as shown in FIG. 64F, the SiO ₂ film 43 is etched back and thinned, and then an Al film 44 is formed as a reflective film on the SiO ₂ film 43 on the slope of the mesa portion 23. The Al film 44 is for reflecting the light generated from the active layer 17 toward the substrate 11 to improve the light extraction efficiency. One end of the Al film 44 is formed in contact with the n-side electrode 24. This is because reflection of light is increased by preventing a gap from being formed between the Al film 44 and the n-side electrode 24. Thereafter, the SiO ₂ film 43 is formed again to have a thickness necessary for the passivation film.

Next, as shown in FIG. 64G, portions of the SiO ₂ film 43 above the Ni film 41 and the n-side electrode 24 are removed by etching to form openings 45 and 46, and the Ni film 41 and The n-side electrode 24 is exposed.
Next, as shown in FIG. 64H, a pad electrode 47 is formed on the Ni film 41 in the opening 45 portion, and a pad electrode 48 is formed on the n-side electrode 24 in the opening 46 portion.
Next, as shown in FIG. 64I, after a bump mask material 49 is formed on the entire surface of the substrate, a portion of the bump mask material 49 above the pad electrode 48 is removed by etching to form an opening 50. The pad electrode 48 is exposed.

Next, as shown in FIG. 64J, Au bumps 51 are formed on the pad electrodes 48 using a bump mask material 49. Next, the bump mask material 49 is removed. Next, after a bump mask material (not shown) is formed again on the entire surface of the substrate, an opening is formed by etching away a portion of the bump mask material above the pad electrode 47, and the pad electrode 47 is formed in this portion. To expose. Next, an Au bump 52 is formed on the pad electrode 47.
Next, if necessary, the substrate 11 on which the light emitting diode structure is formed as described above is reduced in thickness by grinding or lapping from the back side, and then the substrate 11 is scribed, Form. Thereafter, the bar is scribed to form a chip.

Next, a fifteenth embodiment of the invention is described.
In the fifteenth embodiment, in addition to the blue light emitting diode and the green light emitting diode obtained by the method according to the first embodiment, a separately prepared red light emitting diode (for example, an AlGaInP light emitting diode) is used. A case where a light emitting diode backlight is manufactured using the same will be described.
A blue light emitting diode structure is formed on the substrate 11 by the method according to the first embodiment, and bumps (not shown) are formed on the p-side electrode 22 and the n-side electrode 24, respectively, and then formed into chips. Thus, a blue light emitting diode is obtained in the form of a flip chip. Similarly, a green light emitting diode is obtained in the form of a flip chip. On the other hand, as a red light emitting diode, an AlGaInP light emitting diode is formed by stacking an AlGaInP semiconductor layer on an n-type GaAs substrate to form a diode structure and forming a p-side electrode thereon. It shall be used in the form.

Then, after mounting the red light emitting diode chip, the green light emitting diode chip, and the blue light emitting diode chip on a submount made of AlN or the like, each of them is mounted on the submount, for example, an Al substrate or the like. Mount in a predetermined arrangement on the substrate. This state is shown in FIG. 65A. In FIG. 65A, reference numeral 61 denotes a substrate, 62 denotes a submount, 63 denotes a red light emitting diode chip, 64 denotes a green light emitting diode chip, and 65 denotes a blue light emitting diode chip. The chip size of the red light emitting diode chip 63, the green light emitting diode chip 64, and the blue light emitting diode chip 65 is, for example, 350 μm square. Here, the red light emitting diode chip 63 is mounted such that the n-side electrode is on the submount 62, and the green light emitting diode chip 64 and the blue light emitting diode chip 65 are the p side electrode and the n side. The electrode is placed on the submount 62 through the bump. An extraction electrode (not shown) for an n-side electrode is formed in a predetermined pattern shape on the submount 62 on which the red light emitting diode chip 63 is mounted, and a red portion is formed on a predetermined portion on the extraction electrode. The n-side electrode side of the light emitting diode chip 63 for light emission is mounted. A wire 67 is bonded to the p-side electrode of the red light emitting diode chip 63 and a predetermined pad electrode 66 provided on the substrate 61, and the lead electrode A wire (not shown) is bonded to one end and another pad electrode provided on the substrate 61 so as to connect them. On the submount 62 on which the green light emitting diode chip 64 is mounted, a lead electrode for the p-side electrode and a lead electrode for the n-side electrode (both not shown) are respectively formed in a predetermined pattern shape. Bumps in which the p-side electrode and the n-side electrode side of the light emitting diode chip 64 for green light emission are formed on the lead-out electrode for the p-side electrode and the lead-out electrode for the n-side electrode are formed on them. Each is mounted through. A wire (not shown) is bonded to one end of the lead electrode for the p-side electrode of the green light emitting diode chip 64 and a pad electrode provided on the substrate 61 so as to connect them. In addition, a wire (not shown) is bonded to one end of the extraction electrode for the n-side electrode and a pad electrode provided on the substrate 61 so as to connect them. The same applies to the light-emitting diode chip 65 emitting blue light.
However, the submount 62 is omitted, and the red light emitting diode chip 63, the green light emitting diode chip 64, and the blue light emitting diode chip 65 are directly connected to any printed wiring board or printed wiring board having heat dissipation properties. It is also possible to mount directly on a plate having the above function, or on the inner and outer walls of the housing (for example, the inner wall of the chassis), thereby reducing the cost of the light emitting diode backlight or the entire panel.

The red light emitting diode chip 63, the green light emitting diode chip 64, and the blue light emitting diode chip 65 as described above are set as one unit (cell), and a necessary number of them are arranged on the substrate 61 in a predetermined pattern. . An example is shown in FIG. Next, as shown in FIG. 65B, potting of the transparent resin 68 is performed so as to cover this one unit. Thereafter, the transparent resin 68 is cured. By this curing process, the transparent resin 68 is solidified and is slightly reduced accordingly (FIG. 65C). In this way, as shown in FIG. 67, the light emitting diode chip 63 that emits red light, the light emitting diode chip 64 that emits green light, and the light emitting diode chip 65 that emits blue light are arranged on the substrate 61 in an array. A diode backlight is obtained. In this case, since the transparent resin 68 is in contact with the back surface of the substrate 11 of the green light emitting diode chip 64 and the blue light emitting diode chip 65, the back surface of the substrate 11 is in direct contact with air. Accordingly, the difference in refractive index is reduced, and therefore the ratio of the light that is transmitted through the substrate 11 and exits to the outside is reflected by the back surface of the substrate 11, thereby improving the light extraction efficiency, thereby improving the light emission efficiency. Will improve.
This light emitting diode backlight is suitable for use in a backlight of a liquid crystal panel, for example.

Next, a sixteenth embodiment of the invention is described.
In the sixteenth embodiment, as in the fifteenth embodiment, a red light emitting diode chip 63, a green light emitting diode chip 64, and a blue light emitting diode chip 65 are arranged on a substrate 61 in a predetermined pattern. As shown in FIG. 68, the transparent resin 69 suitable for the light emitting diode chip 63 is potted to cover the red light emitting diode chip 63, and the green light emitting diode chip 64 is replaced. The transparent resin 70 suitable for the light emitting diode chip 64 is potted so as to cover, and the transparent resin 71 suitable for the light emitting diode chip 65 is potted so as to cover the blue light emitting diode chip 65. Thereafter, the curing treatment of the transparent resins 69 to 71 is performed. By this curing process, the transparent resins 69 to 71 are solidified and are slightly reduced accordingly. In this way, a light emitting diode backlight in which the red light emitting diode chip 63, the green light emitting diode chip 64, and the blue light emitting diode chip 65 as a unit are arranged in an array on the substrate 61 is obtained. In this case, since the transparent resins 70 and 71 are in contact with the back surface of the substrate 11 of the green light emitting diode chip 64 and the blue light emitting diode chip 65, respectively, the back surface of the substrate 11 is in direct contact with air. The difference in refractive index is smaller than in the case, and therefore the ratio of the light that is transmitted through the substrate 11 and exits to the outside is reduced by the back surface of the substrate 11, thereby improving the light extraction efficiency. The luminous efficiency is improved.
This light emitting diode backlight is suitable for use in a backlight of a liquid crystal panel, for example.

Next, a seventeenth embodiment of the invention is described.
In the seventeenth embodiment, a light source cell unit is manufactured using a separately prepared red light emitting diode in addition to a blue light emitting diode and a green light emitting diode obtained by the method according to the first embodiment. The case will be described.
As shown in FIG. 69A, in the seventeenth embodiment, as in the sixteenth embodiment, a red light emitting diode chip 63, a green light emitting diode chip 64, and a blue light emitting diode chip 65 are provided. A required number of cells 75 each including at least one and arranged in a predetermined pattern are arranged on the printed wiring board 76 in a predetermined pattern. In this example, each cell 75 includes a red light emitting diode chip 63, a green light emitting diode chip 64, and a blue light emitting diode chip 65, which are arranged at the apexes of an equilateral triangle. FIG. 69B shows the cell 75 in an enlarged manner. The interval a between the red light emitting diode chip 63, the green light emitting diode chip 64, and the blue light emitting diode chip 65 in each cell 75 is, for example, 4 mm, but is not limited thereto. The interval b of the cells 75 is, for example, 30 mm, but is not limited to this. As the printed wiring board 76, for example, an FR4 (abbreviation of Flame Retardant Type 4) board, a metal core board, a flexible wiring board, or the like can be used, but any other printed wiring board having heat dissipation can be used. However, it is not limited to these. As in the sixteenth embodiment, the transparent resin 68 is potted so as to cover each cell 76, or the transparent resin is covered so as to cover the red light emitting diode chip 63 as in the seventeenth embodiment. 69, potting of the transparent resin 70 is performed so as to cover the green light emitting diode chip 64, and potting of the transparent resin 71 is performed so as to cover the blue light emitting diode chip 65. In this way, a light source cell unit is obtained in which the cells 75 including the red light emitting diode chip 63, the green light emitting diode chip 64, and the blue light emitting diode chip 65 are arranged on the printed wiring board 76.

Specific examples of the arrangement of the cells 75 on the printed wiring board 76 are shown in FIGS. 70 and 71, but are not limited thereto. The example shown in FIG. 70 has cells 75 arranged in a 4 × 3 two-dimensional array, and the example shown in FIG. 71 has cells 75 arranged in a 6 × 2 two-dimensional array.
FIG. 72 shows another configuration example of the cell 75. In this example, the cell 75 includes one red light emitting diode chip 63, two green light emitting diode chips 64, and one blue light emitting diode chip 65, which are arranged at the apex of a square, for example. Has been. Two green light emitting diode chips 64 are arranged at the vertices of one end of one diagonal of the square, and a red light emitting light emitting diode chip 63 and a blue light emitting light emitting diode chip 65 are disposed at both ends of the other diagonal of the square. It is placed at the vertex.
By arranging one or a plurality of the light source cell units, a light emitting diode backlight suitable for use in a backlight of a liquid crystal panel, for example, can be obtained.

Next, an eighteenth embodiment of the invention is described.
In the eighteenth embodiment, the groove 20 is formed in the threading dislocation 19 as in the twelfth embodiment. In this case, the groove 20 is formed in the portion corresponding to the recess 13 as shown in FIG. The groove 20 is formed to a depth at which the substrate 11 is exposed, and the groove 20 formed in a portion corresponding to the central portion of the convex portion 12 is a depth in the middle of the thickness of the n-type nitride III-V compound semiconductor layer 16. To form. As the material of the convex portion 12, an amorphous material such as SiO ₂ is preferably used so that it can be easily removed by wet etching as necessary.

Next, as shown in FIG. 74, the p-side electrode 22 made of a highly reflective electrode is formed on the p-type nitride-based III-V compound semiconductor layer 18. Next, after an insulating film 81 such as a SiO ₂ film is formed on the entire surface so as to cover the p-side electrode 22, the surface of the insulating film 81 is flattened. Next, a contact hole 82 is formed by selectively etching a portion of the insulating film 81 corresponding to the groove 20 formed in the portion corresponding to the central portion of the convex portion 12, and the contact hole 82 is formed in the contact hole 82. The n-type nitride III-V compound semiconductor layer 16 is exposed. Further, a predetermined portion of the insulating film 81 on the p-side electrode 22 is selectively etched to form a contact hole 83, and the p-side electrode 22 is exposed in the contact hole 83. Next, the n-side electrode 24 is formed on the n-type nitride III-V compound semiconductor layer 16 through the contact hole 82, and the electrode 84 is formed on the p-side electrode 22 through the contact hole 83.

Next, electrodes 85a and 85b are formed on one main surface of a wiring board 85 such as a printed wiring board on which a light emitting diode driving circuit and the like are formed, at positions corresponding to the n-side electrode 24 and the electrode 84 on the board 11. Separately, the electrodes 85a and 85b of the wiring board 85 are opposed to the n-side electrode 24 and the electrode 84 on the board 11, respectively, and these are crimped and bonded as shown in FIG. In this way, a light emitting diode array in which the wiring board 85 is integrated is obtained.
Here, if the pattern of the convex portions 12 and the concave portions 13 of the substrate 11 is a honeycomb pattern as shown in FIG. 10, the pattern of threading dislocations 19 in this case is as shown in FIG. When the groove 20 is formed so as to be removed, and the insulating film 81 is embedded in the groove 20, the light emitting diode having the hexagonal planar shape and the p-side electrode 22 and the n-side electrode 24 is embedded in the insulating film 81. A light-emitting diode array that is two-dimensionally arranged in a honeycomb shape while being electrically separated from each other by the grooves 20 is obtained. Each light emitting diode is driven by a light emitting diode driving circuit formed on the wiring board 85.

  In order to make this light emitting diode array full color, the following may be performed. In one method, each light emitting diode is configured to be capable of emitting ultraviolet light, and excited on the back surface of the portion of the substrate 11 corresponding to the portion of the light emitting diode where it is desired to obtain blue light emission, green light emission and red light emission. A phosphor-containing film containing a phosphor emitting blue light, a phosphor-containing film containing a phosphor emitting green light when excited by ultraviolet light, and emitting red light excited by ultraviolet light A phosphor-containing film containing the phosphor to be formed is formed. FIG. 76 shows a portion where a phosphor-containing film 86 containing a phosphor that emits blue light when excited by ultraviolet light is formed on the back surface of the substrate 11. In this way, blue light is extracted from the phosphor-containing film 86 from the portion where blue light emission is desired, and green light is extracted from the phosphor-containing film similarly from the portion where green light emission is desired. The red light is extracted from the phosphor-containing film from the portion where it is desired to obtain the light. One pixel can be formed by, for example, three adjacent light emitting diodes arranged in a regular triangle shape, but is not limited thereto.

In another method, each light emitting diode is configured to emit blue light, and green light and red light are emitted from the back surface of the portion of the substrate 11 corresponding to the portion of the light emitting diode that is desired to obtain green light emission and red light emission. A phosphor-containing film containing a phosphor that emits light and a phosphor-containing film containing a phosphor that emits red light when excited by blue light are formed. In this way, blue light is extracted directly from the blue light emitting diode from the portion where blue light emission is desired, and green light is extracted from the phosphor-containing film from the portion where green light emission is desired. Thus, red light is extracted from the phosphor-containing film from the portion where red light emission is desired.
According to the eighteenth embodiment, the wiring board 85 on which the light emitting diode driving circuit is formed can be easily integrated with the light emitting diode array. The light emitting diode array in which the wiring board 85 is integrated is suitable for use in a light emitting diode display, a light emitting diode backlight, a light emitting diode illumination device, a light source cell unit, and the like.

Next, a nineteenth embodiment of the present invention is described.
In the nineteenth embodiment, the groove 20 is formed in the threading dislocation 19 as in the twelfth embodiment. In this case, the groove 20 is formed in the portion corresponding to the recess 13 as shown in FIG. Both the groove 20 and the groove 20 formed in the portion corresponding to the central portion of the convex portion 12 are formed to a depth at which the substrate 11 is exposed. The material of the convex portion 12 is preferably an amorphous material such as SiO ₂ so that it can be easily removed by wet etching later. However, the material is not limited to this. Absent.

Next, as shown in FIG. 78, a p-side electrode 22 made of a highly reflective electrode is formed on the p-type nitride III-V compound semiconductor layer 18. Next, after an electrode 84 is formed on the p-side electrode 22, an insulating film 87 such as a SiO ₂ film is formed on the side wall of the electrode 84.
Next, separately prepared is one in which an electrode 88 is formed at a position corresponding to the electrode 84 on the substrate 11 on one main surface of the wiring substrate 85 such as a printed wiring substrate on which a light emitting diode driving circuit or the like is formed, The electrodes 88 of the wiring board 85 are opposed to the electrodes 84 on the board 11, respectively, and are bonded by pressure bonding as shown in FIG.

Next, as shown in FIG. 80, the convex portion 12 is removed by wet etching using an etchant that can selectively etch the convex portion 12 with respect to the nitride III-V compound semiconductor. Thus, the substrate 11 is peeled from the nitride III-V compound semiconductor layer 15. For example, when SiO ₂ is used as the material of the convex portion 12, a hydrofluoric acid-based etching solution is used as the etching solution.
Next, as shown in FIG. 81, an insulating film 89 is buried in the trench 20 and the back surface of the n-type nitride III-V compound semiconductor layer 15 is planarized. A transparent electrode made of ITO or the like is formed. Further, an electrode 90 is formed on a part of the n-side electrode 24 made of this transparent electrode.

  Here, if the pattern of the convex portions 12 and the concave portions 13 of the substrate 11 is a honeycomb pattern as shown in FIG. 10, the pattern of threading dislocations 19 in this case is as shown in FIG. When the groove 20 is formed so as to be removed, and the insulating film 35 is embedded in the groove 20, the light emitting diode having the hexagonal planar shape and the p-side electrode 22 and the n-side electrode 24 is embedded in the insulating film 87. A light-emitting diode array that is two-dimensionally arranged in a honeycomb shape while being electrically separated from each other by the grooves 20 is obtained. Each light emitting diode is driven by a light emitting diode driving circuit formed on the wiring board 85.

  In order to make this light emitting diode array full color, the following may be performed. In one method, each light emitting diode is configured to emit ultraviolet light, and excited on the n-side electrode 24 of the portion corresponding to the light emitting diode of the portion where blue light emission, green light emission and red light emission are desired, respectively. A phosphor-containing film containing a phosphor that emits blue light, a phosphor-containing film containing a phosphor that emits green light when excited by ultraviolet light, and red light that is excited by ultraviolet light. A phosphor-containing film containing a phosphor that emits light is formed. FIG. 81 shows a portion where a phosphor-containing film 86 containing a phosphor that emits blue light when excited by ultraviolet light is formed on the n-side electrode 24. In this way, blue light is extracted from the phosphor-containing film 86 from the portion where blue light emission is desired, and green light is extracted from the phosphor-containing film similarly from the portion where green light emission is desired. The red light is extracted from the phosphor-containing film from the portion where it is desired to obtain the light. One pixel can be formed by, for example, three adjacent light emitting diodes arranged in a regular triangle shape, but is not limited thereto.

  In another method, each light-emitting diode is configured to be capable of emitting blue light, and green light is excited on the n-side electrode 24 of the portion corresponding to the light-emitting diode of the portion where green light emission and red light emission are to be obtained. A phosphor-containing film containing a phosphor that emits light of the above and a phosphor-containing film containing a phosphor that emits red light when excited by blue light. By doing so, blue light is extracted directly from the blue light emitting diode from the portion where blue light emission is desired, and green light is extracted from the phosphor-containing film from the portion where green light emission is desired. Thus, red light is extracted from the phosphor-containing film from the portion where red light emission is desired.

As mentioned above, although embodiment of this invention was described concretely, this invention is not limited to the above-mentioned embodiment, The various deformation | transformation based on the technical idea of this invention is possible.
For example, the numerical values, materials, structures, shapes, substrates, raw materials, processes, orientations of the convex portions 12 and the concave portions 13 and the like given in the first to nineteenth embodiments are merely examples, and if necessary, Different values, materials, structures, shapes, substrates, raw materials, processes, and the like may be used.
Specifically, for example, in the first to nineteenth embodiments described above, the conductivity types of the p-type layer and the n-type layer may be reversed.
Moreover, you may combine 2 or more of the above-mentioned 1st-19th embodiment as needed.
In the fifteenth to nineteenth embodiments, instead of the board 61, the printed wiring board 76, and the wiring board 85, as shown in FIG. 82, the wiring patterns equivalent to the printed wiring board 76 are electrically insulated from each other. One electrode side of the red light emitting diode chip 63, the green light emitting diode chip 64, and the blue light emitting diode chip 65 is placed on a predetermined portion of the thin conductive substrates 91a, 91b, 91c (for example, a lead frame). Each may be directly mounted, and wire bonding may be performed to the other electrode with a wire 67, and then molded with a transparent resin 69 to 71, for example, by an integral molding technique using a mold. Here, the light emitting diode chips 63, 64, and 65 are vertical current injection types such as the light emitting diode shown in FIG. The light-emitting diode chips 63, 64, and 65 are preferably mounted in a desired arrangement and arrangement optimally designed for the purpose of early color mixing (whitening and uniformization). The light emitting diode chips 63, 64 and 65 may be integrally molded with a transparent resin 68. Of the conductive substrates 91a, 91b, 91c, the portion for mounting the light emitting diode chips 63, 64, 65 may be formed in a cup shape having an inclined surface, whereby the light extraction amount is reduced by reflection from the inclined surface. Can be increased. Further, when light is finally extracted from the light emitting diode chips 63, 64, and 65 on the conductive substrates 91a, 91b, and 91c, the light emitting diode chips 63, 64, and 65 are finally removed for the purpose of improving heat dissipation performance. Only the transparent resin 69 to 71 or the transparent resin 68 is molded so that heat is directly radiated from the conductive substrate 91 exposed to the outside on the side opposite to the light emitting diode chips 63, 64, 65. Is desirable. The light emitting diode chips 63, 64, and 65 have various forms such as flip chip (without wire bonding) and face up (with wire bonding), and the light extraction side is also light emitting diode chip 63, 64, 65 side, light emission. Since there is a side opposite to the diode chips 63, 64, 6 and the like, it goes without saying that the mold side and the heat dissipation side may be reversed depending on these forms.

It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 1st Embodiment of this invention. It is sectional drawing which expands and shows the vicinity of the groove | channel and the p side electrode in the light emitting diode by 1st Embodiment of this invention. It is a top view which shows the example of the planar shape of the convex part formed on a board | substrate in the manufacturing method of the light emitting diode by 1st Embodiment of this invention. It is a top view which shows the example of the planar shape of the convex part formed on a board | substrate in the manufacturing method of the light emitting diode by 1st Embodiment of this invention. It is a basic diagram which shows the example of distribution of the threading dislocation of the nitride type III-V compound semiconductor layer grown on the board | substrate in the manufacturing method of the light emitting diode by 1st Embodiment of this invention. It is a basic diagram which shows the example of distribution of the threading dislocation of the nitride type III-V compound semiconductor layer grown on the board | substrate in the manufacturing method of the light emitting diode by 1st Embodiment of this invention. It is a top view of the light emitting diode manufactured by the manufacturing method of the light emitting diode by 1st Embodiment of this invention. It is a basic diagram which shows the board | substrate used in the manufacturing method of the light emitting diode by 1st Embodiment of this invention. It is a basic diagram for demonstrating the mode of growth of the nitride type III-V compound semiconductor layer on a board | substrate in the manufacturing method of the light emitting diode by 1st Embodiment of this invention. It is a basic diagram which shows the mode of the growth of the nitride type III-V group compound semiconductor layer made to grow on a board | substrate in the manufacturing method of the light emitting diode by 1st Embodiment of this invention. FIG. 4 is a schematic diagram for explaining dislocation behavior of a nitride-based III-V compound semiconductor layer grown on a substrate in the method for manufacturing a light-emitting diode according to the first embodiment of the present invention. 5 is a drawing-substituting photograph showing an initial growth stage of a nitride III-V compound semiconductor layer grown on a substrate in the method for manufacturing a light-emitting diode according to the first embodiment of the present invention. In the method for manufacturing a light-emitting diode according to the first embodiment of the present invention, a schematic diagram showing a growth state when the generation of a micro-nucleus is not accompanied at the initial stage of growth of a nitride III-V compound semiconductor layer grown on a substrate. FIG. In the method for manufacturing a light-emitting diode according to the first embodiment of the present invention, a schematic diagram showing a growth state when the generation of a micro-nucleus is not accompanied at the initial stage of growth of a nitride III-V compound semiconductor layer grown on a substrate. FIG. It is a basic diagram which shows the result of the ray tracing simulation of the light emitting diode manufactured by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 2nd Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 2nd Embodiment of this invention. It is sectional drawing which expands and shows the vicinity of the groove | channel and the p side electrode in the light emitting diode by 2nd Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 3rd Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 3rd Embodiment of this invention. It is sectional drawing which expands and shows the vicinity of the groove | channel and the p side electrode in the light emitting diode by 3rd Embodiment of this invention. It is sectional drawing which expands and shows the vicinity of the groove | channel and the p side electrode in the light emitting diode by 4th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 5th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 5th Embodiment of this invention. It is sectional drawing which expands and shows the vicinity of the groove | channel and p side electrode in the light emitting diode by 5th Embodiment of this invention. It is sectional drawing which expands and shows the vicinity of the groove | channel and p side electrode in the light emitting diode by 6th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 7th Embodiment of this invention. It is sectional drawing which expands and shows the vicinity of the groove | channel and the p side electrode in the light emitting diode by 7th Embodiment of this invention. It is sectional drawing which expands and shows the vicinity of the groove | channel and the p side electrode in the light emitting diode by 7th Embodiment of this invention. It is sectional drawing which expands and shows the vicinity of the groove | channel and the p side electrode in the light emitting diode by 8th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 9th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 9th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 9th Embodiment of this invention. It is sectional drawing which expands and shows the vicinity of the groove | channel and the p side electrode in the light emitting diode by 10th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 10th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 10th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 11th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 11th Embodiment of this invention. It is a basic diagram which shows the result of the ray tracing simulation of the light emitting diode manufactured by 11th Embodiment of this invention. It is a basic diagram which shows the result of the ray tracing simulation of the light emitting diode manufactured by 11th Embodiment of this invention. It is a basic diagram which shows the result of the ray tracing simulation of the light emitting diode manufactured by 11th Embodiment of this invention. It is a drawing substitute photograph which shows the AFM image of an example of the light emitting diode of the light emitting diode manufactured by 11th Embodiment of this invention, and the AFM image of an example of the light emitting diode of a comparative example. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 12th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 12th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 13th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 13th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode with a protection element by 13th Embodiment of this invention. It is a basic diagram which shows the equivalent circuit of the light emitting diode with a protection element by 13th Embodiment of this invention. It is sectional drawing which shows the 1st specific example of the light emitting diode with a protection element by 13th Embodiment of this invention. It is a basic diagram which shows the equivalent circuit of the 1st specific example of the light emitting diode with a protection element by 13th Embodiment of this invention. It is sectional drawing which shows the 2nd specific example of the light emitting diode with a protection element by 13th Embodiment of this invention. It is sectional drawing which shows the 3rd specific example of the light emitting diode with a protection element by 13th Embodiment of this invention. It is a basic diagram which shows the equivalent circuit of the 3rd specific example of the light emitting diode with a protection element by 13th Embodiment of this invention. It is sectional drawing which shows the 4th specific example of the light emitting diode with a protection element by 13th Embodiment of this invention. It is a basic diagram which shows the equivalent circuit of the 4th example of the light emitting diode with a protection element by 13th Embodiment of this invention. It is sectional drawing which shows the 5th specific example of the light emitting diode with a protection element by 13th Embodiment of this invention. It is a basic diagram which shows the equivalent circuit of the 5th example of the light emitting diode with a protection element by 13th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 14th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode backlight by 15th Embodiment of this invention. It is a perspective view for demonstrating the manufacturing method of the light emitting diode backlight by 15th Embodiment of this invention. It is a perspective view for demonstrating the manufacturing method of the light emitting diode backlight by 15th Embodiment of this invention. It is a perspective view for demonstrating the manufacturing method of the light emitting diode backlight by 16th Embodiment of this invention. It is the top view which shows the light source cell unit by 17th Embodiment of this invention, and the enlarged view of the cell of this light source cell unit. It is a top view which shows one specific example of the light source cell unit by 17th Embodiment of this invention. It is a top view which shows the other specific example of the light source cell unit by 17th Embodiment of this invention. It is a top view which shows the other structural example of the cell of the light source cell unit by 17th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode array by 18th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode array by 18th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode array by 18th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode array by 18th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode array by 19th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode array by 19th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode array by 19th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode array by 19th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode array by 19th Embodiment of this invention. It is sectional drawing which shows the example of mounting of a light emitting diode. It is sectional drawing for demonstrating the growth method of the GaN-type semiconductor layer on the conventional uneven | corrugated processed substrate. It is sectional drawing for demonstrating the subject of the growth method of the conventional GaN-type semiconductor layer shown in FIG. It is sectional drawing for demonstrating the growth method of the GaN-type semiconductor layer on the conventional uneven | corrugated processed substrate. It is sectional drawing for demonstrating the growth method of the GaN-type semiconductor layer on the other conventional uneven | corrugated processed substrate.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Board | substrate, 12 ... Convex part, 13 ... Recessed part, 14 ... Micro nucleus, 15 ... Nitride type III-V group compound semiconductor layer, 16 ... N-type nitride type III-V group compound semiconductor layer, 17 ... Active layer 18 ... p-type nitride III-V compound semiconductor layer, 19 ... threading dislocation, 20 ... groove, 21 ... dielectric, 22 ... p-side electrode, 23 ... mesa portion, 24 ... n-side electrode, 25 ... reflection Membrane, 26 ... Light scattering particles, 30 ... Protection element, 63 to 65 ... Light emitting diode chip, 68 to 71 ... Transparent resin, 75 ... Cell, 76 ... Printed wiring board, 85 ... Wiring board

Claims (9)

Using a substrate having a plurality of convex portions on one principal surface, the first nitride system through a concave portion having an inverted trapezoidal cross-sectional shape of the substrate having a triangular cross-sectional shape with the bottom surface as a base Growing a group III-V compound semiconductor layer;
A second nitride-based III-V compound semiconductor layer is laterally grown from the first nitride-based III-V compound semiconductor layer on the substrate through a hexagonal cross-sectional shape in the recess. At this time, the first nitride-based III-V compound semiconductor layer is generated in a direction perpendicular to the one main surface from the interface with the bottom surface of the recess and has a triangular cross-sectional shape. A process in which dislocations reaching the slope or the vicinity thereof bend in a direction parallel to the one principal surface ;
On the second nitride III-V compound semiconductor layer, the third conductivity type third nitride III-V compound semiconductor layer, the active layer, and the second conductivity type fourth nitride. Sequentially growing a III-V compound semiconductor layer,
The first nitride III-V compound semiconductor layer, the second nitride III-V compound semiconductor layer, the third nitride III-V compound semiconductor layer, the active layer, and the above Of the fourth nitride-based III-V compound semiconductor layer, a portion corresponding to the central portion between the recess and / or the recesses adjacent to each other is used as the fourth nitride-based III-V compound semiconductor layer. Forming a groove by removing from the surface of the layer in a depth direction until at least the third nitride III-V compound semiconductor layer is exposed;
The groove is filled with a dielectric that is transparent to the light having the emission wavelength from the active layer. At this time, the surface of the dielectric has a concave portion and / or a convex portion, and / or the dielectric is light. manufacturing method of light-emitting diodes and a step to contain scattering particles. 2. The first nitride-based III-V group compound semiconductor layer is grown in the concave portion through a triangular cross-sectional shape having a bottom surface as a base, until the cross-sectional shape becomes a pentagonal shape. The manufacturing method of the light emitting diode of description. The projections manufacturing method of a light-emitting diode 請 Motomeko 1 or 2, wherein ing a different material as the substrate. The dielectric is the first nitride III-V compound semiconductor layer, the second nitride III-V compound semiconductor layer, the third nitride III-V compound semiconductor layer, production method of the active layer and the fourth nitride III-V compound that having a smaller refractive index than the refractive index of the semiconductor layer 請 Motomeko 1-3 emitting diode according to any one claim of. The depth of the recess is d, and the width of the bottom of the recess is W. _g 2d ≧ W where α is the angle formed by the slope of the first nitride-based III-V compound semiconductor layer and the one principal surface in the triangular cross-sectional shape. _g The manufacturing method of the light emitting diode as described in any one of Claims 1-4 with which tan (alpha) is materialized. The manufacturing method of the light emitting diode as described in any one of Claims 1-5 which has the said recessed part and convex part by turns on the said one main surface. The said recessed part is a manufacturing method of the light emitting diode as described in any one of Claims 1-5 extended in one direction. The method for manufacturing a light-emitting diode according to claim 1, wherein the recess extends at least in a first direction and a second direction intersecting each other. 9. The light-emitting diode according to claim 8, wherein the convex portion has a hexagonal planar shape, the convex portions are two-dimensionally arranged in a honeycomb shape, and the concave portion is formed so as to surround the convex portion. Method.

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