JP5140979B2 - AlGaInP light emitting diode, light source cell unit, display and electronic device - Google Patents

Description

  The present invention relates to a semiconductor light-emitting element, a method for manufacturing a semiconductor light-emitting element, a light source cell unit, a backlight, a display, and an electronic device, for example, a light-emitting diode using a III-V group compound semiconductor and various apparatuses using the light-emitting diode Or it is a thing suitable for applying to an apparatus.

Conventionally, in a semiconductor light emitting device using an AlGaInP-based semiconductor or an AlGaAs-based semiconductor, zinc (Zn), which easily obtains a high impurity concentration, has been used as the p-type impurity of the p-type semiconductor layer. However, since Zn easily diffuses, there is a problem that Zn is mixed into the active layer during the manufacturing process of the semiconductor light emitting device or during energization after completion, resulting in a decrease in light output or reliability. was there. In recent years, therefore, magnesium (Mg), which hardly diffuses, is used as a p-type impurity replacing Zn. However, when Mg is used as the p-type impurity, it is difficult to form a p-type contact layer having a high impurity concentration of 1 × 10 ¹⁹ cm ⁻³ or more. When manufactured, the contact resistance of the p-side electrode increases and the device resistance increases.

  As a countermeasure, a structure of a p-type contact layer having a two-layer structure in which Mg is doped on the side close to the active layer of the p-type contact layer and Zn is doped on the junction layer with the p-side electrode has been studied. (For example, refer to Patent Document 1). FIG. 24 shows an impurity concentration profile of a conventional AlGaInP light emitting diode to which such a p-type contact layer having a two-layer structure is applied.

  As shown in FIG. 24, in this conventional AlGaInP light emitting diode, an n-type cladding layer 101 made of AlGaInP doped with Si as an n-type impurity is formed on one main surface of an n-type GaAs substrate (not shown). An active layer 102 having a quantum well (MQW) structure, a p-type cladding layer 103 made of AlGaInP doped with Mg as a p-type impurity, a p-type intermediate layer 104 made of GaInP doped with Mg as a p-type impurity, and a p-type contact Layers 105 are sequentially stacked. The p-type contact layer 105 includes two layers of an Mg-doped layer 105a made of GaP doped with Mg as a p-type impurity and a Zn-doped layer 105b made of GaP doped with Zn as a p-type impurity. A p-side electrode (not shown) is formed on doped layer 105b.

  In this conventional AlGaInP light emitting diode, the Mg doped layer 105a functions as a diffusion suppressing layer that suppresses the diffusion of Zn in the Zn doped layer 105b, and the Zn in the Zn doped layer 105b diffuses into the active layer 102. By suppressing it, it is said that deterioration of the light emission characteristics and deterioration of the lifetime of the element can be prevented.

JP 2006-19695 A

  However, according to the knowledge of the present inventors, when the p-type contact layer 105 is composed of two layers of the Mg-doped layer 105a and the Zn-doped layer 105b as described above, mutual diffusion of Mg and Zn occurs. As a result, the contact resistance of the p-side electrode increases due to a decrease in the impurity concentration of the p-type contact layer 105 in the vicinity of the interface with the p-side electrode, and the luminous efficiency decreases due to the inclusion of Zn in the active layer 102. There was a problem of doing.

FIG. 25 shows the results of secondary ion mass spectrometry (SIMS) of an evaluation sample having a layer structure similar to that of the p-type contact layer of this conventional AlGaInP light emitting diode. As an evaluation sample, an Mg doped layer made of GaP doped with Mg as a p-type impurity and a GaP doped with Zn as a p-type impurity by a metal organic chemical vapor deposition (MOCVD) method on a GaAs substrate. An epitaxial substrate on which a Zn-doped layer made of the material was sequentially grown was used. The growth conditions were set so that the Mg concentration in the Mg doped layer was 1 × 10 ¹⁹ cm ⁻³ and the Zn concentration in the Zn doped layer was 2 × 10 ¹⁹ cm ⁻³ .

As shown in FIG. 25, mutual diffusion of Mg and Zn occurs between the Mg doped layer and the Zn doped layer, Zn in the Zn doped layer becomes Mg doped layer, and Mg in the Mg doped layer becomes Zn doped layer. You can see that it is mixed. The concentration of Zn diffused in the Mg doped layer reaches about (1-7) × 10 ¹⁶ cm ^{−3 in} the vicinity of the interface between the Mg doped layer and the GaAs substrate.

  When such mutual diffusion of Mg and Zn occurs, the following problems occur in the conventional AlGaInP light emitting diode. That is, in FIG. 24, reference numeral 106 indicates the distribution of Zn diffused toward the Mg doped layer 105a, and reference numeral 107 indicates the distribution of Mg diffused toward the Zn doped layer 105b. As shown in FIG. 24, in this AlGaInP-based light emitting diode, due to mutual diffusion of Mg and Zn, the Zn-doped layer 105b corresponding to the junction layer with the p-side electrode in the p-type contact layer 105 has a high concentration. Doped Zn diffuses to the Mg doped layer 105a side and hence to the active layer 102 side. For this reason, the impurity concentration in the vicinity of the interface with the p-side electrode in the p-type contact layer 105 decreases, and there arises a problem that the contact resistance of the p-side electrode increases. Further, as in the past, when diffused Zn is mixed into the active layer 102, a non-light emitting center is generated in the active layer 102, resulting in a problem that the light emission efficiency is lowered.

Therefore, the problem to be solved by the present invention is that when the p-type contact layer is composed of two or more layers laminated with each other and doped with two or more different p-type impurities, these p-type contact layers are formed. By preventing interdiffusion of type impurities, it is possible to suppress an increase in contact resistance of the p-side electrode, and more effectively prevent a decrease in light emission efficiency, resulting in good light emission characteristics and electrical characteristics. And it is providing a highly reliable semiconductor light-emitting device and its manufacturing method.
Another problem to be solved by the present invention is to provide a high-performance light source cell unit, a backlight, a display, and an electronic device using the semiconductor light emitting element as described above.

In order to solve the above problem, the first invention is:
Semiconductor light-emitting device having a structure in which an active layer is sandwiched between an n-type cladding layer and a p-type cladding layer, and a p-type contact layer in contact with the p-side electrode between the p-type cladding layer and the p-side electrode In the element
The p-type contact layer is composed of two or more layers laminated with each other and doped with two or more kinds of different p-type impurities, and at least one of the interfaces of these layers is p It is characterized by being doped with n-type impurities that prevent diffusion of type impurities.

  This semiconductor light emitting element is typically made of a III-V group compound semiconductor such as an AlGaInP semiconductor or AlGaAs semiconductor, but is not limited thereto. The semiconductor light emitting element is a light emitting diode or a semiconductor laser. The p-type contact layer is typically made of GaP or GaAs, but is not limited to this, and other semiconductors may be used as long as ohmic contact with the p-side electrode is possible. The two or more layers constituting the p-type contact layer are typically composed of the same semiconductor, but may be composed of different semiconductors.

  The n-type impurity doped in at least one of the interfaces included in the p-type contact layer is a region of 50 nm or more above and below the interface from the viewpoint of effectively preventing the p-type impurities from diffusing each other. It is preferable to be doped. Here, the region of 50 nm or more above and below the interface refers to a region having a thickness of 50 nm or more from the interface among layers adjacent to the lower layer side of the interface and an interface among layers adjacent to the upper layer side of the interface. Is a region combined with a region having a thickness of 50 nm or more. Therefore, the total thickness of the region doped with n-type impurities is preferably 100 nm or more. This n-type impurity can be doped up to the entire p-type contact layer. However, if the region doped with the n-type impurity in the p-type contact layer is too thick, an increase in the series resistance of the p-type contact layer becomes a problem. It is preferable that the region is doped.

The concentration of the n-type impurity in the region of the p-type contact layer doped with the n-type impurity is preferably higher than 2 × 10 ¹⁷ cm ⁻³ from the viewpoint of effectively preventing the diffusion of the p-type impurity. To be elected. However, from the viewpoint of not hindering carrier injection, it is desirable that the conductivity type of the region doped with the n-type impurity is p-type. Specifically, when the concentration of the p-type impurity differs between the layers adjacent to the upper and lower sides of the interface doped with the n-type impurity, the concentration of the n-type impurity is the p-type of the layer having the lower p-type impurity concentration. It is selected to be lower than the impurity concentration.

Specifically, the p-type impurity of the p-type contact layer is, for example, at least one selected from the group consisting of Mg, Be, and Zn. Specifically, the n-type impurity doped in the p-type contact layer in order to prevent mutual diffusion of the p-type impurity is at least one selected from the group consisting of Si, Se, and S, for example. When Mg, Be, and Zn are used as the p-type impurity, typically, Mg and / or Be as a p-type impurity, which is less prone to diffusion, is formed in a layer near the active layer of the p-type contact layer. In the p-type contact layer, the layer on the p-side electrode side, particularly the layer in contact with the p-side electrode, is doped with Zn that can be doped at high concentration as a p-type impurity. In this case, typically, when the Mg and / or Be is the concentration of the p-type impurity layer is doped with N _a1, the concentration of the p-type impurity layers Zn is doped to a N _a2, A p-type impurity is doped so as to satisfy the relationship of N _a1 <N _a2 . In this case, the concentration of the n-type impurity doped in the interface included in the p-type contact layer is selected to be higher than 2 × 10 ¹⁷ cm ⁻³ from the viewpoint of effectively preventing the mutual diffusion of the p-type impurity, In addition, it is selected to be lower than the concentration _Na1 of the p-type impurity in the layer doped with Mg and / or Be having a low impurity concentration. Therefore, the n-type impurity is doped so as to satisfy the relationship of 2 × 10 ¹⁷ cm ⁻³ <N _d <N _a1 .

In a typical example, the p-type contact layer is composed of two layers of a layer doped with Mg and / or Be as a p-type impurity and a layer doped with Zn as a p-type impurity in order from the active layer side. A region of 50 nm or more above and below the interface between these two layers is doped with an n-type impurity.
In another typical example, the p-type contact layer has a region doped with Mg and / or Be and Zn as p-type impurities in the vicinity of at least one interface. An n-type impurity is doped in a region of 50 nm or more above and below.
In yet another typical example, the p-type contact layer has an undoped p-type region (a region made of a semiconductor layer grown under the condition of being undoped and p-type). An n-type impurity is doped in a region having a thickness of more than 100 nm and a region of 50 nm or more above and below. In this case, preferably, when the carrier concentration (hole concentration) of the undoped p-type region is N _a3 and the concentration of the n-type impurity is N _d , n is satisfied so as to satisfy the relationship of N _d <N _a3. A type impurity is doped.

The second invention is
Semiconductor light-emitting device having a structure in which an active layer is sandwiched between an n-type cladding layer and a p-type cladding layer, and a p-type contact layer in contact with the p-side electrode between the p-type cladding layer and the p-side electrode In the manufacturing method of the element,
The p-type contact layer is formed by two or more layers laminated with each other and doped with two or more kinds of different p-type impurities, and at least one of the interfaces of these layers, The present invention is characterized in that an n-type impurity for preventing the diffusion of the p-type impurity is doped.
In the second invention, what has been described in relation to the first invention is established.

The third invention is
In a light source cell unit in which a plurality of cells each including at least one of a red light emitting semiconductor light emitting element, a green light emitting semiconductor light emitting element, and a blue light emitting semiconductor light emitting element are arranged on a printed wiring board,
At least one of a red light emitting semiconductor light emitting element, a green light emitting semiconductor light emitting element, and a blue light emitting semiconductor light emitting element,
Semiconductor light-emitting device having a structure in which an active layer is sandwiched between an n-type cladding layer and a p-type cladding layer, and a p-type contact layer in contact with the p-side electrode between the p-type cladding layer and the p-side electrode In the element
The p-type contact layer is composed of two or more layers laminated with each other and doped with two or more kinds of different p-type impurities, and at least one of the interfaces of these layers is p It is characterized by being doped with n-type impurities that prevent diffusion of type impurities.

The fourth invention is:
In a backlight in which a plurality of red light emitting semiconductor light emitting elements, green light emitting semiconductor light emitting elements and blue light emitting semiconductor light emitting elements are arranged,
At least one of a red light emitting semiconductor light emitting element, a green light emitting semiconductor light emitting element, and a blue light emitting semiconductor light emitting element,
Semiconductor light-emitting device having a structure in which an active layer is sandwiched between an n-type cladding layer and a p-type cladding layer, and a p-type contact layer in contact with the p-side electrode between the p-type cladding layer and the p-side electrode In the element
The p-type contact layer is composed of two or more layers laminated with each other and doped with two or more kinds of different p-type impurities, and at least one of the interfaces of these layers is p It is characterized by being doped with n-type impurities that prevent diffusion of type impurities.

The fifth invention is:
In a display in which a plurality of red light emitting semiconductor light emitting elements, green light emitting semiconductor light emitting elements and blue light emitting semiconductor light emitting elements are arranged,
At least one of a red light emitting semiconductor light emitting element, a green light emitting semiconductor light emitting element, and a blue light emitting semiconductor light emitting element,
Semiconductor light-emitting device having a structure in which an active layer is sandwiched between an n-type cladding layer and a p-type cladding layer, and a p-type contact layer in contact with the p-side electrode between the p-type cladding layer and the p-side electrode In the element
The p-type contact layer is composed of two or more layers laminated with each other and doped with two or more kinds of different p-type impurities, and at least one of the interfaces of these layers is p It is characterized by being doped with n-type impurities that prevent diffusion of type impurities.

  In the third to fifth inventions, as the green light emitting semiconductor light emitting device and the blue light emitting semiconductor light emitting device, for example, a device using a nitride III-V compound semiconductor such as a GaN semiconductor can be used. As a semiconductor light emitting element emitting red light, for example, a device using an AlGaInP-based semiconductor can be used, and a device using a GaN-based semiconductor can also be used. Typically, a semiconductor light emitting device having a p-type contact layer as described above is used as a red light emitting semiconductor light emitting device.

As the semiconductor light emitting device using the nitride III-V group compound semiconductor described above, a conventionally known device can be used, but a device manufactured by the following method can be preferably used. .
That is, the manufacturing method of this semiconductor light emitting device is as follows:
A substrate having a plurality of convex portions on one main surface, wherein the convex portions are made of a material different from that of the substrate, and the concave portion of the substrate has a triangular cross-sectional shape with the bottom surface as a base. A step of growing a first nitride-based III-V compound semiconductor layer via,
Laterally growing a second nitride III-V compound semiconductor layer on the substrate from the first nitride III-V compound semiconductor layer;
On the second nitride III-V compound semiconductor layer, the third conductivity type third nitride III-V compound semiconductor layer, the active layer, and the second conductivity type fourth nitride. And a step of sequentially growing a group III-V compound semiconductor layer.

The conductivity type of the first nitride III-V compound semiconductor layer and the second nitride III-V compound semiconductor layer may be any of p-type, n-type, and i-type, The conductivity types may or may not be the same conductivity type, and the conductivity types may be within the first nitride III-V compound semiconductor layer or the second nitride III-V compound semiconductor layer. Two or more different parts may be mixed.
Typically, when the first nitride-based III-V compound semiconductor layer is grown, dislocations are generated in a direction perpendicular to the principal surface of the substrate from the interface with the bottom surface of the recess of the substrate. When the dislocation reaches the slope of the first nitride-based III-V compound semiconductor layer in the state of having a triangular cross-sectional shape or the vicinity thereof, a triangular portion is formed in a direction parallel to the one principal surface. Bend away from the camera. Here, the triangular cross-sectional shape or the triangular shape in the triangular portion means not only an accurate triangle, but also includes what can be regarded as an approximate triangle, such as a rounded top (for example) ( The same applies below). Preferably, in the initial stage of growth of the first nitride-based III-V group compound semiconductor layer, a plurality of micronuclei are formed on the bottom surface of the concave portion of the substrate, and these micronuclei grow and coalesce. Thus, dislocations generated from the interface with the bottom surface of the concave portion of the substrate in a direction perpendicular to one main surface of the substrate are repeatedly bent in a direction parallel to the one main surface. By doing so, dislocations that escape to the top during the growth of the first nitride-based III-V compound semiconductor layer can be reduced.

Typically, convex portions and concave portions are alternately and periodically formed on one main surface of the substrate. In this case, the period of a convex part and a recessed part is 3-5 micrometers suitably. Further, the ratio of the length of the bottom of the convex portion to the length of the bottom of the concave portion is preferably 0.5 to 3, and most preferably around 0.5. The height of the convex portion viewed from one main surface of the substrate is preferably 0.3 μm or more, more preferably 1 μm or more. The convex portion preferably has a side surface inclined with respect to one main surface of the substrate (for example, a side surface in contact with one main surface of the substrate), and an angle between the side surface and one main surface of the substrate is θ. Then, from the viewpoint of improving the light extraction efficiency, for example, preferably 100 ° <θ <160 °, more preferably 132 ° <θ <139 ° or 147 ° <θ <154 °, which is most preferable. Is 135 ° or 152 °. The cross-sectional shape of the convex portion may be various shapes, and the side surface may be a curved surface as well as a flat surface. For example, an n-gon (where n is an integer of 3 or more), specifically Triangle, quadrangle, pentagon, hexagon, etc. The cross-sectional shape of the recess may be various shapes, for example, an n-gon (where n is an integer of 3 or more), specifically, a triangle, a quadrangle, a pentagon, a hexagon, and the like. From the viewpoint of improving the light extraction efficiency, preferably, the cross-sectional shape of the recess is an inverted trapezoid. In this case, from the viewpoint of minimizing the dislocation density of the second nitride-based III-V compound semiconductor layer, it is preferable that the depth of the concave portion (same as the height of the convex portion) be d and the width of the bottom surface of the concave portion. when a you a W _g, the angle between the inclined surface and the main surface of the substrate of the first nitride III-V compound semiconductor layer in a state where a triangular cross-sectional shape is alpha, the 2d ≧ W _g tan [alpha D, W _g , and α are determined so as to hold. Since α is normally constant, d and W _g are determined so that this equation is satisfied. If d is too large, the source gas is not sufficiently supplied to the inside of the recess, which hinders the growth of the first nitride-based III-V compound semiconductor layer from the bottom of the recess, and conversely if d is too small. The first nitride-based III-V compound semiconductor layer grows not only on the concave portion of the substrate but also on the convex portions on both sides thereof. From the viewpoint of preventing these, generally, 0.5 μm <d It is selected within the range of <5 μm, and typically selected within the range of 1.0 ± 0.2 μm. W _g is generally 0.5 to 5 μm, and is typically selected within a range of 2 ± 0.5 μm. Further, the width W _t of the top surface of the convex portion is 0 when the cross-sectional shape of the convex portion is triangular, but when the cross-sectional shape of the convex portion is trapezoidal, this convex portion is the second nitride system. Since it is a region used for the lateral growth of the III-V compound semiconductor layer, the longer the area, the larger the area of the portion having a lower dislocation density. When the cross-sectional shape of the convex portion is trapezoidal, W _t is generally 1 to 1000 μm.

  For example, the convex portion or the concave portion may extend in a stripe shape in one direction on the substrate, or may extend in a stripe shape in at least a first direction and a second direction intersecting each other. Accordingly, the convex portion may be an n-gon (where n is an integer of 3 or more), specifically, a triangle, a quadrangle, a pentagon, a hexagon, or the like. In a preferred example, the convex portions have a hexagonal planar shape, the convex portions are two-dimensionally arranged in a honeycomb shape, and concave portions are formed so as to surround the convex portions. By doing so, light emitted from the active layer can be efficiently extracted in all directions of 360 °. When the concave portion of the substrate has a stripe shape, the concave portion extends, for example, in the <1-100> direction of the first nitride-based III-V compound semiconductor layer, or a sapphire substrate is used as the substrate, for example. In some cases, the sapphire substrate may extend in the <11-20> direction. The convex portion is, for example, an n-pyramid (where n is an integer of 3 or more), specifically, a triangular pyramid, a quadrangular pyramid, a pentagonal pyramid, a hexagonal pyramid, or the like.

The material of the convex portion may be various, and may or may not be conductive. For example, a dielectric such as an oxide, nitride, or carbide, or a conductor such as a metal or alloy (including a transparent conductor) ) Etc. As the oxide, for example, silicon oxide (SiO _x ), titanium oxide (TiO _x ), or the like can be used, and two or more of these can be mixed or used in the form of a laminated film. As the nitride, for example, silicon nitride (SiN _x ), TiN, SiON, CrN or the like can be used, and two or more of these can be mixed or used in the form of a laminated film. As the carbide, SiC, HfC, ZrC, or the like can be used, and two or more of these can be mixed or used in the form of a laminated film. As the metal or alloy, B, Al, Ga, In, W, Ni, AgNi, AgPd, AuNi, or the like can be used, and two or more of these can be mixed or used in the form of a laminated film. . As a transparent conductor, ITO (indium-tin composite oxide), IZO (indium-zinc composite oxide), FTO (fluorine-doped tin oxide), etc. can be used, and these two or more types are mixed, Alternatively, it can be used in the form of a laminated film. Further, two or more of the various materials described above can be mixed or used in the form of a laminated film. A convex portion may be formed of metal or the like, and nitride, oxide, or carbide may be formed by nitriding, oxidizing, or carbonizing at least the surface of the convex portion.

The refractive index of the convex portion is determined by design as necessary, but in general, the refractive index is different from the refractive index of the substrate and the refractive index of the nitride III-V compound semiconductor layer grown on the substrate. Typically, it is selected to be equal to or lower than the refractive index of the substrate.
In the third nitride-based III-V compound semiconductor layer, an electrode on the first conductivity type side is formed in a state of being electrically connected thereto. Similarly, an electrode on the second conductivity type side is formed on the fourth nitride-based III-V compound semiconductor layer in a state of being electrically connected thereto.

Various substrates can be used as the substrate. Specifically, the substrate made of a material different from the nitride III-V compound semiconductor includes, for example, sapphire (including a c-plane, a-plane, r-plane, etc., and a plane off from these planes). ), SiC (including 6H, 4H, 3C), Si, CrN (for example, CrN (111)), etc., and preferably a hexagonal substrate or a cubic substrate made of these materials. More preferably, a hexagonal crystal substrate is used. As the substrate, a substrate made of a nitride III-V group compound semiconductor (GaN, AlGaInN, AlN, GaInN, etc.) may be used. Alternatively, a nitride III-V compound semiconductor layer is grown as a substrate on a substrate made of a material different from the nitride III-V compound semiconductor, and the nitride III-V compound semiconductor layer is formed on the nitride III-V compound semiconductor layer. What formed the convex part may be sufficient.
For example, when a substrate such as a nitride III-V group compound semiconductor layer grown on a substrate is used as the substrate, the material of the convex portion is different from that of the layer immediately below the convex portion. It is done.
The substrate may be removed as necessary.

The first to fourth nitride III-V compound semiconductor layer and the nitride constituting the active layer based III-V compound semiconductor layer, most _{commonly, Al X B y Ga 1-} xyz In z As _u N _1-uv P _v (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, 0 ≦ u ≦ 1, 0 ≦ v ≦ 1, 0 ≦ x + y + z <1, 0 ≦ u + v <consists 1), more _{specifically, Al X B y Ga 1-} xyz in z N ( However, 0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ z ≦ 1,0 ≦ x + y + z <1) Typically, it consists of Al _x Ga _{1 -xz} In _z N (where 0 ≦ x ≦ 1, 0 ≦ z ≦ 1). Specific examples are GaN, InN, AlN, AlGaN, InGaN. And AlGaInN. Particularly first first nitride III-V compound semiconductor layer grown on the recessed portions of the substrate, _{preferably, GaN, In X Ga 1-} x N (0 <x <0.5), Al X A material consisting of Ga _1-x N (0 <x <0.5) and Al _x In _y Ga _1-xy N (0 <x <0.5, 0 <y <0.2) is used. The first conductivity type may be n-type or p-type, and the second conductivity type is p-type or n-type accordingly. In addition, as a so-called low-temperature buffer layer that is first grown on the substrate, a GaN buffer layer, an AlN buffer layer, an AlGaN buffer layer, etc. are generally used, and those doped with Cr or CrN buffer layers are used. Also good.
The thickness of the second nitride-based III-V compound semiconductor layer is selected as necessary, and is typically about several μm or less, but is thicker depending on the application, for example, about several tens to 300 μm. It may be.

As the semiconductor light emitting device using the nitride III-V group compound semiconductor, the following semiconductor light emitting device substantially the same as that manufactured by the above manufacturing method can be used.
That is, this semiconductor light emitting device
A substrate having a plurality of protrusions on one principal surface, the protrusions being made of a material different from the substrate;
A fifth nitride-based III-V compound semiconductor layer grown on the substrate without forming a void in the recess of the substrate;
The third nitride III-V compound semiconductor layer of the first conductivity type on the fifth nitride III-V compound semiconductor layer, the active layer, and the fourth nitride of the second conductivity type A system III-V compound semiconductor layer,
In the fifth nitride-based III-V compound semiconductor layer, a dislocation generated in a direction perpendicular to the one main surface from the interface with the bottom surface of the recess is a triangular portion having the bottom surface of the recess as a base. The semiconductor light emitting device is characterized in that it is bent in a direction parallel to the one principal surface.

Here, in this semiconductor light emitting device, the fifth nitride-based III-V compound semiconductor layer includes the first nitride-based III-V compound semiconductor layer and the second nitride-based compound semiconductor layer in the method for manufacturing a semiconductor light-emitting device described above. This corresponds to a nitride III-V compound semiconductor layer.
In this semiconductor light-emitting device, what has been described in relation to the above-described method for manufacturing a semiconductor light-emitting device is valid as long as it does not contradict its properties.

The sixth invention is:
In an electronic device having one or more semiconductor light emitting elements,
At least one of the semiconductor light emitting elements is
Semiconductor light-emitting device having a structure in which an active layer is sandwiched between an n-type cladding layer and a p-type cladding layer, and a p-type contact layer in contact with the p-side electrode between the p-type cladding layer and the p-side electrode In the element
The p-type contact layer is composed of two or more layers laminated with each other and doped with two or more kinds of different p-type impurities, and at least one of the interfaces of these layers is p It is characterized by being doped with n-type impurities that prevent diffusion of type impurities.

  In the sixth invention, the electronic device includes a backlight (such as a backlight of a liquid crystal display), an illumination device, a display, a projector using a semiconductor light emitting element as a light source, a rear projection television, a grating light valve (GLV), and the like. In general, it may be basically any type as long as it has at least one light emitting diode for display, illumination, optical communication, optical transmission and other purposes. In addition to the above, there are mobile phones, mobile devices, robots, personal computers, in-vehicle devices, various household electrical products, optical communication devices, optical transmission devices, etc. It is.

  In the present invention configured as described above, the p-type contact layer is composed of two or more layers that are laminated with each other and are doped with two or more different p-type impurities, and these layers At least one of the interfaces is doped with an n-type impurity that prevents the diffusion of p-type impurities, thereby effectively preventing the p-type impurities doped in the p-type contact layer from diffusing each other. can do.

  According to the present invention, it is possible to effectively prevent the p-type impurities doped in the p-type contact layer from diffusing each other, so that the impurities in the p-type contact layer in the vicinity of the interface with the p-side electrode. The concentration can be prevented from decreasing, and the increase in contact resistance of the p-side electrode can be suppressed, and p-type impurities are mixed into the active layer during the manufacturing process of the semiconductor light emitting device or during energization after completion. Can be effectively prevented, and non-radiative centers can be prevented from occurring in the active layer, resulting in a decrease in luminous efficiency. Therefore, it is possible to obtain a semiconductor light emitting device having both excellent light emission characteristics and electrical characteristics and high reliability. And using this excellent semiconductor light emitting element, a high-performance light source cell unit, backlight, display, various electronic devices, and the like can be realized.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings of the embodiments, the same or corresponding parts are denoted by the same reference numerals.
FIG. 1 shows an AlGaInP light emitting diode according to a first embodiment of the present invention. FIG. 2 shows an impurity concentration profile of the AlGaInP light emitting diode. This AlGaInP light emitting diode is a red light emitting diode.

  As shown in FIGS. 1 and 2, in this AlGaInP-based light emitting diode, an AlGaInP doped with, for example, Si as an n-type impurity is formed on one main surface of an n-type semiconductor substrate 1 such as an n-type GaAs substrate. N-type cladding layer 2, for example, an MQW-structured active layer 3 having an undoped GaInP layer as a quantum well layer and an undoped AlGaInP layer as a barrier layer, for example, a p-type cladding layer made of AlGaInP doped with Mg as a p-type impurity 4. For example, a p-type intermediate layer 5 and a p-type contact layer 6 made of GaInP doped with Mg as a p-type impurity are sequentially stacked. An n-type current diffusion layer made of, for example, n-type AlGaInP may be provided between the n-type semiconductor substrate 1 and the n-type cladding layer 2 as necessary.

  In order from the active layer 3 side, the p-type contact layer 6 includes, for example, an Mg-doped layer 6a made of GaP doped with Mg as a p-type impurity, and a Zn-doped layer 6b made of GaP doped with Zn as a p-type impurity, for example. It consists of two layers. In the p-type contact layer 6, n-type impurities for preventing diffusion of p-type impurities are specifically formed in a region of 50 nm or more above and below the interface between the Mg-doped layer 6 a and the Zn-doped layer 6 b. Si is doped. Reference numeral 7 denotes a region doped with Si in the p-type contact layer 6, that is, an n-type impurity doped region. The n-type impurity doped region 7 is formed in the p-type contact layer 6 so as to straddle the interface between the Mg-doped layer 6a and the Zn-doped layer 6b.

A p-side electrode 8 such as a Ti / Pt / Au electrode is in contact with a portion of the p-type contact layer 6 excluding the light extraction portion on the Zn-doped layer 6b. A number of recesses (recesses) are formed on the surface of the p-type contact layer 6 in the light extraction portion, and light from the active layer 3 can be efficiently extracted from the upper surface. May not necessarily be formed. In the p-type contact layer 6, the Zn concentration of the Zn doped layer 6 b in contact with the p-side electrode 8 is selected to be higher than the Mg concentration of the Mg doped layer 6 a on the active layer 3 side. That is, when the concentration of Mg in the Mg-doped layers 6a and the concentration of Zn in the N _a1, Zn-doped layer 6b and N _a2, N _a1 <Mg and Zn so as to satisfy the relationship of N _a2 is doped, respectively. Specifically, the Mg concentration N _a1 of the Mg doped layer 6a is selected to be, for example, 1 × 10 ¹⁸ cm ⁻³ , and the Zn concentration N _a2 of the Zn doped layer 6b is, for example, 2 × 10 ¹⁹ cm ⁻³ . To be elected. In this case, p-type impurities are respectively doped so that the impurity concentration of the p-type semiconductor layer of the semiconductor layers constituting the light-emitting diode structure gradually increases from the active layer 3 toward the p-side electrode 8. Thus, the contact resistance of the p-side electrode 8 is reduced by providing the Zn-doped layer 6b doped with Zn at a high concentration at the portion where the p-side electrode 8 contacts.

The Si concentration N _{d in} the n-type impurity doped region 7 of the p-type contact layer 6 can effectively prevent mutual diffusion of Mg in the Mg-doped layer 6a and Zn in the Zn-doped layer 6b. For example, it is selected to be higher than 2 × 10 ¹⁷ cm ⁻³ , but the upper limit is selected so that the conductivity type of the n-type impurity doped region 7 is p-type from the viewpoint of preventing troubles in carrier injection. . Here, since the concentration N _a1 of Mg Mg-doped layer 6a is lower than the concentration N _a2 of Zn and Zn-doped layer 6b, the concentration N _d of Si n-type impurity doped region 7, the concentration of Mg in the Mg-doped layer 6a It is selected even lower than _Na1 . That is, it is selected so as to satisfy the relationship of 2 × 10 ¹⁷ cm ⁻³ <N _d <N _a1 <N _a2 . Specifically, the Si concentration N _d of the n-type impurity doped region 7 is selected to be (3-5) × 10 ¹⁷ cm ⁻³ , for example. This n-type impurity doped region 7 functions as a diffusion preventing region for preventing mutual diffusion of Mg and Zn.

The thickness d ₁ of the portion of the n-type impurity doped region 7 in the Mg doped layer 6a and the thickness d ₂ of the portion of the n-type impurity doped region 7 in the Zn doped layer 6b are Mg and Zn Each of them is selected to be 50 nm or more so as to effectively prevent mutual diffusion. Therefore, the thickness (d ₁ + d ₂ ) of the entire n-type impurity doped region 7 in this case is selected to be 100 nm or more. Here, Si as an n-type impurity for preventing diffusion of p-type impurities can be doped at the maximum in the entire p-type contact layer 6, but a region doped with Si, that is, an n-type impurity. If the doped region 7 is too thick, the series resistance of the p-type contact layer 6 increases and the operating voltage increases, so that Si is in a region within several hundreds of nanometers above and below the interface between the Mg doped layer 6a and the Zn doped layer 6b. It is desirable to be doped. The thickness d ₁ of the portion in the Mg doped layer 6a in the n-type impurity doped region 7 and the thickness d ₂ of the portion in the Zn doped layer 6b are typically selected to be approximately the same. The thickness of these parts may be different from each other.
An n-side electrode 9 such as an AuGe / Ni / Au electrode is provided on the back surface of the n-type semiconductor substrate 1.

As an example of the thickness of each semiconductor layer constituting the light emitting diode structure, the thickness of the n-type cladding layer 2 is 1 μm, the thickness of the active layer 3 is 0.5 μm, and the thickness of the p-type cladding layer 4 is 1 μm. The p-type intermediate layer 5 has a thickness of 0.2 μm, and the p-type contact layer 6 has a thickness of 0.6 μm. When an n-type current diffusion layer is provided between the n-type cladding layer 2 and the n-type semiconductor substrate 1, the thickness of the n-type current diffusion layer is, for example, 0.3 μm. Of the p-type contact layer 6, the Mg doped layer 6a has a thickness of 0.4 μm, and the Zn doped layer 6b has a thickness of 0.2 μm. Further, the thickness d ₁ of the portion in the Mg doped layer 6a in the n-type impurity doped region 7 is 50 nm, the thickness d ₂ in the portion in the Zn doped layer 6b is 50 nm, and the entire n-type impurity doped region 7 The thickness (d ₁ + d ₂ ) is 100 nm.

Next, a method for manufacturing the AlGaInP light emitting diode will be described.
In order to manufacture this AlGaInP light emitting diode, for example, an n-type made of AlGaInP doped with Si as an n-type impurity is formed on one main surface of an n-type semiconductor substrate 1 such as an n-type GaAs substrate by MOCVD. Cladding layer 2, MQW structure active layer 3 using an undoped GaInP layer as a quantum well layer, an undoped AlGaInP layer as a barrier layer, a p-type cladding layer 4 made of AlGaInP doped with Mg as a p-type impurity, and a p-type impurity The p-type intermediate layer 5 made of GaInP doped with Mg is epitaxially grown sequentially.

Subsequently, the p-type contact layer 6 is grown on the p-type intermediate layer 5, and the growth of the p-type contact layer 6 is performed in stages as follows.
That is, first, a Ga raw material as a group III element, a P raw material as a group V element, and an Mg raw material as a p-type impurity were supplied into the reaction chamber of the MOCVD apparatus, and Mg was doped as a p-type impurity. GaP is grown by a predetermined thickness, and the lower layer side portion of the Mg doped layer 6a is grown. Next, Si raw material is further supplied as n-type impurities, and GaP doped with Mg as p-type impurities and Si simultaneously as n-type impurities is grown, and the remaining portion of the Mg-doped layer 6a is grown. . At this stage, a portion having a thickness d ₁ in the Mg-doped layer 6a in the n-type impurity doped region 7 is formed. Next, the supply of the Mg raw material is stopped, and the supply of the Zn raw material as the p-type impurity is started, and GaP simultaneously doped with Zn as the p-type impurity and Si as the n-type impurity has a predetermined thickness. The portion on the lower layer side of the Zn-doped layer 6b is grown. At this stage, a portion having a thickness d ₂ in the Zn doped layer 6b in the n-type impurity doped region 7 is formed. Next, the supply of Si raw material is stopped, GaP doped with Zn as a p-type impurity is grown, and the remaining portion of the Zn-doped layer 6b is grown. During growth of this p-type contact layer 6, the concentration N _d of Si in Zn concentration N _a2 and n-type impurity doped region 7 of the Mg concentration N _a1, Zn-doped layer 6b of the Mg-doped layer 6a is, 2 × 10 ¹⁷ Impurities are doped so as to satisfy the relationship cm ⁻³ <N _d <N _a1 <N _a2 . In this manner, the Mg doped layer 6a and the Zn doped layer 6b are sequentially formed from the active layer 3 side, and Si is doped in a predetermined region in the vicinity of the interface between the Mg doped layer 6a and the Zn doped layer 6b. Then, the p-type contact layer 6 having the n-type impurity doped region 7 is formed.

  Next, the n-type semiconductor substrate 1 on which the AlGaInP-based semiconductor layer is grown as described above is taken out from the MOCVD apparatus. Next, for example, a Ti film, a Pt film, and an Au film are sequentially formed on the entire surface of the p-type contact layer 6 by, for example, vacuum deposition or sputtering, and then these films are patterned into a predetermined shape by photolithography. Thus, the p-side electrode 8 made of a Ti / Pt / Au electrode is formed on a predetermined portion on the p-type contact layer 6.

Next, the back surface of the n-type semiconductor substrate 1 on which the AlGaInP-based semiconductor layer has been grown is polished so that its thickness becomes, for example, about 200 μm. Next, for example, an AuGe film, a Ni film, and an Au film are sequentially formed on the polished surface of the n-type semiconductor substrate 1 by, for example, a vacuum evaporation method or a sputtering method, and an n-side electrode 9 made of an AuGe / Ni / Au electrode is formed. After that, the n-side electrode 9 is brought into ohmic contact with the n-type semiconductor substrate 1 by performing an annealing process.
Next, scribing of the n-type semiconductor substrate 1 on which the AlGaInP-based semiconductor layer has been grown is performed to form a bar. Thereafter, the bar is scribed to form a chip.
Thus, the target AlGaInP light emitting diode is manufactured.

  According to the AlGaInP-based light emitting diode according to the first embodiment configured as described above, the following advantages can be obtained. That is, the p-type contact layer 6 is composed of two layers of an Mg doped layer 6a doped with Mg as a p-type impurity and a Zn doped layer 6b doped with Zn as a p-type impurity in order from the active layer 3. In addition, the n-type impurity doped region 7 doped with Si for preventing diffusion of Mg and Zn is formed in a region of 50 nm or more above and below the interface between the Mg doped layer 6a and the Zn doped layer 6b. It is possible to effectively prevent Mg in the Mg doped layer 6a and Zn in the Zn doped layer 6b from diffusing each other. Thereby, it is possible to prevent the impurity concentration of the p-type contact layer 6 in the vicinity of the interface with the p-side electrode 8 from being lowered, to suppress an increase in the contact resistance of the p-side electrode 8, and to the light emitting diode. It is possible to more effectively prevent Zn from diffusing into the active layer 3 during the manufacturing process or during energization after completion, and non-radiative centers are generated in the active layer 3 to reduce luminous efficiency. Can be prevented. Therefore, it is possible to obtain an excellent AlGaInP-based light-emitting diode having both excellent light emission characteristics and electrical characteristics and high reliability.

Next explained is the second embodiment of the invention. FIG. 3 shows an impurity concentration profile of the AlGaInP light emitting diode according to the second embodiment. This AlGaInP light emitting diode is a red light emitting diode.
As shown in FIG. 3, in this AlGaInP-based light-emitting diode, a region where both Mg and Zn are doped in the vicinity of the interface between the Mg-doped layer 6a and the Zn-doped layer 6b of the p-type contact layer 6, ie, over The n-type impurity doped region 7 is formed by doping the Si region preventing diffusion of Mg and Zn into the overlap region 6c and a region of 50 nm or more above and below the overlap region 6c. .

That is, the p-type contact layer 6 is focused on the doped p-type impurity, and sequentially from the active layer 3 side, Mg doped layer 6a made of GaP doped with Mg as the p-type impurity, and Mg as the p-type impurity. And a layer corresponding to the overlap region 6c made of GaP doped with both Zn and Zn, and a Zn-doped layer 6b made of GaP doped with Zn as a p-type impurity. The thickness d ₃ of the overlap region 6c is 0 <d ₃ ≦ 100 nm. Further, a portion of thickness d ₃ corresponding to the overlap region 6c, a portion of thickness d ₁ adjacent to the overlap region 6c in the Mg doped layer 6a, and an overlap region 6c in the Zn doped layer 6b. Si is doped in the region combined with the portion of the thickness d ₂ adjacent to the n-type, whereby the overlap region 6c and the region above 50 nm above and below the overlap region 6c are n-type having a thickness greater than 100 nm. An impurity doped region 7 is formed.

Here, the concentration of Mg in the overlap region 6c is, for example, be chosen equal to the concentration N _a1 of Mg Mg doped region 6a, but is not limited thereto. The concentration of Zn in the overlap region 6c is, for example, be chosen equal to the concentration N _a2 of Zn Zn doped region 6b, but is not limited thereto. The concentration N _d of Si concentration N _a2 and n-type impurity doped region 7 of Zn Mg concentration N _a1, Zn-doped layer 6b of the Mg-doped layer 6a, as in the first embodiment, 2 × 10 ^It is selected so as to satisfy the relationship of ¹⁷ cm ⁻³ <N _d <N _a1 <N _a2 . Specifically, the Si concentration N _d of the n-type impurity doped region 7 is selected, for example, the same as in the first embodiment.

The thickness d ₁ of the portion in the Mg doped layer 6a and the thickness d ₂ of the portion in the Zn doped layer 6b in the n-type impurity doped region 7 are from the viewpoint of effectively preventing mutual diffusion of p-type impurities. Are each selected to be 50 nm or more. Accordingly, the total thickness (d ₁ + d ₂ + d ₃ ) of the n-type impurity doped region 7 in this case is selected to be greater than 100 nm.
When a specific example of the thickness of each part of the p-type contact layer 6 is given, the thickness of the Mg doped layer 6a in the p-type contact layer 6 is 0.3 μm, and the thickness of the part corresponding to the overlap region 6c d ₃ is 0.1 μm, the thickness of the Zn doped layer 6b is 0.2 μm, and the total thickness of the p-type contact layer 6 is 0.6 μm. In addition, the thickness d ₁ of the Mg doped layer 6a in the n-type impurity doped region 7 is 50 nm, and the thickness d ₂ of the Zn doped layer 6b is 50 nm. Therefore, the n-type impurity doped region 7 has a total thickness (d ₁ + d ₂ + d ₃ ) of 200 nm.
Since the other than the above is the same as the AlGaInP light emitting diode according to the first embodiment, the description thereof is omitted.

Next, a method for manufacturing the AlGaInP light emitting diode will be described.
In this AlGaInP light emitting diode manufacturing method, the growth of the p-type contact layer 6 is performed in stages as follows.
That is, first, a Ga raw material as a group III element, a P raw material as a group V element, and an Mg raw material as a p-type impurity were supplied into the reaction chamber of the MOCVD apparatus, and Mg was doped as a p-type impurity. GaP is grown by a predetermined thickness, and the lower layer side portion of the Mg doped layer 6a is grown. Next, Si raw material is further supplied as n-type impurities, and GaP doped with Mg as p-type impurities and Si simultaneously as n-type impurities is grown, and the remaining portion of the Mg-doped layer 6a is grown. . At this stage, a portion having a thickness d ₁ in the Mg-doped layer 6a in the n-type impurity doped region 7 is formed. Next, the supply of Zn as a p-type impurity is started, and GaP doped simultaneously with Mg and Zn as p-type impurities and Si as an n-type impurity is grown in the overlap region 6c. Grow the corresponding part. Next, the supply of the Mg raw material is stopped, and GaP doped with Zn as the p-type impurity and Si as the n-type impurity is grown to a predetermined thickness, and the lower layer side portion of the Zn-doped layer 6b is grown. Grow. At this stage, a portion having a thickness d ₂ in the Zn doped layer 6b in the n-type impurity doped region 7 is formed. Next, the supply of Si raw material is stopped, GaP doped with Zn as a p-type impurity is grown, and the remaining portion of the Zn-doped layer 6b is grown. Further, when the p-type contact layer 6 is grown, impurities are doped so as to satisfy the relationship of 2 × 10 ¹⁷ cm ⁻³ <N _d <N _a1 <N _a2 . For example, the Mg concentration N _a1 of the Mg doped layer 6a is 1 × 10 ¹⁸ cm ⁻³ , the Zn concentration _Na 2 of the Zn doped layer 6b is 2 × 10 ¹⁹ cm ⁻³ , and the Mg concentration of the overlap region 6c is 1. × 10 ¹⁸ cm ^-3, the overlap region 6c of Zn concentrations 2 × 10 ¹⁹ cm ^-3, the impurity such that the concentration n _d of Si n-type impurity doped region 7 becomes 4 × 10 ¹⁷ cm ^-3 Dope. Thus, there is an overlap region 6c doped with both Mg and Zn between the Mg-doped layer 6a and the Zn-doped layer 6b, and the upper and lower sides of the overlap region 6c and the overlap region 6c. A p-type contact layer 6 having an n-type impurity doped region 7 doped with Si in a predetermined region is formed.
Since the other than the above is the same as the manufacturing method of the AlGaInP light emitting diode according to the first embodiment, the description thereof is omitted.
According to the second embodiment, the same advantages as those of the first embodiment can be obtained.

Next explained is the third embodiment of the invention. FIG. 4 shows an impurity concentration profile of the AlGaInP light emitting diode according to the third embodiment. This AlGaInP light emitting diode is a red light emitting diode.
As shown in FIG. 4, this AlGaInP light emitting diode has a region 6d made of undoped p-type GaP between the Mg-doped layer 6a and the Zn-doped 6b of the p-type contact layer 6, This undoped region 6d made of p-type GaP and the region composed of regions of 50 nm or more above and below this region 6d with a thickness larger than 100 nm are doped with Si for preventing the diffusion of Mg and Zn, and an n-type impurity doped region 7 is formed.

That is, the p-type contact layer 6 is focused on the doped p-type impurity, and from the active layer 3 side, the Mg-doped layer 6a made of GaP doped with Mg as the p-type impurity, and the undoped p-type impurity It consists of three layers: a layer corresponding to the region 6d made of GaP and a Zn-doped layer 6b made of GaP doped with Zn as a p-type impurity. The thickness d ₄ of the undoped region 6d made of p-type GaP is, for example, 0 <d ₄ <300 nm. Further, a portion corresponding to the undoped p-type GaP region 6d in the p-type contact layer 6 and a thickness d ₁ adjacent to the undoped p-type GaP region 6d in the Mg-doped layer 6a. parts and are undoped thickness d ₂ of the portion and Si in a region combining the doped adjacent to the region 6d made of p-type GaP of the Zn-doped layer 6b, from which the p-type undoped GaP An n-type impurity doped region 7 having a thickness greater than 100 nm is formed in the region 6d to be formed and a region 50 nm or more above and below the region 6d.

The Mg concentration N _d1 of the Mg doped layer 6a and the Zn concentration N _d2 of the Zn doped layer 6b are selected so as to satisfy the relationship of N _d1 <N _d2 , as in the first embodiment. The carrier concentration N _a3 region 6d made of p-type GaP undoped is suitably selected greater than the concentration N _d of Si n-type impurity doped region 7 formed in this region. That is, the relationship of N _d <N _a3 is satisfied. However, the Si concentration N _d of the n-type impurity doped region 7 is selected so as to satisfy the relationship of 2 × 10 ¹⁷ cm ⁻³ <N _d <N _a1 <N _a2 , as in the first embodiment. Specifically, the Mg concentration N _d1 of the Mg doped layer 6a is selected to be, for example, 1 × 10 ¹⁸ cm ⁻³ , and the Zn concentration N _d2 of the Zn doped layer 6b is, for example, 2 × 10 ¹⁹ cm ⁻³ . The carrier concentration N _a3 of the undoped p-type GaP region 6d is selected to be, for example, 1 × 10 ¹⁸ cm ^−3, and the Si concentration N _d of the n-type impurity doped region 7 is, for example, 4 × 10 ^It is chosen to be ¹⁷ cm ^-3 .

From the viewpoint of effectively preventing diffusion of p-type impurities, the thickness d ₁ of the portion in the Mg-doped layer 6a and the thickness d ₂ of the portion in the Zn-doped layer 6b of the n-type impurity doped region 7 are as follows. Each is selected to be 50 nm or more. Therefore, the total thickness (d ₁ + d ₂ + d ₄ ) of the n-type impurity doped region 7 in this case is selected to be greater than 100 nm.
To give a specific example of the thickness of each part of the p-type contact layer 6, the Mg-doped layer 6a of the p-type contact layer 6 has a thickness of 0.1 μm and is an undoped region made of p-type GaP. The thickness d ₄ of the portion corresponding to 6d is 0.3 μm, the thickness of the Zn doped layer 6b is 0.2 μm, and the total thickness of the p-type contact layer 6 is 0.6 μm. Further, the thickness d ₁ of the Mg doped layer 6a in the n-type impurity doped region 7 is 50 nm, the thickness d ₂ of the Zn doped layer 6b is 50 nm, and the n-type impurity doped region 7 as a whole. The thickness (d ₁ + d ₂ + d ₄ ) is 400 nm.
Since the other than the above is the same as the AlGaInP light emitting diode according to the first embodiment, the description thereof is omitted.

Next, a method for manufacturing the AlGaInP light emitting diode will be described.
In this AlGaInP light emitting diode manufacturing method, the growth of the p-type contact layer 6 is performed in stages as follows.
That is, first, a Ga raw material as a group III element, a P raw material as a group V element, and an Mg raw material as a p-type impurity were supplied into the reaction chamber of the MOCVD apparatus, and Mg was doped as a p-type impurity. GaP is grown by a predetermined thickness, and the lower layer side portion of the Mg doped layer 6a is grown. Next, Si raw material is further supplied as n-type impurities, and GaP doped with Mg as p-type impurities and Si simultaneously as n-type impurities is grown, and the remaining portion of the Mg-doped layer 6a is grown. . At this stage, a portion having a thickness d ₁ in the Mg-doped layer 6a in the n-type impurity doped region 7 is formed. Next, supply of the Mg raw material is stopped, and GaP doped with Si as an n-type impurity is grown under the condition of being undoped and p-type, and a portion corresponding to the region 6d made of p-type GaP is grown undoped. Let Next, the supply of the Zn raw material is started, and GaP doped with Zn as the p-type impurity and Si as the n-type impurity is grown to a predetermined thickness, and a lower layer side portion of the Zn-doped layer 6b is formed. Grow. At this stage, a portion having a thickness d ₂ in the Zn doped layer 6b in the n-type impurity doped region 7 is formed. Next, the supply of Si raw material is stopped, GaP doped with Zn as a p-type impurity is grown, and the remaining portion of the Zn-doped layer 6b is grown. When the p-type contact layer 6 is grown, impurities are doped so as to satisfy the relationship of 2 × 10 ¹⁷ cm ⁻³ <N _d <N _a1 <N _a2 and satisfy the relationship of N _d <N _a3 . Specifically, for example, the Mg concentration N _a1 of the Mg doped layer 6a is 1 × 10 ¹⁸ cm ⁻³ , the Zn concentration N _a2 of the Zn doped layer 6b is 2 × 10 ¹⁹ cm ⁻³ , and is undoped and p-type. Impurities are doped so that the GaP region 6d has a carrier concentration N _a3 of 1 × 10 ¹⁸ cm ⁻³ and the n-type impurity doped region 7 has a Si concentration N _d of 4 × 10 ¹⁷ cm ⁻³ . In this manner, the undoped p-type GaP region 6d is provided between the Mg-doped layer 6a and the Zn-doped layer 6b, and the undoped p-type GaP region 6d and the region 6d. A p-type contact layer 6 having an n-type impurity doped region 7 doped with Si in a predetermined region above and below is formed.
Since the other than the above is the same as the manufacturing method of the AlGaInP light emitting diode according to the first embodiment, the description thereof is omitted.

Next explained is the fourth embodiment of the invention.
In the fourth embodiment, in addition to the red light emitting diode according to any one of the first to third embodiments, a blue light emitting diode and a green light emitting diode, which are separately prepared, are used. The case of manufacturing will be described.
By the method according to any one of the first to third embodiments, an AlGaInP light emitting diode emitting red light in a flip chip form is obtained. Similarly, a GaN-based light emitting diode emitting green light and a GaN-based light emitting diode emitting blue light are obtained in the form of a flip chip.

Then, after mounting the red light emitting diode chip, the green light emitting diode chip, and the blue light emitting diode chip on a submount made of AlN or the like, each of them is mounted on the submount, for example, an Al substrate or the like. Mount in a predetermined arrangement on the substrate. This state is shown in FIG. 5A. 5A, reference numeral 21 denotes a substrate, 22 denotes a submount, 23 denotes a red light emitting diode chip, 24 denotes a green light emitting diode chip, and 25 denotes a blue light emitting diode chip. The chip size of the red light emitting diode chip 23, the green light emitting diode chip 24, and the blue light emitting diode chip 25 is, for example, 350 μm square, but is not limited thereto. Here, the red light emitting diode chip 23 is mounted such that the n-side electrode is on the submount 22, and the green light emitting diode chip 24 and the blue light emitting diode chip 25 are the p-side electrode and the n-side electrode. The electrodes are placed on the submount 22 via the bumps. An extraction electrode (not shown) for an n-side electrode is formed in a predetermined pattern shape on the submount 22 on which the red light emitting diode chip 23 is mounted, and a red portion is formed on a predetermined portion on the extraction electrode. The n-side electrode side of the light emitting diode chip 23 is mounted. A wire 27 is bonded to the p-side electrode of the red light emitting diode chip 23 and a predetermined pad electrode 26 provided on the substrate 21, and the lead electrode A wire (not shown) is bonded to one end and another pad electrode provided on the substrate 21 so as to connect them. On the submount 22 on which the green light emitting diode chip 24 is mounted, an extraction electrode for the p-side electrode and an extraction electrode for the n-side electrode (both not shown) are respectively formed in a predetermined pattern shape. Bumps in which the p-side electrode side and the n-side electrode side of the green light-emitting light-emitting diode chip 24 are formed on the p-side electrode lead electrode and the n-side electrode lead electrode are formed on them. Each is mounted through. A wire (not shown) is bonded to one end of the lead electrode for the p-side electrode of the green light emitting diode chip 24 and a pad electrode provided on the substrate 21 so as to connect them. In addition, a wire (not shown) is bonded to one end of the extraction electrode for the n-side electrode and a pad electrode provided on the substrate 21 so as to connect them. The same applies to the light emitting diode chip 25 emitting blue light.
However, the submount 22 is omitted, and the red light emitting diode chip 23, the green light emitting diode chip 24, and the blue light emitting diode chip 25 are directly attached to any printed wiring board or printed wiring board having heat dissipation properties. It is also possible to mount directly on a plate having the above function, or on the inner and outer walls of the housing (for example, the inner wall of the chassis), thereby reducing the cost of the light emitting diode backlight or the entire panel.

The red light emitting diode chip 23, the green light emitting diode chip 24, and the blue light emitting diode chip 25 as described above are set as one unit (cell), and a necessary number of them are arranged on the substrate 21 in a predetermined pattern. . An example is shown in FIG. Next, as shown in FIG. 5B, potting of the transparent resin 28 is performed so as to cover this one unit. Thereafter, the transparent resin 28 is cured. By this curing process, the transparent resin 28 is solidified and is slightly reduced accordingly (FIG. 5C). In this way, as shown in FIG. 7, the light emitting diode chip 23 that emits red light, the light emitting diode chip 24 that emits green light, and the light emitting diode chip 25 that emits blue light are arranged as an array on the substrate 21. A diode backlight is obtained.
This light emitting diode backlight is suitable for use in a backlight of a liquid crystal panel, for example.

Next explained is the fifth embodiment of the invention.
In the fifth embodiment, as in the fourth embodiment, a red light emitting diode chip 23, a green light emitting diode chip 24, and a blue light emitting diode chip 25 are arranged on a substrate 21 in a predetermined pattern. Then, as shown in FIG. 8, a transparent resin 29 suitable for the light emitting diode chip 23 is potted so as to cover the red light emitting diode chip 23, and the green light emitting diode chip 24 is mounted. The transparent resin 30 suitable for the light emitting diode chip 24 is potted so as to cover, and the transparent resin 31 suitable for the light emitting diode chip 25 is potted so as to cover the blue light emitting diode chip 25.
Since the other than the above is the same as that of the fourth embodiment, the description is omitted.

Next, a sixth embodiment of the present invention will be described.
In the sixth embodiment, in addition to the red light emitting diode according to any one of the first to third embodiments, a light source cell unit is prepared using separately prepared blue light emitting diode and green light emitting diode. The case of manufacturing will be described.
As shown in FIG. 9A, in the sixth embodiment, as in the fourth embodiment, a red light emitting diode chip 23, a green light emitting diode chip 24, and a blue light emitting diode chip 25 are provided. A required number of cells 35 each including at least one and arranged in a predetermined pattern are arranged on the printed wiring board 36 in a predetermined pattern. In this example, each cell 35 includes one red light emitting diode chip 23, one green light emitting diode chip 24, and one blue light emitting diode chip 25, which are arranged at the apexes of an equilateral triangle. FIG. 9B shows the cell 35 in an enlarged manner. The distance a between the red light emitting diode chip 23, the green light emitting diode chip 24, and the blue light emitting diode chip 25 in each cell 35 is, for example, 4 mm, but is not limited thereto. The interval b of the cells 35 is, for example, 30 mm, but is not limited to this. As the printed wiring board 36, for example, an FR4 (abbreviation of Flame Retardant Type 4) board, a metal core board, a flexible wiring board, or the like can be used. However, any other printed wiring board having heat dissipation can be used. However, it is not limited to these. As in the fourth embodiment, the transparent resin 28 is potted so as to cover each cell 35, or the transparent resin is covered so as to cover the red light emitting diode chip 23 as in the fifth embodiment. 29, potting of the transparent resin 30 is performed so as to cover the green light emitting diode chip 24, and potting of the transparent resin 31 is performed so as to cover the blue light emitting diode chip 25. In this way, a light source cell unit is obtained in which the cells 35 including the red light emitting diode chip 23, the green light emitting diode chip 24, and the blue light emitting diode chip 25 are arranged on the printed wiring board 36.

Although the specific example of arrangement | positioning of the cell 35 on the printed wiring board 36 is shown in FIG.10 and FIG.11, it is not limited to these. The example shown in FIG. 10 has the cells 35 arranged in a 4 × 3 two-dimensional array, and the example shown in FIG. 11 has the cells 35 arranged in a 6 × 2 two-dimensional array.
FIG. 12 shows another configuration example of the cell 35. In this example, the cell 35 includes one red light emitting diode chip 23, two green light emitting diode chips 24, and one blue light emitting diode chip 25, which are arranged at the apex of a square, for example. Has been. Two green light emitting diode chips 24 are arranged at the vertices of both ends of one diagonal of the square, and a red light emitting diode chip 23 and a blue light emitting diode chip 25 are disposed at both ends of the other diagonal of the square. It is placed at the vertex.
By arranging one or a plurality of the light source cell units, a light emitting diode backlight suitable for use in a backlight of a liquid crystal panel, for example, can be obtained.

Next explained is the seventh embodiment of the invention.
In the seventh embodiment, in addition to the red light emitting diode according to any one of the first to third embodiments, a blue light emitting diode and a green light emitting diode manufactured as follows are used. A case where a light emitting diode backlight similar to the fourth or fifth embodiment or a light source cell unit similar to the sixth embodiment is manufactured will be described.
FIG. 13 to FIG. 15 show a manufacturing method of this blue light emitting or green light emitting diode in the order of steps. This light-emitting diode uses a nitride III-V compound semiconductor such as GaN.

In the seventh embodiment, as shown in FIG. 13A, first, a substrate 51 having a flat main surface and made of a material different from that of a nitride III-V compound semiconductor is prepared. The convex part 52 whose cross-sectional shape is an isosceles triangle shape is periodically formed in a predetermined planar shape. A concave portion 53 having an inverted trapezoidal cross-sectional shape is formed between the convex portions 52. This substrate 51 is, for example, a sapphire substrate, and its main surface is, for example, a c-plane. The planar shape of the convex portion 52 and the concave portion 53 can be the various planar shapes already described. For example, as shown in FIG. 16, both the convex portion 52 and the concave portion 53 have a stripe shape extending in one direction. In other cases, as shown in FIG. 17, the convex portion 52 has a hexagonal planar shape and is two-dimensionally arranged in a honeycomb shape. Typically, the direction of the dotted line in FIG. 16 (the direction orthogonal to the stripe) is parallel to the a-axis of the nitride III-V compound semiconductor layer 55 described later, and the direction of the dotted line in FIG. The direction in which the portions 52 are connected to each other is set to be parallel to the m-axis of a nitride III-V compound semiconductor layer 55 described later. For example, when the substrate 51 is a sapphire substrate, the extending direction of the stripe-shaped convex portion 52 and the concave portion 53 in FIG. 16 is the <1-100> direction of the sapphire substrate, and the extending direction of the concave portion 53 in FIG. Similarly, it is the <1-100> direction of the sapphire substrate. These extending directions may be the <11-20> direction of the sapphire substrate. Can be used as is already mentioned as the material of the convex portion 52, from the viewpoint of ease of processing, preferably for example SiO _2, SiN, CrN, SiON, etc. CrON is used.

In order to form the convex part 52 whose cross-sectional shape is an isosceles triangle shape on the board | substrate 51, a conventionally well-known method can be used. For example, a film (for example, a SiO ₂ film) that is a material of the convex portion 52 is formed on the entire surface of the substrate 51 by CVD, vacuum deposition, sputtering, or the like. Next, a resist pattern having a predetermined shape is formed on the film by lithography. Next, this film is etched using the resist pattern as a mask under conditions where taper etching is performed by a reactive ion etching (RIE) method or the like, so that a convex portion 52 having an isosceles triangular cross section is formed. The

  Next, after cleaning the surfaces of the substrate 51 and the convex portion 52 by performing thermal cleaning or the like, for example, a GaN buffer layer or an AlN buffer is formed on the substrate 51 at a growth temperature of, for example, about 550 ° C. A buffer layer (not shown) such as a layer is grown. Next, epitaxial growth of a nitride III-V compound semiconductor is performed by, for example, MOCVD. This nitride-based III-V group compound semiconductor is, for example, GaN. At this time, as shown in FIG. 13B, first, growth is started from the bottom surface of the recess 53, and a plurality of micronuclei 54 made of a nitride III-V group compound semiconductor are generated. Next, as shown in FIG. 13C, an isosceles triangular shape having a bottom face of the concave portion 53 and a facet inclined with respect to the main surface of the substrate 51 on the slope through the growth and coalescence process of the micronuclei 54. The nitride III-V compound semiconductor layer 55 is grown so as to have a cross-sectional shape. In this example, the height of the nitride-based III-V group compound semiconductor layer 55 having an isosceles triangular cross-sectional shape is larger than the height of the convex portion 52. For example, the extending direction of the nitride III-V compound semiconductor layer 55 is the <1-100> direction, and the facet of the inclined surface is the (1-101) plane. The nitride III-V compound semiconductor layer 55 may be undoped or doped with an n-type impurity or a p-type impurity. The growth conditions for the nitride III-V compound semiconductor layer 55 will be described later. The extending direction of the nitride-based III-V compound semiconductor layer 55 may be the <11-20> direction.

Subsequently, by performing growth of the nitride-based III-V compound semiconductor layer 55 while maintaining the facet plane orientation of the slope, as shown in FIG. 14A, the nitride-based III-V compound semiconductor layer 55 Both end portions grow to the lower portion of the side surface of the convex portion 52, and the cross-sectional shape becomes a pentagonal shape.
Next, when the growth condition is set to a condition in which the lateral growth is dominant and the growth is continued, as shown in FIG. 14B, the nitride-based III-V compound semiconductor layer 55 has a lateral shape as indicated by an arrow. It grows in the direction and spreads on the convex portion 52 in a state where the cross-sectional shape becomes a hexagonal shape. In FIG. 14B, a dotted line indicates a growth interface in the middle of growth (the same applies hereinafter).
When the lateral growth is further continued, as shown in FIG. 14C, the nitride III-V compound semiconductor layer 55 grows while increasing its thickness, and finally the nitride III-III grown from the adjacent recess 53. The group V compound semiconductor layers 55 come into contact with each other on the convex portion 52 and are associated with each other.
Subsequently, as shown in FIG. 14C, the nitride-based III-V compound semiconductor layer 55 is laterally grown until the surface thereof becomes a flat surface parallel to the main surface of the substrate 51. The nitride-based III-V group compound semiconductor layer 55 thus grown has a very low dislocation density in the portion above the recess 53.
In some cases, the state shown in FIG. 13C can be shifted directly to the state shown in FIG. 14B without going through the state shown in FIG. 14A.

Next, as shown in FIG. 15, the n-type nitride III-V compound semiconductor layer 56, the nitride III-V group is formed on the nitride III-V compound semiconductor layer 55 by, eg, MOCVD. An active layer 57 using a compound semiconductor and a p-type nitride-based III-V compound semiconductor layer 58 are epitaxially grown sequentially. In this case, the nitride III-V compound semiconductor layer 55 is assumed to be n-type.
Next, the substrate 51 on which the nitride III-V compound semiconductor layer is grown in this way is taken out from the MOCVD apparatus.
Next, a p-side electrode 59 is formed on the p-type nitride III-V compound semiconductor layer 58. As a material of the p-side electrode 59, for example, an ohmic metal having a high reflectance is preferably used.
Thereafter, in order to activate the p-type impurity of the p-type nitride III-V compound semiconductor layer 58, for example, a mixed gas of N ₂ and O ₂ (composition is, for example, 99% N ₂ and O ₂ In a 1% atmosphere, heat treatment is performed at a temperature of 550 to 750 ° C. (for example, 650 ° C.) or 580 to 620 ° C. (for example, 600 ° C.). Here, for example, activation is easily caused by mixing O ₂ with N ₂ . Further, for example, nitrogen halide (NF ₃ , NCl _3, etc.) is mixed in a mixed gas atmosphere of N ₂ or N ₂ and O ₂ as a raw material such as F and Cl having high electronegativity as in O and N. You may do it. The time for this heat treatment is, for example, 5 minutes to 2 hours or 40 minutes to 2 hours, generally about 10 to 60 minutes. The reason for the relatively low temperature of the heat treatment is to prevent the active layer 57 and the like from being deteriorated during the heat treatment. This heat treatment may be performed after the p-type nitride-based III-V group compound semiconductor layer 58 is epitaxially grown and before the p-side electrode 59 is formed.
Next, the n-type nitride III-V compound semiconductor layer 56, the active layer 57, and the p-type nitride III-V compound semiconductor layer 58 are formed into a predetermined shape by, for example, the RIE method, the powder blast method, the sand blast method, or the like. Then, the mesa portion 60 is formed.

Next, the n-side electrode 61 is formed on the n-type nitride-based III-V group compound semiconductor layer 55 in a portion adjacent to the mesa portion 60.
Next, if necessary, the substrate 51 on which the light emitting diode structure is formed as described above is reduced in thickness by grinding or lapping from the back side thereof, and then the substrate 51 is scribed, and the bar Form. Thereafter, the bar is scribed to form a chip.
Thus, the target light emitting diode is manufactured.

The growth source of the above-mentioned nitride III-V compound semiconductor layer is, for example, triethylgallium ((C ₂ H ₅ ) ₃ Ga, TEG) or trimethyl gallium ((CH ₃ ) ₃ Ga, TMG as a Ga source. ), Trimethylaluminum ((CH ₃ ) ₃ Al, TMA) as a raw material of Al, triethylindium ((C ₂ H ₅ ) ₃ In, TEI) or trimethylindium ((CH ₃ ) ₃ In, TMI), and ammonia (NH ₃ ) is used as a raw material for N. As for the dopant, for example, silane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used as the n-type dopant, and bis (methylcyclopentadienyl) magnesium ((CH ₃ C ₅ H ₄ ) ₂ is used as the p-type dopant. Mg), bis (ethylcyclopentadienyl) magnesium ((C ₂ H ₅ C ₅ H ₄ ) ₂ Mg) or bis (cyclopentadienyl) magnesium ((C ₅ H ₅ ) ₂ Mg) is used. For the carrier gas atmosphere during the growth of the nitride-based III-V compound semiconductor layer, eg, H ₂ gas is used.

  A specific structural example of the light emitting diode will be described, but is not limited thereto. That is, for example, the nitride III-V compound semiconductor layer 55 is an n-type GaN layer, and the n-type nitride III-V compound semiconductor layer 56 is an n-type GaInN layer, an n-type GaN layer, and an n-type in order from the bottom. A p-type GaInN layer, a p-type nitride-based III-V group compound semiconductor layer 58 are a p-type GaInN layer, a p-type AlInN layer, a p-type GaN layer, and a p-type GaInN layer in order from the bottom. The active layer 57 has, for example, a GaInN-based multiple quantum well (MQW) structure (for example, one in which GaInN quantum well layers and GaN barrier layers are alternately stacked), and the In composition of the active layer 57 is the light emission of the light emitting diode. It is selected according to the wavelength. For example, it is ˜11% at an emission wavelength of 405 nm, ˜18% at 450 nm, and ˜24% at 520 nm. As the material of the p-side electrode 59, for example, Ag, Pd / Ag, or the like is used, or a barrier metal made of Ti, W, Cr, WN, CrN, or the like is used in addition to this, if necessary. As the n-side electrode 61, for example, a Ti / Pt / Au structure is used.

  In the light emitting diode shown in FIG. 15 thus obtained, light is emitted by applying a forward voltage between the p-side electrode 59 and the n-side electrode 61 to flow current, and light is transmitted to the outside through the substrate 51. Take out. Depending on the selection of the In composition of the active layer 57, red to ultraviolet light emission, particularly blue light emission, green light emission or red light emission can be obtained. In this case, of the light generated from the active layer 57, the light directed to the substrate 51 is refracted at the interface between the substrate 51 and the nitride-based III-V compound semiconductor layer 55 of the recess 53 and then passes through the substrate 51. Of the light generated from the active layer 57, the light traveling toward the p-side electrode 59 is reflected by the p-side electrode 59, travels toward the substrate 51, and travels outside through the substrate 51. .

In the seventh embodiment, in order to minimize the threading dislocation density of the nitride-based III-V compound semiconductor layer 55, the width W _g of the bottom surface of the concave portion 53, the depth of the concave portion 53, that is, the convex portion 52. And the angle α formed by the slope of the nitride III-V compound semiconductor layer 55 in the state shown in FIG. 13C and the main surface of the substrate 51 are determined so as to satisfy the following formula ( (See FIG. 18).
2d ≧ W _g tan α
For example, when W _g = 2.1 μm and α = 59 °, d ≧ 1.75 μm, W _g = 2 μm, and when α = 59 °, d ≧ 1.66 μm, W _g = 1.5 μm, α When d = 59 °, d ≧ 1.245 μm, W _g = 1.2 μm, and when α = 59 °, d ≧ 0.966 μm. However, in any case, it is desirable that d <5 μm.

During the growth of the nitride-based III-V group compound semiconductor layer 55 in the steps shown in FIGS. 13B and 13A and FIG. 14A, it is preferable to set the growth temperature low so as to increase the V / III ratio of the growth material. Specifically, when the growth of the nitride III-V compound semiconductor layer 55 is performed under a pressure condition of 1 atm, the V / III ratio of the growth material is in the range of, for example, 13000 ± 2000, and the growth temperature is, for example, 1100. It is preferable to set in the range of ± 50 ° C. Regarding the V / III ratio of the growth material, when the growth of the nitride-based III-V compound semiconductor layer 55 is performed under a pressure condition of x atmospheric pressure, the pressure is determined from Bernoulli's law that defines the relationship between the flow velocity and the pressure. It is preferable to set the V / III ratio corresponding to the square of the amount of change, specifically (13000 ± 2000) × x ² . For example, when the growth is performed at 0.92 atmospheres (700 Torr), the V / III ratio of the growth raw material is preferably set to a range of 11000 ± 1700 (for example, 10530). x is generally from 0.01 to 2 atmospheres. As for the growth temperature, when growth is performed under a pressure condition of 1 atm or less, the lateral growth of the nitride III-V compound semiconductor layer 55 is suppressed, and the nitride III-V compound semiconductor in the recess 53 is suppressed. In order to facilitate selective growth of the layer 55, it is preferable to set a lower growth temperature. For example, when growth is performed at 0.92 atmospheres (700 Torr), the growth temperature is preferably set in a range of 1050 ± 50 ° C. (for example, 1050 ° C.). By doing so, the nitride III-V compound semiconductor layer 55 grows as shown in FIGS. 13B and 13C and FIG. 14A. At this time, the nitride III-V compound semiconductor layer 55 does not start to grow from above the convex portion 52. The growth rate is generally 0.5 to 5.0 μm / h, preferably about 3.0 μm / h. When the nitride III-V compound semiconductor layer 55 is a GaN layer, for example, the flow rate of the source gas is, for example, 20 SCCM for TMG and 20 SLM for NH ₃ . On the other hand, the growth (lateral growth) of the nitride-based III-V compound semiconductor layer 55 in the steps shown in FIGS. 14B and 14C is performed by setting the growth temperature higher while lowering the V / III ratio of the growth material. Specifically, when the growth of the nitride III-V compound semiconductor layer 55 is performed under a pressure condition of 1 atm, the V / III ratio of the growth material is in the range of 5000 ± 2000, for example, and the growth temperature is, for example, 1200. Set in the range of ± 50 ° C. Regarding the V / III ratio of the growth material, when the growth of the nitride-based III-V compound semiconductor layer 55 is performed under a pressure condition of x atmospheric pressure, the pressure is determined from Bernoulli's law that defines the relationship between the flow velocity and the pressure. It is preferable to set the V / III ratio corresponding to the square of the amount of change, specifically (5000 ± 2000) × x ² . For example, when the growth is performed at 0.92 atmospheres (700 Torr), the V / III ratio of the growth material is preferably set in the range of 4200 ± 1700 (for example, 4232). As for the growth temperature, when growth is performed under a pressure condition of 1 atm or less, the surface of the nitride III-V compound semiconductor layer 55 is prevented from being roughened, and the lateral growth is favorably performed. It is preferable to set the temperature. For example, when growth is performed at 0.92 atmospheres (700 Torr), the growth temperature is preferably set in the range of 1150 ± 50 ° C. (eg, 1110 ° C.). When the nitride-based III-V group compound semiconductor layer 55 is, for example, a GaN layer, the flow rate of the source gas is, for example, 40 SCCM for TMG and 20 SLM for NH ₃ . By doing so, as shown in FIGS. 14B and 14C, the nitride-based III-V compound semiconductor layer 55 grows laterally.

FIG. 19 schematically shows the results of examining the crystal defect distribution of the nitride-based III-V compound semiconductor layer 55 using a transmission electron microscope (TEM). In FIG. 19, reference numeral 62 indicates threading dislocations. As can be seen from FIG. 19, although the dislocation density is high in the vicinity of the central portion of the convex portion 52, that is, at the association portion between the nitride-based III-V compound semiconductor layers 55 grown from the concave portions 53 adjacent to each other, the concave portion In other parts including the part above 53, the dislocation density is low. For example, when the depth d of the concave portion 53 is 1 μm and the width W _{g of} the bottom surface is 2 μm, the dislocation density of this low dislocation density portion is 6 × 10 ⁷ / cm ² , and the substrate 51 subjected to uneven processing is used. The dislocation density is reduced by 1 to 2 digits as compared with the case of no. It can also be seen that no dislocation occurs in the direction perpendicular to the side wall of the recess 53.
In FIG. 19, the average thickness of the high dislocation density and poor crystallinity region of the nitride III-V compound semiconductor layer 55 in contact with the substrate 51 in the recess 53 is the nitride in contact with the substrate 51 in the protrusion 52. This is about 1.5 times the average thickness of the region with poor dislocation and high dislocation density of the III-V compound semiconductor layer 55. This is a result reflecting the fact that the nitride III-V compound semiconductor layer 55 grows laterally on the convex portion 52.

Next, the growth mode of the nitride-based III-V compound semiconductor layer 55 from the beginning of growth and the state of dislocation propagation will be described with reference to FIG.
When the growth is started, as shown in FIG. 20A, first, a plurality of micronuclei 54 made of a nitride III-V compound semiconductor are generated on the bottom surface of the recess 53. In these micronuclei 54, dislocations (shown by dotted lines) propagate in the vertical direction from the interface with the substrate 51, and the dislocations escape from the side surfaces of the micronuclei 54. When the growth is continued, as shown in FIGS. 20B and 20C, the nitride-based III-V group compound semiconductor layer 55 grows through the process of growth and coalescence of the micronuclei 54. In the process of growth and coalescence of these micronuclei 54, dislocations are bent in a direction parallel to the main surface of the substrate 51. As a result, dislocations that escape to the top are reduced. As the growth continues further, as shown in FIG. 20D, the nitride-based III-V compound semiconductor layer 55 has an isosceles triangular cross-sectional shape with the bottom surface of the recess 53 as the base. At this point, the dislocations that escape from the nitride-based III-V compound semiconductor layer 55 to the upper part are greatly reduced. Next, as shown in FIG. 20E, a nitride-based III-V compound semiconductor layer 55 is grown in the lateral direction. In this process, the dislocations that have escaped to the side surface of the nitride-based III-V compound semiconductor layer 55 having an isosceles triangular cross-section with the bottom surface of the recess 53 as the base are located at a position lower than the protrusion 52. The nitride system III that has been stretched parallel to the main surface of the substrate 51 and disappeared while continuing to extend to the side surface of the convex portion 52 and that is higher than the convex portion 52 extends parallel to the main surface of the substrate 51 and is laterally grown. -It escapes to the side surface of the group V compound semiconductor layer 55. When the lateral growth of the nitride-based III-V compound semiconductor layer 55 is further continued, as shown in FIG. 20F, the nitride-based III-V compound semiconductor layers 55 grown on both sides of the convex portion 52 are formed. Eventually, the surface of the nitride-based III-V compound semiconductor layer 55 becomes a flat surface parallel to the main surface of the substrate 51. Dislocations in the nitride-based III-V compound semiconductor layer 55 are bent upward (in a direction perpendicular to the main surface of the substrate 51) when meeting on the convex portion 52, and become threading dislocations.

According to the seventh embodiment, since no gap is formed between the substrate 51 and the nitride-based III-V group compound semiconductor layer 55, it is possible to prevent a decrease in light extraction efficiency due to the gap. it can. Further, the threading dislocations in the nitride III-V compound semiconductor layer 55 are concentrated in the vicinity of the central portion of the convex portion 52 of the substrate 51, and the dislocation density in other portions is, for example, about 6 × 10 ⁷ / cm ² . Since it is greatly reduced as compared with the case of using a concavo-convex processed substrate, a nitride III-V compound semiconductor layer such as the nitride III-V compound semiconductor layer 55 and an active layer 57 grown thereon is provided. The crystallinity of this material is greatly improved, and the non-luminescent center and the like are also greatly reduced. As a result, a nitride III-V compound semiconductor light emitting diode with extremely high luminous efficiency can be obtained.
In addition, the epitaxial growth necessary for manufacturing the nitride III-V compound semiconductor light emitting diode is only required once, and not only a growth mask is unnecessary, but also the protrusion 52 on the substrate 51 is formed on the substrate 51. A film that forms the material of the protrusion 52, for example, a film such as a SiO ₂ film, a SiON film, a SiN film, a CrN film, or a CrON film is formed, and this is formed only by processing by etching, powder blasting, sand blasting, etc. Therefore, it is not necessary to process the substrate 51 such as a sapphire substrate, which is difficult to process, so that the manufacturing process is simple and the nitride III-V compound semiconductor light emitting diode is manufactured at low cost. be able to.

Next, an eighth embodiment of the invention will be described.
In the eighth embodiment, as shown in FIG. 21A, convex portions 52 having a trapezoidal cross section are periodically formed on a substrate 51 in a predetermined plane shape. A concave portion 53 having an inverted trapezoidal cross-sectional shape is formed between the convex portions 52.
Next, a nitride III-V compound semiconductor layer 55 is grown in the same manner as in the seventh embodiment. Specifically, a nitride having an isosceles triangular cross-section with the bottom surface of the recess 53 as the bottom, as shown in FIG. As shown in FIG. 21C, a III-V group compound semiconductor layer 55 having a flat surface and a low threading dislocation density is obtained after the III-V group compound semiconductor layer 55 is grown. Grow.
Next, the process proceeds in the same manner as in the seventh embodiment, and the target nitride-based III-V compound semiconductor light-emitting diode is manufactured as shown in FIG.
Other than the above are the same as in the first embodiment.
FIG. 23 schematically shows the result of examining the crystal defect distribution of the nitride-based III-V compound semiconductor layer 55 by TEM.
According to the eighth embodiment, the same advantages as those of the seventh embodiment can be obtained.

As mentioned above, although embodiment of this invention was described concretely, this invention is not limited to the above-mentioned embodiment, The various deformation | transformation based on the technical idea of this invention is possible.
For example, the numerical values, materials, structures, shapes, arrangements, substrates, raw materials, processes, and the like given in the first to eighth embodiments are merely examples, and numerical values, materials, and structures different from these as necessary. , Shapes, arrangements, substrates, raw materials, processes, etc. may be used.

  Specifically, in the above-described first to third embodiments, GaAs may be used as the material of the p-type contact layer 6 instead of GaP, and AlGaInP is used as the material of the n-type cladding layer 2. Alternatively, AlInP may be used, AlAlP may be used instead of AlGaInP as the material of the p-type cladding layer 4, and AlGaInP may be used as the material of the p-type intermediate layer 5 instead of GaInP.

In the first to third embodiments described above, instead of the Mg-doped layer 6a constituting the p-type contact layer 6, a layer doped with Be as a p-type impurity, or Mg and p-type impurities. A layer doped with Be may be used. That is, Be may be used instead of Mg, or both Mg and Be may be used as the p-type impurity doped in the active layer 3 side of the p-type contact layer 6. In the second embodiment, the overlap region 6c may be a layer doped with Be and Zn as p-type impurities, or a layer doped with Mg, Be, and Zn as p-type impurities. .
In the first to third embodiments described above, Si is used as the n-type impurity doped in the n-type impurity doped region 7 of the p-type contact layer 6, but Se or S is used as necessary. May be used, or two or more of Si, Se and S may be used in combination.

In the first to third embodiments described above, the present invention is applied to an AlGaInP light emitting diode. However, the present invention is not limited to an AlGaInP semiconductor laser but also a semiconductor using these AlGaInP semiconductors. In addition to the light emitting element, for example, the present invention may be applied to a semiconductor light emitting element using an AlGaAs semiconductor.
Furthermore, the arrangement of the cells 35 to be mounted on a substrate (including a heat dissipation substrate) such as the printed wiring board 36 is not limited to that shown in FIGS. 9 to 12 and may be other arrangements. For example, the cell 35 shown in FIGS. 9 to 12 may be rotated around its center at an arbitrary angle, for example, 45 degrees counterclockwise. Further, the arrangement and number of the red light emitting diode chip 23, the green light emitting diode chip 24, and the blue light emitting diode chip 25 in the cell 35 are not limited to those shown in FIGS. Or a number.

1 is a cross-sectional view showing an AlGaInP-based LED according to a first embodiment of the present invention. It is a basic diagram which shows the impurity concentration profile of AlGaInP type LED by 1st Embodiment of this invention. It is a basic diagram which shows the impurity concentration profile of AlGaInP type LED by 2nd Embodiment of this invention. It is a basic diagram which shows the impurity concentration profile of AlGaInP type LED by 3rd Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode backlight by 4th Embodiment of this invention. It is a perspective view for demonstrating the manufacturing method of the light emitting diode backlight by 4th Embodiment of this invention. It is a perspective view for demonstrating the manufacturing method of the light emitting diode backlight by 4th Embodiment of this invention. It is a perspective view for demonstrating the manufacturing method of the light emitting diode backlight by 5th Embodiment of this invention. It is the top view which shows the light source cell unit by the 6th Embodiment of this invention, and the enlarged view of the cell of this light source cell unit. It is a top view which shows one specific example of the light source cell unit by the 6th Embodiment of this invention. It is a top view which shows the other specific example of the light source cell unit by the 6th Embodiment of this invention. It is a top view which shows the other structural example of the cell of the light source cell unit by 6th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 7th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 7th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 7th Embodiment of this invention. It is a top view which shows the example of the planar shape of the convex part formed on a board | substrate in the manufacturing method of the light emitting diode by 7th Embodiment of this invention. It is a top view which shows the example of the planar shape of the convex part formed on a board | substrate in the manufacturing method of the light emitting diode by 7th Embodiment of this invention. It is a basic diagram which shows the board | substrate used in the manufacturing method of the light emitting diode by 7th Embodiment of this invention. FIG. 10 is a schematic diagram for explaining dislocation behavior obtained by TEM observation of a nitride III-V compound semiconductor layer grown on a substrate in a light emitting diode manufacturing method according to a seventh embodiment of the present invention; is there. It is a basic diagram which shows the example of distribution of the threading dislocation of the nitride type III-V compound semiconductor layer grown on the board | substrate in the manufacturing method of the light emitting diode by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 8th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the light emitting diode by 8th Embodiment of this invention. FIG. 10 is a schematic diagram for explaining dislocation behavior obtained by TEM observation of a nitride III-V compound semiconductor layer grown on a substrate in a light emitting diode manufacturing method according to an eighth embodiment of the present invention; is there. It is a basic diagram which shows the impurity concentration profile of the conventional AlGaInP type light emitting diode which improved the p-type contact layer. It is a basic diagram which shows the result of the SIMS analysis of the sample for evaluation which has the same layer structure as the p-type contact layer of the conventional AlGaInP type light emitting diode.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... n-type semiconductor substrate, 2 ... n-type clad layer, 3 ... active layer, 4 ... p-type clad layer, 5 ... p-type intermediate layer, 6 ... p-type contact layer, 6a ... Mg doped layer, 6b ... Zn dope Layer, 6c ... overlapping region, 6d ... undoped p-type GaP region, 7 ... n-type impurity doped region, 8 ... p-side electrode, 9 ... n-side electrode, 23-25 ... light emitting diode chip, 28- DESCRIPTION OF SYMBOLS 31 ... Transparent resin, 35 ... Cell, 36 ... Printed wiring board, 51 ... Board | substrate, 52 ... Convex part, 53 ... Concave part, 54 ... Micro nucleus, 55 ... Nitride type III-V group compound semiconductor layer, 56 ... N type Nitride III-V compound semiconductor layer, 57... Active layer, 58... P-type nitride III-V compound semiconductor layer, 59... P-side electrode, 60.

Claims (12)

An n-type cladding layer made of AlGaInP doped with Si as an n-type impurity on one main surface of an n-type GaAs substrate, a multi-quantum well structure having an undoped GaInP layer as a quantum well layer and an undoped AlGaInP layer as a barrier layer An active layer, a p-type cladding layer made of AlGaInP doped with Mg as a p-type impurity, a p-type intermediate layer made of GaInP doped with Mg as a p-type impurity, and a p-type contact layer are sequentially laminated,
The p-type contact layer includes, in order from the active layer side, an Mg-doped layer made of GaP doped with Mg as a p-type impurity, and a Zn-doped layer made of GaP doped with Zn as a p-type impurity,
An n-type impurity doped region doped with Si is formed so as to straddle the interface between the Mg doped layer and the Zn doped layer,
The p-side electrode is in contact with the portion other than the light extraction portion on the Zn-doped layer,
Zn concentration N of the Zn doped layer _a2 Is the Mg concentration N of the Mg doped layer _a1 N against _a1 <N _a2 Chosen to satisfy the relationship
Si concentration N in the n-type impurity doped region _d Is 2 × 10 ¹⁷ cm ^-3 <N _d <N _a1 <N _a2 Chosen to satisfy the relationship
The thickness d of the n-type impurity doped region in the Mg doped layer ₁ And the thickness d of the portion in the Zn doped layer in the n-type impurity doped region ₂ Are AlGaInP light emitting diodes each selected to be 50 nm or more. An n-type cladding layer made of AlGaInP doped with Si as an n-type impurity on one main surface of an n-type GaAs substrate, a multi-quantum well structure having an undoped GaInP layer as a quantum well layer and an undoped AlGaInP layer as a barrier layer An active layer, a p-type cladding layer made of AlGaInP doped with Mg as a p-type impurity, a p-type intermediate layer made of GaInP doped with Mg as a p-type impurity, and a p-type contact layer are sequentially laminated,
The p-type contact layer includes, in order from the active layer side, an Mg-doped layer made of GaP doped with Mg as a p-type impurity, and an Mg- and Zn-doped layer made of GaP doped with Mg and Zn as p-type impurities. And a Zn-doped layer made of GaP doped with Zn as a p-type impurity,
An n-type impurity doped region doped with Si is formed in the Mg doped layer and the Mg doped layer above and below the Mg and Zn doped layer and the Zn doped layer,
The p-side electrode is in contact with the portion other than the light extraction portion on the Zn-doped layer,
Zn concentration N of the Zn doped layer _a2 Is the Mg concentration N of the Mg doped layer _a1 N against _a1 <N _a2 Chosen to satisfy the relationship
Si concentration N in the n-type impurity doped region _d Is 2 × 10 ¹⁷ cm ^-3 <N _d <N _a1 <N _a2 Chosen to satisfy the relationship
The thickness d of the n-type impurity doped region in the Mg doped layer ₁ And the thickness d of the portion in the Zn doped layer in the n-type impurity doped region ₂ Are each selected to be 50 nm or more, and the thickness d of the portion in the Mg and Zn doped layer in the n-type impurity doped region _Three Is 0 <d _Three ≦ 100 nm AlGaInP light emitting diode selected. An n-type cladding layer made of AlGaInP doped with Si as an n-type impurity on one main surface of an n-type GaAs substrate, a multi-quantum well structure having an undoped GaInP layer as a quantum well layer and an undoped AlGaInP layer as a barrier layer An active layer, a p-type cladding layer made of AlGaInP doped with Mg as a p-type impurity, a p-type intermediate layer made of GaInP doped with Mg as a p-type impurity, and a p-type contact layer are sequentially laminated,
The p-type contact layer includes, in order from the active layer side, a Mg-doped layer made of GaP doped with Mg as a p-type impurity, a p-type region made of undoped p-type GaP, and Zn as a p-type impurity. A Zn-doped layer made of doped GaP,
N-type impurity doped regions doped with Si are formed in the Mg-doped layer and the Zn-doped layer above and below the p-type region and the p-type region,
The p-side electrode is in contact with the portion other than the light extraction portion on the Zn-doped layer,
Zn concentration N of the Zn doped layer _a2 Is the Mg concentration N of the Mg doped layer _a1 N against _a1 <N _a2 Chosen to satisfy the relationship
Si concentration N in the n-type impurity doped region _d Is 2 × 10 ¹⁷ cm ^-3 <N _d <N _a1 <N _a2 Chosen to satisfy the relationship
Hole concentration N in the p-type region _a3 Is the Si concentration N in the n-type impurity doped region. _d N against _d <N _a3 Chosen to satisfy the relationship
The thickness d of the n-type impurity doped region in the Mg doped layer ₁ And the thickness d of the portion in the Zn doped layer in the n-type impurity doped region ₂ Is selected to be 50 nm or more, and the thickness d of the portion in the p-type region of the n-type impurity doped region is d _Four Is 0 <d _Four <AlGaInP light-emitting diode selected to be 300 nm. A plurality of cells each including at least one of a red light emitting semiconductor light emitting element, a green light emitting semiconductor light emitting element, and a blue light emitting semiconductor light emitting element are arranged on the printed wiring board,
The semiconductor light emitting element emitting red light is
An n-type cladding layer made of AlGaInP doped with Si as an n-type impurity on one main surface of an n-type GaAs substrate, a multi-quantum well structure having an undoped GaInP layer as a quantum well layer and an undoped AlGaInP layer as a barrier layer An active layer, a p-type cladding layer made of AlGaInP doped with Mg as a p-type impurity, a p-type intermediate layer made of GaInP doped with Mg as a p-type impurity, and a p-type contact layer are sequentially laminated,
The p-type contact layer includes, in order from the active layer side, an Mg-doped layer made of GaP doped with Mg as a p-type impurity, and a Zn-doped layer made of GaP doped with Zn as a p-type impurity,
An n-type impurity doped region doped with Si is formed so as to straddle the interface between the Mg doped layer and the Zn doped layer,
The p-side electrode is in contact with the portion other than the light extraction portion on the Zn-doped layer,
Zn concentration N of the Zn doped layer _a2 Is the Mg concentration N of the Mg doped layer _a1 N against _a1 <N _a2 Chosen to satisfy the relationship
Si concentration N in the n-type impurity doped region _d Is 2 × 10 ¹⁷ cm ^-3 <N _d <N _a1 <N _a2 Chosen to satisfy the relationship
The thickness d of the n-type impurity doped region in the Mg doped layer ₁ And the thickness d of the portion in the Zn doped layer in the n-type impurity doped region ₂ Is a light source cell unit that is an AlGaInP light emitting diode selected to be 50 nm or more. A plurality of cells each including at least one of a red light emitting semiconductor light emitting element, a green light emitting semiconductor light emitting element, and a blue light emitting semiconductor light emitting element are arranged on the printed wiring board,
The semiconductor light emitting element emitting red light is
An n-type cladding layer made of AlGaInP doped with Si as an n-type impurity on one main surface of an n-type GaAs substrate, a multi-quantum well structure having an undoped GaInP layer as a quantum well layer and an undoped AlGaInP layer as a barrier layer An active layer, a p-type cladding layer made of AlGaInP doped with Mg as a p-type impurity, a p-type intermediate layer made of GaInP doped with Mg as a p-type impurity, and a p-type contact layer are sequentially laminated,
The p-type contact layer includes, in order from the active layer side, an Mg-doped layer made of GaP doped with Mg as a p-type impurity, and an Mg- and Zn-doped layer made of GaP doped with Mg and Zn as p-type impurities. And a Zn-doped layer made of GaP doped with Zn as a p-type impurity,
An n-type impurity doped region doped with Si is formed in the Mg doped layer and the Mg doped layer above and below the Mg and Zn doped layer and the Zn doped layer,
The p-side electrode is in contact with the portion other than the light extraction portion on the Zn-doped layer,
Zn concentration N of the Zn doped layer _a2 Is the Mg concentration N of the Mg doped layer _a1 N against _a1 <N _a2 Chosen to satisfy the relationship
Si concentration N in the n-type impurity doped region _d Is 2 × 10 ¹⁷ cm ^-3 <N _d <N _a1 <N _a2 Chosen to satisfy the relationship
The thickness d of the n-type impurity doped region in the Mg doped layer ₁ And the thickness d of the portion in the Zn doped layer in the n-type impurity doped region ₂ Are each selected to be 50 nm or more, and the thickness d of the portion in the Mg and Zn doped layer in the n-type impurity doped region _Three Is 0 <d _Three A light source cell unit which is an AlGaInP light emitting diode selected to be ≦ 100 nm. A plurality of cells each including at least one of a red light emitting semiconductor light emitting element, a green light emitting semiconductor light emitting element, and a blue light emitting semiconductor light emitting element are arranged on the printed wiring board,
The semiconductor light emitting element emitting red light is
An n-type cladding layer made of AlGaInP doped with Si as an n-type impurity on one main surface of an n-type GaAs substrate, a multi-quantum well structure having an undoped GaInP layer as a quantum well layer and an undoped AlGaInP layer as a barrier layer An active layer, a p-type cladding layer made of AlGaInP doped with Mg as a p-type impurity, a p-type intermediate layer made of GaInP doped with Mg as a p-type impurity, and a p-type contact layer are sequentially laminated,
The p-type contact layer includes, in order from the active layer side, a Mg-doped layer made of GaP doped with Mg as a p-type impurity, a p-type region made of undoped p-type GaP, and Zn as a p-type impurity. A Zn-doped layer made of doped GaP,
N-type impurity doped regions doped with Si are formed in the Mg-doped layer and the Zn-doped layer above and below the p-type region and the p-type region,
The p-side electrode is in contact with the portion other than the light extraction portion on the Zn-doped layer,
Zn concentration N of the Zn doped layer _a2 Is the Mg concentration N of the Mg doped layer _a1 N against _a1 <N _a2 Chosen to satisfy the relationship
Si concentration N in the n-type impurity doped region _d Is 2 × 10 ¹⁷ cm ^-3 <N _d <N _a1 <N _a2 Chosen to satisfy the relationship
Hole concentration N in the p-type region _a3 Is the Si concentration N in the n-type impurity doped region. _d N against _d <N _a3 Chosen to satisfy the relationship
The thickness d of the n-type impurity doped region in the Mg doped layer ₁ And the thickness d of the portion in the Zn doped layer in the n-type impurity doped region ₂ Is selected to be 50 nm or more, and the thickness d of the portion in the p-type region of the n-type impurity doped region is d _Four Is 0 <d _Four A light source cell unit which is an AlGaInP light emitting diode selected to be <300 nm. A plurality of red light emitting semiconductor light emitting elements, green light emitting semiconductor light emitting elements and blue light emitting semiconductor light emitting elements are arranged,
The semiconductor light emitting element emitting red light is
An n-type cladding layer made of AlGaInP doped with Si as an n-type impurity on one main surface of an n-type GaAs substrate, a multi-quantum well structure having an undoped GaInP layer as a quantum well layer and an undoped AlGaInP layer as a barrier layer An active layer, a p-type cladding layer made of AlGaInP doped with Mg as a p-type impurity, a p-type intermediate layer made of GaInP doped with Mg as a p-type impurity, and a p-type contact layer are sequentially laminated,
The p-type contact layer includes, in order from the active layer side, an Mg-doped layer made of GaP doped with Mg as a p-type impurity, and a Zn-doped layer made of GaP doped with Zn as a p-type impurity,
An n-type impurity doped region doped with Si is formed so as to straddle the interface between the Mg doped layer and the Zn doped layer,
The p-side electrode is in contact with the portion other than the light extraction portion on the Zn-doped layer,
Zn concentration N of the Zn doped layer _a2 Is the Mg concentration N of the Mg doped layer _a1 N against _a1 <N _a2 Chosen to satisfy the relationship
Si concentration N in the n-type impurity doped region _d Is 2 × 10 ¹⁷ cm ^-3 <N _d <N _a1 <N _a2 Chosen to satisfy the relationship
The thickness d of the n-type impurity doped region in the Mg doped layer ₁ And the thickness d of the portion in the Zn doped layer in the n-type impurity doped region ₂ Is a display which is an AlGaInP light emitting diode each selected to be 50 nm or more. A plurality of red light emitting semiconductor light emitting elements, green light emitting semiconductor light emitting elements and blue light emitting semiconductor light emitting elements are arranged,
The semiconductor light emitting element emitting red light is
An n-type cladding layer made of AlGaInP doped with Si as an n-type impurity on one main surface of an n-type GaAs substrate, a multi-quantum well structure having an undoped GaInP layer as a quantum well layer and an undoped AlGaInP layer as a barrier layer An active layer, a p-type cladding layer made of AlGaInP doped with Mg as a p-type impurity, a p-type intermediate layer made of GaInP doped with Mg as a p-type impurity, and a p-type contact layer are sequentially laminated,
The p-type contact layer includes, in order from the active layer side, an Mg-doped layer made of GaP doped with Mg as a p-type impurity, and an Mg- and Zn-doped layer made of GaP doped with Mg and Zn as p-type impurities. And a Zn-doped layer made of GaP doped with Zn as a p-type impurity,
An n-type impurity doped region doped with Si is formed in the Mg doped layer and the Mg doped layer above and below the Mg and Zn doped layer and the Zn doped layer,
The p-side electrode is in contact with the portion other than the light extraction portion on the Zn-doped layer,
Zn concentration N of the Zn doped layer _a2 Is the Mg concentration N of the Mg doped layer _a1 N against _a1 <N _a2 Chosen to satisfy the relationship
Si concentration N in the n-type impurity doped region _d Is 2 × 10 ¹⁷ cm ^-3 <N _d <N _a1 <N _a2 Chosen to satisfy the relationship
The thickness d of the n-type impurity doped region in the Mg doped layer ₁ And the thickness d of the portion in the Zn doped layer in the n-type impurity doped region ₂ Are each selected to be 50 nm or more, and the thickness d of the portion in the Mg and Zn doped layer in the n-type impurity doped region _Three Is 0 <d _Three A display which is an AlGaInP light emitting diode selected to be ≦ 100 nm. A plurality of red light emitting semiconductor light emitting elements, green light emitting semiconductor light emitting elements and blue light emitting semiconductor light emitting elements are arranged,
The semiconductor light emitting element emitting red light is
An n-type cladding layer made of AlGaInP doped with Si as an n-type impurity on one main surface of an n-type GaAs substrate, a multi-quantum well structure having an undoped GaInP layer as a quantum well layer and an undoped AlGaInP layer as a barrier layer An active layer, a p-type cladding layer made of AlGaInP doped with Mg as a p-type impurity, a p-type intermediate layer made of GaInP doped with Mg as a p-type impurity, and a p-type contact layer are sequentially laminated,
The p-type contact layer includes, in order from the active layer side, a Mg-doped layer made of GaP doped with Mg as a p-type impurity, a p-type region made of undoped p-type GaP, and Zn as a p-type impurity. A Zn-doped layer made of doped GaP,
N-type impurity doped regions doped with Si are formed in the Mg-doped layer and the Zn-doped layer above and below the p-type region and the p-type region,
The p-side electrode is in contact with the portion other than the light extraction portion on the Zn-doped layer,
Zn concentration N of the Zn doped layer _a2 Is the Mg concentration N of the Mg doped layer _a1 N against _a1 <N _a2 Chosen to satisfy the relationship
Si concentration N in the n-type impurity doped region _d Is 2 × 10 ¹⁷ cm ^-3 <N _d <N _a1 <N _a2 Chosen to satisfy the relationship
Hole concentration N in the p-type region _a3 Is the Si concentration N in the n-type impurity doped region. _d N against _d <N _a3 Chosen to satisfy the relationship
The thickness d of the n-type impurity doped region in the Mg doped layer ₁ And the thickness d of the portion in the Zn doped layer in the n-type impurity doped region ₂ Is selected to be 50 nm or more, and the thickness d of the portion in the p-type region of the n-type impurity doped region is d _Four Is 0 <d _Four <Display which is an AlGaInP light emitting diode selected at 300 nm. Having one or more semiconductor light emitting elements,
At least one of the semiconductor light emitting elements is
An n-type cladding layer made of AlGaInP doped with Si as an n-type impurity on one main surface of an n-type GaAs substrate, a multi-quantum well structure having an undoped GaInP layer as a quantum well layer and an undoped AlGaInP layer as a barrier layer An active layer, a p-type cladding layer made of AlGaInP doped with Mg as a p-type impurity, a p-type intermediate layer made of GaInP doped with Mg as a p-type impurity, and a p-type contact layer are sequentially laminated,
The p-type contact layer includes, in order from the active layer side, an Mg-doped layer made of GaP doped with Mg as a p-type impurity, and a Zn-doped layer made of GaP doped with Zn as a p-type impurity,
An n-type impurity doped region doped with Si is formed so as to straddle the interface between the Mg doped layer and the Zn doped layer,
The p-side electrode is in contact with the portion other than the light extraction portion on the Zn-doped layer,
Zn concentration N of the Zn doped layer _a2 Is the Mg concentration N of the Mg doped layer _a1 N against _a1 <N _a2 Chosen to satisfy the relationship
Si concentration N in the n-type impurity doped region _d Is 2 × 10 ¹⁷ cm ^-3 <N _d <N _a1 <N _a2 Chosen to satisfy the relationship
The thickness d of the n-type impurity doped region in the Mg doped layer ₁ And the thickness d of the portion in the Zn doped layer in the n-type impurity doped region ₂ Is an electronic device which is an AlGaInP light emitting diode selected to be 50 nm or more. Having one or more semiconductor light emitting elements,
At least one of the semiconductor light emitting elements is
An n-type cladding layer made of AlGaInP doped with Si as an n-type impurity on one main surface of an n-type GaAs substrate, a multi-quantum well structure having an undoped GaInP layer as a quantum well layer and an undoped AlGaInP layer as a barrier layer An active layer, a p-type cladding layer made of AlGaInP doped with Mg as a p-type impurity, a p-type intermediate layer made of GaInP doped with Mg as a p-type impurity, and a p-type contact layer are sequentially laminated,
The p-type contact layer includes, in order from the active layer side, an Mg-doped layer made of GaP doped with Mg as a p-type impurity, and an Mg- and Zn-doped layer made of GaP doped with Mg and Zn as p-type impurities. And a Zn-doped layer made of GaP doped with Zn as a p-type impurity,
An n-type impurity doped region doped with Si is formed in the Mg doped layer and the Mg doped layer above and below the Mg and Zn doped layer and the Zn doped layer,
The p-side electrode is in contact with the portion other than the light extraction portion on the Zn-doped layer,
Zn concentration N of the Zn doped layer _a2 Is the Mg concentration N of the Mg doped layer _a1 N against _a1 <N _a2 Chosen to satisfy the relationship
Si concentration N in the n-type impurity doped region _d Is 2 × 10 ¹⁷ cm ^-3 <N _d <N _a1 <N _a2 Chosen to satisfy the relationship
The thickness d of the n-type impurity doped region in the Mg doped layer ₁ And the thickness d of the portion in the Zn doped layer in the n-type impurity doped region ₂ Are each selected to be 50 nm or more, and the thickness d of the portion in the Mg and Zn doped layer in the n-type impurity doped region _Three Is 0 <d _Three Electronic equipment which is an AlGaInP light emitting diode selected to be ≦ 100 nm. Having one or more semiconductor light emitting elements,
At least one of the semiconductor light emitting elements is
An n-type cladding layer made of AlGaInP doped with Si as an n-type impurity on one main surface of an n-type GaAs substrate, a multi-quantum well structure having an undoped GaInP layer as a quantum well layer and an undoped AlGaInP layer as a barrier layer An active layer, a p-type cladding layer made of AlGaInP doped with Mg as a p-type impurity, a p-type intermediate layer made of GaInP doped with Mg as a p-type impurity, and a p-type contact layer are sequentially laminated,
The p-type contact layer includes, in order from the active layer side, a Mg-doped layer made of GaP doped with Mg as a p-type impurity, a p-type region made of undoped p-type GaP, and Zn as a p-type impurity. A Zn-doped layer made of doped GaP,
N-type impurity doped regions doped with Si are formed in the Mg-doped layer and the Zn-doped layer above and below the p-type region and the p-type region,
The p-side electrode is in contact with the portion other than the light extraction portion on the Zn-doped layer,
Zn concentration N of the Zn doped layer _a2 Is the Mg concentration N of the Mg doped layer _a1 N against _a1 <N _a2 Chosen to satisfy the relationship
Si concentration N in the n-type impurity doped region _d Is 2 × 10 ¹⁷ cm ^-3 <N _d <N _a1 <N _a2 Chosen to satisfy the relationship
Hole concentration N in the p-type region _a3 Is the Si concentration N in the n-type impurity doped region. _d N against _d <N _a3 Chosen to satisfy the relationship
The thickness d of the n-type impurity doped region in the Mg doped layer ₁ And the thickness d of the portion in the Zn doped layer in the n-type impurity doped region ₂ Is selected to be 50 nm or more, and the thickness d of the portion in the p-type region of the n-type impurity doped region is d _Four Is 0 <d _Four <Electronic device which is an AlGaInP light emitting diode selected at 300 nm.

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