JP2016195171A - Semiconductor light emitting element and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a semiconductor light emitting element having high yield.SOLUTION: A semiconductor light emitting element comprises: a substrate; a first semiconductor layer, an active layer and a second semiconductor layer which are formed in upper layers on the substrate; and a first electrode. The second semiconductor layer is composed of a nitride semiconductor having a conductivity type different from that of the first semiconductor layer and a surface located in a first region and opposite to the active layer is composed to include an uneven surface and a surface located in a second region different from the first region and on the side opposite to the active layer is composed of a flat surface. The first electrode contacts the first semiconductor layer in the second region and is formed in a state off having an insulation property against the active layer and the second semiconductor layer. In upper layers on the first semiconductor layer, which are located in a region out of the second region, where the first electrode contacts, the active layer and the second semiconductor layer are not formed.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor light emitting device and a method for manufacturing the same.

  As one of element structures of a semiconductor light emitting element, development of a so-called via structure type semiconductor light emitting element is underway. For example, in Patent Document 1 below, by adopting a via structure type semiconductor light emitting element, the distance that the current should spread in the lateral direction in the semiconductor is reduced, the series resistance can be reduced, and high current drive is achieved. It is described that it can be realized.

JP 2004-047988 A

  The present inventor has found a unique problem that the yield deteriorates when manufacturing the semiconductor light emitting element having the via structure as described above, and has reached the present invention.

The semiconductor light emitting device according to the present invention is
A substrate,
A first semiconductor layer made of an n-type or p-type nitride semiconductor, formed on an upper layer of the substrate;
An active layer formed on the first semiconductor layer and made of a nitride semiconductor;
Formed on the active layer and made of a nitride semiconductor having a conductivity type different from that of the first semiconductor layer, the surface located on the opposite side of the active layer in the first region includes an uneven surface. On the other hand, in a second region different from the first region, a second semiconductor layer having a flat surface on the side opposite to the active layer,
In the second region, in contact with the first semiconductor layer, comprising a first electrode formed in an insulating state with respect to the active layer and the second semiconductor layer,
In the second region, the active layer and the second semiconductor layer are not formed in an upper layer of the first semiconductor layer located in a region in contact with the first electrode.

  According to the semiconductor light emitting device described above, the second semiconductor layer has irregularities formed on the surface opposite to the active layer, so that the amount of light that can be taken out of the device from the light emitted from the active layer As a result, the light extraction efficiency is improved.

  The first electrode is formed in contact with the first semiconductor layer in a region where the active layer and the second semiconductor layer are not present. This first electrode is not in the first region where the surface of the second semiconductor layer opposite to the active layer is configured to include an uneven surface, but opposite to the active layer of the second semiconductor layer The surface located in the side is provided in the 2nd area | region comprised by the flat surface.

  In order to form a region where the active layer and the second semiconductor layer do not exist, the second semiconductor layer and the active layer located in the region are formed by performing etching or the like, for example. Since the upper surface of the second semiconductor layer is a flat surface, the energy applied during the etching process can be uniformly applied to the target portion. For this reason, when a plurality of first electrodes are formed on the same element, etching regions for forming the first electrodes can be formed with the same dimensions. Therefore, the electrical characteristics between the manufactured elements can be made uniform, and a semiconductor light emitting element with a high yield is realized.

  This semiconductor light emitting device can have a flip chip type structure as well as a via type structure.

In the second region, there is a hole that penetrates at least the second semiconductor layer and the active layer and reaches the first semiconductor layer,
The first electrode may be formed so as to be inserted into the hole and in contact with the first semiconductor layer while maintaining an insulating state with respect to the active layer and the second semiconductor layer. I do not care. Thereby, a semiconductor light emitting device having a via structure with a high yield is realized.

  In the above element, the active layer may be made of a nitride semiconductor having a nonpolar plane as a crystal plane.

  In a semiconductor light emitting device composed of a nitride semiconductor, there is another problem that light emission efficiency is reduced due to an internal electric field. Conventionally, a semiconductor light emitting device using a nitride semiconductor has been manufactured by c-plane growth. Here, “c-plane growth” means epitaxial growth along a direction perpendicular to the c-plane, that is, along the c-axis.

  With respect to the c-axis direction, Ga atoms and N atoms are arranged asymmetrically. At this time, in the c-plane which is the growth surface of the GaN layer, the Ga atom surface containing only Ga atoms is slightly charged positively, while the N atom surface containing only N atoms is slightly charged negatively. Spontaneous polarization occurs in the c-axis direction. In addition, when heterogeneous semiconductor layers are heteroepitaxially grown on the GaN crystal layer, compressive strain or tensile strain is generated in the GaN crystal due to the difference in lattice constant between the two, and piezoelectric polarization (piezo polarization) in the c-axis direction in the GaN crystal. Will occur.

  The active layer generally has a quantum well structure. In forming a quantum well structure, the above heteroepitaxial growth is required. Therefore, when a semiconductor layer including an active layer is grown using the c-plane as a growth surface, an internal electric field due to spontaneous polarization or piezoelectric polarization is generated in the c-axis direction in the quantum well. As a result, the recombination probability of electrons and holes decreases, and the light emission efficiency decreases.

  On the other hand, according to the semiconductor light emitting device described above, since the active layer is configured by a nonpolar plane, the internal electric field is reduced as compared with the case where all active layers are configured by a polar plane, and the recombination is performed. Probability increases.

  In the above configuration, the active layer has an uneven surface on both the surface located on the first semiconductor layer side and the surface located on the second semiconductor layer side over the first region and the second region. It may be configured to include.

  In another aspect, the active layer has a flat surface on the first semiconductor layer side and a surface on the second semiconductor layer side across the first region and the second region. It may be configured as a plane.

In addition, the semiconductor light emitting element is
Comprising a second electrode in contact with the second semiconductor layer;
The first electrode may be in contact with the first semiconductor layer in an insulated state with respect to the second electrode.

The present invention also provides:
Preparing a substrate (a);
A step (b) of growing a first semiconductor layer made of an n-type or p-type nitride semiconductor on the upper layer of the substrate;
A step (c) of growing an active layer made of a nitride semiconductor on the first semiconductor layer;
A step (d) of growing a second semiconductor layer made of a nitride semiconductor having a conductivity type different from that of the first semiconductor layer on the active layer;
Forming an uneven shape on at least a part of the upper surface of the second semiconductor layer located in the first region of the upper surface of the second semiconductor layer; and
Etching the second semiconductor layer and the active layer in at least a part of the second region different from the first region to expose the first semiconductor layer on the bottom surface;
And (g) forming the first electrode on at least a part of the upper surface of the first semiconductor layer exposed while being electrically insulated from the second semiconductor layer and the active layer. .

  According to the above method, a semiconductor light emitting device with improved light extraction efficiency can be manufactured while achieving uniform dimensions between devices.

  In the above method, the step (b) may be a step of growing the first semiconductor layer using a nonpolar plane as a crystal growth plane. As a result, a semiconductor light emitting device having a reduced internal electric field and an improved recombination probability is realized.

  By the way, as a method for realizing the above-described step (b), various methods can be adopted.

  As an example, after the step (a), a third semiconductor layer made of a nitride semiconductor is grown on the upper surface of the substrate, and then a groove (hereinafter referred to as “first”) extending in a predetermined direction with respect to the third semiconductor layer. Step (b1) is formed. The first groove has a depth within a range where the surface of the substrate is not exposed.

  After the execution of the step (b1), the step (b2) of growing the third semiconductor layer is executed again. Before execution of the step (b2), an uneven surface is formed due to the presence of the first groove portion, and a third semiconductor layer is grown on the uneven surface, so that at least a nonpolar surface is used as a growth surface. A semiconductor layer is formed.

  After the execution of the step (b2), a step (b3) for growing the first semiconductor layer is executed. Since the first semiconductor layer continues to grow on the growth surface of the third semiconductor layer, at least the nonpolar surface is formed as the growth surface. The steps (b1) to (b3) can realize the step (b).

  As another example, the step (b) may be realized by executing the step (b3) of growing the first semiconductor layer after the execution of the step (b1). That is, before the execution of the step (b3), an uneven surface is formed by the presence of the first groove, and the first semiconductor layer grows on the uneven surface, so that at least a nonpolar surface is defined as the growth surface. The first semiconductor layer is formed.

  As another example, after the step (a), a step (b4) of growing a third semiconductor layer made of a nitride semiconductor on the upper surface of the substrate and then growing the first semiconductor layer is performed. Thereafter, a step (b5) of forming a groove extending in a predetermined direction is performed on the first semiconductor layer. Then, after the execution of the step (b5), the step (b6) of growing the first semiconductor layer is executed again. Before the execution of the step (b6), an uneven surface is formed by the presence of the first groove, and the first semiconductor layer grows on the uneven surface, so that at least a nonpolar surface is the growth surface. One semiconductor layer is formed. By the steps (b4) to (b6), the step (b) can be realized.

The step (f) is a step of etching the second semiconductor layer and the active layer in at least a part of the second region to form a groove part in which the first semiconductor layer is exposed on the bottom surface. Yes,
The step (g) may be a step of forming the first electrode by filling the groove with a conductive material while being electrically insulated from the second semiconductor layer and the active layer. .

  According to this method, since the first electrode is filled in a groove (hereinafter referred to as “second groove” as appropriate) penetrating the second semiconductor layer and the active layer, a so-called via structure type semiconductor light emitting device is formed. Realized. Thereby, the uniformity of the current distribution density is improved, and a semiconductor light emitting element suitable for high current driving is realized.

  The step (b) may be a step of growing the first semiconductor layer over the first region and the second region with a nonpolar plane as a crystal growth plane.

Further, in the above method, after the completion of the step (d), before the start of the step (f), a step (h) of forming a second electrode at least on the second semiconductor layer in the first region Have
The step (g) may be a step of forming the first electrode while being electrically insulated from the second electrode.

  According to the above configuration, in the semiconductor light emitting device having an uneven shape on the surface of the active layer, when the first electrode is formed, the etching amount can be minimized, and a semiconductor light emitting device with a high yield is realized. The

  According to the present invention, a semiconductor light emitting device having a high yield can be realized.

It is drawing which shows typically the structure of the semiconductor light-emitting device of 1st embodiment. It is one process figure which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment. It is one process figure which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment. It is one process figure which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment. It is one process figure which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment. It is one process figure which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment. It is one process figure which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment. It is one process figure which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment. It is one process figure which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment. It is one process figure which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment. It is one process figure which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment. It is one process figure which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment. It is one process figure which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment. It is one process figure which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment. It is one process figure which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment. It is one process figure which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment. It is one process figure which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment. It is one process figure which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment. It is drawing which shows typically the structure of the semiconductor light-emitting device of 2nd embodiment. It is one process figure which shows the manufacturing process of the semiconductor light-emitting device of 2nd embodiment. It is one process figure which shows the manufacturing process of the semiconductor light-emitting device of 2nd embodiment. It is one process figure which shows the manufacturing process of the semiconductor light-emitting device of 2nd embodiment. It is one process figure which shows the manufacturing process of the semiconductor light-emitting device of 2nd embodiment. It is one process figure which shows the manufacturing process of the semiconductor light-emitting device of 2nd embodiment. It is another drawing which shows typically the structure of the semiconductor light-emitting device of 2nd embodiment.

  A semiconductor light emitting device and a method for manufacturing the same according to the present invention will be described with reference to the drawings. In each figure, the dimensional ratio in the drawing does not necessarily match the actual dimensional ratio.

[First embodiment]
A first embodiment of the present invention will be described.

<Construction>
FIG. 1 is a drawing schematically showing the structure of a semiconductor light emitting device, and corresponds to a so-called “via structure type” device. In FIG. 1, (a) is a schematic plan view when viewed from the side opposite to the light extraction surface, and (b) is a schematic cross section when cut along the line AA in (a). Here, it corresponds to a schematic cross-sectional view taken along a plane formed in the [0001] direction and the [1-100] direction.

  In the present specification, the symbol “-” attached immediately before the number in parentheses indicating the Miller index indicates the inversion of the index and is synonymous with “bar” in the drawings. In this specification, the {1-101} plane means the (1-101) plane and a plane crystallographically equivalent to the (1-101) plane, that is, the (10-11) plane, (01 The concept includes a (-11) plane, a (0-111) plane, a (-1101) plane, and a (-1011) plane. In the present specification, the <11-20> direction refers to the [11-20] direction and a crystallographically equivalent direction to the [11-20] direction, that is, the [1-210] direction, [− 2110] direction, [-1-120] direction, [-12-10] direction, and [2-1-10] direction.

  In addition, in the present specification, when “AlGaN” is simply indicated, it means that the nitride semiconductor contains Al and Ga, and the description of the composition ratio of Al and Ga is simply omitted. However, the present invention is not limited to the case where the composition ratio of Al and Ga is 1: 1. The same applies to the notations InGaN and AlInGaN.

  The semiconductor light emitting device 1 includes a substrate 11, a first semiconductor layer 15, an active layer 17, a second semiconductor layer 19, and a first electrode 41. The first semiconductor layer 15 is formed in the upper layer of the substrate 11, the active layer 17 is formed in the upper layer of the first semiconductor layer 15, and the second semiconductor layer 19 is formed in the upper layer of the active layer 17. In addition, the semiconductor light emitting device 1 has a first electrode 41 and a second electrode 21.

  Here, for convenience of explanation, the semiconductor light emitting element 1 is divided into two regions, a first region 3 and a second region 4, as shown in FIG. The second region 4 corresponds to a region where the first electrode 41 is formed and a region in the vicinity thereof, and the first region 3 is farther from the location where the first electrode 41 is disposed than the second region 4 in the semiconductor light emitting device 1. Corresponds to the area.

  In the present embodiment, the second semiconductor layer 19 is configured so that the surface located on the opposite side of the active layer 17 in the first region 3 includes an uneven surface, while the active layer 17 in the second region 4 The surface located on the opposite side is a flat surface. The semiconductor light emitting element 1 has a hole 7 in the second region 4, and a first electrode 41 is formed so as to be inserted into the hole 7.

  Hereinafter, an example of a detailed configuration of each element will be described.

(Substrate 11 and element substrate 12)
The substrate 11 is composed of, for example, a sapphire substrate. The element substrate 12 is configured by providing a wiring pattern on a conductive substrate such as CuW, W, and Mo, a semiconductor substrate such as Si, or an insulating substrate such as AlN. As shown in FIG. 1B, in the element substrate 12, the region electrically connected to the first electrode 41 and the region electrically connected to the second electrode 21 are insulative. Is secured. Various methods can be adopted as a method for ensuring the insulation, but as an example, it can be realized by patterning. In the semiconductor light emitting device 1 shown in FIG. 1, the substrate 11 side constitutes a light extraction surface.

(Junction layer 43)
The bonding layer 43 is made of, for example, Au—Sn, Au—In, Au—Cu—Sn, Cu—Sn, Pd—Sn, Sn, or the like. The bonding layer 43 functions as a layer for ensuring adhesion between the substrate 11 and the element substrate 12 when bonded.

(Protective layer 42)
The protective layer 42 is made of, for example, a Pt-based metal (an alloy of Ti and Pt), W, Mo, Ni, or the like. When joining via the joining layer 43, the function which prevents the fall of the light extraction efficiency by the material which comprises the joining layer 43 diffuse | diffusing to the 2nd electrode 21 side, and the reflectance in the 2nd electrode 21 falls. Plays.

  As shown in FIG. 1B, a protective layer 42 may be provided on the upper surface of the first electrode 41 for the purpose of preventing the material constituting the bonding layer 43 from diffusing to the first electrode 41 side. Absent.

(First electrode 41)
The first electrode 41 is made of, for example, Cr—Au. As shown in FIG. 1A, the semiconductor light emitting device 1 of the present embodiment has a configuration having a plurality of first electrodes 41 arranged discretely.

  The first electrode 41 is formed by being inserted into the hole 7 that penetrates the second semiconductor layer 19 and the active layer 17 in the second region 4 and reaches the first semiconductor layer 15. In the present embodiment, the first semiconductor layer 15 is an n-type semiconductor layer, and the second semiconductor layer 19 is a p-type semiconductor layer. At this time, the first electrode 41 corresponds to an n-side electrode.

(Second electrode 21)
The second electrode 21 is formed on the surface of the second semiconductor layer 19 and can be made of a metal material containing, for example, an Ag-based metal (an alloy of Ni and Ag), Al, or Rh. These materials are conductive materials that can reflect light emitted from the active layer 17. With this configuration, the light emitted from the active layer 17 toward the element substrate 12 can be reflected by the second electrode 21 and guided to the extraction surface side (substrate 11 side). High light extraction efficiency is realized. In the present embodiment, the second electrode 21 corresponds to a p-side electrode.

(Insulating layer 54)
As described above, the insulating layer 54 has the insulating property between the first electrode 41 and the second electrode 21, the insulating property between the first electrode 41 and the second semiconductor layer 19, and the first electrode 41 and the active layer. 17 is provided for the purpose of ensuring insulation between the two. In the present embodiment, the insulating layer 54 is provided on a part of the outer surface of the first electrode 41 and a part of the surface of the second electrode 21 on the element substrate 12 side. Within the realizable range, the location and form of the insulating layer 54 can be changed as appropriate. The insulating layer 54 may be composed of SiO ₂ , SiN, Zr ₂ O _3, Al ₂ O _3, or the like.

(First semiconductor layer 15)
In the present embodiment, the first semiconductor layer 15 is composed of an n-type AlN layer. In addition to AlN, it can be composed of an n-type nitride semiconductor layer defined by the general formula Al _x2 Ga _y2 In _{1 -x2-y2} N (0 ≦ x2 ≦ 1, 0 ≦ y2 ≦ 1). In the present embodiment, as described later with reference to FIG. 2D and the like, the first semiconductor layer 15 includes a growth surface 15a parallel to a nonpolar surface (for example, {1-101} surface) and a polar surface (for example, The growth surface 15b is parallel to the {0001} plane.

(Active layer 17)
In the present embodiment, the active layer 17 has a configuration in which Al _x3 Ga _1-x3 N (0 <x3 ≦ 1) / AlN is laminated in one cycle or multiple cycles. As an example, a light emitting layer made of Al _0.8 Ga _0.2 N and a barrier layer made of AlN are configured to be repeated multiple times. The configuration of the active layer 17 is appropriately selected according to the emission wavelength. In the present embodiment, as will be described later with reference to FIG. 2E and the like, the active layer 17 is a growth plane parallel to a nonpolar plane (for example, {1-101} plane), like the first semiconductor layer 15. 17a and a growth surface 17b parallel to a polar surface (for example, {0001} surface). The active layer 17 may be formed by laminating two types of nitride semiconductor layers (AlGaN or AlInGaN) having different band gap energies by different Al compositions in one cycle or multiple cycles.

(Second semiconductor layer 19)
In the present embodiment, the second semiconductor layer 19 includes a p _- type cladding layer made of p-type Al _x4 Ga _{1 -X4} N (0 <x4 ≦ 1) and p ⁺ -type GaN formed on the p-type cladding layer. A p-type contact layer made of A second electrode 21 is formed so as to be in contact with the p-type contact layer. The p-type contact layer may be made of p ⁺ -type Al _x5 Ga _{1 -X5} N (0 <x5 ≦ 1).

(Third semiconductor layer 13)
In the present embodiment, the semiconductor light emitting device 1 includes a third semiconductor layer 13, and the first semiconductor layer 15 is formed on the third semiconductor layer 13. The first semiconductor layer 15 is a layer formed by epitaxial growth on the third semiconductor layer 13.

In the present embodiment, the third semiconductor layer 13 is composed of an AlN layer. In addition to AlN, it can be composed of a nitride semiconductor layer defined by the general formula Al _x1 Ga _y1 In _1-x1-y1 N (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1). Incidentally, the emission wavelength from the _{Al x1 Ga y1 In 1-x1} -y1 N the In composition is preferably 1% or less, _{Al x1 Ga y1 In 1-x1} -y1 N Al composition, the active layer 17 It is selected as appropriate.

  The third semiconductor layer 13 has a groove (recessed portion) 14 extending along a predetermined direction (here, referred to as [11-20] direction). In the present embodiment, the extending direction of the groove portion 14 is the [11-20] direction. The extending direction is a crystallographically equivalent direction to the [11-20] direction, that is, <11-20>. It may be a direction, or may be another direction.

  According to this configuration, since the active layer 17 has the growth surface 17a (see FIG. 2E described later) parallel to the nonpolar plane, the influence of the internal electric field is suppressed, and the light emitting element with high light emission efficiency Is realized.

  In a via structure type semiconductor light emitting device, as shown in FIG. 1A, a plurality of via electrodes (corresponding to the first electrode 41 here) are usually formed in the same device. In the second region 4 in which the hole 7 in which the first electrode 41 is inserted is formed, as described above, the upper surface of the second semiconductor layer 19 is a flat surface. As will be described later, the hole 7 is formed by etching. Thus, the etching target surface is formed as a flat surface, so that the etching energy can be uniformly applied to the active layer 17. Therefore, since the hole 7 for inserting the first electrode 41 can be formed with the same size, the electrical characteristics between the manufactured semiconductor light emitting elements 1 are made uniform, and a high yield can be realized.

<Production method>
A method for manufacturing the semiconductor light emitting device 1 according to the first embodiment will be described with reference to FIGS. 1 and 2A to 2Q. 2A to 2G, 2N to 2Q, and 2H (b) to 2M (b) in the following drawings, as in FIG. 1 (b), at each time point. This corresponds to a schematic cross-sectional view when the element is cut at a position corresponding to the line AA in FIG. 2H (a) to 2M (a) correspond to schematic plan views when the element at each time point is viewed from the side opposite to the light extraction surface, as in FIG. 1 (a).

(Step S1)
A substrate 11 is prepared (see FIG. 2A). As this substrate 11, for example, a sapphire substrate having a (0001) plane can be used.

  As a preparation step, the substrate 11 is cleaned. As a more specific example of this cleaning, a growth substrate 11 is placed in a processing furnace of a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, and hydrogen having a flow rate of, for example, 10 slm is placed in the processing furnace. While flowing the gas, the temperature in the furnace is raised to, for example, 1150 ° C.

  This step S1 corresponds to the step (a).

(Step S2)
As shown in FIG. 2B, a third semiconductor layer 13 made of, for example, AlN is formed on the (0001) plane of the substrate 11. As an example of a specific method, the temperature in the furnace of the MOCVD apparatus is set to a temperature of 900 ° C. or higher and 1600 ° C. or lower, and trimethylaluminum (TMA) and ammonia are treated as source gases while flowing nitrogen gas and hydrogen gas as carrier gases. Supply into the furnace. By setting the flow rate ratio of TMA and ammonia (V / III ratio) to a value of 10 to 4000, the growth pressure to a value of 1 kPa to 70 kPa, and adjusting the supply time as appropriate, AlN having a desired film thickness is formed. The Here, the third semiconductor layer 13 made of AlN having a thickness of 600 nm was formed.

In the case where Al _x1 Ga _y1 In _1-x1-y1 N (0 <x1 ≦ 1, 0 ≦ y1 ≦ 1) is formed as the third semiconductor layer 13, trimethylgallium ( TMG) and trimethylindium (TMI) may be supplied at a predetermined flow rate corresponding to the composition.

(Step S3)
As shown in FIG. 2C, a groove (first groove) 14 is formed in the third semiconductor layer 13 along a predetermined direction, for example, <11-20>. It is preferable to control so that the groove part 14 is formed with a depth within a range where the substrate 11 is not exposed on the bottom surface of the groove part 14.

  As an example of a specific method, the wafer obtained by executing up to step S2 is taken out of the processing furnace, and the third semiconductor layer 13 is <11-20 by photolithography and reactive ion etching (RIE). A plurality of grooves parallel to the> direction are formed at predetermined intervals. In FIG. 2C, the groove 14 is extended in the [11-20] direction, which is one direction crystallographically equivalent to the <11-20> direction.

  Steps S2 to S3 correspond to step (b1).

(Step S4)
As shown in FIG. 2D, the first semiconductor layer 15 is formed on the upper surface of the third semiconductor layer 13 in which the groove 14 along the <11-20> direction is formed. As an example of a specific method, the wafer after completion of the execution of step S3 is again placed in the furnace of the MOCVD apparatus, the furnace temperature of the MOCVD apparatus is set to a temperature of 900 ° C. or higher and 1600 ° C. or lower, and nitrogen gas and While flowing hydrogen gas, TMA, ammonia, and tetraethylsilane as n-type dopant are supplied into the processing furnace as raw material gases. By setting the flow rate ratio of TMA and ammonia (V / III ratio) to a value of 10 to 4000, the growth pressure to a value of 1 kPa to 70 kPa, and appropriately adjusting the supply time, AlN having a desired film thickness is formed. The Here, the first semiconductor layer 15 made of n-type AlN having a thickness of 3000 nm was formed.

When n-type Al _x2 Ga _y2 In _1-x2-y2 N (0 <x2 ≦ 1, 0 ≦ y2 ≦ 1) is formed as the first semiconductor layer 15, TMA, ammonia, and tetraethylsilane are used. In addition, TMG and TMI may be supplied at a predetermined flow rate according to the composition.

  By growing a crystal on the upper surface of the third semiconductor layer 13 in which the groove 14 having a depth that does not expose the upper surface of the substrate 11 is formed, on a nonpolar plane (here, as an example, the {1-101} plane) A first semiconductor layer 15 having parallel growth surfaces 15a is formed. In the configuration shown in FIG. 2D, the first semiconductor layer 15 has a growth surface 15b parallel to the polar surface at some locations, but the first semiconductor layer 15 is a growth surface parallel to the nonpolar surface. The structure which has only 15a may be sufficient.

  This step S4 corresponds to the step (b3). Steps S2 to S4 correspond to step (b).

(Step S5)
As shown in FIG. 2E, the first semiconductor layer has a growth surface 15a parallel to the nonpolar plane (here {1-101} plane) and a growth plane 15b parallel to the polar plane (here {0001} plane). An active layer 17 is grown on the upper surface of 15. As an example of a specific method, the furnace temperature of the MOCVD apparatus is set to a temperature of 900 ° C. to 1600 ° C., and nitrogen gas and hydrogen gas are allowed to flow as carrier gases, while TMA and ammonia are used as source gases in the processing furnace. The step of supplying a predetermined time according to the thickness and the step of supplying TMA, TMG and ammonia as source gases into the processing furnace for a predetermined time according to the film thickness are repeated a predetermined number of times according to the number of cycles. As a result, an active layer 17 made of multi-period Al _x3 Ga _1-x3 N (0 <x3 ≦ 1) / AlN is formed.

Incidentally, as the active layer _{17, Al x3 Ga y3 In 1} -x3-y3 N (0 <x3 ≦ 1,0 ≦ y3 ≦ 1) / Al x4 Ga y4 In 1-x4-y4 N (0 <x4 ≦ 1, In the case of forming 0 ≦ y4 ≦ 1), TMA, ammonia, TMG, and TMI may be supplied as source gases at a predetermined flow rate according to the composition.

  In step S4, since the first semiconductor layer 15 having the growth surface 15a parallel to the nonpolar surface and the growth surface 15b parallel to the polar surface is formed, epitaxial growth is performed in this step S5 in this state. As shown to 2E, the active layer 17 which has the growth surface 17a parallel to a nonpolar surface and the growth surface 17b parallel to a polar surface is formed. In step S4, when the first semiconductor layer 15 has only the growth surface 15a parallel to the nonpolar surface, in this step S5, only the growth surface 17a in which the active layer 17 is parallel to the nonpolar surface. It may be configured to have.

  This step S5 corresponds to the step (c).

(Step S6)
As shown in FIG. 2F, a second semiconductor layer 19 is grown on the upper surface of the active layer 17. As an example of a specific method, the pressure in the furnace of the MOCVD apparatus is 100 kPa, the furnace temperature is 830 ° C., and the source gas is biscyclopenta for forming p-type impurities in addition to ammonia, TMA and TMG. Further growth is carried out including dienylmagnesium (Cp ₂ Mg). As a result, the second semiconductor layer 19 made of p-type Al _x4 Ga _{1 -X4} N (0 <x4 ≦ 1) is formed on the active layer 17. Further, the p ⁺ -type GaN layer may be formed as an upper layer by changing the flow rate of the source gas. In this case, the second semiconductor layer 19 is constituted by p-type Al _x4 Ga _{1 -X4} N (0 <x4 ≦ 1) and the p ⁺ -type GaN layer. The p ⁺ type GaN layer may be made of p ⁺ type Al _x5 Ga _{1 -X5} N (0 <x5 ≦ 1).

  In the present embodiment, as shown in FIG. 2F, the upper surface of the second semiconductor layer 19 is formed to be a flat surface. By appropriately setting the film forming conditions of the second semiconductor layer 19, the upper surface of the second semiconductor layer 19 can be made flat as described above.

  This step S6 corresponds to the step (d).

(Step S7)
An activation process is performed on the wafer obtained through steps S1 to S6. More specifically, activation is performed at 650 ° C. for 15 minutes in a nitrogen atmosphere using an RTA (Rapid Thermal Anneal) device.

(Step S8)
Next, with respect to the exposed surface of the second semiconductor layer 19, the second semiconductor layer 19 in the first region 3 is exposed in a state where the second semiconductor layer 19 in the second region 4 is masked. Soak an alkaline solution such as KOH. Thereby, as shown in FIG. 2G, the uneven shape 5 is formed on the upper surface of the second semiconductor layer 19 only in the first region 3.

  This step S8 corresponds to the step (e). Note that step S8 may be executed before step S7.

(Step S9)
As shown in FIG. 2H, the second electrode 21 is formed on the upper surface of the second semiconductor layer 19. Specifically, the second electrode 21 is selectively formed on a region other than the one or more island-like regions 24 on the upper surface of the second semiconductor layer 19. The wafer having undergone step S9 has a region 24 where the second semiconductor layer 19 is exposed in an island shape and a region where the second electrode 21 is exposed on the upper surface. Here, the island-like region 24 is formed in the second region 4.

  A specific method for forming the second electrode 21 is, for example, as follows.

  First, a resist is applied by patterning to a region on the upper surface of the second semiconductor layer 19 corresponding to a region where the second electrode 21 is not formed. The region where the resist is applied corresponds to a region where the first electrode 41 is to be formed later and a region where current is likely to concentrate near the first electrode 41. Thereafter, Ag having a film thickness of 150 nm and Ni having a film thickness of 30 nm are formed on the entire surface including the upper surface of the resist by, for example, a sputtering apparatus. As this material film, in order to improve the adhesion to the second semiconductor layer 19, Ni having a thickness of about 1.5 nm may be formed under the Ag layer.

  Next, after the resist is lifted off, contact annealing is performed using an RTA apparatus or the like in a dry air or inert gas atmosphere at 400 ° C. to 550 ° C. (for example, 400 ° C.) for 60 seconds to 300 seconds, and the second electrode 21 is formed. When annealing is performed in an inert gas atmosphere, Ag diffusion to the second semiconductor layer 19 side due to migration can be reduced, so that the Schottky effect can be further enhanced as compared with a dry air atmosphere.

  This step S9 corresponds to the step (h).

(Step S10)
As shown in FIG. 2I, etching is performed on the surface of the second semiconductor layer 19 located in the second region 4 exposed through step S <b> 9 to expose the upper surface of the first semiconductor layer 15.

  Specifically, a resist 51 is applied to the upper surface of the second electrode 21 formed at the end of step S9 by patterning. Thereafter, using the resist 51 as a mask, the second semiconductor layer 19 and the active layer 17 are removed by dry etching using an ICP apparatus until a part of the upper surface of the first semiconductor layer 15 is exposed. In step S10, the first semiconductor layer 15 may be partially removed by etching. By this step S10, the groove portion 7 is formed. This groove portion 7 corresponds to a “second groove portion”.

  The groove 7 formed in step S <b> 10 becomes a space for embedding the first electrode 41 for supplying current to the first semiconductor layer 15 thereafter. For this reason, in step S10, it is necessary to proceed the etching until the surface of the first semiconductor layer 15 is exposed in the entire region of the bottom surface of the groove portion 7.

  Here, the case where this step S10 is performed with respect to the surface of the 2nd semiconductor layer 19 in which the uneven | corrugated shape 5 is formed in step S8 is considered. Since the wet etching process executed in step S8 has poor controllability compared to dry etching, the pitch and height of the uneven shape 5 formed on the surface of the second semiconductor layer 19 are determined randomly. As a result, in this step S10, it is assumed that the etching amount required until the surface of the first semiconductor layer 15 is exposed in all the regions of the bottom surface of the groove portion 7 is different for each element. For this reason, in each manufactured element, in order to reliably expose the surface of the first semiconductor layer 15 in the entire region of the bottom surface of the groove portion 7, it is necessary to secure a large etching amount in the etching step. . As a result, the supplied etching energy may increase.

  In addition, since the concavo-convex shape 5 is formed on the surface of the semiconductor layer at the start of etching, the input etching energy is easily dispersed in a plane direction parallel to the substrate 11, and the etching does not easily proceed at the beginning of the etching. The etching energy supplied may increase.

  On the other hand, when the groove 7 is formed by etching the second region 4 as in the present embodiment, the upper surface of the second semiconductor layer 19 related to the etching target region is configured to be flat. In addition, the shape of the active layer 17 can be controlled by the thickness of the first semiconductor layer 15 and the pitch and depth of the groove 7. In other words, based on the information such as the thickness of the first semiconductor layer 15 and the pitch and depth of the groove 7 that has been set in the stage before this step S9, the depth of etching is advanced in this step S10. Then, it can be calculated in advance whether the surface of the first semiconductor layer 15 can be exposed. That is, with the method according to the present embodiment, the amount of energy applied during etching can be reduced as compared with the case where the first region 3 is etched.

  This step S10 corresponds to the step (f).

(Step S11)
Next, after the resist 51 formed in Step 10 is lifted off, as shown in FIG. 2J, a resist 53 is formed by patterning on the central portion of the bottom surface of the groove 7 and the upper surface of the second electrode 21. That is, the upper surface of the first semiconductor layer 15 is exposed on the outer periphery of the resist 53 at the bottom surface of the groove portion 7. Thereafter, an insulating layer 54 is formed on the entire surface. The insulating layer 54 can be used _{SiO 2, SiN, Zr 2 O} 3, AlN, Al 2 O 3 or the like.

  Thereafter, as shown in FIG. 2K, the resist 53 is lifted off. At this time, the insulating layer 54 is formed on the inner surface of the groove 7 and a partial upper surface of the second electrode 21.

(Step S12)
A resist 55 is formed on the upper surface of the second electrode 21 by patterning. Thereafter, a conductive material is deposited to fill the groove 7 to form the first electrode 41 (see FIG. 2L). As an example of a method for forming the first electrode 41, Cr having a film thickness of 100 nm and Au having a film thickness of 0.5 to 3 μm are vapor-deposited, followed by annealing at 250 ° C. for about 1 minute in a nitrogen atmosphere. Thereafter, the resist 55 is lifted off (see FIG. 2M).

  Through steps S11 to S12, the first electrode 41 is formed in the groove portion 7 in a state of being electrically insulated from the second electrode 21. Steps S11 to S12 correspond to the step (g).

(Last step)
A protective layer 42 and a bonding layer 43 are formed on the exposed upper surfaces of the first electrode 41 and the second electrode 21, and the element substrate 12 is bonded through the bonding layer 43 (see FIG. 1). A specific example is as follows.

  A protective layer 42 is formed by forming three periods of Ti and Pt with an electron beam vapor deposition apparatus (EB apparatus), and then Ti and Au—Sn solder are vapor-deposited on the upper surface (Pt surface) of the protective layer 42. By doing so, the bonding layer 43 is formed. And the element substrate 12 for applying a voltage with respect to each electrode (41, 21) through this joining layer 43 is bonded together. As the element substrate 12, as described above, a conductive substrate such as CuW, W, and Mo, a semiconductor substrate such as Si, or an insulating substrate such as AlN provided with a wiring pattern can be used.

<Another manufacturing method>
In the above-described method, the step (b) is executed by steps S2 to S4. However, the step (b) can be realized by various methods. Step S5 and subsequent steps are omitted because they are the same as described above.

  The first method is a method in which the step (b2) of growing the third semiconductor layer 13 again from the state shown in FIG. 2C is performed, and then the first semiconductor layer 15 is grown in the same manner as in step S4 (FIG. 2N reference). Before the execution of the step (b2), an uneven surface is formed by the presence of the groove 14 in the first region 3, and the third semiconductor layer 13 grows on the uneven surface, so that at least nonpolarity is formed. A third semiconductor layer 13 having the surface 13a as a growth surface is formed. Therefore, by growing the first semiconductor layer 15 after that, as shown in FIG. 2O, the first semiconductor layer 15 having the growth surface 15a parallel to at least the nonpolar surface is formed.

  In the second method, after performing the step (b4) of growing the first semiconductor layer 15 from the state shown in FIG. 2B, the step (b5) of forming a groove along a predetermined <11-20> direction, for example, is performed. It is a method to execute (refer FIG. 2P). Then, after the execution of the step (b5), the step (b6) of growing the first semiconductor layer 15 is executed again. Before the step (b6) is performed, the first semiconductor layer 15 has an uneven surface, and the first semiconductor layer 15 is regrown on the uneven surface, so that at least non-existing as shown in FIG. 2Q. A first semiconductor layer 15 having a growth surface 15a parallel to the polar surface is formed.

[Second Embodiment]
A second embodiment of the present invention will be described. In the present embodiment, elements common to the first embodiment are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

<Construction>
FIG. 3 is a drawing schematically showing the structure of the semiconductor light emitting device. 3A is a schematic plan view when viewed from the side opposite to the light extraction surface, and FIG. 3B is a cross-sectional view taken along line AA in FIG. It is typical sectional drawing at the time. Elements common to the first embodiment are denoted by the same reference numerals. Since the semiconductor light emitting element 1a of this embodiment does not have a structure having a nonpolar plane as a growth plane, unlike the first embodiment, the Miller index is not displayed in the drawing.

  Also in the semiconductor light emitting device 1a of the present embodiment, as in the first embodiment, the second semiconductor layer 19 has an uneven surface on the side opposite to the active layer 17 in the first region 3. On the other hand, the surface located on the opposite side to the active layer 17 in the second region 4 is a flat surface. The semiconductor light emitting element 1 has a hole 7 in the second region 4, and a first electrode 41 is formed so as to be inserted into the hole 7.

  Also in the semiconductor light emitting device 1a of the present embodiment, the hole 24 is formed by etching as in the first embodiment. As shown in FIG. 3, the etching target surface is formed as a flat surface, so that the etching energy can be uniformly applied to the active layer 17. Therefore, since the hole 7 for inserting the first electrode 41 can be formed with the same size, the electrical characteristics between the manufactured semiconductor light emitting elements 1a are made uniform, and a high yield can be realized.

<Production method>
A method for manufacturing the semiconductor light emitting device 1a according to the second embodiment will be described with reference to FIGS. 3 and 4A to 4E. 4A to 4B and FIGS. 4C (b) to 4E (b), similarly to FIG. 3 (b), the element at each time point is represented by AA in FIG. 3 (a). This corresponds to a schematic cross-sectional view when cut at a position corresponding to a line. 4C (a) to 4E (a) correspond to schematic plan views when the element at each time point is viewed from the side opposite to the light extraction surface, as in FIG. 3 (a). Note that a description of portions common to the first embodiment is omitted.

(Step S21)
As in step S1, the substrate 11 is prepared. As this substrate 11, for example, a sapphire substrate having a (0001) plane can be used. Step S21 corresponds to step (a).

(Steps S22 to S24)
As shown in FIG. 4A, the first semiconductor layer 15, the active layer 17, and the second semiconductor layer 19 are formed on the substrate 11. An example of a specific method is as follows.

(Step S22)
First, a low-temperature buffer layer made of GaN is formed on the surface of the substrate 11, and a base layer made of GaN is further formed thereon. These low-temperature buffer layer and underlayer correspond to the undoped layer 36. A specific method for forming the undoped layer 36 is, for example, as follows. First, the furnace pressure of the МОCVD apparatus is 100 kPa, and the furnace temperature is 480 ° C. Then, while flowing nitrogen gas and hydrogen gas having a flow rate of 5 slm respectively as carrier gases in the processing furnace, TMG having a flow rate of 50 μmol / min and ammonia having a flow rate of 250,000 μmol / min are fed into the processing furnace for 68 seconds. Supply. As a result, a low-temperature buffer layer made of GaN having a thickness of 20 nm is formed on the surface of the substrate 11.

  Next, the furnace temperature of the MOCVD apparatus is raised to 1150 ° C. Then, while flowing nitrogen gas having a flow rate of 20 slm and hydrogen gas having a flow rate of 15 slm as a carrier gas in the processing furnace, TMG having a flow rate of 100 μmol / min and ammonia having a flow rate of 250,000 μmol / min are introduced into the processing furnace as source gases. Feed for 30 minutes. As a result, a base layer made of GaN having a thickness of 1.7 μm is formed on the surface of the low-temperature buffer layer.

Then, the first semiconductor layer 15 is formed on the undoped layer 36. Subsequently, the furnace pressure of the MOCVD apparatus is set to 30 kPa in a state where the furnace temperature is 1150 ° C. Then, while flowing nitrogen gas having a flow rate of 20 slm and hydrogen gas having a flow rate of 15 slm as a carrier gas into the processing furnace, TMG having a flow rate of 94 μmol / min, TMA having a flow rate of 6 μmol / min, and a flow rate of 250,000 μmol / min. Ammonia of min and tetraethylsilane having a flow rate of 0.013 μmol / min are supplied into the processing furnace for 60 minutes. Thereby, for example, the first semiconductor layer 15 having a composition of Al _0.06 Ga _0.94 N, a Si concentration of 5 × 10 ¹⁹ / cm ³ , and a thickness of 2 μm is formed on the undoped layer 36.

  After that, the supply of TMA is stopped, and other source gases are supplied for 6 seconds, whereby a first protective layer made of n-type GaN having a thickness of about 5 nm is formed on the n-type AlGaN layer. The semiconductor layer 15 may be realized.

  In the above description, the case where Si is used as the n-type impurity contained in the first semiconductor layer 15 has been described. However, as the n-type impurity, Ge, S, Se, Sn, Te, or the like can be used in addition to Si. .

  This step S22 corresponds to the step (b).

(Step S23)
Next, an active layer 17 in which a light emitting layer made of, for example, InGaN and a barrier layer made of n-type AlGaN are periodically repeated is formed on the first semiconductor layer 15.

  Specifically, first, the furnace pressure of the MOCVD apparatus is set to 100 kPa, and the furnace temperature is set to 830 ° C. Then, while flowing nitrogen gas having a flow rate of 15 slm and hydrogen gas having a flow rate of 1 slm as a carrier gas in the processing furnace, TMG having a flow rate of 10 μmol / min, TMI having a flow rate of 12 μmol / min, and a flow rate of 300,000 μmol / min. A step of supplying min of ammonia into the processing furnace for 48 seconds is performed. Thereafter, TMG having a flow rate of 10 μmol / min, TMA having a flow rate of 1.6 μmol / min, tetraethylsilane having a flow rate of 0.002 μmol / min, and ammonia having a flow rate of 300,000 μmol / min are supplied into the processing furnace for 120 seconds. Hereinafter, by repeating these two steps, the active layer 17 in which the light-emitting layer made of InGaN having a thickness of 2 nm and the barrier layer made of n-type AlGaN having a thickness of 7 nm are repeated 15 cycles, the first semiconductor layer 15 It is formed in the upper layer.

  This step S23 corresponds to the step (c).

(Step S24)
Next, a second semiconductor layer 19 made of, for example, AlGaN is formed on the active layer 17. A specific method for forming the second semiconductor layer 19 is, for example, as follows.

Specifically, the furnace pressure of the MOCVD apparatus is maintained at 100 kPa, and the furnace temperature is raised to 1025 ° C. while nitrogen gas having a flow rate of 15 slm and hydrogen gas having a flow rate of 25 slm are supplied as carrier gases in the processing furnace. To do. Thereafter, TMG having a flow rate of 35 μmol / min, TMA having a flow rate of 20 μmol / min, ammonia having a flow rate of 250,000 μmol / min, and Cp ₂ Mg having a flow rate of 0.1 μmol / min for doping p-type impurities are used as source gases. Supply to the processing furnace for 60 seconds. Thereby, a hole supply layer having a composition of Al _0.3 Ga _0.7 N having a thickness of 20 nm is formed on the surface of the active layer 33. Thereafter, by changing the flow rate of TMA to 4 μmol / min and supplying the source gas for 360 seconds, a hole supply layer having a composition of Al _0.13 Ga _0.87 N having a thickness of 120 nm is formed. The second semiconductor layer 19 is formed by these hole supply layers.

After that, the supply of TMA is stopped, the flow rate of Cp ₂ Mg is changed to 0.2 μmol / min, and the source gas is supplied for 20 seconds, whereby the thickness is about 5 nm and the p-type impurity concentration is 1 ×. A p-type contact layer of about 10 ²⁰ / cm ³ may be formed. In this case, the second semiconductor layer 19 also includes this p-type contact layer.

  This step S24 corresponds to the step (d).

(Step S25)
An activation process is performed on the wafer. More specifically, activation is performed at 650 ° C. for 15 minutes in a nitrogen atmosphere using an RTA (Rapid Thermal Anneal) device.

(Step S26)
Next, with respect to the exposed surface of the second semiconductor layer 19, the second semiconductor layer 19 in the first region 3 is exposed in a state where the second semiconductor layer 19 in the second region 4 is masked. Soak an alkaline solution such as KOH. Thereby, as shown in FIG. 4B, the uneven shape 5 is formed on the upper surface of the second semiconductor layer 19 only in the first region 3.

  This step S26 corresponds to the step (e). This step S26 may be executed before step S25.

(Step S27)
As shown in FIG. 4C, the second electrode 21 is formed as in step S9. This step S27 corresponds to the step (h).

(Step S28)
As shown in FIG. 4D, the top surface of the first semiconductor layer 15 is etched by etching the surface of the second semiconductor layer 19 located in the second region 4 exposed through the step S27, as in step S10. To expose. In step S28, as in step S10 in the first embodiment, etching is performed on the second semiconductor layer 19 in the second region 4 and the active layer 17 below the second semiconductor layer 19, the upper surface of which is a flat surface. Therefore, the first semiconductor layer 15 can be exposed with an etching amount having the same dimension in the adjacent locations.

  This step S28 corresponds to the step (f).

(Step S29)
As shown in FIG. 4E, the insulating layer 54 and the first electrode 41 are formed by the same method as in steps S11 to S12. This step S29 corresponds to the step (g).

(Last step)
Thereafter, through the same steps as in the first embodiment, a semiconductor light emitting device 1a as shown in FIG. 3 is realized.

  Thereafter, a step of peeling the substrate 11 may be performed. As a more specific example, the substrate 11 is irradiated with a KrF excimer laser from the substrate 11 side with the substrate 11 facing upward and the element substrate 12 facing downward to decompose the interface between the substrate 11 and the epitaxial layer. 11 is peeled off. Thereafter, GaN (undoped layer 36) remaining on the wafer is removed by wet etching using hydrochloric acid or the like, or dry etching using an ICP apparatus, and the first semiconductor layer 15 is exposed. Through this step, the semiconductor light emitting element 1a shown in FIG. 5 is realized. 5A is a schematic plan view as viewed from the light extraction surface side (first semiconductor layer 15 side), and FIG. 5B is a cross-sectional view of the element 1a taken along line AA in FIG. It is typical sectional drawing when doing.

[Another embodiment]
The configuration of another embodiment will be described below.

  <1> In the configuration of the first embodiment, the case where the active layer 17 has the growth surface 17a parallel to the nonpolar surface in both the first region 3 and the second region 4 has been described. However, the active layer 17 may be configured to have a growth surface 17a parallel to the nonpolar surface in at least a part of the region.

  <2> In the first embodiment, the case where the extending direction of the groove 14 is the <11-20> direction has been described as an example, but this is only an example, and the active layer 17 is parallel to the nonpolar plane. As long as it can grow with the growth surface 17a, the extending direction of the groove portion 14 may be another direction.

  <3> In each of the above embodiments, the first semiconductor layer 15 is described as an n-type semiconductor layer, and the second semiconductor layer 19 is described as a p-type semiconductor layer. However, this is merely an example, and the configuration of the above embodiment is described. In other words, the present invention is not intended to exclude the semiconductor light emitting device in which the n-type and the p-type are inverted.

  <4> In each of the above embodiments, the semiconductor light emitting device 1 having a via structure in which the first electrode 41 is formed in the hole 7 has been described. However, for example, by using the second region 4 as an end region of the substrate 11, similarly, a horizontal or flip-chip type semiconductor light emitting device 1 with a high yield can be realized.

1, 1a: Semiconductor light emitting element 3: First region 4: Second region 5: Concave and convex shape 7: Hole / groove (second groove)
11: Substrate 12: Element substrate 13: Third semiconductor layer 14: Groove (first groove)
15: First semiconductor layer 15a: Nonpolar surface of the first semiconductor layer 15b: Polar surface of the first semiconductor layer 17: Active layer 17a: Nonpolar surface of the active layer 17b: Polar surface of the active layer 19: Second semiconductor layer 21: second electrode 24: island region 36: undoped layer 41: first electrode 42: protective layer 43: bonding layer 51: resist 53: resist 54: insulating layer 55: resist

Claims (11)

A substrate,
A first semiconductor layer made of an n-type or p-type nitride semiconductor, formed on an upper layer of the substrate;
An active layer formed on the first semiconductor layer and made of a nitride semiconductor;
Formed on the active layer and made of a nitride semiconductor having a conductivity type different from that of the first semiconductor layer, the surface located on the opposite side of the active layer in the first region includes an uneven surface. On the other hand, in a second region different from the first region, a second semiconductor layer having a flat surface on the side opposite to the active layer,
In the second region, in contact with the first semiconductor layer, comprising a first electrode formed in an insulating state with respect to the active layer and the second semiconductor layer,
In the second region, the active layer and the second semiconductor layer are not formed in an upper layer of the first semiconductor layer located in a region in contact with the first electrode. element. In the second region, there is a hole that penetrates at least the second semiconductor layer and the active layer and reaches the first semiconductor layer,
The first electrode is formed so as to be inserted into the hole and in contact with the first semiconductor layer while maintaining an insulating state with respect to the active layer and the second semiconductor layer. The semiconductor light emitting device according to claim 1.   3. The semiconductor light emitting element according to claim 1, wherein the active layer is made of a nitride semiconductor having a nonpolar plane as a crystal plane.   The active layer is configured so that both the surface located on the first semiconductor layer side and the surface located on the second semiconductor layer side include an uneven surface across the first region and the second region. The semiconductor light emitting element according to claim 3, wherein   In the active layer, both the surface located on the first semiconductor layer side and the surface located on the second semiconductor layer side are flat surfaces across the first region and the second region. The semiconductor light emitting element according to claim 1 or 2. Comprising a second electrode in contact with the second semiconductor layer;
6. The semiconductor according to claim 1, wherein the first electrode is in contact with the first semiconductor layer in an insulated state with respect to the second electrode. Light emitting element. A method for manufacturing a semiconductor light emitting device, comprising:
Preparing a substrate (a);
A step (b) of growing a first semiconductor layer made of an n-type or p-type nitride semiconductor on the upper layer of the substrate;
A step (c) of growing an active layer made of a nitride semiconductor on the first semiconductor layer;
A step (d) of growing a second semiconductor layer made of a nitride semiconductor having a conductivity type different from that of the first semiconductor layer on the active layer;
Forming an uneven shape on at least a part of the upper surface of the second semiconductor layer located in the first region of the upper surface of the second semiconductor layer; and
Etching the second semiconductor layer and the active layer in at least a part of the second region different from the first region to expose the first semiconductor layer on the bottom surface;
And (g) forming the first electrode on at least a part of the upper surface of the first semiconductor layer exposed while being electrically insulated from the second semiconductor layer and the active layer. A method for manufacturing a semiconductor light emitting device. The step (f) is a step of etching the second semiconductor layer and the active layer in at least a part of the second region to form a groove part in which the first semiconductor layer is exposed on the bottom surface. Yes,
The step (g) is a step of forming the first electrode by filling the groove with a conductive material while being electrically insulated from the second semiconductor layer and the active layer. The manufacturing method of the semiconductor light-emitting device according to claim 7.   9. The method of manufacturing a semiconductor light emitting element according to claim 7, wherein the step (b) is a step of growing the first semiconductor layer using a nonpolar plane as a crystal growth plane.   10. The semiconductor light emitting device according to claim 9, wherein the step (b) is a step of growing the first semiconductor layer over the first region and the second region using a nonpolar plane as a crystal growth plane. Device manufacturing method. After the completion of the step (d), before the start of the step (f), the method includes a step (h) of forming a second electrode at least on the second semiconductor layer in the first region,
The semiconductor light emitting element according to claim 7, wherein the step (g) is a step of forming the first electrode in a state of being electrically insulated from the second electrode. Manufacturing method.

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