TWI545798B - Nitride semiconductor light emitting device and manufacturing method thereof - Google Patents

Description

Nitride semiconductor light-emitting element and method of manufacturing same

The present invention relates to a nitride semiconductor light-emitting element and a method of manufacturing the same.

The III-V compound semiconductor (III-nitride semiconductor) containing nitrogen has a band gap energy equivalent to the energy of light having a wavelength from the infrared region to the ultraviolet region. Therefore, the group III nitride semiconductor can be used as a material for emitting a light-emitting element having light having a wavelength from an infrared region to an ultraviolet region, or as a material for receiving a light-receiving element having light having a wavelength from an infrared region to an ultraviolet region.

Further, the bonding between the atoms constituting the group III nitride semiconductor is strong, and the breakdown breakdown voltage of the group III nitride semiconductor is high, and the saturation electron velocity is large. Thereby, the group III nitride semiconductor can also be used as a material of an electronic device such as a high temperature resistant, high output, high frequency transistor, or the like. Furthermore, Group III nitride semiconductors have attracted attention as materials that are easy to handle because they hardly harm the environment.

In the nitride semiconductor light-emitting device using the group III nitride semiconductor, a quantum well structure is generally used as the light-emitting layer. When a voltage is applied to the nitride semiconductor light-emitting element, electrons and holes are recombined in the well layer constituting the light-emitting layer to generate light. The luminescent layer can also be a single quantum well (SQW) structure or a multiple quantum well (MQW) structure in which the well layer and the barrier layer are alternately stacked.

In order to manufacture a practical nitride semiconductor light-emitting device using a Group III nitride semiconductor as the above-described excellent material, it is necessary to form a film (Group III nitride semiconductor layer) containing a Group III nitride semiconductor on a specific substrate, and form a specific one. Component construction.

Here, as the substrate, a substrate containing a group III nitride semiconductor having a lattice constant or a thermal expansion coefficient which allows the group III nitride semiconductor layer to directly grow on the substrate is preferably used. As the substrate including the group III nitride semiconductor, for example, a gallium nitride (GaN) substrate or the like can be exemplified. However, the GaN substrate is not practical in the current state because it has a small size of 2 inches or less and is extremely expensive. Therefore, in the current state of the art, a substrate for manufacturing a nitride semiconductor light-emitting device is a sapphire substrate or a tantalum carbide (SiC) substrate having a large difference in lattice constant and a large difference in thermal expansion coefficient from the group III nitride semiconductor.

There is a difference in lattice constant of about 16% between sapphire and GaN (a representative example of a group III nitride semiconductor). There is a difference in lattice constant of about 6% between SiC and GaN. When a difference in lattice constant of such a size exists between the substrate material and the group III nitride semiconductor grown on the substrate, it is generally difficult to crystallize the crystal containing the group III nitride semiconductor on the substrate. For example, when GaN crystals are directly epitaxially grown on a sapphire substrate, there is a problem in that three-dimensional growth of GaN crystals cannot be avoided, and GaN crystals having a flat surface cannot be obtained.

Therefore, between the substrate and the group III nitride semiconductor layer, a layer called a buffer layer for eliminating a difference in lattice constant between the substrate material and the group III nitride semiconductor is generally formed.

For example, in JP-A No. 2-229476, a buffer layer containing AlN is formed on a sapphire substrate by an organometallic vapor phase growth method (MOVPE method), and then Al _x Ga _1-x N is included. A method of growing a nitride semiconductor layer.

In order to grow a high-quality nitride semiconductor film, the nitride semiconductor film is grown from the convex portion of the substrate to the concave portion of the substrate in order to grow the high-quality nitride semiconductor film.

A method of growing a group III nitride semiconductor layer as described below is described in Japanese Laid-Open Patent Publication No. 2006-352084. First, a sapphire substrate subjected to embossing processing is prepared. Secondly, the epitaxial growth of GaN is started from the bottom surface of the concave portion of the sapphire substrate, and The GaN is grown so that the bottom surface is a base and the cross-sectional shape of the equilateral triangle having a crystal plane inclined with respect to the main surface of the sapphire substrate. Then, if the growth conditions are set under the conditions of growth in the lateral direction and continue to grow, the GaN layer is increased in thickness and spread over the convex portion of the sapphire substrate, and then the GaN layers growing from the concave portions of the adjacent sapphire substrate are mutually grown. Contacted on the convex portion of the sapphire substrate.

In the case of arranging a specific convex portion on a substrate and growing the underlayer, the crystal growth film having excellent crystallinity at the initial stage of crystal growth is obtained, and an excellent epitaxial film is produced. Template substrate. In the case of forming a light-emitting layer using a template substrate having excellent crystallinity, it is possible to produce a high-output semiconductor light-emitting device having excellent light extraction efficiency.

When manufacturing a semiconductor light-emitting device according to the method described in International Publication No. 2011/074534, it is necessary to change the film forming apparatus or transfer between the film forming apparatuses such as the template substrate from the manufacturing step of the template substrate to the next step. . At this time, the template substrate or the like is exposed to a gas such as air, oxygen, nitrogen, hydrogen or argon. Further, the template substrate or the like is subjected to some thermal processes such as temperature reduction to a temperature suitable for transport. Therefore, formation of a natural oxide film or the like, excessive doping of an n-type dopant, or concentration of lattice defects is likely to occur at the boundary surface where the manufacturing method is changed. Thereby, the film quality of the nitride semiconductor layer formed on the boundary surface is deteriorated. Further, in the manufactured semiconductor light-emitting device, an increase in leakage current or a decrease in electrostatic withstand voltage is caused. Based on these defects, a method of reducing the above-described natural oxide film by forming an n-type nitride semiconductor layer on a template substrate at a high temperature of 1000 ° C or higher by using a mixed gas atmosphere of H ₂ and NH ₃ is used.

However, if the n-type nitride semiconductor layer is formed at a high temperature of 1000 ° C or higher, the temperature lowering step after the formation of the n-type nitride semiconductor layer takes a long time. Therefore, the processing capacity per unit time (processing amount: Throughput) is reduced. Moreover, due to the high temperature treatment, a strong and large amount of deposits adhere to the chamber of the film forming apparatus, so the film formation must be frequently maintained. Device.

The present invention has been made in view of the above, and an object thereof is to improve the productivity of a nitride semiconductor light-emitting device.

The inventors of the present invention have found that the characteristics of the nitride semiconductor light-emitting device are not increased even when the n-type nitride semiconductor layer is grown at a temperature lower than the temperature at which the template substrate is formed, after the formation of the template substrate at a high temperature. Deterioration. That is, it is found that after the formation of the template substrate, after the temperature is lowered to a temperature lower than the growth temperature of the n-type nitride semiconductor layer (preferably 100 ° C or lower), the temperature is increased to form an n-type nitride semiconductor layer. The deterioration of the characteristics of the obtained nitride semiconductor light-emitting element can be prevented, and the productivity of the nitride semiconductor light-emitting element can be improved. Further, after the temperature is lowered to a temperature lower than the growth temperature of the n-type nitride semiconductor layer, the template substrate is temporarily taken out from the chamber of the growth device, and the template substrate is placed in a different chamber to form the same. It is effective to form an n-type nitride semiconductor layer at a temperature lower than the temperature of the template substrate.

The nitride semiconductor light-emitting device of the present invention includes: a first laminate including one or more first n-type nitride semiconductor layers; and a second n-type nitride semiconductor layer including a first surface of the first laminate. A laminate, a light-emitting layer provided on the second laminate, and a p-type nitride semiconductor layer provided on the light-emitting layer. The second n-type nitride semiconductor layer is formed at a lower temperature than the temperature at which the first n-type nitride semiconductor layer is formed.

In the nitride semiconductor light-emitting device of the present invention, the formation temperature of the second n-type nitride semiconductor layer is lower than the formation temperature of the first n-type nitride semiconductor layer. Therefore, since the time required for the temperature lowering step after the formation of the second n-type nitride semiconductor layer can be shortened, a high processing amount can be maintained. Moreover, the amount of deposits adhering to the chamber of the apparatus for forming the second n-type nitride semiconductor layer is reduced as compared with the case where the formation temperature of the second n-type nitride semiconductor layer is high. Thereby, the frequency of the apparatus for forming the second layered body (the second layered body including the second n-type nitride semiconductor layer) is maintained. For these reasons, the productivity of the nitride semiconductor light-emitting element becomes high.

The second layered body is preferably between the second n-type nitride semiconductor layer and the light-emitting layer, and further includes one or more third n-type nitride semiconductor layers. The third n-type nitride semiconductor layer is preferably formed at a temperature lower than the formation temperature of the second n-type nitride semiconductor layer.

The semiconductor layer constituting the first surface of the first layered body is preferably an undoped layer. In this case, the second n-type nitride semiconductor layer is preferably a doped layer.

The semiconductor layer constituting the first surface of the first layered body is preferably a doped layer. In this case, the second n-type nitride semiconductor layer is preferably an undoped layer.

The method for producing a nitride semiconductor light-emitting device according to the present invention includes at least a step of forming a first layered body including a first n-type nitride semiconductor layer of one or more layers, and forming a layer including the first surface of the first layered body. a step of forming a second layered body of the second n-type nitride semiconductor layer; a step of forming a light-emitting layer on the second layered body; and a step of forming a p-type nitride semiconductor layer on the light-emitting layer. The second n-type nitride semiconductor layer is formed at a lower temperature than the temperature at which the first n-type nitride semiconductor layer is formed. After the step of forming the first layered body and before the step of forming the second layered body, a step of lowering the temperature to a temperature lower than the temperature at which the second layered body is formed is further included.

In the method for producing a nitride semiconductor device of the present invention, the formation temperature of the second n-type nitride semiconductor layer which is in contact with the first surface of the first layered body is lower than the formation temperature of the first n-type nitride semiconductor layer. Further, before the step of forming the first layered body and before the step of forming the second layered body, the temperature is lowered to a temperature lower than the temperature at which the second layered body is formed. Based on this, since the time required for the temperature lowering step after the formation of the second n-type nitride semiconductor layer can be shortened, a high processing amount can be maintained. Moreover, the amount of deposits adhering to the chamber in which the second n-type nitride semiconductor layer is formed is reduced as compared with the case where the formation temperature of the second n-type nitride semiconductor layer is high. Thereby, the frequency of the apparatus for forming the second layered body (the second layered body including the second n-type nitride semiconductor layer) is maintained. As described above, the productivity of the nitride semiconductor light-emitting element becomes high.

After the step of forming the first layered body and before the step of forming the second layered body, it is preferred to It includes a step of exposing the first laminate to the atmosphere.

The above and other objects, features, aspects and advantages of the present invention will become apparent from

1‧‧‧Nitride semiconductor light-emitting elements

3‧‧‧Substrate

3a‧‧‧ convex

3b‧‧‧ recess

3t‧‧‧imaginary triangle

5‧‧‧buffer layer

6‧‧‧1st laminate

7‧‧‧ basal layer

8‧‧‧n type contact layer

8A‧‧‧n type contact layer

8B‧‧‧n type contact layer

9‧‧‧n type modulation doping layer

9A‧‧‧n ⁺ layer

9B‧‧‧n ^- layer

10‧‧‧V pit generation layer

11‧‧‧2nd layered body

14‧‧‧Lighting layer

14A‧‧‧Baffle

14A0~14A7‧‧‧Baffle layer

14AZ‧‧ ‧ barrier layer

14W~14W2‧‧‧ Well

15‧‧‧V pit

16‧‧‧p-type nitride semiconductor layer

17‧‧‧p-type nitride semiconductor layer

18‧‧‧p-type nitride semiconductor layer

21‧‧‧n side electrode

23‧‧‧Transparent electrode

25‧‧‧p side electrode

27‧‧‧Transparent protective film

30‧‧‧Face

61‧‧‧1st

71‧‧‧1st basal layer

71a‧‧‧Sloping facets

71b‧‧‧ upper surface

75‧‧‧2nd basal layer

75b‧‧‧ upper surface

121‧‧‧Multilayer structure

121A‧‧‧ nitride semiconductor layer

121B‧‧‧ nitride semiconductor layer

122‧‧‧Superlattice layer

122A‧‧‧ wide band gap layer

122B‧‧‧Narrow band gap layer

123‧‧‧Undoped nitride semiconductor layer

124‧‧‧n type nitride semiconductor layer

Eg‧‧‧ band gap energy

Fig. 1 is a schematic cross-sectional view showing a nitride semiconductor light-emitting device according to an embodiment of the present invention.

Fig. 2 is a schematic plan view showing a nitride semiconductor light-emitting device shown in Fig. 1;

Fig. 3 is an energy diagram schematically showing the magnitude of the band gap energy Eg of the n-type contact layer to the p-type nitride semiconductor layer of the nitride semiconductor light-emitting device shown in Fig. 1.

4 is an enlarged plan view showing a substrate of the nitride semiconductor light-emitting device shown in FIG. 1.

5(a) is a graph showing a temperature distribution of a manufacturing step of the nitride semiconductor light-emitting device shown in FIG. 1, and FIG. 5(b) is a graph showing a temperature distribution of a manufacturing step of the nitride semiconductor light-emitting device of Comparative Example 1. .

Fig. 6 is a schematic cross-sectional view showing a nitride semiconductor light-emitting device of a sixth embodiment.

Fig. 7 is an energy diagram schematically showing the magnitude of the band gap energy Eg of the n-type contact layer to the p-type nitride semiconductor layer of the nitride semiconductor light-emitting device shown in Example 6.

Hereinafter, the nitride semiconductor light-emitting device of the present invention will be described using a schematic diagram. In the drawings, the same reference numerals are used to refer to the same or equivalent parts. Further, the dimensional relationship of the length, the width, the thickness, the depth, and the like is appropriately changed in order to clarify and simplify the drawing, and does not indicate the actual size relationship.

Hereinafter, in order to show the positional relationship, the portion described on the lower side in FIG. 1 is referred to as "lower", and the portion described on the upper side in FIG. 1 is referred to as "upper". This is an indication of the simplicity of the diagram, which is different from the "up" and "down" depending on the direction of gravity.

The "barrier layer" is the layer that is sandwiched by the well layer. The barrier layer that is not sandwiched by the well layer is expressed as the "initial barrier layer" or the "last barrier layer", and the barrier that is sandwiched by the well layer The layer changes the expression.

The "dopant concentration" and the concentration of electrons or holes generated by doping with an n-type dopant or a p-type dopant are "carrier concentration". These relationships will be described later.

The "carrier gas" is a gas other than the group III source gas, the group V source gas, and the dopant source gas. The atoms constituting the carrier gas are not taken into the film or the like.

The "n-type nitride semiconductor layer" may also include an n-type layer or an undoped layer having a low carrier concentration which is practically not to impede the extent of electron flow. The "p-type nitride semiconductor layer" may also include a p-type layer or an undoped layer having a low carrier concentration which is practically not inhibiting the thickness of the hole. The term "practical does not hinder" means that the operating voltage of the nitride semiconductor light-emitting element is a practical level.

<Configuration of Nitride Semiconductor Light Emitting Element>

1 and 2 are a schematic cross-sectional view and a schematic plan view of a nitride semiconductor light-emitting device 1 according to an embodiment of the present invention. Fig. 1 is a cross-sectional view corresponding to the I-I line shown in Fig. 2. 3 is an energy diagram schematically showing the magnitude of the band gap energy Eg of the n-type contact layer 8 to the p-type nitride semiconductor layer 16 of the nitride semiconductor light-emitting element 1 shown in FIG. 1. The vertical axis direction of Fig. 3 indicates the upper and lower directions of the nitride semiconductor light-emitting element 1 shown in Fig. 1, and the Eg of the horizontal axis of Fig. 3 schematically indicates the magnitude of the band gap energy in each layer. In FIG. 3, a small dot is indicated on the right side of the layer doped with the n-type dopant and described as "n". 4 is an enlarged plan view showing a substrate 3 of the nitride semiconductor light-emitting device 1 shown in FIG. 1.

The nitride semiconductor light-emitting device 1 shown in FIG. 1 includes a first layered body 6, a second layered body 11, a light-emitting layer 14, and p-type nitride semiconductor layers 16, 17, and 18. In the present embodiment, a portion in which the substrate 3, the buffer layer 5, the underlayer 7, the n-type contact layer 8, and the n-type modulation doping layer 9 are laminated is referred to as a first layered body 6, and V-concave The portion in which the pit generating layer 10, the multilayer structure 121, and the superlattice layer 122 are laminated is referred to as a second laminated body 11 so as to be distinguished from each other.

In this embodiment, at least one of the n-type contact layer 8 and the n-type modulation doping layer 9 In the "1n-type nitride semiconductor layer" in the patent application, the V-pit generation layer 10 corresponds to the "2n-type nitride semiconductor layer" in the patent application, and constitutes the multilayer structure 121 and the superlattice layer. At least one of the layers of at least one of 122 corresponds to the "3n-type nitride semiconductor layer" in the patent application.

The present invention is characterized in that the formation of the n-type nitride semiconductor layer is separated into two stages, and in the subsequent formation step, the n-type nitride semiconductor layer can be formed without performing high-temperature processing which is the main cause of the reduction in the amount of processing. aspect. Further, it is important that the layer initially formed as the second layered body 11 is an n-type nitride semiconductor layer formed at a low temperature. Therefore, in the present invention, the layer which is first formed as the second layered body 11 is not limited to the layer which functions as the V-pit generation layer 10, and is not limited to the layer formed after the V-pit generation layer 10 as a plurality of layers. Each of the structure 121 and the superlattice layer 122 functions as a layer. However, in the present invention, the layer which is initially formed as the second layered body 11 functions as a layer of the V-pit generation layer 10, and is formed as a multilayer structure 121 and super after the V-pit generation layer 10. The lattice layer 122 functions as a layer, and the synergistic effect of the combination can be expected.

One portion of the first layered body 6, the second layered body 11, the light-emitting layer 14, and the p-type nitride semiconductor layers 16, 17, 18 are etched to constitute the mesa portion 30. On the p-type nitride semiconductor layer 18, a p-side electrode 25 is provided through the transparent electrode 23. On the outer side of the mesa portion 30 (on the right side of FIG. 1), a portion of the upper surface of the n-type contact layer 8 is exposed from the n-type modulation doped layer 9 or the like, and an n-side electrode 21 is provided on the exposed surface of the n-type contact layer 8. . The transparent protective film 27 covers the transparent electrode 23 and the side faces of the respective layers exposed by etching, and exposes the n-side electrode 21 and the p-side electrode 25.

When the cross section of the nitride semiconductor light-emitting device 1 was observed by a super high-magnification STEM (Scanning Transmission Electron Microscopy), it was confirmed that the V-pit 15 was generated. In the nitride semiconductor light-emitting device 1 of the present embodiment, the V-pit generation layer 10 is provided to control the generation of the V-pits 15.

<1st laminated body>

In the present embodiment, the first layered body 6 includes the substrate 3, the buffer layer 5, and the base layer 7, The n-type contact layer 8 and the n-type modulation doping layer 9 may include at least one of the n-type contact layer 8 and the n-type modulation doping layer 9. The nitride semiconductor light-emitting device 1 of the present embodiment may not include the substrate 3. In this case, the first layered body 6 includes the under layer 7, the n-type contact layer 8, and the n-type modulation doping layer 9.

The first layered body 6 has a first surface 61. The first surface 61 means the surface of the first layered body 6 and is connected to the surface of the V-pit generation layer 10 (the second n-type nitride semiconductor layer). The first layered body 6 of the present embodiment is formed by sequentially laminating the buffer layer 5, the underlying layer 7, the n-type contact layer 8, and the n-type modulation doping layer 9 on the substrate 3. Therefore, the first surface 61 corresponds to n. The upper surface of the type modulation doping layer 9 (the surface of the n-type modulation doping layer 9 on the opposite side to the interface between the n-type contact layer 8 and the n-type modulation doping layer 9).

The semiconductor layer constituting the first surface 61 is preferably an undoped layer (for example, n ^- layer 9B described below). In this case, the V-pit generation layer 10 is preferably a doped layer. In the present specification, the "semiconductor layer constituting the first surface 61" corresponds to the layer which is the farthest from the n-type contact layer 8 among the two or more layers constituting the n-type modulation doping layer 9. An "undoped layer" means not only a layer that is completely undoped with a conductive dopant, but also a layer that is unintentionally doped with a conductive dopant during crystal growth. That is, the undoped layer may include, for example, a conductive dopant of 0 cm ^-3 or more and 3 × 10 ¹⁸ cm ^-3 or less. By "doped layer" is meant a layer that is intentionally doped with a conductive dopant during crystal growth. The doped layer preferably contains, for example, a conductive dopant of 1 × 10 ¹⁹ cm ^-3 or more.

The semiconductor layer constituting the first surface 61 may be a doped layer (for example, the n ⁺ layer 9A described below). In this case, the V-pit generation layer 10 may also be an undoped layer.

<Substrate>

The substrate 3 may be an insulating substrate such as a sapphire substrate or a conductive substrate including GaN, SiC or ZnO. The thickness of the substrate 3 is preferably 900 μm or more and 1200 μm or less when the nitride semiconductor layer is grown, and is preferably 50 μm or more and 300 μm or less in the nitride semiconductor light-emitting device 1 to be produced. That is, the method of manufacturing the nitride semiconductor light-emitting device 1 may include the step of polishing the substrate 3. Further, a nitride semiconductor light-emitting element The manufacturing method of 1 may also include the step of removing the substrate 3.

The surface of the substrate 3 on which the buffer layer 5 or the like is provided (the upper surface of the substrate 3) preferably has an uneven shape in which the convex portion 3a and the concave portion 3b are alternately formed as shown in FIG. The convex portion 3a preferably has a slightly circular shape in the upper surface of the substrate 3 as shown in FIG. 4, and is preferably disposed at the apex of the imaginary triangle 3t as shown in FIG. The interval between the apexes of the adjacent convex portions 3a (one side of the imaginary triangle 3t shown in Fig. 4) is preferably 1 μm or more and 5 μm or less. The convex portion 3a may also have a trapezoidal shape when viewed from the side, and the apex of the convex portion 3a is preferably rounded as shown in FIG.

<buffer layer>

The buffer layer 5 is provided on the convex portion 3a of the substrate 3 and on the concave portion 3b thereof. The buffer layer 5 is preferably, for example, a layer of Al _so Ga _to O _uo N _1-uo (0≦s0≦1, 0≦t0≦1, 0≦u0≦1, s0+t0≠0), more preferably an AlN layer or AlON layer. When the buffer layer 5 is an AlON layer, a very small portion (0.5 to 2%) of N in the AlON layer is replaced with oxygen. Thereby, since the buffer layer 5 is formed so as to be elongated in the normal direction of the growth surface of the substrate 3, the buffer layer 5 including the aggregate of the uniform columnar crystals of the crystal grains is obtained. The thickness of the buffer layer 5 is not particularly limited, but is preferably 3 nm or more and 100 nm or less, and more preferably 5 nm or more and 50 nm or less. When the buffer layer 5 is an AlON layer formed by a sputtering method, the half value width of the peak appearing in the X-ray spectrum (the index of the crystal quality of the underlayer 7) is narrowed. Thereby, the buffer layer 5 is preferably an AlON layer formed by sputtering.

<base layer>

The base layer 7 preferably has a first base layer 71 and a second base layer 75. Thereby, the half value width of the peak appearing in the X-ray spectrum (the index of the crystal quality of the underlayer 7) is narrowed, that is, the crystal quality of the underlayer 7 becomes high. The first base layer 71 is provided on the concave portion 3b of the substrate 3 via the buffer layer 5, and preferably has a shape in which the side surface including the inclined crystal surface 71a is slightly triangular, and may have an upper surface 71b. The "inclined crystal face" is a surface extending in a direction inclined by an angle of 10 degrees or more with respect to the concave portion 3b of the substrate 3, and is preferably a nitride semiconductor crystal face. The second base layer 75 covers the first base layer 71 and covers the convex portion 3 a of the substrate 3 via the buffer layer 5 , and is in contact with the buffer layer 5 and the first base layer 71 . The surface of the base layer 7 that is in contact with the n-type contact layer 8 (base layer 7) The upper surface 75b) is flat. In the present specification, the first base layer 71 and the second base layer 75 are collectively shown as the base layer 7 unless otherwise specified.

The first base layer 71 preferably contains, for example, Al _x2 Ga _y2 In _z2 N (0≦x2≦1, 0≦y2≦1, 0≦z2≦1, x2+y2+z2≠0). The second underlayer 75 preferably includes, for example, Al _x3 Ga _y3 In _z3 N (0≦x3≦1, 0≦y3≦1, 0≦z3≦1, x3+y3+z3≠0).

Each of the first underlayer 71 and the second underlayer 75 is preferably a nitride semiconductor layer containing Ga as a group III element. Thereby, the first underlayer 71 and the second underlayer 75 can be formed without continuing the crystal defects such as the dislocation in the buffer layer 5 including the aggregate of the columnar crystals. In order to provide the first base layer 71 and the second base layer 75 without continuing the crystal defects in the buffer layer 5, it is necessary to form a misalignment ring in the vicinity of the interface with the buffer layer 5 (the upper surface of the buffer layer 5). When the first underlayer 71 and the second underlayer 75 are Group III nitride semiconductor layers containing Ga, a misaligned loop is likely to occur in the vicinity of the interface with the buffer layer 5. In other words, when the first underlayer 71 and the second underlayer 75 are nitride semiconductor layers containing Ga as a group III element, crystal defects in the buffer layer 5 are cyclized and sealed in the vicinity of the interface with the buffer layer 5. Thereby, it is possible to prevent the crystal defects in the buffer layer 5 from continuing to the first base layer 71 and the second base layer 75. For example, the first underlayer 71 includes Al _x2 Ga _y2 N (0≦x2<1, 0<y2<1), and the second underlayer 75 includes Al _x3 Ga _y3 N (0≦x3<1, 0<y3<1) In the case where GaN is included in each of the first underlayer 71 and the second underlayer 75, the crystal defects in the buffer layer 5 are easily cyclized and sealed near the interface with the buffer layer 5. Thereby, the first underlayer 71 and the second underlayer 75 having a good crystal quality with a small dislocation density are obtained.

The first underlayer 71 and the second underlayer 75 may include, for example, an n-type dopant of 1 × 10 ¹⁷ cm ^-3 or more and 1 × 10 ¹⁹ cm ^-3 or less. The n-type dopant contained in the underlayer 7 is preferably at least one of Si, Ge, and Sn, and more preferably Si. In the case where the n-type dopant is Si, the material gas of the n-type dopant is preferably, for example, decane or decane. However, from the viewpoint of maintaining good crystal quality, the first underlayer 71 and the second underlayer 75 are preferably undoped layers, respectively.

The thickness of the base layer 7 (the surface of the base layer 7 and the base layer 7 which are in contact with the recess 3b of the substrate 3) The distance between the upper surfaces 75b) is not particularly limited. If the thickness of the base layer 7 is large, the crystal defects in the base layer 7 are smaller. However, if the thickness of the underlayer 7 is as large as a certain level or more, the effect of reducing the crystal defects in the underlayer 7 may be saturated. For these reasons, the thickness of the underlayer 7 is preferably 1 μm or more and 8 μm or less, more preferably 3 μm or more and 5 μm or less.

The method of forming the first underlayer 71 and the second underlayer 75 is preferably MOCVD (Metal Organic Chemical Vapor Deposition). The first underlayer 71 preferably grows in a crystal growth mode in which the inclined crystal faces 71a are formed. Thereby, the first underlayer 71 having few crystal defects and high crystal quality is formed. The second base layer 75 is preferably grown in an embedded growth mode in which the inclined crystal face 71a can be embedded and the flat upper surface 75b is formed. Thereby, the second underlayer 75 having the flat upper surface 75b and having few crystal defects and high crystal quality is formed.

The growth temperature of the first underlayer 71 and the second underlayer 75 is preferably 800° C. or higher and 1250° C. or lower, and more preferably 900° C. or higher and 1150° C. or lower. Thereby, the first underlayer 71 and the second underlayer 75 having few crystal defects and excellent crystal quality can be formed. In the present specification, "growth temperature" means the temperature of the substrate 3 when the layer is crystal grown.

<n type contact layer>

The n-type contact layer 8 is provided on the upper surface 75b of the second base layer 75. The n-type contact layer 8 is preferably doped with, for example, a layer of Al _s2 Ga _t2 In _u2 N (0≦s2≦1, 0≦t2≦1, 0≦u2≦1, s2+t2+u2≒1). The layer of the type dopant is more preferably doped with an n-type layer in the layer of Al _s2 Ga _1-s2 N (0≦s2≦1, preferably 0≦s2≦0.5, more preferably 0≦s2≦0.1). A layer of dopants. The n-type contact layer 8 may further comprise an undoped layer or a low carrier concentration layer or the like.

The n-type dopant contained in the n-type contact layer 8 is not particularly limited, but is preferably Si, P, As or Sb, and more preferably Si. The n-type dopant concentration of the n-type contact layer 8 is not particularly limited, but is preferably 1 × 10 ¹⁹ cm ^-3 .

The thicker the n-type contact layer 8 is, the lower the resistance of the n-type contact layer 8 becomes. however, If the thickness of the n-type contact layer 8 is too large, the manufacturing cost of the nitride semiconductor light-emitting element 1 is increased. The maximum thickness of the n-type contact layer 8 is preferably 1 μm or more and 10 μm or less, based on both.

The configuration of the n-type contact layer 8 is not particularly limited. For example, the n-type contact layer 8 may be formed as a single layer by continuously forming the n-type contact layer 8A and the n-type contact layer 8B. The n-type contact layer 8 may also include three or more n-type nitride semiconductor layers. When the n-type contact layer 8 includes two or more n-type nitride semiconductor layers, the two or more n-type nitride semiconductor layers may have the same composition or may have different compositions. Further, the two or more n-type nitride semiconductor layers may have the same thickness or may have different thicknesses.

<Modulated doped layer>

The n-type modulation doped layer 9 is preferably provided on the n-type contact layer 8, and is formed by, for example, alternately stacking the n ⁺ layer 9A and the n ^- layer 9B. The "modulation-doped layer" means a layer in which two or more layers of different amounts of dopants are alternately laminated.

The n ⁺ layer 9A is preferably an Al _s3 Ga _t3 In _u3 N having an n-type dopant concentration of 1.0 × 10 ¹⁹ cm ^-3 or more (0≦s3≦1, 0≦t3≦1, 0≦u3≦1, s3) The +t3+u3≒1) layer is more preferably a GaN layer having an n-type dopant concentration of 1.0 × 10 ¹⁹ cm ^-3 or more. The n-type dopant is not particularly limited, and is preferably Si, P, As or Sb, etc., more preferably Si.

The n ^- layer 9B is preferably a nitride semiconductor layer having a lower n-type dopant concentration than the n ⁺ layer 9A, more preferably an Al _s4 Ga having an n-type dopant concentration of 3 × 10 ¹⁸ cm ^-3 or less. _T4 In _u4 N (0≦s4≦1, 0≦t4≦1, 0≦u4≦1, s4+t4+u4≒1) layer, and more preferably an undoped layer. For example, the n ^- layer 9B is preferably a GaN layer having an n-type dopant concentration of 3 × 10 ¹⁸ cm ^-3 or less, more preferably an undoped GaN layer.

The number of layers of each of the n ⁺ layer 9A and the n ^- layer 9B is not particularly limited. The n-type modulation doped layer 9 may have a combination of two or more n ⁺ layers 9A and n ^- layers 9B, or may include only one layer of n ^- layer 9B.

The thickness of each of the n ⁺ layers 9A is preferably, for example, 5 nm or more and 500 nm or less. The thickness of each of the n ^- layers 9B is preferably, for example, 5 nm or more and 500 nm or less.

<2nd laminated body>

The second layered body 11 includes a V-pit generation layer 10, a multilayer structure 121, and a superlattice layer 122. The V-pit generation layer 10 is preferably formed at a temperature lower than the formation temperature of the first laminate body 6, for example, preferably higher than the growth temperature of the n-type contact layer 8 or the n-type modulation doping layer 9 (formation of the first n-type) The temperature of the nitride semiconductor layer is formed at a low temperature.

The layer in contact with the first layered body 6 is more preferably formed at 950 ° C or lower. Thereby, when the V-pit generation layer 10 is in contact with the first layered body 6, the V-pit generation layer 10 is more preferably formed at 950 ° C or lower.

When the second layered body 11 is composed of a plurality of layers having different compositions (for example, when the second layered body 11 is composed of the V-pit generating layer 10, the multilayered structure 121, and the superlattice layer 122), and the first layered body The 6-joined layer is further preferably formed at a temperature of 850 ° C or lower. Therefore, when the V-pit generation layer 10 is in contact with the first layered body 6, the V-pit generation layer 10 is further preferably formed at 850 ° C or lower.

As described above, since the time required for the temperature lowering step after the formation of the second layered body 11 can be shortened, a high throughput can be maintained. Further, the amount of adhering matter adhering to the chamber of the apparatus for forming the V-pit generation layer 10 is reduced as compared with the case where the growth temperature of the V-pit generation layer 10 is high. Thereby, the frequency of maintaining the apparatus for forming the second layered body 11 is lowered. For these reasons, the productivity of the nitride semiconductor light-emitting element 1 becomes high. The V-pit generation layer 10 is more preferably formed at a temperature of 700 ° C or higher, and more preferably formed at a temperature of 750 ° C or higher. Thereby, the luminous efficiency of the higher MQW light-emitting layer 14 can be maintained.

In the following, as a configuration of the second layered product 11, the second layered body 11 is provided with a V-pit generation layer 10, a multilayer structure 121, and a superlattice layer 122. However, the configuration of the second layered body 11 is not limited to the configuration shown below. For example, the second layered body 11 may include a single layer, and may also include a plurality of layers having different impurity concentrations or compositions.

The multilayer structure 121 is preferably formed at a temperature lower than the growth temperature of the V-pit generation layer 10, and more preferably formed at the same temperature as the growth temperature of the V-pit generation layer 10. Multilayer construction When the growth temperature of the body 121 is equal to or lower than the growth temperature of the V-pit generation layer 10, the effect of increasing the size of the V-pit 15 is obtained. The "the temperature at which the multilayer structure 121 is formed at a temperature lower than the growth temperature of the V-pit generation layer 10" means that the growth temperature of the multilayer structure 121 is (the growth temperature of the V-pit generation layer -250 ° C) or more and the V-pit The growth temperature of the layer 10 is not more than the growth temperature of the layer 10, and the growth temperature of the multilayer structure 121 is preferably (the growth temperature of the V-pit layer 10 is -150 ° C) or more and the growth temperature of the V-pit generation layer 10 is not more than the growth temperature. The "multilayer structure 121 is formed at the same temperature as the growth temperature of the V-pit generation layer 10" means that the growth temperature of the multilayer structure 121 is (the growth temperature of the V-pit generation layer 10 is ±10 ° C). The above can also be said to be the growth temperature of the superlattice layer 122.

When the growth temperature of the multilayer structure 121 is equal to or lower than the growth temperature of the V-pit generation layer 10, the effect of increasing the size of the V-pit 15 can be obtained. However, if the growth temperature of the multilayer structure 121 is too low, the film quality of the multilayer structure 121 is lowered. Therefore, the growth temperature of the multilayer structure 121 is preferably 600 ° C or higher, and more preferably 700 ° C or higher. This can also be said to be the growth temperature of the superlattice layer 122. Hereinafter, the constituent elements of the second layered body 11 are respectively shown.

<V pit generation layer>

The V-pit generation layer 10 is in contact with the first surface 61 of the first layered body 6 to form a layer of the V-pit 15 so that the average position of the starting point of the V-pit 15 is more effective than the function as a light-emitting layer. The layer (in the present embodiment, the light-emitting layer 14) is located further in the layer on the side of the first layered body 6 (in the present embodiment, the superlattice layer 122). The "starting point of the V-pit 15" means the bottom of the V-pit 15 (the lowermost end of the V-pit 15 in Fig. 1). The "average position of the starting point of the V-pit 15" means a position obtained by averaging the starting point of the V-pit 15 in the thickness direction of the nitride semiconductor light-emitting element 1 (vertical direction in FIG. 1).

The V-pit generation layer 10 is preferably, for example, a highly doped n-type GaN layer having a thickness of 25 nm. The term "highly doped" means that it is more meaningful than the n-type contact layer 8 or the n-type modulation doping layer 9 located under the V-pit generation layer 10 (for example, 1.1 times or more, preferably 1.4 times or more, more Better than 1.8 times) increase the n-type doping concentration. Specifically, the n-type doping concentration of the V-pit generation layer 10 is preferably 5 × 10 ¹⁸ cm ^-3 or more, more preferably 7 × 10 ¹⁸ cm ^-3 or more, and still more preferably 1 × 10 ¹⁹ cm ^{- 3} or more. Thereby, since the film quality of the V-pit generation layer 10 is lower than that of the n-type modulation doping layer 9, the V-pit generation effect of the V-pit generation layer 10 is effectively exerted.

However, if the n-type dopant concentration of the V-pit generation layer 10 becomes too high, the luminous efficiency of the light-emitting layer 14 formed on the V-pit generation layer 10 is lowered. Therefore, the n-type dopant concentration of the V-pit generation layer 10 is preferably 10 times or less of the n-type dopant concentration of the n ⁺ layer 9A of the n-type modulation doped layer 9, and is preferably n-type. The concentration of the n-type dopant of the n ⁺ layer 9A of the doped layer 9 is 3 times or less.

The n-type dopant concentration of the V-pit layer 10 may also be the same as the n-type dopant concentration of the n ⁺ layer 9A of the n-type modulation doping layer 9. In this case, the size of the V-pit 15 generated by the V-pit generation layer 10 can be increased. Thereby, the defect rate caused by ESD (Electro-Static Discharge) can be reduced.

The V-pit generation layer 10 is preferably more meaningful than the first surface 61 of the first layered body 6 (for example, 1.1 times, preferably 1.4 times or more, more preferably 1.8 times or more), and the n-type dopant concentration is increased. Thereby, the V-pit generation effect of the V-pit generation layer 10 is effectively exerted.

When the semiconductor layer constituting the first surface 61 of the first layered body 6 is the n ⁺ layer 9A, the V-pit generation layer 10 may be an undoped layer, for example, preferably 10 nm thick. A heteronitride semiconductor layer.

The V-pit generation layer 10 is preferably doped, for example, in a layer of Al _s5 Ga _t5 In _u5 N (0≦s5≦1, 0≦t5≦1, 0≦u5≦1, s5+t5+u5≒1). The layer of the n-type dopant is more preferably doped with n-type doping in the layer of In _u5 Ga _1-u5 N (0≦u5≦1, preferably 0≦u5≦0.5, more preferably 0≦u5≦0.15) The layer of debris. In the case where the V-pit generation layer 10 contains In, the In composition of the V-pit generation layer 10 is preferably higher than the respective In composition ratios of the n ⁺ layer 9A and the n ^- layer 9B of the n-type modulation doping layer 9. Thereby, since the film quality of the V-pit generation layer 10 is lower than that of the n-type modulation doping layer 9, the V-pit generation effect of the V-pit generation layer 10 is effectively exerted.

The thickness of the V-pit generation layer 10 is preferably 5 nm or more, more preferably 10 nm or more. Thereby, the number of V-pits per unit number of the through-dislocation increases.

<Multilayer structure>

In the nitride semiconductor light-emitting device 1 of the present embodiment, the starting point of the V-pit 15 is located closer to the first layered body 6 than the light-emitting layer 14. Thereby, the number of layers of the barrier layer (especially the non-doped barrier layer) constituting the light-emitting layer 14 is increased, and the volume of the light-emitting layer 14 contributing to light emission can be increased (described below). Thereby, the luminous efficiency at the time of driving at a high current can be maintained, and the luminous efficiency at a high temperature can be maintained. However, if the volume of the light-emitting layer 14 which contributes to light emission is increased by increasing the number of layers of the barrier layer (especially, the non-doped barrier layer) constituting the light-emitting layer 14, it is understood that the defect rate caused by ESD is increased.

On the other hand, if the number of layers of the barrier layer (especially the non-doped barrier layer) constituting the light-emitting layer 14 is increased, the interval between the V-pit generation layer 10 and the light-emitting layer 14 which contributes to light emission is narrowed. As a result, it is not preferable that the starting point of the V-pit 15 is located near the light-emitting layer 14 which contributes to light emission. In order to prevent the average position of the starting point of the V-pit 15 from being present in the light-emitting layer 14 (at least the upper portion of the light-emitting layer 14), it is preferable to separate the V-pit generation layer 10 from the light-emitting layer 14 as much as possible. However, if the thickness of the superlattice layer 122 provided between the light-emitting layer 14 and the V-pit generation layer 10 is increased in order to achieve the object, the quality of the light-emitting layer 14 is deteriorated. Further, the productivity of the nitride semiconductor light-emitting element 1 is also lowered.

For the purpose of separating the V-pit generation layer 10 and the light-emitting layer 14 as much as possible, the temperature between the V-pit generation layer 10 and the superlattice layer 122 below the growth temperature of the V-pit generation layer 10 is only thickened. When the n-type GaN layer is formed, the luminous efficiency at the time of high-temperature driving and large-current driving is lowered, and the defect rate caused by ESD is increased. The reason for this is considered as follows. When an n-type GaN layer (for example, 200 nm or more) is formed at a temperature lower than the growth temperature of the V-pit generation layer 10, the grown surface of the n-type GaN layer has an uneven shape (the growth surface of the n-type GaN layer appears white turbid) ). Therefore, it adversely affects the layer formed on the n-type GaN layer. For example, causing a layer formed on the n-type GaN layer The crystal quality is lowered.

However, when the multilayer structure 121 is provided between the V-pit generation layer 10 and the superlattice layer 122, since the growth surface of the multilayer structure 121 can be prevented from being uneven, it can be maintained in a multilayer structure. The crystalline quality of the layer on the body 121. Thereby, the luminous efficiency at the time of high-temperature driving or high-current driving can be maintained, and the defective rate caused by ESD can be reduced. The configuration of the multilayer structure 121 will be described.

The multilayer structure 121 is preferably composed of a plurality of nitride semiconductor layer layers having different band gap energies, that is, the nitride semiconductor layer 121A having a relatively large band gap energy and the nitride semiconductor layer 121B having a relatively small band gap energy are alternately formed. It is composed of layers. Thereby, the size of the V-pit 15 generated by the V-pit generation layer 10 becomes large. Thereby, the defect rate caused by ESD is lowered. Further, the thickness of the superlattice layer 122 and the thickness of the light-emitting layer 14 become large. Further, the thickness of each layer constituting the multilayer structure 121 is preferably larger than the thickness of each layer constituting the superlattice layer 122.

The n-type dopant concentration of the nitride semiconductor layer constituting the multilayer structure 121 is preferably lower than the n-type dopant concentration of the V-pit generation layer 10, and is preferably, for example, 7 × 10 ¹⁷ cm ^-3 or less. As described above, when the n-type dopant concentration of the multilayer structure 121 is lowered, the depletion layer is widened by the application of the reverse bias voltage, so that the electric field applied to the light-emitting layer 14 at the time of application of the reverse voltage can be alleviated. Thereby, the multilayer structure 121 and the superlattice layer 122 can function together as an electric field relaxation layer. Further, when the driving voltage of the nitride semiconductor light-emitting device 1 does not exceed the allowable range, the nitride semiconductor layer constituting the multilayer structure 121 may be an undoped layer.

Although the reason why the nitride semiconductor layer (for example, InGaN layer or n-type InGaN layer) 121B having a relatively small band gap energy in the multilayer structure 121 is not necessary is considered to be the reason as shown below. If the temperature is below the growth temperature of the V-pit generation layer 10, the nitrogen having a relatively small band gap energy is grown in the growth of the nitride semiconductor layer (for example, GaN or n-type GaN layer) 121A having a relatively large band gap energy. When the semiconductor layer 121B is grown, the two-dimensional growth of the material constituting the nitride semiconductor layer 121A having a relatively large band gap energy is promoted. Therefore, even if the total thickness of the multilayer structure 121 is increased, the total thickness of the multilayer structure 121 can be prevented from increasing. The adverse effect and the layer grown on the multilayer structure 121 (for example, the superlattice layer 122, etc.). For example, by increasing the total thickness of the multilayer structure 121, the crystal quality of the superlattice layer 122 can be prevented from being lowered.

In order to effectively obtain this effect, the thickness of the nitride semiconductor layer 121B having a relatively small band gap energy is preferably thinner than the thickness of the nitride semiconductor layer 121A having a relatively large band gap energy, and more preferably a nitrogen having a relatively large band gap energy. The thickness of the semiconductor layer 121A is 1/5 times or more and 1/2 times or less. Further, the thickness of the nitride semiconductor layer 121A having a relatively large band gap energy is preferably 5 nm or more and 100 nm or less, and more preferably 10 nm or more and 40 nm or less.

One example of the multilayer structure 121 is an n-type InGaN layer having a thickness of 7 nm, an n-type GaN layer having a thickness of 30 nm, an n-type InGaN layer having a thickness of 7 nm, and a thickness of 20 nm, which are sequentially stacked on the V-pit generation layer 10. N-type GaN layer.

The specific composition of the nitride semiconductor layer constituting the multilayer structure 121 is not particularly limited. The nitride semiconductor layer 121A having a relatively large band gap energy is preferably, for example, an Al _i1 Ga _j1 In _(1-i1-j1) N (0≦i1<1, 0<j1≦1) layer, more preferably a GaN layer. The nitride semiconductor layer 121B having a relatively small band gap energy is preferably, for example, a layer of Al _i2 Ga _j2 In _(1-i2-j2) N (0≦i2<1, 0≦j2<1, j1<j2), more preferably Is a layer of Ga _j3 In _(1-j3) N (0<j3<1). More specifically, the multilayer structure 121 may also be an Al _i1 Ga _j1 In _(1-i1-j1) N (0≦i1<1, 0<j1≦1) layer and Al _i2 Ga _j2 In _{(1-i2- J2)} N (0≦i2<1, 0≦j2<1, j1<j2) layers are alternately layered, and may be a GaN layer and a Ga _j3 In _(1-j3) N (0<j3<1) layer It is composed of alternate layers.

When the nitride semiconductor layer constituting the multilayer structure 121 contains In, the composition of In in the nitride semiconductor 121B having a relatively small band gap energy is preferably the same as the composition ratio of In in the superlattice layer 122 (±5%). ). Thereby, when the superlattice layer 122 is formed after the formation of the multilayer structure 121, the step of changing the supply amount of the material gas of In can be omitted. Thereby, the productivity of the nitride semiconductor light-emitting device 1 is further improved. More preferably, when the nitride semiconductor layer 121B having a relatively small band gap energy is a layer of Ga _j3 In _(1-j3) N (0<j3<1), Ga _j3 In _(1-j3) N (0<j3< 1) The In composition ratio (1-j3) in the layer is the same as the In composition ratio in the narrow band gap layer 122B (described below) constituting the superlattice layer 122.

The number of layers of each of the nitride semiconductor layer 121A having a relatively large band gap energy and the nitride semiconductor layer 121B having a relatively small band gap energy is not particularly limited. The multilayer structure 121 preferably has two or more nitride semiconductor layers 121A having a relatively large band gap energy and a nitride semiconductor layer 121B having a relatively small band gap energy. Thereby, the thickness of the multilayer structure 121 can be increased. Thereby, the average position of the starting point of the V-pit 15 is more toward the first layered body 6 side than the center of the superlattice layer 122 in the thickness direction. Therefore, the luminous efficiency at the time of high-temperature driving or high-current driving can be maintained.

<Superlattice layer>

A superlattice layer 122 is provided between the V-pit generation layer 10 and the light-emitting layer 14, that is, on the multilayer structure 121. The main function of the superlattice layer 122 is such that the V-pit generation layer 10 is further separated from the light-emitting layer 14, and the position of the starting point of the V-pit 15 is set in the lower side of the light-emitting layer 14 or in the superlattice layer 122. . The superlattice layer 122 may comprise a single layer or a layer of 2 to 3 layers.

By "superlattice layer" is meant a layer comprising a crystalline lattice having a periodic structure that is substantially thinner than a substantially unitary crystal lattice by alternately laminating a very thin crystalline layer. The superlattice layer 122 is formed by laminating a plurality of nitride semiconductor layers and constituting a superlattice structure, and the wide band gap layer 122A having a relatively large band gap energy as shown in FIG. 3 is alternated with the narrow band gap layer 122B having a relatively small band gap energy. The layers are laminated to form a superlattice structure.

The superlattice layer 122 may also sequentially stack a semiconductor layer, a wide band gap layer 122A, and a narrow band gap layer 122B which are different from the wide band gap layer 122A and the narrow band gap layer 122B to form a superlattice structure. The length of one period of the superlattice layer 122 (the total thickness of the wide band gap layer 122A and the thickness of the narrow band gap layer 122B) is preferably shorter than the length of one period of the light-emitting layer 14 described below, and more preferably, for example, 1 nm or more and 10 nm. the following.

Each of the wide band gap layers 122A is preferably, for example, a layer of Al _a1 Ga _b1 In _(1-a1-b1) N (0≦a1≦1, 0<b1≦1), more preferably a GaN layer. Each narrow band gap layer 122B preferably has a smaller band gap energy than the wide band gap layer 122A, and more preferably has a larger band gap energy than each well layer 14W (described below). The narrow band gap layer 122B is preferably, for example, Al _a2 Ga _b2 In _(1-a2-b2) N (0≦a2<1, 0<b2<1, (1-a1-b1)<(1-a2-b2)) The layer is more preferably a Ga _b2 In _(1-b2) N (0 < b2 < 1) layer.

At least one of each of the wide bandgap layer 122A and each of the narrow bandgap layers 122B preferably includes an n-type dopant, and preferably contains, for example, an n-type dopant of 1 × 10 ¹⁹ cm ^-3 or more. The n-type dopant is not particularly limited, and is preferably, for example, Si, P, As, or Sb, and more preferably Si.

If both the wide band gap layer 122A and the narrow band gap layer 122B are undoped layers, there is a case where the driving voltage rises. On the other hand, if all of the nitride semiconductor layers constituting the superlattice layer 122 are doped layers, it is difficult to expand the depletion layer due to the application of the reverse bias, so that it is difficult for electrons to escape from the superlattice layer 122. Therefore, there is a case where the electric field relaxation effect cannot be sufficiently obtained. However, the superlattice layer 122 also has a layer provided to inject electrons into the light-emitting layer 14. Thereby, at least two nitride semiconductor layers located on the side of the light-emitting layer 14 are doped, and the nitride semiconductor layer located on the side closer to the first laminated body 6 is set to be smaller than the doped layer. By doping the layer, the number of electrons injected into the luminescent layer 14 can be increased. Thereby, the light output is increased and the driving voltage is lowered. However, if the thickness of the undoped layer is increased, it is necessary to apply a voltage for moving electrons, and thus the driving voltage is increased. In order to maintain a low driving voltage, it is preferable to form at least two nitride semiconductor layers on the side of the first layered body 6 as an undoped layer.

The number of layers of the wide band gap layer 122A and the narrow band gap layer 122B is not particularly limited. The superlattice layer 122 preferably has more than 20 sets of the wide band gap layer 122A and the narrow band gap layer 122B. Thereby, the V-pit generation layer 10 can be further provided from the light-emitting layer 14 to be provided. Therefore, the average position of the starting point of the V-pit 15 can be set in the superlattice layer 122.

When the superlattice layer 122 has 20 or more wide band gap layers 122A and narrow band gap layers 122B, the five sets of the wide band gap layer 122A and the narrow band gap layer 122B on the side of the light emitting layer 14 are preferably doped layers. Thereby, since the number of electrons injected into the light-emitting layer 14 can be further increased, the light-emission output is further increased, and the driving voltage is further lowered.

In other examples of superlattice layer 122, undoped superlattice structure and doped superlattice The fabrication is sequentially performed on the multilayer structure 121. The undoped superlattice structure preferably comprises 17 sets of undoped wide bandgap layer 122A and undoped narrow bandgap layer 122B. The doped superlattice structure preferably comprises three sets of doped wide bandgap layers 122A and doped narrow bandgap layers 122B.

In still another example of the superlattice layer 122, the first doped superlattice structure, the undoped superlattice structure, and the second doped superlattice structure are sequentially provided on the multilayer structure 121. The first and second doped superlattice structures preferably each comprise five sets of doped wide bandgap layers 122A and doped narrow bandgap layers 122B. The undoped superlattice structure preferably comprises 10 sets of undoped wide bandgap layer 122A and undoped narrow bandgap layer 122B.

The superlattice layer 122 is a layer that is provided to further improve the characteristics of the light-emitting layer 14, and is not essential for the nitride semiconductor light-emitting device 1. However, if the superlattice layer 122 is provided between the V-pit generation layer 10 and the light-emitting layer 14, the V-pit generation layer 10 and the light-emitting layer 14 can be separated. Thereby, the average position of the starting point of the V-pit 15 can be prevented from being present in the light-emitting layer 14 (at least the upper portion of the light-emitting layer 14). Therefore, the nitride semiconductor light-emitting element 1 preferably includes the superlattice layer 122 between the V-pit generation layer 10 and the light-emitting layer 14. Preferably, the thickness of the superlattice layer 122 is 40 nm or more, more preferably the thickness of the superlattice layer 122 is 50 nm or more, and further preferably the thickness of the superlattice layer 122 is 60 nm or more. On the other hand, if the thickness of the superlattice layer 122 is too large, the crystal quality of the light-emitting layer 14 is deteriorated. Therefore, the thickness of the superlattice layer 122 is preferably 100 nm or less, more preferably 80 nm or less. Further, the thickness of each of the wide band gap layers 122A is preferably, for example, 1 nm or more and 3 nm or less. The thickness of each of the narrow band gap layers 122B is preferably, for example, 1 nm or more and 3 nm or less.

<Light Emitting Layer>

The light-emitting layer 14 is provided on the second layered body 11. V pits 15 are partially formed on the light emitting layer 14. By "partially forming the V-pit 15", it is observed that the V-pit 15 is observed as a dot on the upper surface of the light-emitting layer 14 when the upper surface of the light-emitting layer 14 is observed by an AFM (Atomic Force Microscope). The density of the number of V-pits in the upper surface of the light-emitting layer 14 is preferably 1 × 10 ⁸ cm ^-2 or more and 1 × 10 ¹⁰ cm ^-2 or less. In the past, although V-pits were formed in the light-emitting layer, the density of the number of V-pits in the upper surface of the conventional light-emitting layer was less than 1 × 10 ⁸ cm ^-2 .

The light-emitting layer 14 is preferably as shown in FIG. 3, and has a laminated structure in which the barrier layer 14A and the well layer 14W are alternately laminated. Immediately above the superlattice layer 122, an initial barrier layer 14AZ is preferably provided. The last barrier layer 14A0 is preferably disposed on the well layer 14W1 closest to the p-type nitride semiconductor layer 16 side in the well layer 14W.

In the present embodiment, in order to identify each of the barrier layer 14A and the well layer 14W, the p-type nitride semiconductor layer 16 is numbered toward the lattice layer 122 and is expressed as a well layer 14W1, a barrier layer 14A1, a well layer 14W2, and a barrier layer 14A2. ,...Wait. In addition, it is expressed as "barrier layer 14A" and "well layer 14W" except for the case where each of the barrier layers 14A and each of the well layers 14W is specified.

The light-emitting layer 14 may have a laminated structure in which one or more layers of the semiconductor layer, the barrier layer 14A, and the well layer 14W which are different from the barrier layer 14A and the well layer 14W are sequentially laminated. Further, the length of one period of the light-emitting layer 14 (the sum of the thickness of the barrier layer 14A and the thickness of the well layer 14W) is preferably, for example, 5 nm or more and 100 nm or less.

The composition of each well layer 14W is preferably adjusted in accordance with the wavelength of light emitted by the nitride semiconductor light-emitting device 1, and is preferably, for example, Al _c Ga _d In _(1-cd) N (0≦c<1, 0<d) ≦1) is more preferably In _e Ga _(1-e) N (0<e≦1) which does not contain Al. When the nitride semiconductor light-emitting element 1 emits ultraviolet light having a wavelength of, for example, 375 nm or less, since the band gap energy of the light-emitting layer 14 must be increased, the composition of each well layer 14W preferably contains Al.

The composition of each well layer 14W is preferably the same. Thereby, the wavelength of light emitted by recombining electrons and holes in each well layer 14W can be made the same. Therefore, the width of the light-emitting spectrum of the nitride semiconductor light-emitting element 1 can be narrowed.

The well layer 14W on the side of the p-type nitride semiconductor layer 16 is preferably free of dopants as much as possible. In other words, it is preferable that the well layer 14W located on the side of the p-type nitride semiconductor layer 16 is grown without introducing a dopant material. Thereby, since it is not easy to cause non-lighting recombination in each well layer 14W, the luminous efficiency is good. On the other hand, the well layer 14W located on the side of the first layered body 6 may also contain an n-type dopant. Thereby, the driving voltage of the nitride semiconductor light-emitting element 1 is lowered. The tendency.

The thickness of each well layer 14W is not particularly limited, and is preferably the same. If the thickness of each well layer 14W is the same, the quantum level of each well layer 14W is also the same. Therefore, light of the same wavelength is generated in each well layer 14W by recombination of electrons and holes in each well layer 14W. Therefore, the width of the light-emitting spectrum of the nitride semiconductor light-emitting device 1 is preferably narrow. On the other hand, if the composition or thickness of the well layer 14W is deliberately different, the width of the light-emitting spectrum of the nitride semiconductor light-emitting device 1 can be made wider. When the nitride semiconductor light-emitting device 1 is used for applications such as illumination, since the width of the light-emitting spectrum of the nitride semiconductor light-emitting device 1 is wider, it is preferable to intentionally make the composition or thickness of the well layer 14W different. For example, it is preferable to appropriately set the thickness of each well layer 14W in the range of 1 nm or more and 7 nm or less. Thereby, high luminous efficiency can be maintained.

The material constituting each of the barrier layers 14A (14A1 to 14A7), the first barrier layer 14AZ, and the last barrier layer 14A0 is preferably larger than the material constituting each of the well layers 14W. Specifically, each of the barrier layers 14A (14A1 to 14A7), the first barrier layer 14AZ, and the last barrier layer 14A0 preferably include Al _f Ga _g In _(1-fg) N (0≦f<1, 0<g≦1). More preferably, it includes In _h Ga _(1-h) N (0<h≦1, e>h) which does not contain Al, and further preferably contains Al _f Ga _{g which} is substantially the same as the lattice constant of the material constituting the well layer 14W. In _(1-fg) N (0≦f<1, 0<g≦1).

The thickness of each barrier layer 14A is not particularly limited, but is preferably 1 nm or more and 10 nm or less, and more preferably 3 nm or more and 7 nm or less. The thinner the thickness of each of the barrier layers 14A is, the lower the driving voltage is. If the thickness of each of the barrier layers 14A is extremely thin, the luminous efficiency tends to be lowered. The thickness of the first barrier layer 14AZ is not particularly limited, but is preferably 1 nm or more and 10 nm or less. The thickness of the last barrier layer 14A0 is not particularly limited, but is preferably 1 nm or more and 40 nm or less.

The concentration of the n-type dopant in each of the barrier layers 14A (14A1 to 14A7) and the first barrier layer 14AZ is not particularly limited, and is preferably set as appropriate. Further, in the plurality of barrier layers 14A, the barrier layer 14A on the side of the first laminate 6 preferably includes an n-type dopant, and the barrier layer 14A on the side of the p-type nitride semiconductor layer 16 preferably contains the first laminate. 6-side barrier layer 14A lower concentration n-type dopant, or no n-type dopant. Each of the barrier layers 14A (14A1 to 14A7), the first barrier layer 14AZ, and the last barrier layer 14A0 may also intentionally contain an n-type dopant. Further, in each of the barrier layers 14A (14A1 to 14A7), the first barrier layer 14AZ, and the last barrier layer 14A0, p-type doping is doped by thermal diffusion during growth of the p-type nitride semiconductor layers 16, 17, 18. Things.

The number of layers of the well layer 14W is not particularly limited, but is preferably 2 or more and 20 or less, more preferably 3 or more and 15 or less, and still more preferably 4 or more and 12 or less.

<p type nitride semiconductor layer>

The p-type nitride semiconductor layers 16, 17, and 18 are sequentially provided on the light-emitting layer 14. The number of layers of the p-type nitride semiconductor layer is not limited to three, and may be two or less, or four or more. The p-type nitride semiconductor layers 16, 17, 18 are preferably, for example, Al _s6 Ga _t6 In _u6 N (0≦s6≦1, 0≦t6≦1, 0≦u6≦1, s6+t6+u6≠0) a layer doped with a p-type dopant in the layer, more preferably a p-type dopant doped in a layer of Al _s6 Ga _(1-s6) N (0<s6≦0.4, preferably 0.1≦s6≦0.3) Layer. For example, the p-type nitride semiconductor layer 16 is a p-type AlGaN layer, the p-type nitride semiconductor layer 17 is a p-type GaN layer, and the p-type nitride semiconductor layer 18 has a p-type dopant concentration higher than that of the p-type nitride semiconductor layer 17. A higher p-type GaN layer.

The p-type dopant is not particularly limited, and is preferably, for example, Mg. The carrier concentration of the p-type nitride semiconductor layers 16, 17, 18 is preferably 1 × 10 ¹⁷ cm ^-3 or more. Here, the activity ratio of the p-type dopant is about 0.01, and thus the p-type dopant concentration (different from the carrier concentration) of the p-type nitride semiconductor layers 16, 17, 18 is preferably 1 × 10 ¹⁹ cm ^{- 3} or more. The p-type dopant concentration in the portion of the p-type nitride semiconductor layer 16 on the side of the light-emitting layer 14 may be less than 1 × 10 ¹⁹ cm ^-3 .

The total thickness of the p-type nitride semiconductor layers 16, 17, and 18 is not particularly limited, but is preferably 50 nm or more and 300 nm or less. When the thickness of the p-type nitride semiconductor layers 16, 17, and 18 is reduced, the heating time during the growth is shortened, so that the p-type dopant can be prevented from diffusing into the light-emitting layer 14.

<n side electrode, transparent electrode, p side electrode>

The n-side electrode 21 and the p-side electrode 25 are electrodes for supplying driving power to the nitride semiconductor light-emitting device 1. FIG. 2 shows a case where the n-side electrode 21 and the p-side electrode 25 are formed only by pad electrode portions. However, the elongated protrusion (branch electrode) for the purpose of current spreading may be connected to the n-side electrode 21 and the p-side electrode 25 shown in FIG. Further, on the lower side of the p-side electrode 25, an insulating layer for preventing an electric current from being injected into the p-side electrode 25 is preferably provided. Thereby, the amount of light emitted from the light-emitting layer 14 can be reduced by the p-side electrode 25.

The n-side electrode 21 preferably has, for example, a laminated structure in which a titanium layer, an aluminum layer, and a gold layer are sequentially laminated. It is assumed that the thickness of the n-side electrode 21 is preferably 1 μm or more in the case where the n-side electrode 21 is bonded by wire bonding.

The p-side electrode 25 preferably has a laminated structure in which a nickel layer, an aluminum layer, a titanium layer, and a gold layer are sequentially laminated, and may include the same material as the n-side electrode 21. It is assumed that the thickness of the p-side electrode 25 is preferably 1 μm or more in the case where the p-side electrode 25 is bonded by wire bonding.

The transparent electrode 23 preferably contains a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), and more preferably has a thickness of 20 nm or more and 200 nm or less.

<V pit start point>

In the nitride semiconductor light-emitting device 1 of the present embodiment, most of the starting point of the V-pit 15 does not exist in the light-emitting layer 14, and a majority of the number is considered to exist in the superlattice layer 122. The V-pit 15 is considered to be caused by the through-dislocation, and it is considered that the through-dislocation is mostly located inside the V-pit 15. Therefore, it is possible to suppress the penetration of the electrons and holes injected into the light-emitting layer 14 into the inside of the V-pit 15. Therefore, it is considered that it is possible to suppress the occurrence of non-light-emitting recombination in order to capture electrons and holes in the through-dislocation. Thereby, high luminous efficiency can be maintained. This effect is particularly noticeable at high temperatures or when driven at high currents.

Specifically, since the movement of the injection carrier (hole or electron) to the light-emitting layer 14 is active at a high temperature, the probability of the injected carrier reaching the through-dislocation is increased. However, in the embodiment In the nitride semiconductor light-emitting device 1, since the through-dislocation in the light-emitting layer 14 is mostly covered by the V-pit 15 (the inside of the V-pit 15 is often caused by the through-dislocation), the non-light-emitting recombination of the through-dislocation is suppressed. Thereby, the luminous efficiency at a high temperature can be maintained.

Moreover, since the starting point of the V-pit 15 is located on the lower side of the light-emitting layer 14, the number of layers of the barrier layer (especially the non-dopant barrier layer) can be increased, and the volume of the light-emitting layer 14 can be increased. Thereby, the luminous efficiency at the time of driving at a high current can be maintained.

<About carrier concentration and dopant concentration>

The carrier concentration means the concentration of electrons or holes, not determined by the amount of n-type dopant or the amount of p-type dopant. The carrier concentration is calculated based on the voltage characteristic of the nitride semiconductor light-emitting device 1 and the carrier concentration in the state where the current is not injected, and is a self-ionized impurity, a crystallized defect of the donor, and a The total number of carriers produced by the crystallized defects of the body.

The activation rate of the n-type dopant, that is, Si or the like is high. Thereby, the n-type carrier concentration can be considered to be substantially the same as the n-type dopant concentration. Further, the n-type dopant concentration can be easily obtained by measuring the concentration distribution in the depth direction by SIMS (Secondary Ion Mass Spectroscopy). Further, the relative relationship (ratio) of the dopant concentration is substantially the same as the relative relationship (ratio) of the carrier concentration. The average n-type dopant concentration can be obtained by averaging the measured n-type dopant concentration in the thickness direction.

<Other effects and effects on the n-type modulation doping layer and superlattice layer>

In the nitride semiconductor light-emitting device 1 of the present embodiment, an n-type modulation doped layer 9 and a V-pit are sequentially stacked from the n-type contact layer 8 side between the n-type contact layer 8 and the light-emitting layer 14. The layer 10, the multilayer structure 121, and the superlattice layer 122 are produced. Thereby, when a high voltage in the reverse bias direction which is the cause of ESD destruction is applied between the n-side electrode 21 and the p-side electrode 25, the depletion layer is formed in the n-type modulation doping layer 9 and the superlattice. The layer 122 is elongated on the side. Thereby, the reverse offset voltage (electric field) applied to the light-emitting layer 14 can be reduced. Therefore, the threshold voltage (i.e., ESD withstand voltage) that causes ESD destruction becomes high.

In the case where the nitride semiconductor light-emitting device of the present embodiment is configured such that the V-pit 15 is not intentionally introduced, the leakage current when the offset voltage is applied in the forward direction can be more effectively reduced, and the V can be prevented. The light-emitting area caused by the formation of the pits 15 is lowered. Therefore, in this case as well, the light-emitting characteristics of the nitride semiconductor light-emitting element 1 can be effectively prevented from being lowered.

In the case where the nitride semiconductor light-emitting device 1 of the present embodiment includes only one of the n-type modulation doped layer 9 or the superlattice layer 122, the above-described actions and effects can be obtained. However, the nitride semiconductor light-emitting device 1 of the present embodiment preferably includes both the n-type modulation doped layer 9 and the superlattice layer 122. Thereby, the ESD withstand voltage becomes high. The leakage current when the offset voltage is applied in the forward direction can be more effectively reduced, and the decrease in the light-emitting area caused by the formation of the V-pit 15 can be prevented.

<Manufacture of nitride semiconductor light-emitting element>

Fig. 5(a) is a graph showing the temperature distribution of the manufacturing steps of the nitride semiconductor light-emitting device 1 shown in Fig. 1. The vertical axis of Fig. 5(a) indicates the growth temperature, and the horizontal axis of Fig. 5(a) indicates the growth time. In addition, FIG. 5(b) is a graph showing the temperature distribution in the manufacturing steps of the nitride semiconductor light-emitting device of Comparative Example 1 below.

First, the first layered body 6 is formed. After the buffer layer 5 is formed on the substrate 3 by sputtering, for example, the underlayer 7, the n-type contact layer 8, and the n-type modulation doping layer 9 are sequentially formed on the buffer layer 5 by, for example, MOCVD. The underlayer 7, the n-type contact layer 8, and the n-type modulation doped layer 9 are preferably grown in the first crystal growth apparatus. These layers are preferably grown at 800 ° C or higher and 1250 ° C or lower, more preferably at 900 ° C or higher and 1150 ° C or lower.

The first underlayer 71 preferably grows in a crystal growth mode in which the inclined crystal faces 71a are formed. The second base layer 75 is preferably grown in an embedded growth mode in which the inclined crystal face 71a can be embedded and the flat upper surface 75b is formed. Specifically, the first underlayer 71 is preferably formed under an ambient gas which is more easily grown in three dimensions than the second underlayer 75, and more preferably formed at a higher pressure and lower temperature than the second underlayer 75. For example, the first base layer 71 is preferably formed under a pressure of 500 Torr and a temperature of 990 ° C. The second underlayer 75 is preferably formed under a pressure of 200 Torr and at a temperature of 1080 °C.

After the first layered body 6 is formed, the temperature is temporarily lowered (the temperature lowering step), and the temperature is raised again to form the second layered body 11. In the temperature lowering step, it is preferably lowered to a temperature lower than the temperature at which the second layered body 11 is formed (for example, 500 ° C or lower), and more preferably lowered to room temperature or higher and 100 ° C or lower. The "temperature of the cooling step" means the temperature of the substrate 3 and the temperature of the higher of the temperature in the film forming apparatus or the growth apparatus. Further, after the cooling step, the first layered body 6 is preferably exposed to the atmosphere. As a method of exposing the first layered body 6 to the atmosphere, for example, a method of taking out the first layered body 6 from the first crystal growth apparatus and putting it into the second crystal growth apparatus is exemplified. After the temperature is raised again, the V-pit generation layer 10, the multilayer structure 121, and the superlattice layer 122 are sequentially formed on the n-type modulation doped layer 9 by, for example, MOCVD.

The growth temperature of the V-pit generation layer 10 is preferably lower than the formation temperature of the first laminate body 6, lower than, for example, the growth temperature of the n-type contact layer 8 or the n-type modulation doping layer 9 (formation of the first n-type nitride semiconductor) The temperature of the layer). As shown in FIG. 5(a), the light-emitting layer 14 is formed at a temperature lower than the formation temperature of the first layered body 6. Therefore, if the growth temperature of the V-pit generation layer 10 is lower than the growth temperature of the n-type contact layer 8 or the n-type modulation doping layer 9 (the temperature at which the first n-type nitride semiconductor layer is formed), the second laminate can be shortened. The time required for the cooling step after the formation of the body 11 is such that a higher throughput can be maintained. Further, the amount of adhering matter adhering to the chamber of the apparatus for forming the V-pit generation layer 10 is reduced as compared with the case where the growth temperature of the V-pit generation layer 10 is high. Thereby, the frequency of the film forming apparatus for forming the second layered body 11 is lowered. For these reasons, the productivity of the nitride semiconductor light-emitting element 1 becomes high. The growth temperature of the V-pit generation layer 10 is more preferably 700 ° C or higher, and further preferably 750 ° C or higher, from the viewpoint of maintaining the luminous efficiency of the higher MQW light-emitting layer 14 .

It is also possible to increase the n-type dopant concentration and form the V-pit generation layer 10 than the n-type modulation doped layer 9. Thereby, the V-pit forming effect of the V-pit generation layer 10 is increased.

The growth temperature of the multilayer structure 121 is preferably not higher than the growth temperature of the V-pit generation layer 10, and more preferably the same as the growth temperature of the V-pit generation layer 10. If the multilayer structure 121 is formed When the long temperature is below the growth temperature of the V-pit generation layer 10, the size of the V-pit 15 can be increased, and the defective rate caused by ESD becomes low. In order to effectively obtain this effect, the growth temperature of the multilayer structure 121 is more preferably 600 ° C or higher.

The growth temperature of the superlattice layer 122 is preferably lower than the growth temperature of the V-pit generation layer 10, and more preferably the same as the growth temperature of the V-pit generation layer 10. If the growth temperature of the superlattice layer 122 is less than the growth temperature of the V-pit layer 10, the time required for the temperature-lowering step after the formation of the second layered body 11 can be further shortened, thereby maintaining a higher throughput. . Moreover, the frequency of maintaining the film forming apparatus for forming the superlattice layer 122 is further reduced. For these reasons, the productivity of the nitride semiconductor light-emitting element 1 is further increased. In addition, since the size of the V-pit 15 can be increased, the defective rate caused by the ESD becomes low. In order to effectively obtain this effect, the growth temperature of the superlattice layer 122 is more preferably 600 ° C or higher.

Then, the light-emitting layer 14 and the p-type nitride semiconductor layers 16, 17, and 18 are sequentially formed on the second layered body 11. The method of forming the light-emitting layer 14 is not particularly limited. As a method of forming the MQW structure, a well-known method can be used without particular limitation. The method of forming the p-type nitride semiconductor layers 16, 17, and 18 is not particularly limited, and a known method can be used as the method of forming the p-type nitride semiconductor layer.

Then, the p-type nitride semiconductor layers 16, 17, 18, the light-emitting layer 14, the second laminate 11, the n-type modulation doping layer 9, and the n-type contact layer are etched so as to expose a portion of the n-type contact layer 8. 8. An n-side electrode 21 is formed on the upper surface of the n-type contact layer 8 exposed by the etching. Further, the transparent electrode 23 and the p-side electrode 25 are sequentially laminated on the upper surface of the p-type nitride semiconductor layer 18. Thereafter, the transparent protective film 27 is formed so as to cover the transparent electrode 23 and the side faces of the respective layers exposed by the above etching. Thereby, the nitride semiconductor light-emitting element 1 shown in FIG. 1 is obtained.

Alternatively, the substrate 3 can be removed. The timing at which the substrate 3 is removed is not particularly limited, and the substrate 3 can be removed, for example, after the step of forming the first layered body 6.

The underlayer 7 and the n-type contact layer 8 may be formed in the first crystal growth apparatus, and may be in the second The n-type modulation doped layer 9 and the second layered body 11 are formed in the crystal growth apparatus. However, when the underlayer 7, the n-type contact layer 8, and the n-type modulation doped layer 9 are formed in the first crystal growth apparatus, and the second layered body 11 is formed in the second crystal growth apparatus, the second layer can be further shortened. The time required for the temperature-lowering step after the formation of the layered body 11.

As described above, the nitride semiconductor light-emitting device 1 shown in FIG. 1 includes the first layered body 6 including the first n-type nitride semiconductor layers 8 and 9 of one or more layers, and the first layer 6 including the first layered body 6. The second layered body 11 of the second n-type nitride semiconductor layer 10 in contact with the surface 61, the light-emitting layer 14 provided on the second layered body 11, and the p-type nitride semiconductor layers 16 and 17 provided on the light-emitting layer 14. 18. The second n-type nitride semiconductor layer 10 is formed at a temperature lower than a temperature at which the first n-type nitride semiconductor layer is formed (for example, a growth temperature of the n-type contact layer 8 or the n-type modulation doping layer 9). Thereby, the productivity of the nitride semiconductor light-emitting element 1 shown in FIG. 1 becomes high.

The second layered body 11 is preferably provided between the second n-type nitride semiconductor layer 10 and the light-emitting layer 14, and further includes one or more third n-type nitride semiconductor layers 121 and 122. The third n-type nitride semiconductor layers 121 and 122 are preferably formed at a temperature lower than the formation temperature of the second n-type nitride semiconductor layer 10. Thereby, the productivity of the nitride semiconductor light-emitting element 1 shown in FIG. 1 is further increased.

The semiconductor layer constituting the first surface 61 of the first layered body 6 is preferably an undoped layer. In this case, the second n-type nitride semiconductor layer 10 is preferably a doped layer.

The semiconductor layer constituting the first surface 61 of the first layered body 6 is preferably a doped layer. In this case, the second n-type nitride semiconductor layer 10 is preferably an undoped layer.

The method for producing the nitride semiconductor light-emitting device 1 of the present invention includes at least a step of forming the first layered body 6 including the first n-type nitride semiconductor layers 8 and 9 of one or more layers, and forming and including the first layered body 6. a step of forming the second layered body 11 of the second n-type nitride semiconductor layer 10 in contact with the first surface 61, a step of forming the light-emitting layer 14 on the second layered body 11, and forming a p-type nitride semiconductor on the light-emitting layer 14 The steps of layers 16, 17, 18. After the step of forming the first layered body 6 and before the step of forming the second layered body 11, the temperature is further lowered to form the second The step of lowering the temperature of the laminate 11 at a lower temperature. Thereby, the productivity of the nitride semiconductor light-emitting element 1 shown in Fig. 1 can be improved.

It is preferable to further expose the first layered body to the atmosphere before the step of forming the first layered body and before the step of forming the second layered body. Thereby, the productivity of the nitride semiconductor light-emitting element 1 shown in FIG. 1 can be further improved.

[Examples]

Hereinafter, the present invention will be described in more detail by way of examples, but the invention is not limited thereto.

<Example 1>

First, a wafer containing a 100 mm diameter sapphire substrate is prepared. On the upper surface of the wafer, a concavo-convex shape in which the convex portion 3a and the concave portion 3b are alternately formed is formed.

A method of forming the uneven shape of the wafer is displayed. First, a mask in which the planes of the convex portions 3a shown in Fig. 4 are arranged is placed on the wafer. Second, the mask is used to dry etch the upper surface of the wafer. The portion that is dry etched becomes the concave portion 3b, whereby the concave portion 3b having the planar arrangement shown in Fig. 4 is formed on the upper surface of the wafer. Thereby, the convex portions 3a are arranged in the a (sub)axis direction (<11-20> direction) of the upper surface of the wafer, and are respectively disposed at +60° to the a (sub) axis direction of the upper surface of the wafer. The direction of the tilt is in the direction of the inclination of -60° to the a(sub)axis direction of the upper surface of the wafer (both in the u direction). The convex portions 3a are arranged on the upper surface of the wafer, and are respectively arranged at the vertices of the imaginary triangles 3t shown by broken lines in FIG. 4, and are arranged periodically along the respective sides of the three sides of the imaginary triangle 3t.

The shape of the convex portion 3a in the upper surface of the wafer is circular, and the diameter of the circle is about 1.2 μm. The interval between the apexes of the adjacent convex portions 3a (one side of the imaginary triangle 3t shown in Fig. 4) is 2 μm, and the height of the convex portion 3a is about 0.6 μm. The convex portion 3a has a side view shape as shown in Fig. 1, and its front end is rounded. The recess 3b has a side view shape as shown in FIG.

After the convex portion 3a and the concave portion 3b are formed, the upper surface of the wafer is subjected to RCA cleaning. The RCA-cleaned wafer was placed in a chamber, N ₂ , O ₂ , and Ar were introduced into the chamber, and the wafer in the chamber was heated to 650 ° C. The AlON crystal is formed on the upper surface of the wafer on which the convex portion 3a and the recess 3b are formed by a reactive sputtering method in which an Al target is sputtered under a mixed atmosphere of N ₂ , O ₂ , and Ar. Buffer layer 5 (thickness 25 nm). The buffer layer 5 formed is an aggregate of columnar crystals elongated in the normal direction on the upper surface of the wafer, that is, an aggregate of uniform crystal grains of crystal grains.

The wafer in which the buffer layer 5 has been formed is placed in the first MOCVD apparatus. The first underlayer 71 containing undoped GaN was crystal grown by MOCVD under a pressure of 500 Torr and a temperature of 990 °C. Further, the second underlayer 75 containing undoped GaN was crystal grown by MOCVD under a pressure of 200 Torr and a temperature of 1080 °C. The thickness of the base layer 7 was 4 μm. Thereafter, the Si-doped n-type GaN layer (n-type contact layer 8) is crystal grown by MOCVD. The n-type contact layer 8 has a thickness of 3 μm, and the n-type contact layer 8 has an n-type dopant concentration of 1 × 10 ¹⁹ cm ^-3 .

The wafer temperature was set to 1081 ° C, and a nitride semiconductor layer containing Si-doped n-type GaN having a thickness of 50 nm was grown on the n-type contact layer 8 by MOCVD (n ⁺ layer 9A, n-type doping) Material concentration: i × 10 ¹⁹ cm ^-3 ), a nitride semiconductor layer (n ^- layer 9B) containing undoped GaN having a thickness of 87 nm, and a nitride semiconductor layer containing Si-doped n-type GaN having a thickness of 50 nm (n ⁺ Layer 9A, n-type dopant concentration: 1 × 10 ¹⁹ cm ^-3 ), and a nitride semiconductor layer (n ^- layer 9B) containing undoped GaN having a thickness of 87 nm. Thereby, the n-type modulation doping layer 9 is formed.

After the n-type modulation doping layer 9 is formed, the wafer temperature is lowered to 80 °C. After the wafer was temporarily taken out from the first MOCVD apparatus to the atmosphere, it was placed in a second MOCVD apparatus. The temperature of the wafer was set to 801 ° C, and a Si-doped GaN layer (V-pit generation layer 10) having a thickness of 25 nm was grown by MOCVD. The crystal-grown Si-doped GaN layer is in contact with the uppermost layer of the n-type modulation doped layer 9, and has an n-type dopant concentration of 1 × 10 ¹⁹ cm ^-3 .

The multilayer structure 121 is crystal grown in a state where the wafer temperature is maintained at 801 °C. A Si-doped InGaN layer having a thickness of 7 nm, a Si-doped GaN layer having a thickness of 30 nm, a Si-doped InGaN layer having a thickness of 7 nm, and a Si-doped GaN layer having a thickness of 20 nm were alternately laminated in two layers. In any of the layers constituting the multilayer structure 121, the n-type dopant concentration was also set to 7 × 10 ¹⁷ cm ^-3 . The In composition ratio of the InGaN layer is set to be the same as the In composition ratio of the narrow band gap layer 122B of the subsequently grown superlattice layer 122.

The superlattice layer 122 is crystal grown while maintaining the temperature of the wafer at 801 °C. The wide band gap layer 122A containing Si-doped GaN and the narrow band gap layer 122B containing Si-doped InGaN were alternately grown for 20 cycles. Each of the wide band gap layers 122A has a thickness of 2.05 nm. Each of the narrow band gap layers 122B has a thickness of 2.05 nm. The n-type dopant concentration of each of the wide band gap layers 122A is 1 × 10 ¹⁹ cm ^-3 in 5 layers on the side of the light-emitting layer 14 in the wide-band gap layer 122A, and is closer to the side of the first layered body 6 than the 5 layers. The layer is 0 cm ^-3 (non-doped). The n-type dopant concentration of each of the narrow band gap layers 122B is 1 × 10 ¹⁹ cm ^-3 in the five layers on the side of the light-emitting layer 14 in the narrow band gap layer 122B, and is closer to the side of the first layered body 6 than the five layers. The layer is 0 cm ^-3 (non-doped). The well layer 14W of the light-emitting layer 14 adjusts the flow rate of TMI (trimethyl indium) in such a manner that the wavelength of light emitted by photoluminescence becomes 375 nm, and thus the composition of each narrow band gap layer 122B is In _y Ga _1-y N ( y=0.04).

The temperature of the wafer was lowered to 672 ° C to crystallize the light-emitting layer 14 . The barrier layer 14A and the well layer 14W containing InGaN are alternately crystal grown, and the well layer 14W is crystal grown to have 8 layers. Each of the barrier layers 14A has a thickness of 4.2 nm. The initial barrier layer 14AZ and the barrier layer 14A7 have an n-type dopant concentration of 4.3 × 10 ¹⁸ cm ^-3 , and the other barrier layers 14A6, 14A5, ..., 14A1 are undoped.

Here, the thickness of the first barrier layer 14AZ is preferably larger than the thickness of the barrier layer 14A7, and may be, for example, 5.05 nm. Thereby, the narrow band gap layer 122B can be formed closest to the light-emitting layer 14 side in the superlattice layer 122, and the wide band gap layer 122A not included in the number of superlattice layers 122 can be maintained. The n-type dopant concentration of the first barrier layer 14AZ may also be set to 1×10 ¹⁹ cm in the upper portion of the first barrier layer 14AZ (from the region where the barrier layer 14AZ and the well layer 14W8 are separated by 1.55 nm). ^-3 , the portion below the first barrier layer 14AZ (the portion other than the upper portion of the first barrier layer 14AZ) is set to 4.3 × 18 ¹⁸ cm ^-3 .

Alternatively, the n-type dopant may be doped only in the lower portion of the barrier layer 14A7 (a region away from the interface of the well layer 14W8 and the barrier layer 14A7 by 3.5 nm), and the upper portion of the barrier layer 14A7 (the portion other than the lower portion of the barrier layer 14A7) ) set to non-doped. Thus, by making the upper portion of the barrier layer 14A7 non-doped, it is possible to prevent the injection carrier of the well layer 14W7 from coming into direct contact with the n-type doped barrier layer portion.

The well layer 14W is a non-doped In _x Ga _1-x N layer (x = 0.20) in which crystal growth is performed using nitrogen gas as a carrier gas. The thickness of each well layer 14W is 2.7 nm. The well layer 14W adjusts the flow rate of the TMI so that the wavelength of the light emitted by the photoluminescence becomes 448 nm, and sets the composition x of In in the well layer 14W.

On the uppermost well layer 14W1, the last barrier layer 14A0 (thickness 10 nm) containing undoped GaN was crystal grown.

The temperature of the wafer is raised to 1000 ° C, and on the upper surface of the last barrier layer 14A0, a p-type Al _0.18 Ga _0.82 N layer (p-type nitride semiconductor layer 16), a p-type GaN layer (p-type nitride) is used. The semiconductor layer 17) and the p-type contact layer (p-type nitride semiconductor layer 18) are sequentially crystal grown.

In the crystal growth of each of the above layers, TMG (trimethylgallium) is used as the raw material gas system of Ga, TMA (trimethylaluminum) is used as the raw material gas system of Al, and TMI (trimethylmethyl) is used as the raw material gas system of In. Indium), NH _{3 is} used as a raw material gas system for N. Further, SiH _{4 is} used as the raw material gas system of Si as the n-type dopant, and Cp ₂ Mg is used as the raw material gas system of Mg as the p-type dopant. However, the material gas is not limited to the above gas, and may be used without limitation as long as it is a gas used as a material gas for MOCVD. For example, TEG (triethylgallium) can be used as a raw material gas of Ga, TEA (triethylaluminum) can be used as a raw material gas of Al, and TEI (triethylindium) can be used as a raw material gas of In, and DMHy can be used. As the raw material gas of N, an organic nitrogen compound such as (dimethyl hydrazine) can be used as a raw material gas of Si by using Si ₂ H ₆ or organic Si.

The wafer is taken out from the second MOCVD apparatus. Thereafter, the p-type contact layer (p-type nitride semiconductor layer 18), the p-type GaN layer (p-type nitride semiconductor layer 17), and p-type Al _0.18 Ga _{0.82 are} etched so as to expose a portion of the n-type contact layer 8. N-layer (p-type nitride semiconductor layer 16), light-emitting layer 14, superlattice layer 122, multilayer structure 121, Si-doped GaN layer (V-pit generation layer 10), n-type modulation doped layer 9 and N-type contact layer 8. On the upper surface of the n-type contact layer 8 exposed by the etching, an n-side electrode 21 containing Au is formed. On the upper surface of the p-type contact layer 18, a transparent electrode 23 containing ITO and a p-side electrode 25 containing Au are sequentially formed. A transparent protective film 27 containing SiO ₂ is formed so as to mainly cover the transparent electrode 23 and the side faces of the respective layers exposed by the etching. Thereafter, the wafer was divided into wafers having a size of 620 × 680 μm. Thereby, the nitride semiconductor light-emitting element of Example 1 was obtained.

In the present embodiment, the time required for the temperature lowering step after the formation of the Si-doped GaN layer (V-pit generation layer 10) is shortened, whereby a high throughput can be maintained. Moreover, the frequency of maintaining the second MOCVD apparatus is lowered.

<Example 2>

In the same manner as in the first embodiment, after the underlayer 7 and the n-type contact layer 8 were formed in the first MOCVD apparatus, the temperature of the wafer was set to 1081 ° C to form an n-type modulation doped layer 9. A nitride semiconductor layer containing Si-doped n-type GaN having a thickness of 50 nm is grown on the n-type contact layer 8 by MOCVD (n ⁺ layer 9A, n-type dopant concentration: 1 × 10 ¹⁹ cm ^{-3 )} a nitride semiconductor layer (n ^- layer 9B) containing undoped GaN having a thickness of 87 nm, and a nitride semiconductor layer containing Si-doped n-type GaN having a thickness of 50 nm (n ⁺ layer 9A, n-type dopant concentration) : 1 × 10 ¹⁹ cm ^-3 ).

Next, the wafer was taken out from the first MOCVD apparatus and placed in the second MOCVD apparatus. The temperature of the wafer was set to 801 ° C, and an undoped GaN layer (n ^- layer 9BL) having a thickness of 10 nm was grown by MOCVD. Then, in the same manner as in the first embodiment, a Si-doped GaN layer (V-pit generation layer 10), a multilayer structure 121, and a superlattice are formed in the second MOCVD apparatus while maintaining the wafer temperature at 801 °C. Layer 122. The nitride semiconductor light-emitting element of the present embodiment was fabricated in this manner. In the present embodiment, the time required for the temperature lowering step after the formation of the n ^- layer 9BL is also shortened.

<Example 3>

The nitride semiconductor of the present embodiment was fabricated according to the method described in the above first embodiment, except that the V-pit generation layer 10, the multilayer structure 121, and the superlattice layer 122 were crystallized by setting the temperature of the wafer to 750 °C. Light-emitting element. In the present embodiment, the time required for the temperature lowering step after the formation of the Si-doped GaN layer (V-pit generation layer 10) is also shortened. Moreover, the luminous efficiency of the higher MQW light-emitting layer 14 can be maintained.

<Example 4>

The nitride semiconductor light-emitting device of the present example was produced by the method described in the above first embodiment except that the multilayer structure 121 and the superlattice layer 122 were crystallized by setting the temperature of the wafer to 750 °C. In the present embodiment, the time required for the temperature lowering step after the formation of the Si-doped GaN layer (V-pit generation layer 10) is also shortened. Further, the size of the V-pit 15 becomes large.

<Example 5>

The nitride semiconductor light-emitting device of the present example was produced by the method described in the above Example 4 except that the temperature of the wafer was set to 700 ° C to crystallize the superlattice layer 122. In the present embodiment, the time required for the temperature lowering step after the formation of the Si-doped GaN layer (V-pit generation layer 10) is also shortened. Further, the size of the V-pit 15 becomes large.

<Example 6>

In the sixth embodiment, the first laminate is composed of a substrate, a buffer layer, a base layer, and an n-type contact layer, and the second laminate includes a low-doped n-type nitride semiconductor layer and an undoped nitride semiconductor layer. In the configuration of the n-type nitride semiconductor layer, the composition of the barrier layer of the light-emitting layer was made of AlGaN, and a nitride semiconductor light-emitting device was produced according to the method described in the first embodiment. That is, in the present embodiment, the low-doped n-type nitride semiconductor layer corresponds to the "second n-type nitride semiconductor layer" in the patent application.

Fig. 6 is a schematic cross-sectional view showing the nitride semiconductor light-emitting device 1 of the present embodiment. Fig. 7 is an energy diagram schematically showing the magnitude of the band gap energy Eg in the n-type contact layer 8 to the p-type nitride semiconductor layer 16 of the nitride semiconductor light-emitting element 1 of the present embodiment. In Figure 6 and Figure 7, in the package The layer having the same composition as that of the above-described embodiment 1 is denoted by the same reference numeral as the symbol in Fig. 1. Further, in FIG. 7, a small dot is indicated on the right side of the layer doped with the n-type dopant and described as "n".

The wafer in which the buffer layer 5 is formed is placed in the first MOCVD apparatus. The first underlayer 71 containing undoped GaN was grown by MOCVD at a pressure of 500 Torr and a temperature of 990 °C. Further, the second underlayer 75 containing undoped GaN was grown by MOCVD at a pressure of 200 Torr and a temperature of 1080 °C. The thickness of the base layer 7 was 3 μm. Thereafter, a Si-doped n-type GaN layer (n-type contact layer 8) was grown by MOCVD at a temperature of 1,100 °C. The n-type contact layer 8 has a thickness of 4 μm, and the n-type contact layer 8 has an n-type dopant concentration of 1 × 10 ¹⁹ cm ^-3 .

After the formation of the n-type contact layer 8, the wafer temperature is lowered to below 500 ° C (down to 100 ° C if possible). After the wafer was temporarily taken out from the first MOCVD apparatus to the atmosphere, it was placed in a second MOCVD apparatus. The temperature of the wafer was set to 870 ° C, and a Si-doped GaN layer (low-doped n-type nitride semiconductor layer 10A) having a thickness of 74 nm was grown by MOCVD. The crystallized low-doped n-type nitride semiconductor layer 10A is in contact with the uppermost layer of the n-type contact layer 8 (the first surface 61 of the first layered body 6), and has an n-type dopant concentration of 7 × 10 ^{17 .} Cm ^-3 .

The undoped GaN layer (undoped nitride semiconductor layer 123) having a thickness of 63.5 nm was grown in a state where the wafer temperature was maintained at 870 °C.

A Si-doped AlGaN layer (n-type nitride semiconductor layer 124) having a thickness of 20.5 nm was grown in a state where the wafer temperature was maintained at 870 °C. Through crystal growth of the contact layer 14 of n-type nitride-based semiconductor layer 124 and the light emitting layer, an n-type dopant concentration which is based 1 × 10 ¹⁹ cm ^-3.

In the present embodiment, the temperature of the wafer when the low-doped n-type nitride semiconductor layer 10A, the undoped nitride semiconductor layer 123, and the n-type nitride semiconductor layer 124 are formed is fixed at 870 °C. However, the temperature of the wafer when the layers are formed can be arbitrarily set as long as it is in the temperature range of 850 to 950 °C. For example, from the viewpoint of improving the surface flatness of the second layered body 11 In addition, the temperature of the wafer when the low-doped n-type nitride semiconductor layer 10A and the undoped nitride semiconductor layer 123 are formed may be 870 ° C, and the n-type nitride semiconductor layer 124 will be formed. The temperature of the wafer was set to 900 °C. Further, the temperatures of the wafers at the time of forming the three layers can be set to different temperatures.

<Comparative Example 1>

After the wafer was taken out from the first MOCVD apparatus and placed in the second MOCVD apparatus, the temperature of the wafer was set to 1,100 ° C, and the n-type modulation doping layer 9 was crystal grown. The method described in the above Example 1 was used. A nitride semiconductor light-emitting device of a comparative example. In the present comparative example, the time required for the temperature lowering step after the formation of the superlattice layer 122 becomes longer than that of the above-described first embodiment. Moreover, the frequency of maintaining the second MOCVD apparatus is higher than that of the first embodiment.

The embodiments of the present invention have been described by way of example only. The scope of the present invention is defined by the scope of the claims, and is intended to be

1‧‧‧Nitride semiconductor light-emitting elements

3‧‧‧Substrate

3a‧‧‧ convex

3b‧‧‧ recess

5‧‧‧buffer layer

6‧‧‧1st laminate

7‧‧‧ basal layer

8‧‧‧n type contact layer

8A‧‧‧n type contact layer

8B‧‧‧n type contact layer

9‧‧‧n type modulation doping layer

10‧‧‧V pit generation layer

11‧‧‧2nd layered body

14‧‧‧Lighting layer

15‧‧‧V pit

16‧‧‧p-type nitride semiconductor layer

17‧‧‧p-type nitride semiconductor layer

18‧‧‧p-type nitride semiconductor layer

21‧‧‧n side electrode

23‧‧‧Transparent electrode

25‧‧‧p side electrode

27‧‧‧Transparent protective film

30‧‧‧Face

61‧‧‧1st

71‧‧‧1st basal layer

71a‧‧‧Sloping facets

71b‧‧‧ upper surface

75‧‧‧2nd basal layer

75b‧‧‧ upper surface

121‧‧‧Multilayer structure

122‧‧‧Superlattice layer

Claims (6)

A nitride semiconductor light-emitting device comprising: a first layered body including one or more first n-type nitride semiconductor layers; and a second layered body including a first surface of the first layered body a 2n-type nitride semiconductor layer; a light-emitting layer provided on the second layered body; and a p-type nitride semiconductor layer provided on the light-emitting layer; wherein the second n-type nitride semiconductor layer is formed The temperature of the first n-type nitride semiconductor layer is formed at a lower temperature. The nitride semiconductor light-emitting device according to claim 1, wherein the second build-up system further includes one or more third n-type nitride semiconductor layers between the second n-type nitride semiconductor layer and the light-emitting layer; The 3n-type nitride semiconductor layer is formed at a temperature equal to or lower than the formation temperature of the second n-type nitride semiconductor layer. The nitride semiconductor light-emitting device according to claim 1 or 2, wherein the semiconductor layer constituting the first surface of the first layered body is an undoped layer; and the second n-type nitride semiconductor layer is a doped layer. The nitride semiconductor light-emitting device according to claim 1 or 2, wherein the semiconductor layer constituting the first surface of the first layered body is a doped layer; and the second n-type nitride semiconductor layer is an undoped layer. A method for producing a nitride semiconductor light-emitting device, comprising: a step of forming a first layered body including a first n-type nitride semiconductor layer of one or more layers; and forming a first surface of the first layered body a step of forming a second layered body of the second n-type nitride semiconductor layer; a step of forming a light-emitting layer on the second layered body; and a step of forming a p-type nitride semiconductor layer on the light-emitting layer; and forming the above temperature at a temperature lower than a temperature at which the first n-type nitride semiconductor layer is formed The second n-type nitride semiconductor layer further includes a temperature lowering step of lowering the temperature to a temperature lower than a temperature at which the second layered body is formed, after the step of forming the first layered body and forming the second layered body. The method for producing a nitride semiconductor light-emitting device according to claim 5, further comprising the step of exposing the first layered body to the atmosphere before the step of forming the second layered body after the step of lowering the temperature.