JP6124740B2 - Nitride semiconductor light emitting device manufacturing method, nitride semiconductor light emitting device, and base substrate for nitride semiconductor light emitting device - Google Patents

Description

  The present invention relates to a method for manufacturing a nitride semiconductor light emitting device, a nitride semiconductor light emitting device, and a base substrate for the nitride semiconductor light emitting device.

  A group III-V compound semiconductor (group III nitride semiconductor) containing nitrogen has a band gap energy corresponding to the energy of light having a wavelength in the infrared region to the ultraviolet region. Therefore, Group III nitride semiconductors are useful as materials for light-emitting elements that emit light having wavelengths from the infrared region to the ultraviolet region, or as materials for light-receiving devices that receive light having wavelengths from the infrared region to the ultraviolet region. It is.

  Further, the bonds between the atoms constituting the group III nitride semiconductor are strong, the breakdown voltage of the group III nitride semiconductor is high, and the saturation electron velocity is high. Therefore, the group III nitride semiconductor is also useful as a material for electronic devices such as high temperature resistance, high output, and high frequency transistors.

  Further, group III nitride semiconductors are attracting attention as easy-to-handle materials because they hardly harm the environment.

  In order to manufacture a practical nitride semiconductor device using a group III nitride semiconductor, which is an excellent material as described above, a thin film (group III nitride semiconductor) made of a group III nitride semiconductor on a predetermined substrate is used. Layer) to form a predetermined element structure.

  Here, as the substrate, it is most preferable to use a substrate made of a group III nitride semiconductor having a lattice constant, a thermal expansion coefficient, or the like capable of directly growing the group III nitride semiconductor on the substrate. Examples of the substrate made of a group III nitride semiconductor include a gallium nitride (GaN) substrate. However, the GaN substrate is not practical because its size is currently as small as 2 inches or less in diameter and is very expensive. Therefore, at present, as a substrate for manufacturing a nitride semiconductor element, a sapphire substrate or a silicon carbide (SiC) substrate having a large lattice constant difference and a large thermal expansion coefficient difference from a group III nitride semiconductor is used.

  There is a lattice constant difference of about 16% between sapphire and GaN (a typical example of a group III nitride semiconductor). There is a lattice constant difference of about 6% between SiC and GaN. When such a large lattice constant difference exists between a substrate material and a group III nitride semiconductor grown on the substrate, it is common to epitaxially grow a crystal made of a group III nitride semiconductor on the substrate. Is difficult. For example, when a GaN crystal is directly epitaxially grown on a sapphire substrate, there is a problem that a three-dimensional growth of the GaN crystal is inevitable and a GaN crystal having a flat surface cannot be obtained.

  Therefore, a so-called buffer layer is generally formed between the substrate and the group III nitride semiconductor layer so as to eliminate the lattice constant difference between the substrate material and the group III nitride semiconductor. It is done.

For example, in Patent Document 1, a buffer layer made of AlN is formed on a sapphire substrate by metal organic vapor phase epitaxy (MOVPE method), and then a group III nitride semiconductor layer made of Al _x Ga _1-x N is grown. Is described.

  Patent Document 2 describes the following method as a method for growing a group III nitride semiconductor layer. First, a sapphire substrate having a concavo-convex process is prepared. Next, epitaxial growth of GaN is started from the bottom surface of the concave portion of the sapphire substrate, and the GaN layer is formed to have an isosceles triangular cross-sectional shape with the bottom surface as a base and a facet inclined with respect to the main surface of the sapphire substrate. Grow. Subsequently, when the growth condition is set to a condition in which the lateral growth becomes dominant and the growth is continued, the GaN layer spreads on the convex portion of the sapphire substrate while increasing its thickness, and finally the adjacent sapphire substrate. The GaN layers grown from the recesses are in contact with each other on the protrusions of the sapphire substrate.

  When growing a group III nitride semiconductor layer, in general, an n-type nitride semiconductor layer, a light emitting layer, and a p-type nitride semiconductor layer are sequentially formed in the same metal organic vapor phase growth apparatus. However, when dopants having different conductivity types are supplied into the same metal organic vapor phase growth apparatus, there may be a problem that unintended impurities are doped.

  Therefore, in Patent Document 3, in the first organometallic chemical vapor deposition apparatus, an underlayer, a first n-type semiconductor layer, and a second n-type semiconductor layer are sequentially stacked on a substrate, and second organometallic chemical vapor deposition is performed. In the device, a light emitting layer and a p-type semiconductor layer are sequentially stacked after a regrowth layer of the second n-type semiconductor layer is formed on the second n-type semiconductor layer. However, since the cooling of the substrate and the heating of the substrate are repeated each time the growth chamber is changed, it may not be possible to obtain a semiconductor light emitting device with excellent performance. In Patent Document 4, it is proposed to perform heat treatment before forming the regrowth layer. Patent Document 5 proposes that the temperature of the substrate when forming the regrowth layer be in the range of 600 ° C to 900 ° C.

JP-A-2-229476 JP 2006-352084 A JP 2012-119390 A JP 2012-4155 A JP 2011-181673 A JP 2012-248656 A JP 2012-146736 A JP2011-138893A

  If heat treatment is performed before forming the regrowth layer as proposed in Patent Document 4, it takes extra time to manufacture the nitride semiconductor light emitting device, which increases the manufacturing cost. Further, the substrate may be broken by the heat treatment.

  If the temperature of the substrate when forming the regrowth layer as proposed in Patent Document 5 is lowered, the crystal quality of the nitride semiconductor layer is lowered. Therefore, the n-type nitride semiconductor layer described in Patent Document 6 (the n-type contact layer, the undoped semiconductor layer, and the n-type multilayer film layer are sequentially stacked) is configured according to the method described in Patent Document 5. However, it is difficult to obtain the effect described in Patent Document 6 that leakage current when applying a reverse bias can be prevented while reducing the forward voltage.

  When the substrate is transported from the first metal organic chemical vapor deposition apparatus to the second metal organic chemical vapor deposition apparatus, the surface of the substrate is oxidized by moisture or oxygen in the atmosphere, so that the regrowth surface is abnormal. May bring. As a method for solving this problem, Patent Document 7 describes forming a layer that can be removed by heat treatment on the outermost surface of the substrate. However, in the method described in Patent Document 7, an extra layer is formed on the substrate. In addition, extra heat treatment is required to remove the layer formed on the outermost surface of the substrate. Thus, since it takes extra time to manufacture the nitride semiconductor light emitting device, the manufacturing cost increases. In addition, the substrate is cracked by heat treatment.

  In Patent Document 8, a first n-type semiconductor layer is formed on a substrate in a first metal organic chemical vapor deposition apparatus, and the first n-type semiconductor layer is formed in a second metal organic chemical vapor deposition apparatus. In this document, a regrowth layer made of an n-type semiconductor and a second n-type semiconductor layer doped with high-concentration Si exceeding the first n-type semiconductor layer are sequentially formed. However, in the method described in Patent Document 8, an abnormality may occur at the interface between the regrowth layer and the second n-type semiconductor layer due to a sharp increase in the amount of Si doping (pile-up). In addition, problems such as an increase in forward voltage or generation of leakage current when reverse bias is applied may occur.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a nitride semiconductor light emitting device having a high light emission output without being limited by growth conditions.

The method for manufacturing a nitride semiconductor light emitting device according to the present invention includes a step of preparing a base substrate having a growth surface. The step of preparing the base substrate includes a step of forming a first n-type nitride semiconductor layer on the substrate, and an n-type dopant concentration on the first n-type nitride semiconductor layer as compared with the first n-type nitride semiconductor layer. Forming a second n-type nitride semiconductor layer including a low n ⁻ layer.

  The semiconductor layer constituting the growth surface may be an undoped layer or a doped layer.

Forming a second 2n-type nitride semiconductor layer, the second 1n-type nitride semiconductor layer side, n ^- and layer, n-type dopant concentration the n ^- a step of alternately laminating high n ⁺ layer than the layer It is preferable to include. The thickness of the n ⁺ layer is preferably less than or equal to the thickness of the n ⁻ layer. The thickness of the second n ⁺ layer counting from the first n-type nitride semiconductor layer side is preferably 50 nm or more and 100 nm or less. The thickness of the third n ⁺ layer counted from the first n-type nitride semiconductor layer side is preferably equal to or less than the thickness of the second n ⁺ layer counted from the first n-type nitride semiconductor layer side. .

  The first n-type nitride semiconductor layer and the second n-type nitride semiconductor layer are preferably formed by metal organic chemical vapor deposition, hydride vapor deposition, or liquid phase growth.

  The nitride semiconductor light emitting device according to the present invention is manufactured according to the method for manufacturing a nitride semiconductor light emitting device according to the present invention.

The base substrate for a nitride semiconductor light emitting device according to the present invention includes a first n-type nitride semiconductor layer and an n-type dopant concentration lower than that of the first n-type nitride semiconductor layer on the first n-type nitride semiconductor layer. ^- and a second 2n-type nitride semiconductor layer including layers.

  According to the present invention, a nitride semiconductor light emitting device having a high light emission output can be manufactured without being limited by growth conditions.

1 is a schematic cross-sectional view of a nitride semiconductor light emitting device according to an embodiment of the present invention. FIG. 2 is a schematic plan view of the nitride semiconductor light emitting device shown in FIG. 1. FIG. 2 is an energy diagram schematically showing the magnitude of band gap energy Eg from the first n-type nitride semiconductor layer to the p-type nitride semiconductor layer of the nitride semiconductor light emitting device shown in FIG. 1. FIG. 2 is an enlarged plan view of a substrate of the nitride semiconductor light emitting device shown in FIG. FIG. 2 is a flowchart showing a part of the method for manufacturing the nitride semiconductor light emitting device shown in FIG. FIG. 6 is a flowchart showing one step in the method of manufacturing the nitride semiconductor light emitting device shown in FIG. FIG. 7 is a flowchart showing a part of another method for manufacturing the nitride semiconductor light emitting device shown in FIG. 1 in the order of steps.

  Hereinafter, the nitride semiconductor light emitting device of the present invention will be described with reference to the drawings. In the drawings of the present invention, the same reference numerals represent the same or corresponding parts. In addition, dimensional relationships such as length, width, thickness, and depth are changed as appropriate for clarity and simplification of the drawings, and do not represent actual dimensional relationships.

  In the following, in order to express the positional relationship, the portion described on the lower side of FIG. 1 may be expressed as “lower”, and the portion described on the upper side of FIG. 1 may be expressed as “upper”. This is an expression for convenience and is different from “upper” and “lower” defined for the direction of gravity.

  A “barrier layer” represents a layer sandwiched between well layers. The barrier layer not sandwiched between the well layers is referred to as “first barrier layer” or “last barrier layer”, and the description is changed from the barrier layer sandwiched between the well layers.

  “Dopant concentration” and “carrier concentration” which is the concentration of electrons or holes generated by doping with an n-type dopant or a p-type dopant are used. These relationships will be described later.

  The “carrier gas” is a gas other than the group III source gas, the group V source gas, and the dopant source gas. The atoms constituting the carrier gas are not taken into the film.

  The “n-type nitride semiconductor layer” may include a low carrier concentration n-type layer or an undoped layer with a thickness that does not impede practically the flow of electrons. The “p-type nitride semiconductor layer” may include a low carrier concentration p-type layer or an undoped layer having a thickness that does not impede the flow of holes in practice. “Not practically hindered” means that the operating voltage of the nitride semiconductor light emitting device is at a practical level.

<Structure of nitride semiconductor light emitting device>
1 and 2 are a schematic cross-sectional view and a schematic plan view, respectively, of a nitride semiconductor light emitting device 1 according to an embodiment of the present invention. FIG. 1 corresponds to a cross-sectional view taken along the line II shown in FIG. FIG. 3 is an energy diagram schematically showing the magnitude of the band gap energy Eg from the first n-type nitride semiconductor layer 8 to the p-type nitride semiconductor layer 16 of the nitride semiconductor light emitting device 1 shown in FIG. The vertical axis direction in FIG. 3 represents the vertical direction of the nitride semiconductor light emitting device 1 shown in FIG. 1, and Eg on the horizontal axis in FIG. 3 schematically represents the magnitude of the band gap energy in each layer. In FIG. 3, a dot is added to the right side of the layer doped with the n-type dopant, and “n” is indicated. 4 is an enlarged plan view of the substrate 3 of the nitride semiconductor light emitting device 1 shown in FIG.

  A nitride semiconductor light emitting device 1 shown in FIG. 1 includes a base substrate for nitride semiconductor light emitting devices (hereinafter simply referred to as “base substrate”) 6. The base substrate 6 includes a substrate 3, a buffer layer 5, a base layer 7, a first n-type nitride semiconductor layer (n-type contact layer) 8, and a second n-type nitride semiconductor layer (modulation doped layer) 9. Prepare. On the growth surface 61 of the base substrate 6, the third n-type nitride semiconductor layer 11, the light emitting layer 14, and the first p-type nitride semiconductor layer 19 are provided in this order. The third n-type nitride semiconductor layer 11 includes a V pit generation layer 10, a multilayer structure 121, and a superlattice layer 122. The first p-type nitride semiconductor layer 19 includes p-type nitride semiconductor layers 16, 17, and 18.

  Part of the base substrate 6, the third n-type nitride semiconductor layer 11, the light emitting layer 14, and the first p-type nitride semiconductor layer 19 are etched to form a mesa portion 30. A p-side electrode 25 is provided on the p-type nitride semiconductor layer 18 via a transparent electrode 23. Outside the mesa portion 30 (on the right side in FIG. 1), a part of the upper surface of the first n-type nitride semiconductor layer 8 is exposed from the second n-type nitride semiconductor layer 9 and the like. An n-side electrode 21 is provided on the exposed surface. The transparent protective film 27 covers the transparent electrode 23 and the side surface of each layer exposed by etching, and exposes the n-side electrode 21 and the p-side electrode 25.

  When the cross section of the nitride semiconductor light emitting device 1 is observed with ultra high magnification STEM (Scanning Transmission Electron Microscopy), it is confirmed that the V pit 15 is generated. In the nitride semiconductor light emitting device 1 according to this embodiment, the generation of the V pit 15 is controlled by providing the V pit generation layer 10.

<Base substrate>
In this embodiment, the base substrate 6 includes the substrate 3, the buffer layer 5, the base layer 7, the first n-type nitride semiconductor layer 8, and the second n-type nitride semiconductor layer 9, but the first n-type nitride semiconductor layer 8. And the second n-type nitride semiconductor layer 9 may be provided. The nitride semiconductor light emitting device 1 according to this embodiment may not include the substrate 3, and in this case, the base substrate 6 is the base layer 7, the first n-type nitride semiconductor layer 8, and the second n-type nitride semiconductor. Layer 9.

The 2n-type nitride semiconductor layer 9 in this embodiment, n-type dopant concentration is lower n than the 1n-type nitride semiconductor layer 8 ^- comprising a layer 9A. Thereby, the crystal quality of the third n-type nitride semiconductor layer 11 can be maintained higher than that in the case where the second n-type nitride semiconductor layer 9 does not include the n ⁻ layer 9A. Therefore, since the crystal quality of the light emitting layer 14 provided on the third n-type nitride semiconductor layer 11 can be maintained high, the light emission output of the nitride semiconductor light emitting element 1 can be increased. "Lower n-type dopant concentration than the 1n-type nitride semiconductor layer 8 n ^- layer 9A" is a, n ^- 1 is n-type dopant concentration of the layer 9A of n-type dopant concentration of the 1n-type nitride semiconductor layer 8 / It means 1000 times or more and less than 1 time. n ^- When the n-type dopant concentration of the layer 9A is 1/1000 of n-type dopant concentration of the 1n-type nitride semiconductor layer 8, the n ^- layer 9A is an undoped layer. That is, the “n ⁻ layer 9A having an n-type dopant concentration lower than that of the first n-type nitride semiconductor layer 8” includes an undoped layer. Thus, in this specification, the “undoped layer” includes not only a layer in which no conductive dopant is doped, but also a layer in which a conductive dopant is unintentionally doped during crystal growth. The “undoped layer” can also be said to be a layer containing a conductive dopant of 0 cm ⁻³ or more and 1 × 10 ¹⁶ cm ⁻³ or less.

  The base substrate 6 has a growth surface 61. The growth surface 61 means the surface of the base substrate 6 on which the third n-type nitride semiconductor layer 11 is crystal-grown. In the present embodiment, the base substrate 6 is formed by stacking the buffer layer 5, the base layer 7, the first n-type nitride semiconductor layer 8, and the second n-type nitride semiconductor layer 9 in this order from the substrate 3 side. The surface 61 is the upper surface of the second n-type nitride semiconductor layer 9 (the second n-type nitride semiconductor layer 9 located on the opposite side of the interface between the first n-type nitride semiconductor layer 8 and the second n-type nitride semiconductor layer 9). Equivalent to the surface).

  The semiconductor layer constituting the growth surface 61 is preferably an undoped layer. Thereby, even when the growth surface 61 is exposed to the atmosphere, the growth surface 61 can be prevented from being oxidized by moisture or oxygen in the atmosphere. Therefore, the crystal quality of the layer on the growth surface 61 (for example, the third n-type nitride semiconductor layer 11) can be further improved. Further, when an n-type nitride semiconductor layer is grown on the growth surface 61, an increase (pile-up) of the doping amount of the n-type dopant at the interface between the growth surface 61 and the n-type nitride semiconductor layer is prevented. Can do. From these things, since the crystal quality of the light emitting layer 14 can further be improved, the light emission output of the nitride semiconductor light-emitting device 1 can further be improved. The “semiconductor layer constituting the growth surface 61” corresponds to the second n-type nitride semiconductor layer 9 when the second n-type nitride semiconductor layer 9 is composed of one layer, and the second n-type nitride semiconductor layer 9 has 2 layers. In the case of having the above layers, it corresponds to a layer located farthest from the first n-type nitride semiconductor layer 8 among the two or more layers constituting the second n-type nitride semiconductor layer 9.

The semiconductor layer constituting the growth surface 61 may be a doped layer. In this case, the second n-type nitride semiconductor layer 9 includes, from the first n-type nitride semiconductor layer 8 side, an n ⁻ layer 9A and an n ⁺ layer 9B having an n-type dopant concentration higher than that of the n ⁻ layer 9A. It is preferable that they are laminated alternately. As a result, the forward voltage can be reduced, and the occurrence of leakage current when a reverse bias is applied can be prevented. “Doped layer” means a layer in which a conductive dopant is intentionally doped during crystal growth. The doped layer preferably contains, for example, a conductive dopant of 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less. The n-type dopant concentration of the n ⁺ layer 9B is preferably greater than 1 and less than or equal to 100 times the n-type dopant concentration of the first n-type nitride semiconductor layer 8. Hereinafter, the components of the base substrate 6 are shown.

<Board>
The substrate 3 may be, for example, an insulating substrate such as a sapphire substrate or a conductive substrate made of GaN, SiC, ZnO, or the like. The thickness of the substrate 3 is preferably 900 μm or more and 1200 μm or less when the nitride semiconductor layer is grown, and in the manufactured nitride semiconductor light emitting device 1, it is preferably 50 μm or more and 300 μm or less. That is, the method for manufacturing the nitride semiconductor light emitting device 1 may include a step of polishing the substrate 3. In addition, the method for manufacturing the nitride semiconductor light emitting device 1 may include a step of removing the substrate 3.

  The surface of the substrate 3 on which the buffer layer 5 and the like are provided (the upper surface of the substrate 3) preferably has an uneven shape in which convex portions 3a and concave portions 3b are alternately formed as shown in FIG. The convex portion 3a preferably has a substantially circular shape on the upper surface of the substrate 3 as shown in FIG. 4, and is preferably arranged at the apex of the virtual triangle 3t shown in FIG. The distance between the apexes of adjacent convex portions 3a (one side of the virtual triangle 3t shown in FIG. 4) is preferably 1 μm or more and 5 μm or less. The convex portion 3a may have a trapezoidal shape in a side view, but the vertex of the convex portion 3a is preferably rounded as shown in FIG.

<Buffer layer>
The buffer layer 5 is provided on the convex portion 3a of the substrate 3 and the concave portion 3b. The buffer layer 5 is preferably, for example, an Al _so Ga _to O _u N _1-uo (0 ≦ s0 ≦ 1, 0 ≦ t0 ≦ 1, 0 ≦ u0 ≦ 1, s0 + t0 ≠ 0) layer, More preferably, it is an AlON layer. When the buffer layer 5 is an AlON layer, it is preferable that a small part (0.5 to 2%) of N in the AlON layer is replaced with oxygen. Thereby, since the buffer layer 5 is formed so as to extend in the normal direction of the growth surface of the substrate 3, the buffer layer 5 made of an aggregate of columnar crystals with uniform crystal grains is obtained. The thickness of the buffer layer 5 is not particularly limited, but is preferably 3 nm or more and 100 nm or less, and more preferably 5 nm or more and 50 nm or less. If the buffer layer 5 is an AlON layer formed by sputtering, the half width of the peak appearing in the X-ray spectrum (index of crystal quality of the underlayer 7) is narrowed. Therefore, the buffer layer 5 is preferably an AlON layer formed by sputtering.

<Underlayer>
The underlayer 7 preferably has a first underlayer 71 and a second underlayer 75. Thereby, the half width of the peak appearing in the X-ray spectrum (index of crystal quality of the underlayer 7) is narrowed, that is, the crystal quality of the underlayer 7 is increased. The first base layer 71 is provided on the recess 3b of the substrate 3 with the buffer layer 5 interposed therebetween, and preferably has a substantially triangular shape in a side view including the oblique facet surface 71a, and may have an upper surface 71b. The “oblique facet plane” is a plane extending in a direction inclined at an angle of 10 ° or more with respect to the recess 3b of the substrate 3, and is preferably a crystal plane of a nitride semiconductor. The second underlayer 75 covers the first underlayer 71 and covers the convex portion 3 a of the substrate 3 with the buffer layer 5 interposed therebetween, and is in contact with the buffer layer 5 and the first underlayer 71. The surface of the foundation layer 7 in contact with the first n-type nitride semiconductor layer 8 (the upper surface 75b of the foundation layer 7) is flat. In the present specification, the first underlayer 71 and the second underlayer 75 are sometimes collectively referred to as the underlayer 7 unless otherwise specified.

The first underlayer 71 is preferably made of, for example, Al _x2 Ga _y2 In _z2 N (0 ≦ x2 ≦ 1, 0 ≦ y2 ≦ 1, 0 ≦ z2 ≦ 1, x2 + y2 + z2 ≠ 0). The second underlayer 75 is preferably made of, for example, Al _x3 Ga _y3 In _z3 N (0 ≦ x3 ≦ 1, 0 ≦ y3 ≦ 1, 0 ≦ z3 ≦ 1, x3 + y3 + z3 ≠ 0).

The first underlayer 71 and the second underlayer 75 are each preferably a nitride semiconductor layer containing Ga as a group III element. As a result, the first underlayer 71 and the second underlayer 75 can be formed without taking over crystal defects such as dislocations in the buffer layer 5 made of an aggregate of columnar crystals. Specifically, in order to provide the first underlayer 71 and the second underlayer 75 without taking over crystal defects in the buffer layer 5, dislocations are looped near the interface with the buffer layer 5 (the upper surface of the buffer layer 5). There is a need. If the first underlayer 71 and the second underlayer 75 are group III nitride semiconductor layers containing Ga, dislocation loops are likely to occur near the interface with the buffer layer 5. That is, if the first underlayer 71 and the second underlayer 75 are nitride semiconductor layers containing Ga as a group III element, crystal defects in the buffer layer 5 are looped and confined near the interface with the buffer layer 5. It is done. Therefore, it is possible to prevent crystal defects in the buffer layer 5 from being taken over by the first underlayer 71 and the second underlayer 75. For example, the first underlayer 71 is made of Al _x2 Ga _y2 N (0 ≦ x2 <1, 0 <y2 <1), and the second underlayer 75 is Al _x3 Ga _y3 N (0 ≦ x3 <1, 0 <y3 < In the case of 1), particularly when the first underlayer 71 and the second underlayer 75 are each made of GaN, crystal defects in the buffer layer 5 are looped near the interface with the buffer layer 5 and are easily confined. Thereby, the first underlayer 71 and the second underlayer 75 having a small dislocation density and good crystal quality are obtained.

The first underlayer 71 and the second underlayer 75 may include, for example, an n-type dopant of 1 × 10 ¹⁷ cm ⁻³ or more and 1.5 × 10 ¹⁹ cm ⁻³ or less. The n-type dopant contained in the underlayer 7 is preferably, for example, at least one of Si, Ge, and Sn, and more preferably Si. When the n-type dopant is Si, the source gas for the n-type dopant is preferably, for example, silane or disilane. However, from the viewpoint of maintaining good crystal quality, it is preferable that each of the first underlayer 71 and the second underlayer 75 is an undoped layer.

  The thickness of the foundation layer 7 (the distance between the surface of the foundation layer 7 in contact with the recess 3b of the substrate 3 and the upper surface 75b of the foundation layer 7) is not particularly limited. As the thickness of the underlayer 7 increases, crystal defects in the underlayer 7 decrease. However, if the thickness of the underlayer 7 is increased to some extent, the effect of reducing crystal defects in the underlayer 7 may be saturated. For these reasons, the thickness of the underlayer 7 is preferably 1 μm or more and 8 μm or less, and more preferably 3 μm or more and 5 μm or less.

  The formation method of the first underlayer 71 and the second underlayer 75 is preferably an MOCVD (Metal Organic Chemical Vapor Deposition) method. The first underlayer 71 is preferably grown in a facet growth mode in which the oblique facet surface 71a is formed. Thereby, the first underlayer 71 having few crystal defects and high crystal quality is formed. The second underlayer 75 is preferably grown in a buried growth mode in which the oblique facet surface 71a is buried to form a flat upper surface 75b. As a result, the second underlayer 75 having a flat upper surface 75b, few crystal defects, and high crystal quality is formed.

  The growth temperature of the first underlayer 71 and the second underlayer 75 is preferably 800 ° C. or higher and 1250 ° C. or lower, and more preferably 900 ° C. or higher and 1150 ° C. or lower. Thereby, the first underlayer 71 and the second underlayer 75 having few crystal defects and excellent crystal quality can be formed. In this specification, “growth temperature” means the temperature of the substrate 3 when the layer is crystal-grown.

<First n-type nitride semiconductor layer>
The first n-type nitride semiconductor layer 8 is provided on the upper surface 75b of the second foundation layer 75 and functions as an n-type contact layer. In the first n-type nitride semiconductor layer 8, for example, an Al _{s2 Gat 2} In _{u 2} N (0 ≦ s2 ≦ 1, 0 ≦ t2 ≦ 1, 0 ≦ u2 ≦ 1, s2 + t2 + u2≈1) layer is doped with an n-type dopant. Al _s2 Ga _{1 -s2} N (0 ≦ s2 ≦ 1, preferably 0 ≦ s2 ≦ 0.5, more preferably 0 ≦ s2 ≦ 0.1) layer is doped with n-type dopant More preferably, it is a layer formed. The first n-type nitride semiconductor layer 8 may further include an undoped layer or a low carrier concentration layer.

The n-type dopant contained in the first n-type nitride semiconductor layer 8 is not particularly limited, but is preferably Si, P, As, or Sb, and more preferably Si. The n-type dopant concentration of the first n-type nitride semiconductor layer 8 is not particularly limited, but is preferably 1.5 × 10 ¹⁹ cm ⁻³ or less.

  The thicker the first n-type nitride semiconductor layer 8 is, the lower the resistance of the first n-type nitride semiconductor layer 8 is. However, if the thickness of the first n-type nitride semiconductor layer 8 is increased, the manufacturing cost of the nitride semiconductor light emitting device 1 may be increased. In consideration of both, it is preferable that the maximum thickness of the first n-type nitride semiconductor layer 8 is not less than 1 μm and not more than 10 μm.

  The configuration of the first n-type nitride semiconductor layer 8 is not particularly limited. The first n-type nitride semiconductor layer 8 may consist of only one n-type nitride semiconductor layer in which the n-type dopant is uniformly doped, or the n-type nitride semiconductor layers 8A having different n-type dopant concentrations. , 8B, or three or more n-type nitride semiconductor layers. When the first n-type nitride semiconductor layer 8 includes two or more n-type nitride semiconductor layers, the two or more n-type nitride semiconductor layers may have the same composition or different compositions. . Two or more n-type nitride semiconductor layers may have the same thickness or different thicknesses.

<Second n-type nitride semiconductor layer>
The second n-type nitride semiconductor layer 9 is provided on the first n-type nitride semiconductor layer 8. The second n-type nitride semiconductor layer 9 may consist of only the n ⁻ layer 9A, but is preferably a modulation doped layer. If the second n-type nitride semiconductor layer 9 is a modulation doped layer, the forward voltage can be sufficiently reduced, and the occurrence of leakage current when a reverse bias is applied can be sufficiently prevented. The “modulation doped layer” means a layer formed by alternately laminating two or more kinds of layers having different kinds of dopants or different amounts of dopants. For example, the second n-type nitride semiconductor layer 9 is preferably formed by alternately stacking n ⁻ layers 9A and n ⁺ layers 9B from the first n-type nitride semiconductor layer 8 side.

The n ⁻ layer 9A is a nitride semiconductor layer having an n-type dopant concentration lower than that of the first n-type nitride semiconductor layer 8, and is preferably a nitride semiconductor layer having an n-type dopant concentration lower than that of the n ⁺ layer 9B. More preferably, it is an undoped layer. The n ⁻ layer 9A is formed of, for example, Al _{s3 Gat3} In _u3 N (0 ≦ s3 ≦ 1, 0 ≦ t3 ≦ 1, 0 ≦ u3 ≦ 1, s3 + t3 + u3 having an n-type dopant concentration of 3 × 10 ¹⁸ cm ⁻³ or less. ≈1) layer, preferably undoped Al _{s3 Gat3} In _u3 N (0 ≦ s3 ≦ 1, 0 ≦ t3 ≦ 1, 0 ≦ u3 ≦ 1, s3 + t3 + u3≈1) layer.

N ⁺ layer 9B is preferably a nitride semiconductor layer having an n-type dopant concentration higher than that of n ⁻ layer 9A. For example, Al _s4 Ga having an n-type dopant concentration of 1.0 × 10 ¹⁹ cm ⁻³ or more. _t4 In _u4 N (0 ≦ s4 ≦ 1, 0 ≦ t4 ≦ 1, 0 ≦ u4 ≦ 1, s4 + t4 + u4≈1) layer is preferable, and the n-type dopant concentration is 1.0 × 10 ¹⁹ cm ⁻³ or more 3 It is more preferable that the GaN layer be × 10 ¹⁹ cm ⁻³ or less. The n-type dopant is not particularly limited, but is preferably Si, P, As, or Sb, and more preferably Si.

The number of stacked layers of n ⁻ layer 9A and n ⁺ layer 9B is not particularly limited. The second n-type nitride semiconductor layer 9 preferably has two or more combinations of the n ⁻ layer 9A and the n ⁺ layer 9B, but includes only one n ⁻ layer 9A as described above. Also good.

Each thickness of n ⁻ layer 9A is preferably, for example, 5 nm or more and 500 nm or less, and more preferably 50 nm or more and 100 nm or less. If the thickness of each of the n ⁻ layers 9A is 50 nm or more, the n ⁺ layer 9B having excellent crystal quality can be formed, so that the effect obtained by providing the modulation doped layer can be sufficiently obtained. it can. Specifically, the forward voltage can be sufficiently reduced, and the occurrence of leakage current when a reverse bias is applied can be sufficiently prevented. If the thickness of each of the n ⁻ layers 9A is 100 nm or less, the driving voltage can be suppressed low.

Each thickness of n ⁺ layer 9B is, for example, preferably 5 nm or more and 500 nm or less, and more preferably 10 nm or more and 100 nm or less. If each thickness of n ⁺ layer 9B is 10 nm or more, second n-type nitride semiconductor layer 9 can sufficiently function as an n-type layer. If the thickness of each of the n ⁺ layers 9B is 100 nm or less, the driving voltage can be suppressed low. The thickness of n ⁺ layer 9B is preferably equal to or less than the thickness of n ⁻ layer 9A. Thereby, ESD (Electrostatic Discharge) breakdown voltage can be improved.

The 2n-type nitride semiconductor layer 9 the n ^- If the combination of the layer 9A and the n ⁺ layer 9B has two pairs, the thickness of the 3n-type nitride semiconductor layer 11 side of the n ⁺ layer 9B Part 1n It is preferable that the thickness is smaller than the thickness of n ⁺ layer 9B on the side of type nitride semiconductor layer 8. For example, when the thickness of the n ⁺ layer 9B on the first n-type nitride semiconductor layer 8 side is 50 nm, if the n ⁺ layer 9B on the third n-type nitride semiconductor layer 11 side is 25 nm or more and 50 nm or less, the forward direction The thickness of the second n-type nitride semiconductor layer 9 can be reduced while reducing the voltage, preventing the occurrence of leakage current when applying a reverse bias, and improving the ESD withstand voltage.

<Third n-type nitride semiconductor layer>
The third n-type nitride semiconductor layer 11 includes a V pit generation layer 10, a multilayer structure 121, and a superlattice layer 122. Hereinafter, components of the third n-type nitride semiconductor layer 11 will be shown.

<V pit generation layer>
The V pit generation layer 10 is provided on the growth surface 61 of the base substrate 6, and the average position of the starting point of the V pit 15 effectively functions as a light emitting layer (in the present embodiment, the light emitting layer 14). This is a layer for forming the V pits 15 so as to be located in the layer (in this embodiment, the superlattice layer 122) located on the base substrate 6 side. The “starting point of the V pit 15” means the bottom of the V pit 15 (the lowest end of the V pit 15 in FIG. 1). The “average position of the starting point of the V pit 15” means that the position of the starting point of the V pit 15 formed in the light emitting layer 14 is averaged in the thickness direction of the nitride semiconductor light emitting device 1 (vertical direction in FIG. 1). It means the position obtained.

V pit generation layer 10 is preferably a highly doped n-type GaN layer having a thickness of 25 nm, for example. “Highly doped” is significantly (eg, 1.1 times or more, preferably 1.4 times or more) than the first n-type nitride semiconductor layer 8 or the second n-type nitride semiconductor layer 9 located under the V pit generation layer 10. This means that the n-type dopant concentration is high. Specifically, the n-type dopant concentration of the V pit generation layer 10 is preferably 5 × 10 ¹⁸ cm ⁻³ or more, more preferably 7 × 10 ¹⁸ cm ⁻³ or more, and 1 × 10 ^19. More preferably, it is cm ⁻³ or more. As a result, the film quality of the V pit generation layer 10 is lower than the film quality of the second n-type nitride semiconductor layer 9, so that the V pit generation effect by the V pit generation layer 10 is effectively exhibited.

When the semiconductor layer constituting the growth surface 61 of the base substrate 6 is the n ⁺ layer 9B, the V pit generation layer 10 may be an undoped layer, for example, an undoped nitride semiconductor layer having a thickness of 10 nm. It is preferable that

<Multilayer structure>
In the nitride semiconductor light emitting device 1 according to the present embodiment, the starting point of the V pit 15 is located closer to the base substrate 6 than the light emitting layer 14. If the multilayer structure 121 is provided between the V pit generation layer 10 and the superlattice layer 122, the V pit 15 formed by the V pit generation layer 10 may reach the multilayer structure 121 before reaching the V pit 15. Can be increased. Therefore, the light emission efficiency during high temperature driving or large current driving can be maintained high, and the defect rate due to ESD decreases.

  The multilayer structure 121 is configured by laminating a plurality of types of nitride semiconductor layers having different band gap energies, and a nitride semiconductor layer having a relatively small band gap energy and a relatively large band gap energy. It is preferable that the nitride semiconductor layers are alternately stacked. Thereby, the size of the V pit 15 generated in the V pit generation layer 10 is increased. Therefore, the defect rate due to ESD decreases.

  An example of the multilayer structure 121 includes an n-type InGaN layer having a thickness of 7 nm, an n-type GaN layer having a thickness of 30 nm, an n-type InGaN layer having a thickness of 7 nm on the V pit generation layer 10. An n-type GaN layer having a thickness of 20 nm is sequentially stacked.

  In the multilayer structure 121, the number of nitride semiconductor layers having a relatively small band gap energy and the number of nitride semiconductor layers having a relatively large band gap energy are not particularly limited. The multilayer structure 121 preferably includes two or more pairs of nitride semiconductor layers having a relatively small band gap energy and nitride semiconductor layers having a relatively large band gap energy. Thereby, the thickness of the multilayer structure 121 can be increased. Therefore, most of the average positions of the starting points of the V pits 15 are closer to the base substrate 6 than the vicinity of the center of the superlattice layer 122 in the thickness direction. Therefore, it is possible to maintain high light emission efficiency during high temperature driving or large current driving.

<Superlattice layer>
A superlattice layer 122 is provided between the V pit generation layer 10 and the light emitting layer 14 and on the multilayer structure 121. The main function of the superlattice layer 122 is to provide the V pit generation layer 10 further away from the light emitting layer 14 and to set the start point of the V pit 15 below the light emitting layer 14 or inside the super lattice layer 122. is there. The superlattice layer 122 may be composed of a single layer or may be formed by laminating two to three layers.

  The “superlattice layer” means a layer made of a crystal lattice whose periodic structure is longer than the basic unit cell by alternately laminating very thin crystal layers. The superlattice layer 122 has a superlattice structure formed by laminating a plurality of types of nitride semiconductor layers. As shown in FIG. 3, the wideband gap layer 122A and the bandgap energy are relatively large. Relatively small narrow band gap layers 122B are alternately stacked to form a superlattice structure.

<Light emitting layer>
The light emitting layer 14 is provided on the third n-type nitride semiconductor layer 11. In the light emitting layer 14, V pits 15 are partially formed. “Partial V pits 15 are formed” means that the V pits 15 are point-like on the upper surface of the light emitting layer 14 when the upper surface of the light emitting layer 14 is observed with an AFM (Atomic Force Microscope). Means to be observed. The density of the number of V pits on the upper surface of the light emitting layer 14 is preferably 1 × 10 ⁸ cm ⁻² or more and 1 × 10 ¹⁰ cm ⁻² or less. Conventionally, V pits were formed in the light emitting layer, but the density of the number of V pits on the upper surface of the conventional light emitting layer was less than 1 × 10 ⁸ cm ⁻² .

  As shown in FIG. 3, the light emitting layer 14 preferably has a stacked structure in which barrier layers 14A and well layers 14W are alternately stacked. The first barrier layer 14Az is preferably provided immediately above the superlattice layer 122. The last barrier layer 14A0 is preferably provided on the well layer 14W1 located closest to the first p-type nitride semiconductor layer 19 in the well layer 14W.

  In the present embodiment, in order to identify each barrier layer 14A and each well layer 14W, the p-type nitride semiconductor layer 16 is numbered from the superlattice layer 122 to the well layer 14W1, the barrier layer 14A1, and the well layer. 14W2, barrier layer 14A2,... Unless otherwise specified, each barrier layer 14A and each well layer 14W are referred to as “barrier layer 14A” and “well layer 14W”.

The composition of each well layer 14 </ b> W is preferably adjusted according to the emission wavelength required for the nitride semiconductor light emitting device 1, for example, Al _c Ga _d In _(1-cd) N (0 ≦ c <1, 0 <D ≦ 1) is preferable, and In _e Ga _(1-e) N (0 <e ≦ 1) not containing Al is more preferable. For example, when the nitride semiconductor light emitting device 1 emits ultraviolet light having a wavelength of 375 nm or less, it is necessary to increase the band gap energy of the light emitting layer 14, and therefore the composition of each well layer 14W preferably includes Al. .

<First p-type nitride semiconductor layer>
The first p-type nitride semiconductor layer 19 is provided on the light emitting layer 14. As shown in FIG. 1, the first p-type nitride semiconductor layer 19 may be formed by stacking three p-type nitride semiconductor layers 16, 17, and 18, or two or less p-type nitride layers. A semiconductor layer may be included, or four or more p-type nitride semiconductor layers may be included. p-type nitride semiconductor layer 16, 17 and 18, for _{example, Al s6 Ga t6 In u6 N} (0 ≦ s6 ≦ 1,0 ≦ t6 ≦ 1,0 ≦ u6 ≦ 1, s6 + t6 + u6 ≠ 0) layer on the p-type dopant Is preferably a doped layer, and Al _s6 Ga _(1-s6) N (0 <s6 ≦ 0.4, preferably 0.1 ≦ s6 ≦ 0.3) layer is doped with a p-type dopant More preferably, it is a layer. For example, the p-type nitride semiconductor layer 16 is a p-type AlGaN layer. The p-type nitride semiconductor layer 17 is a p-type GaN layer. The p-type nitride semiconductor layer 18 is a p-type GaN layer having a p-type dopant concentration higher than that of the p-type nitride semiconductor layer 17.

A p-type dopant is not specifically limited, For example, it is preferable that it is Mg. The carrier concentration of the p-type nitride semiconductor layers 16, 17, 18 is preferably 1 × 10 ¹⁷ cm ⁻³ or more. Here, since the activation rate of the p-type dopant is about 0.01, the p-type dopant concentration (different from the carrier concentration) of the p-type nitride semiconductor layers 16, 17 and 18 is 1 × 10 ¹⁹ cm ^−3. The above is preferable. However, the p-type dopant concentration in the portion located on the light emitting layer 14 side of the p-type nitride semiconductor layer 16 may be less than 1 × 10 ¹⁹ cm ⁻³ .

  The total thickness of p-type nitride semiconductor layers 16, 17, and 18 (thickness of first p-type nitride semiconductor layer 19) is not particularly limited, and is preferably 50 nm or more and 300 nm or less. If the thickness of the p-type nitride semiconductor layers 16, 17, 18 is reduced, the heating time during the growth is shortened, so that the p-type dopant can be prevented from diffusing into the light emitting layer 14.

<N-side electrode, transparent electrode, p-side electrode>
The n-side electrode 21 and the p-side electrode 25 are electrodes for supplying driving power to the nitride semiconductor light emitting device 1. FIG. 2 shows that the n-side electrode 21 and the p-side electrode 25 are composed only of the pad electrode portion. However, elongated protrusions (branch electrodes) for current diffusion may be connected to the n-side electrode 21 and the p-side electrode 25 shown in FIG. In addition, an insulating layer for preventing current from being injected into the p-side electrode 25 is preferably provided below the p-side electrode 25. Thereby, the quantity by which the light which the light emitting layer 14 emitted is shielded by the p side electrode 25 can be decreased.

  The n-side electrode 21 preferably has a laminated structure in which, for example, a titanium layer, an aluminum layer, and a gold layer are laminated in this order. Assuming the case where wire bonding is performed on the n-side electrode 21, the thickness of the n-side electrode 21 is preferably 1 μm or more.

  The p-side electrode 25 preferably has a laminated structure in which, for example, a nickel layer, an aluminum layer, a titanium layer, and a gold layer are laminated in this order, but may be made of the same material as the n-side electrode 21. Assuming the case where wire bonding is performed on the p-side electrode 25, the thickness of the p-side electrode 25 is preferably 1 μm or more.

  The transparent electrode 23 is preferably made of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), and preferably has a thickness of 20 nm to 200 nm.

<V-pit start point>
In the nitride semiconductor light emitting device 1 according to the present embodiment, most of the starting points of the V pits 15 are not present in the light emitting layer 14, and the majority is considered to be present in the superlattice layer 122. Since the V pit 15 is considered to be generated due to threading dislocations, most of the threading dislocations are considered to be inside the V pit 15. Therefore, the electrons and holes injected into the light emitting layer 14 can be prevented from reaching threading dislocations inside the V pit 15. Therefore, it is considered that generation of non-radiative recombination can be suppressed because electrons and holes are captured by threading dislocations. Thereby, the fall of luminous efficiency can be prevented. This becomes conspicuous at a high temperature or during a large current drive.

  Specifically, since the movement of injected carriers (holes or electrons) to the light emitting layer 14 becomes active at high temperatures, the probability that the injected carriers reach threading dislocations increases. However, in the nitride semiconductor light emitting device 1 according to the present embodiment, many threading dislocations in the light emitting layer 14 are covered with the V pits 15 (since many threading dislocations exist inside the V pits 15), Non-radiative recombination at the dislocation is suppressed. Therefore, the light emission efficiency at high temperatures can be maintained high.

  In addition, since the starting point of the V pit 15 is located below the light emitting layer 14, the volume of the light emitting layer 14 can be increased by increasing the number of barrier layers (particularly the undoped barrier layer). Thereby, the light emission efficiency at the time of a large current drive can be maintained high.

<About carrier concentration and dopant concentration>
The carrier concentration means the concentration of electrons or holes, and is not determined only by the amount of n-type dopant or the amount of p-type dopant. Such a carrier concentration is calculated based on the result of the voltage-capacitance characteristics of the nitride semiconductor light emitting device 1, and means a carrier concentration in a state where no current is injected. The total number of carriers generated from defects and acceptor crystal defects.

  The activation rate of Si, which is an n-type dopant, is high. Therefore, it can be considered that the n-type carrier concentration is almost the same as the n-type dopant concentration. The n-type dopant concentration can be easily obtained by measuring the concentration distribution in the depth direction with SIMS (Secondary Ion Mass Spectroscopy). Furthermore, the relative relationship (ratio) of the dopant concentration is substantially the same as the relative relationship (ratio) of the carrier concentration. If the n-type dopant concentration obtained by the measurement is averaged in the thickness direction, the average n-type dopant concentration can be obtained.

<Other functions and effects of the second n-type nitride semiconductor layer and the superlattice layer>
In the nitride semiconductor light emitting device 1 according to this embodiment, the second n-type nitride semiconductor layer is disposed between the first n-type nitride semiconductor layer 8 and the light-emitting layer 14 in order from the first n-type nitride semiconductor layer 8 side. 9 (preferably n-type modulation doped layer), V pit generation layer 10, multilayer structure 121 and superlattice layer 122 are laminated. Thus, when a high voltage in the reverse bias direction that causes ESD breakdown is applied between the n-side electrode 21 and the p-side electrode 25, the depletion layer becomes the second n-type nitride semiconductor layer 9 and the superlattice. It extends to the layer 122 side. Therefore, the reverse bias voltage (electric field) applied to the light emitting layer 14 can be reduced. Therefore, the threshold voltage (that is, ESD withstand voltage) at which ESD breakdown occurs increases.

  Even when the nitride semiconductor light emitting device 1 according to the present embodiment is configured not to intentionally introduce the V pit 15, an increase in leakage current when a bias voltage is applied in the forward direction is suppressed. It is also possible to suppress a decrease in the light emitting area due to the formation of the V pit 15. Therefore, even if the nitride semiconductor light emitting device 1 according to the present embodiment is configured not to intentionally introduce the V pit 15, it is possible to effectively prevent the light emission characteristics of the nitride semiconductor light emitting device 1 from being deteriorated. can do.

  Even when the nitride semiconductor light emitting device 1 according to the present embodiment includes only one of the second n-type nitride semiconductor layer 9 and the superlattice layer 122, the above-described functions and effects can be obtained. However, the nitride semiconductor light emitting device 1 according to the present embodiment preferably includes both the second n-type nitride semiconductor layer 9 and the superlattice layer 122. Thereby, ESD withstand voltage becomes higher. An increase in leakage current when a bias voltage is applied in the forward direction can be more effectively reduced. In addition, it is possible to more effectively suppress the reduction of the light emitting area due to the formation of the V pit 15.

<Manufacture of nitride semiconductor light emitting device>
FIG. 5 is a flowchart showing a part of the manufacturing method of the nitride semiconductor light emitting device 1 shown in FIG. FIG. 6 is a flowchart showing the preparation steps of the base substrate shown in FIG. 5 in the order of steps. FIG. 7 is a flowchart showing a part of another method for manufacturing the nitride semiconductor light emitting device 1 shown in FIG. The composition or thickness of each component of nitride semiconductor light emitting device 1 is as described above in <Configuration of nitride semiconductor light emitting device>.

  In step S501 shown in FIG. 5, the base substrate 6 is prepared. For example, the buffer layer 5 is formed on the substrate 3 by sputtering or the like. The substrate 3 on which the buffer layer 5 is formed is placed in the first crystal growth apparatus, and the base layer 7 is formed on the buffer layer 5 by, for example, the MOCVD method. Next, after forming the first n-type nitride semiconductor layer 8 in step S511 shown in FIG. 6, the second n-type nitride semiconductor layer 9 is formed in step S512 shown in FIG.

  The growth temperature of the underlayer 71, the first n-type nitride semiconductor layer 8, and the second n-type nitride semiconductor layer 9 is preferably 800 ° C. or higher, more preferably 900 ° C. or higher, and 1000 ° C. or higher. More preferably. The higher the growth temperature, the better the crystal quality of the formed nitride semiconductor layer. However, if the growth temperature is too high, the formed nitride semiconductor layer is affected by nitrogen depletion or the like, and as a result, the crystal quality of the formed nitride semiconductor layer may be deteriorated. Therefore, these growth temperatures are preferably 1250 ° C. or lower, and more preferably 1200 ° C. or lower.

  The first underlayer 71 is preferably grown in a facet growth mode in which the oblique facet surface 71a is formed. The second underlayer 75 is preferably grown in a buried growth mode in which the oblique facet surface 71a is buried to form a flat upper surface 75b. Specifically, the first underlayer 71 is preferably formed in an atmosphere in which three-dimensional growth is easier than the second underlayer 75, and is formed at a higher pressure and lower temperature than the second underlayer 75. Is more preferable. For example, the first underlayer 71 is preferably formed under a pressure of 500 Torr and a temperature of 990 ° C., and the second underlayer 75 is formed under a pressure of 200 Torr and a temperature of 1080 ° C. preferable.

  The first n-type nitride semiconductor layer 8 and the second n-type nitride semiconductor layer 9 are each preferably formed by MOCVD, hydride vapor phase growth, or liquid phase growth, and are preferably formed by MOCVD. More preferred. When the first n-type nitride semiconductor layer 8 is formed by the MOCVD method, the first n-type nitride semiconductor layer 8 having excellent crystal quality can be obtained. Similar effects can be obtained when the second n-type nitride semiconductor layer 9 is formed by MOCVD. When the first n-type nitride semiconductor layer 8 is formed by a hydride vapor phase growth method or a liquid phase growth method, the first n-type nitride semiconductor layer 8 can be formed at low cost. The same effect can be obtained when the second n-type nitride semiconductor layer 9 is formed by hydride vapor phase epitaxy or liquid phase epitaxy. The liquid phase growth method is preferably, for example, a liquid phase epitaxy method.

The first n-type nitride semiconductor layer 8 and the second n are so arranged that the n-type dopant concentration of the n ⁻ layer 9A of the second n-type nitride semiconductor layer 9 is lower than the n-type dopant concentration of the first n-type nitride semiconductor layer 8. A type nitride semiconductor layer 9 is formed. Thereby, the third n-type nitride semiconductor layer 11 having excellent crystal quality can be formed as compared with the case where the second n-type nitride semiconductor layer 9 is formed without forming the n ⁻ layer 9A at all. Therefore, since the light emitting layer 14 having excellent crystal quality can be formed, the nitride semiconductor light emitting device 1 having a high light emission output can be obtained. As described above, in this embodiment, the nitride semiconductor light emitting device 1 with high light emission output can be obtained without performing heat treatment or film formation for obtaining the nitride semiconductor light emitting device 1 with high light emission output. Therefore, the nitride semiconductor light emitting device 1 having a high light emission output can be manufactured without being limited by the growth conditions of the third n-type nitride semiconductor layer 11 and the like.

  When forming the second n-type nitride semiconductor layer 9, it is preferable that the semiconductor layer constituting the growth surface 61 be an undoped layer. Thereby, for example, even if the growth surface 61 of the base substrate 6 is exposed to the atmosphere by taking out the base substrate 6 from the first crystal growth apparatus, the growth surface 61 is oxidized by moisture or oxygen in the air. Can be prevented. In addition, an increase (pile-up) of the n-type dopant doping at the interface between the growth surface 61 and the third n-type nitride semiconductor layer 11 (specifically, the V pit generation layer 10) can be prevented. As a result, the third n-type nitride semiconductor layer 11 with better crystal quality can be grown, and thus the light emitting layer 14 with better crystal quality can be obtained. Therefore, the nitride semiconductor light emitting device 1 having a higher light emission output can be obtained.

When forming the second n-type nitride semiconductor layer 9, the semiconductor layer constituting the growth surface 61 may be a doped layer. In this case, it is preferable to form the second n-type nitride semiconductor layer 9 by alternately stacking the n ⁻ layers 9A and the n ⁺ layers 9B from the first n-type nitride semiconductor layer 8 side. That is, it is preferable that the second n-type nitride semiconductor layer 9 is a modulation doped layer. When the second n-type nitride semiconductor layer 9 is a modulation dope layer and the second n-type nitride semiconductor layer 9 is grown at a temperature of 800 ° C. to 1250 ° C., the following effects are obtained.

  In order to increase the light emission output of the nitride semiconductor light emitting device 1, it is preferable to maintain the crystal quality of the light emitting layer 14 high. Therefore, a layer (specifically, the first layer located closer to the base substrate 6 than the light emitting layer 14). It is preferable to keep the crystal quality of the 3n-type nitride semiconductor layer 11) high. In general, it is believed that the higher the growth temperature, the higher the crystal quality of the grown layer. Therefore, it is conceivable that the third n-type nitride semiconductor layer 11 having excellent crystal quality is obtained by growing the third n-type nitride semiconductor layer 11 at a high temperature.

  However, when the third n-type nitride semiconductor layer 11 is grown at a high temperature, crystal defects caused by particles may occur during the crystal growth. For example, the third n-type nitride semiconductor layer 11 is grown at 1000 ° C., the light-emitting layer 14 and the first p-type nitride semiconductor layer 19 are grown at 800 ° C., and then different nitride semiconductor light-emitting elements 1 are manufactured. Consider the case where the third n-type nitride semiconductor layer 11 is grown at 1000 ° C. At this time, during the growth of the light emitting layer 14 or the first p-type nitride semiconductor layer 19, unreacted materials may adhere to the inner wall surface of the chamber. Here, the growth temperature of the third n-type nitride semiconductor layer 11 is higher than the growth temperatures of the light emitting layer 14 and the first p-type nitride semiconductor layer 19. Therefore, when the third n-type nitride semiconductor layer 11 is grown for the second time, the unreacted material may be peeled off from the inner wall surface of the chamber, and the unreacted material that has been peeled off is growing as particles or impurities. The third n-type nitride semiconductor layer 11 may be taken in. As a result, in the growing third n-type nitride semiconductor layer 11, crystal defects due to the incorporated particles or impurities are generated.

On the other hand, when the second n-type nitride semiconductor layer 9 is grown at a temperature of 800 ° C. or higher and 1250 ° C. or lower, the crystal quality of the second n-type nitride semiconductor layer 9 can be improved. In particular, the crystal quality of the semiconductor layer (n ⁻ layer 9A or n ⁺ layer 9B) constituting the growth surface 61 of the base substrate 6 can be improved. Therefore, even if the third n-type nitride semiconductor layer 11 is grown at a relatively low temperature, the third n-type nitride semiconductor layer 11 with high crystal quality can be formed. Therefore, the growth temperature of the third n-type nitride semiconductor layer 11 can be made lower than the growth temperature of the base substrate 6, for example, 850 ° C. or less. As a result, when the third n-type nitride semiconductor layer 11 is grown, unreacted substances can be prevented from peeling off from the inner wall surface of the chamber, so that the unreacted substances become particles or impurities and are growing. Incorporation into the physical semiconductor layer 11 can be prevented. In this way, if the second n-type nitride semiconductor layer 9 is grown at a temperature of 800 ° C. or higher and 1250 ° C. or lower, the third n-type nitride semiconductor layer 11 is grown without generating crystal defects due to particles. Therefore, the crystal quality of the light emitting layer 14 can be further improved. In addition, since the second n-type nitride semiconductor layer 9 having excellent crystal quality can be obtained, the growth conditions of the third n-type nitride semiconductor layer 11 or the light emitting layer 14 are not limited. From the above, it is possible to manufacture a nitride semiconductor light emitting device having a high light emission output without being limited by growth conditions.

  In addition, since the growth temperature of the third n-type nitride semiconductor layer 11 can be made lower than the growth temperature of the base substrate 6, the time required for raising the temperature during the growth of the third n-type nitride semiconductor layer 11 can be shortened. Can do. Therefore, since the manufacturing time of the nitride semiconductor light emitting device 1 can be shortened, the manufacturing cost of the nitride semiconductor light emitting device 1 can be kept low. Moreover, since the crack of the board | substrate 3 or the base substrate 6 can be suppressed at the time of the growth of the 3rd n-type nitride semiconductor layer 11, a manufacturing yield can be maintained high.

  When the preparation process of the base substrate 6 is completed, the base substrate 6 is taken out from the first crystal growth apparatus and placed in the second crystal growth apparatus. Thereafter, in step S502 shown in FIG. 5, the third n-type nitride semiconductor layer 11 is formed on the growth surface 61 of the base substrate 6. On the growth surface 61 of the base substrate 6, the V pit generation layer 10, the multilayer structure 121, and the superlattice layer 122 are formed in this order.

The method for forming V pit generation layer 10 is not particularly limited, but the growth temperature is higher than the growth temperature of base substrate 6 (for example, the growth temperature of first n-type nitride semiconductor layer 8 or second n-type nitride semiconductor layer 9). It is preferable that it is low, for example, it is preferable that it is 850 degrees C or less. However, if the growth temperature of the V pit generation layer 10 is too low, the light emission efficiency of the light emitting layer 14 may be reduced. Therefore, the growth temperature of the V pit generation layer 10 is more preferably 700 ° C. or higher, and further preferably 750 ° C. or higher. The V pit generation layer 10 may be formed so that the n-type dopant concentration is higher than that of the n ⁺ layer 9B of the second n-type nitride semiconductor layer 9. Thereby, the formation effect of V pit 15 by V pit generation layer 10 can be increased.

  The method for forming multilayer structure 121 is not particularly limited, but the growth temperature is lower than the growth temperature of base substrate 6 (for example, the growth temperature of first n-type nitride semiconductor layer 8 or second n-type nitride semiconductor layer 9). It is preferable that the temperature is lower than the growth temperature of the V pit generation layer 10, and it is more preferable that the temperature is the same (± 10 ° C.) as the growth temperature of the V pit generation layer 10. If the growth temperature of the multilayer structure 121 is equal to or lower than the growth temperature of the V pit generation layer 10, the size of the V pit 15 generated in the V pit generation layer 10 increases, and the defect rate due to ESD decreases. To do. In order to effectively obtain this effect, the growth temperature of the multilayer structure 121 is preferably 600 ° C. or higher, and more preferably 600 ° C. or higher and 900 ° C. or lower.

  The formation method of superlattice layer 122 is not particularly limited, but the growth temperature is lower than the growth temperature of base substrate 6 (for example, the growth temperature of first n-type nitride semiconductor layer 8 or second n-type nitride semiconductor layer 9). It is preferable that the temperature is lower than the growth temperature of the V pit generation layer 10, and it is more preferable that the temperature is the same (± 10 ° C.) as the growth temperature of the V pit generation layer 10. If the growth temperature of the superlattice layer 122 is equal to or lower than the growth temperature of the V pit generation layer 10, the size of the V pit 15 generated in the V pit generation layer 10 increases, so the defect rate due to ESD decreases. To do. In order to effectively obtain this effect, the growth temperature of the superlattice layer 122 is preferably 600 ° C. or higher and 900 ° C. or lower, and more preferably 600 ° C. or higher and 800 ° C. or lower.

  Subsequently, in step S503 illustrated in FIG. 5, the light emitting layer 14 is formed. The formation method of the light emitting layer 14 is not specifically limited, A method well-known as a formation method of MQW structure can be used without being specifically limited.

  Subsequently, in step S504 shown in FIG. 5, the first p-type nitride semiconductor layer 19 is formed. The formation method of the 1st p-type nitride semiconductor layer 19 is not specifically limited, A well-known method can be used without being specifically limited as a formation method of a p-type nitride semiconductor layer.

  Subsequently, the first p-type nitride semiconductor layer 19, the light emitting layer 14, the third n-type nitride semiconductor layer 11, the second n-type nitride semiconductor layer 9 and the first n-type nitride semiconductor layer 8 are exposed so that a part of the first n-type nitride semiconductor layer 8 is exposed. A part of the first n-type nitride semiconductor layer 8 is etched. An n-side electrode 21 is formed on the upper surface of the first n-type nitride semiconductor layer 8 exposed by this etching. Further, the transparent electrode 23 and the p-side electrode 25 are sequentially stacked on the upper surface of the p-type nitride semiconductor layer 18. Then, the transparent protective film 27 is formed so that the transparent electrode 23 and the side surface of each layer exposed by the said etching may be covered. Thereby, the nitride semiconductor light emitting device 1 shown in FIG. 1 is obtained.

  The method for manufacturing a nitride semiconductor light emitting device according to this embodiment may include step S505 of removing the substrate 3 as shown in FIG. The timing for removing the substrate 3 is not limited to the timing shown in FIG. 7 and may be after step S501 for preparing the base substrate 6, for example.

As described above, the method of manufacturing the nitride semiconductor light emitting device 1 shown in FIGS. 5 and 6 includes the step S501 of preparing the base substrate 6 having the growth surface 61. The step S501 for preparing the base substrate 6 includes the step S511 for forming the first n-type nitride semiconductor layer 8 on the substrate 3, and the n-type dopant concentration on the first n-type nitride semiconductor layer 8 in the first n-type nitride. Forming a second n-type nitride semiconductor layer 9 including an n ⁻ layer 9A lower than the semiconductor layer 8. Thereby, the nitride semiconductor light emitting device 1 having a high light emission output can be obtained without being limited by the growth conditions.

  The semiconductor layer constituting the growth surface 61 is preferably an undoped layer. Thereby, the nitride semiconductor light emitting device 1 having higher light emission output can be obtained. The semiconductor layer constituting the growth surface 61 may be a doped layer.

In step S512 of forming the second n-type nitride semiconductor layer 9, the n ⁻ layer 9A and the n ⁺ layer 9B having an n-type dopant concentration higher than the n ⁻ layer 9A are formed from the first n-type nitride semiconductor layer 8 side. It is preferable to include the process of laminating | stacking alternately. As a result, the nitride semiconductor light emitting device 1 having a low forward voltage and preventing a leakage current when a reverse bias is applied can be obtained.

The thickness of n ⁺ layer 9B is preferably equal to or less than the thickness of n ⁻ layer 9A. Thereby, the ESD withstand voltage can be improved.

The thickness of the second n ⁺ layer 9B counted from the first n-type nitride semiconductor layer 8 side is preferably 50 nm or more and 100 nm or less. The thickness of the third n ⁺ layer 9B counted from the first n-type nitride semiconductor layer 8 side is equal to or less than the thickness of the second n ⁺ layer 9B counted from the first n-type nitride semiconductor layer 8 side. Preferably there is. As a result, the thickness of the second n-type nitride semiconductor layer 9 can be reduced while reducing the forward voltage, preventing the occurrence of leakage current when a reverse bias is applied, and improving the ESD withstand voltage.

  The first n-type nitride semiconductor layer 8 and the second n-type nitride semiconductor layer 9 are preferably formed by metal organic chemical vapor deposition, hydride vapor deposition, or liquid phase growth. Thereby, the first n-type nitride semiconductor layer 8 or the second n-type nitride semiconductor layer 9 excellent in crystal quality can be formed.

  The nitride semiconductor light emitting device 1 according to the present invention is manufactured according to the method for manufacturing the nitride semiconductor light emitting device 1 according to the present invention.

The base substrate 6 for a nitride semiconductor light emitting device according to the present invention has an n-type dopant concentration on the first n-type nitride semiconductor layer 8 and the first n-type nitride semiconductor layer 8. And a second n-type nitride semiconductor layer 9 including a lower n ⁻ layer 9A.

  EXAMPLES Hereinafter, although an Example is given and this invention is demonstrated in detail, this invention is not limited to these.

<Example 1>
First, a wafer made of a 100 mm diameter sapphire substrate was prepared. On the upper surface of the wafer, a concavo-convex shape in which convex portions 3a and concave portions 3b were alternately formed was formed.

  The formation method of the uneven | corrugated shape with respect to a wafer is shown. First, a mask in which the planar arrangement of the convex portions 3a shown in FIG. 4 was defined was provided on the wafer. Next, the upper surface of the wafer was dry etched using this mask. The dry-etched portion became the recess 3b, and thus the recess 3b having the planar arrangement shown in FIG. 4 was formed on the upper surface of the wafer. Accordingly, the convex portions 3a are arranged in the a (sub) axis direction (<11-20> direction) of the upper surface of the wear, and have an inclination of + 60 ° with respect to the a (sub) axis direction of the upper surface of the wear. And a direction that forms an inclination of −60 ° with respect to the a (sub) axis direction on the upper surface of the wafer (both directions). The convex portions 3a are respectively arranged at the vertices of the virtual triangle 3t indicated by the broken line in FIG. 4 on the upper surface of the wafer, and are periodically arranged in the direction of each of the three sides of the virtual triangle 3t.

  The shape of the convex portion 3a on the upper surface of the wafer was circular, and the diameter of the circle was about 1.2 μm. The interval between the apexes of adjacent convex portions 3a (one side of the virtual triangle 3t shown in FIG. 4) was 2 μm, and the height of the convex portion 3a was about 0.6 μm. The convex part 3a had the side view shape shown in FIG. 1, and its tip was rounded. The recess 3b had a side view shape shown in FIG.

After forming the convex portions 3a and the concave portions 3b, the upper surface of the wafer was RCA cleaned. The wafer after RCA cleaning was placed in a chamber, N ₂ , O _2, and Ar were introduced into the chamber, and the wafer in the chamber was heated to 650 ° C. A buffer layer 5 (thickness of AlON crystal) is formed on the upper surface of the wafer on which the convex portions 3a and the concave portions 3b are formed by a reactive sputtering method in which an Al target is sputtered in a mixed atmosphere of N ₂ , O ₂ and Ar. 25 nm). The formed buffer layer 5 was an aggregate of columnar crystals extending in the normal direction of the upper surface of the wafer, and an aggregate of columnar crystals with uniform crystal grains.

The wafer on which the buffer layer 5 was formed was placed in the first MOCVD apparatus. The first underlayer 71 made of undoped GaN was grown by MOCVD at a pressure of 500 Torr and a temperature of 990 ° C. Further, the second underlayer 75 made of undoped GaN was grown by MOCVD at a pressure of 200 Torr and a temperature of 1080 ° C. The thickness of the underlayer 7 was 4 μm. Thereafter, the first n-type nitride semiconductor layer 8 made of Si-doped n-type GaN was grown by MOCVD at a temperature of 1110 ° C. The thickness of the first n-type nitride semiconductor layer 8 was 4.5 μm, and the n-type dopant concentration of the first n-type nitride semiconductor layer 8 was 1 × 10 ¹⁹ cm ⁻³ .

The second n-type nitride semiconductor layer 9 was crystal-grown with the wafer temperature maintained at 1110 ° C. On the first n-type nitride semiconductor layer 8, an undoped GaN layer (n ⁻ layer 9A) having a thickness of 87 nm and a Si-doped n-type GaN layer (n ⁺ layer 9B (n-type dopant concentration: 1 × 10 ¹⁹ ) having a thickness of 50 nm are formed. cm ⁻³ )), an undoped GaN layer having a thickness of 87 nm (n ⁻ layer 9A), and a Si doped n-type GaN layer having a thickness of 25 nm (n ⁺ layer 9B (n-type dopant concentration: 1 × 10 ¹⁹ cm ⁻³⁾ )) Were grown in this order by MOCVD.

The wafer was taken out from the first MOCVD apparatus and placed in the second MOCVD apparatus. After the temperature of the wafer was set to 801 ° C., a Si-doped GaN layer (V pit generation layer 10) having a thickness of 25 nm was grown by MOCVD. The crystal-grown Si-doped GaN layer was in contact with the uppermost layer of the second n-type nitride semiconductor layer 9, and the n-type dopant concentration was 1 × 10 ¹⁹ cm ⁻³ .

The multilayer structure 121 was crystal-grown with the wafer temperature maintained at 801 ° C. Two Si-doped InGaN layers having a thickness of 7 nm, Si-doped GaN layers having a thickness of 30 nm, Si-doped InGaN layers having a thickness of 7 nm, and two Si-doped GaN layers having a thickness of 20 nm were alternately stacked. In any of the layers constituting the multilayer structure 121, the n-type dopant concentration was 7 × 10 ¹⁷ cm ⁻³ . The In composition ratio of the InGaN layer was set to be the same as the In composition ratio of the narrow band gap layer 122B of the superlattice layer 122 to be grown next.

The superlattice layer 122 was crystal-grown with the wafer temperature maintained at 801 ° C. A wide band gap layer 122A made of Si-doped GaN and a narrow band gap layer 122B made of Si-doped InGaN were alternately grown for 20 periods. The thickness of each wide band gap layer 122A was 1.55 nm. Each narrow band gap layer 122B had a thickness of 1.55 nm. The n-type dopant concentration of each wide band gap layer 122A is 1 × 10 ¹⁹ cm ⁻³ in five layers located on the light emitting layer 14 side in the wide band gap layer 122A, and the base substrate 6 side than the five layers. In the layer located at 0, it was 0 cm ⁻³ (undoped). The n-type dopant concentration of each narrow band gap layer 122B is 1 × 10 ¹⁹ cm ⁻³ in five layers of the narrow band gap layer 122B located on the light emitting layer 14 side, and is located closer to the base substrate 6 than the five layers. It was 0 cm < ^-3 > (undoped) in the layer to perform. Since the flow rate of TMI (trimethylindium) is adjusted so that the wavelength of light emitted from the well layer 14W of the light emitting layer 14 by photoluminescence is 448 nm, the composition of each narrow band gap layer 122B is In _y Ga _1-y N (y = 0.04).

The temperature of the wafer was lowered to 672 ° C., and the light emitting layer 14 was crystal-grown. The barrier layers 14A and the well layers 14W made of InGaN were alternately grown to grow eight layers of well layers 14W. Each barrier layer 14A had a thickness of 4.2 nm. The n-type dopant concentration of the first barrier layer 14Az and the barrier layer 14A7 was 4.3 × 10 ¹⁸ cm ⁻³ , and the other barrier layers 14A6, 14A5,..., 14A1 were undoped.

Here, the thickness of the first barrier layer 14Az may be larger than the thickness of the barrier layer 14A7, and may be, for example, 5.05 nm. As a result, the narrow band gap layer 122B can be formed closest to the light emitting layer 14 in the superlattice layer 122, and the action of the wide band gap layer 122A not included in the number of superlattice layer 122 sets can be provided. . The n-type dopant concentration of the first barrier layer 14Az is set to 1 × 10 ¹⁹ cm ^{−3 on} the upper portion of the first barrier layer 14Az (a region 1.55 nm away from the interface between the first barrier layer 14Az and the well layer 14W8), The lower portion of the first barrier layer 14Az (a portion other than the upper portion of the first barrier layer 14Az) may be 4.3 × 10 ¹⁸ cm ⁻³ .

  The n-type dopant is doped only in the lower part of the barrier layer 14A7 (region 3.5 nm away from the interface between the well layer 14W8 and the barrier layer 14A7), and the upper part of the barrier layer 14A7 (the part other than the lower part of the barrier layer 14A7) is undoped. It is good. Thus, by making the upper part of the barrier layer 14A7 undoped, it is possible to prevent the injected carriers of the well layer 14W7 from being in direct contact with the n-type doped barrier layer part.

The well layer 14W was crystal-grown using nitrogen gas as a carrier gas, and was an undoped In _x Ga _1-x N layer (x = 0.20). The thickness of each well layer 14W was 2.7 nm. The flow rate of TMI was adjusted so that the wavelength of light emitted from the well layer 14W by photoluminescence was 448 nm, and the In composition x in the well layer 14W was set.

  The last barrier layer 14A0 (thickness 10 nm) made of an undoped GaN layer was grown on the uppermost well layer 14W1.

The wafer temperature is raised to 1000 ° C., and a p-type Al _0.18 Ga _0.82 N layer (p-type nitride semiconductor layer 16) and a p-type GaN layer (p-type nitride semiconductor layer 17) are formed on the upper surface of the last barrier layer 14A0. And a p-type contact layer (p-type nitride semiconductor layer 18) were grown in order.

In the crystal growth of each layer described above, TMG (trimethylgallium) is used as the Ga source gas, TMA (trimethylaluminum) is used as the Al source gas, and TMI (trimethylindium) is used as the In source gas. NH ₃ was used as the N source gas. Further, SiH ₄ was used as a source gas for Si as an n-type dopant, and Cp ₂ Mg was used as a source gas for Mg as a p-type dopant. However, the source gas is not limited to the above gas, and any gas that can be used as a MOCVD source gas can be used without limitation. For example, TEG (triethylgallium) can be used as a Ga source gas, TEA (triethylaluminum) can be used as an Al source gas, and TEI (triethylindium) can be used as an In source gas, An organic nitrogen compound such as DMHy (dimethylhydrazine) can be used as the N source gas, and Si ₂ H ₆ or organic Si can be used as the Si source gas.

The wafer was taken out from the second MOCVD apparatus. Thereafter, a p-type contact layer (p-type nitride semiconductor layer 18), a p-type GaN layer (p-type nitride semiconductor layer 17), and p-type Al _0.18 so that a part of the first n-type nitride semiconductor layer 8 is exposed. Ga _0.82 N layer (p-type nitride semiconductor layer 16), light emitting layer 14, superlattice layer 122, multilayer structure 121, Si-doped GaN layer (V pit generation layer 10), second n-type nitride semiconductor layer 9 and The 1n type nitride semiconductor layer 8 was etched. An n-side electrode 21 made of Au was formed on the upper surface of the first n-type nitride semiconductor layer 8 exposed by this etching. On the upper surface of the p-type contact layer 18, a transparent electrode 23 made of ITO and a p-side electrode 25 made of Au were formed in this order. A transparent protective film 27 made of SiO ₂ was formed so as to mainly cover the transparent electrode 23 and the side surfaces of each layer exposed by the etching. Thereafter, the wafer was divided into 620 × 680 μm size chips. Thereby, the nitride semiconductor light emitting device according to Example 1 was obtained.

  In the obtained nitride semiconductor light emitting device, at a forward current of 120 mA, the emission wavelength was 448 nm, the emission output was 170 mW, and the forward voltage was 3.1V. Further, when a reverse voltage of 5 V was applied, the leakage current was 0.0 mA.

<Example 2>
A nitride semiconductor light emitting device of this example was obtained according to the method described in Example 1 except that the second n-type nitride semiconductor layer 9 shown below was crystal-grown. On the first n-type nitride semiconductor layer 8, an undoped GaN layer (n ⁻ layer 9A) having a thickness of 87 nm and a Si-doped n-type GaN layer (n ⁺ layer 9B (n-type dopant concentration: 1 × 10 ¹⁹ ) having a thickness of 50 nm are formed. cm ⁻³ )) and an undoped GaN layer (n ⁻ layer 9A) having a thickness of 87 nm were grown in this order by MOCVD.

<Example 3>
A nitride semiconductor light emitting device of this example was obtained according to the method described in Example 1 except that the second n-type nitride semiconductor layer 9 shown below was crystal-grown. On the first n-type nitride semiconductor layer 8, an undoped GaN layer (n ⁻ layer 9A) having a thickness of 87 nm and a Si-doped n-type GaN layer (n ⁺ layer 9B having a thickness of 50 nm (n-type dopant concentration: 1 × 10 ¹⁹ cm ⁻³ )) were grown in this order by MOCVD.

<Example 4>
A nitride semiconductor light emitting device of this example was obtained according to the method described in Example 1 except that the second n-type nitride semiconductor layer 9 shown below was crystal-grown. On the first n-type nitride semiconductor layer 8, an undoped GaN layer (n ⁻ layer 9A) having a thickness of 87 nm was grown by MOCVD.

<Comparative Example 1>
In Comparative Example 1, the nitride semiconductor layers after the second n-type nitride semiconductor layer 9 were grown on the base substrate made of the first n-type nitride semiconductor layer 8 in the second MOCVD apparatus. Specifically, on the sapphire substrate on which the concavo-convex shape is formed, the buffer layer 5, the base layer having a thickness of 4.0 μm, and the Si-doped n-type GaN layer having a thickness of 3.0 μm (first n-type nitride semiconductor) Layer 8) was crystal grown by MOCVD. Thereby, a base substrate was obtained.

Next, in the second MOCVD apparatus, in a state where the temperature of the sapphire substrate is 1110 ° C., a Si-doped GaN layer having a thickness of 1.5 μm, an undoped GaN layer (n ⁻ layer 9A) having a thickness of 87 nm, and a thickness of 50 nm. Si-doped n-type GaN layer (n ⁺ layer 9B (n-type dopant concentration: 1 × 10 ¹⁹ cm ⁻³ )), undoped GaN layer (n ⁻ layer 9A) having a thickness of 87 nm, and Si-doped n having a thickness of 25 nm A type GaN layer (n ⁺ layer 9B (n-type dopant concentration: 1 × 10 ¹⁹ cm ⁻³ )) was grown in this order by MOCVD. Thereafter, in the second MOCVD apparatus, the temperature of the sapphire substrate was set to 801 ° C., and then a nitride semiconductor light emitting device was manufactured according to the same method as in Example 1.

  In Examples 1 to 4, as compared with Comparative Example 1, the leakage-related defects including ESD defects, VF defects, and IR defects were reduced by about 10%.

The forward voltage was highest in Example 4 among Examples 1 to 4, and decreased in the order of Example 3, Example 2, and Example 1. The leakage current during reverse bias application was highest in Example 4 among Examples 1 to 4, and decreased in the order of Example 3, Example 2, and Example 1. The following can be considered as these reasons. In Example 4, the second n-type nitride semiconductor layer 9 is composed only of the n ⁻ layer 9A, whereas in Example 3, the second n-type nitride semiconductor layer is composed of the n ⁻ layer 9A and the n ⁺ layer 9B. In the second embodiment, the second n-type nitride semiconductor layer 9 includes an n ⁻ layer 9A, an n ⁺ layer 9B, and an n ⁻ layer 9A. In the first embodiment, the second n-type nitride semiconductor layer 9 includes the n ⁻ layer 9A. The n ⁺ layer 9B, the n ⁻ layer 9A, and the n ⁺ layer 9B are configured.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

DESCRIPTION OF SYMBOLS 1 Nitride semiconductor light-emitting device, 3 board | substrate, 3a convex part, 3b recessed part, 3t virtual triangle, 5 buffer layer, 6 ground substrate (ground substrate for nitride semiconductor light-emitting devices), 7 ground layer, 8 1st n-type nitride semiconductor Layer, 9 second n-type nitride semiconductor layer, 9A n ⁻ layer, 9B n ⁺ layer, 10 V pit generation layer, 11 third n type nitride semiconductor layer, 14 light emitting layer, 15 V pit, 16, 17, 18 p Type nitride semiconductor layer, 19 first p-type nitride semiconductor layer, 21 n-side electrode, 23 transparent electrode, 25 p-side electrode, 27 transparent protective film, 30 mesa portion, 61 growth surface, 71 first underlayer, 71a diagonally Facet surface, 71b upper surface, 75 second underlayer, 75b upper surface, 121 multilayer structure, 122 superlattice layer, 122A wide band gap layer, 122B narrow band gap layer.

Claims (3)

Preparing a base substrate having a growth surface;
The step of preparing the base substrate includes
Forming a first n-type nitride semiconductor layer on the substrate;
The second 1n-type nitride semiconductor layer, n-type dopant concentration is lower n than the first 1n-type nitride semiconductor layer ^- have a forming a second 2n-type nitride semiconductor layer including layers,
In the step of forming the second n-type nitride semiconductor layer, the n ⁻ layer and the n ⁺ layer having an n-type dopant concentration higher than the n ⁻ layer are alternately formed from the first n-type nitride semiconductor layer side. Including the step of laminating,
Each of the n ⁻ layers has a thickness of 50 nm to 100 nm, and each of the n ⁺ layers has a thickness of 10 nm to 100 nm,
The thickness of the second n ⁺ layer counted from the first n-type nitride semiconductor layer side is less than the thickness of the first n ⁺ layer counted from the first n-type nitride semiconductor layer side ,
The thickness of the second n ⁺ layer counted from the first n-type nitride semiconductor layer side is 50 nm or more and 100 nm or less,
The thickness of the third n ⁺ layer counted from the first n-type nitride semiconductor layer side is equal to or less than the thickness of the second n ⁺ layer counted from the first n-type nitride semiconductor layer side . A method for manufacturing a nitride semiconductor light emitting device. The thickness of the n ⁺ layer, the n ^- is less than the thickness of the layer, the method of manufacturing the nitride semiconductor light emitting device according to claim 1. A first n-type nitride semiconductor layer;
A second n-type nitride semiconductor layer including an n ⁻ layer having an n-type dopant concentration lower than that of the first n-type nitride semiconductor layer on the first n-type nitride semiconductor layer;
In the second n-type nitride semiconductor layer, the n ⁻ layer and the n ⁺ layer having an n-type dopant concentration higher than the n ⁻ layer are alternately stacked from the first n-type nitride semiconductor layer side. ,
Each of the n ⁻ layers has a thickness of 50 nm to 100 nm, and each of the n ⁺ layers has a thickness of 10 nm to 100 nm,
The thickness of the second n ⁺ layer counted from the first n-type nitride semiconductor layer side is less than the thickness of the first n ⁺ layer counted from the first n-type nitride semiconductor layer side ,
The thickness of the second n ⁺ layer counted from the first n-type nitride semiconductor layer side is 50 nm or more and 100 nm or less,
The thickness of the third n ⁺ layer counted from the first n-type nitride semiconductor layer side is equal to or less than the thickness of the second n ⁺ layer counted from the first n-type nitride semiconductor layer side . A base substrate for a nitride semiconductor light emitting device.

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