JP6026116B2 - Nitride semiconductor light emitting device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a nitride semiconductor light emitting device and a method for manufacturing the same.

  A group III-V compound semiconductor material containing nitrogen (hereinafter referred to as a “nitride semiconductor material”) has a band gap corresponding to the energy of light having a wavelength from the infrared region to the ultraviolet region, and therefore has an infrared It is useful as a material for a light emitting element that emits light having a wavelength from the region to the ultraviolet region, or as a material for a light receiving element that receives light having a wavelength in the region.

  Further, the bonds between the atoms constituting the nitride semiconductor are strong, the dielectric breakdown voltage of the nitride semiconductor material is high, and the saturation electron velocity of the nitride semiconductor material is high. For these reasons, nitride semiconductor materials are also useful as materials for electronic devices such as high-temperature transistors with high temperature resistance and high output.

  Furthermore, the nitride semiconductor material has attracted attention as an easy-to-handle material because it hardly harms the environment.

  In a nitride semiconductor light emitting device using such a nitride semiconductor material, a quantum well structure is generally adopted as a light emitting layer. When a voltage is applied to the nitride semiconductor light emitting device, electrons and holes are recombined in the well layer constituting the light emitting layer, thereby generating light. The light emitting layer may have a single quantum well structure or may have a multiple quantum well (MQW) structure in which well layers and barrier layers are alternately stacked.

  By the way, a nitride semiconductor light emitting device using a nitride semiconductor material includes a V pit (V-pit, V-shaped pit, V-shaped recess), a V defect, or an inverted hexagonal pyramid defect. It is known that there is a defect of the shape called.

  Since the V pit is a defect, it is generally considered that the characteristics of the light emitting element can be improved by suppressing the generation thereof. However, Patent Document 1 discloses that a high-efficiency light-emitting element can be provided by forming a plurality of “hexagonal pyramid cavities” on the surface of a nitride semiconductor layer constituting the light-emitting element.

  Non-Patent Document 1 reports the effect of V-shaped pits in the MQW light-emitting layer. According to this, when there is a V pit in the MQW light emitting layer, the quantum well width on the slope of the V pit is narrowed, so that electrons and holes injected into the quantum well become threading dislocations that are crystal defects inside the V pit. It is said that the non-radiative recombination in the MQW light emitting layer is suppressed as a result.

  Further, Non-Patent Document 2 reports that it is ideal if the apical angle of the V pit is 56 °.

  Incidentally, as a configuration of the MQW light emitting layer, for example, Patent Document 2 discloses an active layer in which an undoped GaN barrier layer and an InGaN quantum well layer doped with an n-type impurity (corresponding to an n-type dopant in the present application) are sequentially stacked. (Corresponding to the light emitting layer in the present application). Patent Document 2 describes that a diffusion prevention film is provided at the interface where the undoped GaN barrier layer is in contact with the InGaN quantum well layer, and this diffusion prevention film is more than the InGaN quantum well layer. It also describes containing low concentrations of n-type impurities.

  Patent Document 3 describes that the active layer contains an n-type impurity, and the n-type impurity concentration in the active layer located on the n-layer side is n-type in the active layer located on the p-layer side. It is also described that when the concentration is higher than the impurity concentration, the supply of donors from the n-layer side to the active layer can be supplemented, and a nitride semiconductor device having a high light emission output can be obtained.

JP 2005-277423 A JP 2005-109425 A JP 2005-057308 A

A. Hangleiter, F. Hitzel, C. Netzel, D. Fuhrmann, U. Rossow, G. Ade, and P. Hinze, “Suppression of Nonradiative Recombination by V-Shaped Pits in GaInN / GaN Quantum Wells Produces a Large Increase in the Light Emission Efficiency ”, Physical Review Letters 95, 127402 (2005) M. Shiojiri, C. C. Chuo, J. T. Hsu, J. R. Yang and H. Saijo, “Structure and formation mechanism of V defects in multiple InGaN / GaN quantum well layers”, JOURNAL OF APPLIED PHYSICS 99, 073505 (2006)

  If a nitride semiconductor light emitting device is manufactured according to the conventional technique and the manufactured nitride semiconductor light emitting device is driven at a high temperature or a large current, the light emission efficiency may be reduced. Therefore, the light emission efficiency per unit power (power efficiency) may be reduced.

  Further, when the volume of the light emitting layer is increased in order to prevent a decrease in light emission efficiency during high temperature driving or large current driving, the defect rate due to ESD (Electrostatic Discharge) may increase.

  The present invention has been made in view of the above points, and an object of the present invention is to prevent a decrease in light emission efficiency at the time of high temperature driving or high current driving and to prevent an increase in defect rate due to ESD. An improved nitride semiconductor light emitting device is provided.

  The nitride semiconductor light-emitting device of the present invention includes an n-type nitride semiconductor layer, a V pit generation layer, an intermediate layer, a multiple quantum well light-emitting layer, and a p-type nitride semiconductor layer in this order. The multiple quantum well light emitting layer is a layer formed by alternately laminating barrier layers and well layers having band gap energy smaller than that of the barrier layers. V pits are partially formed in the multiple quantum well light emitting layer. A multilayer structure in which a plurality of nitride semiconductor layers having different band gap energies are stacked is provided between the V pit generation layer and the intermediate layer. The average position of the starting point of the V pit is in the intermediate layer, and many of them are located closer to the V pit generation layer than near the center in the thickness direction of the intermediate layer. The multilayer structure is preferably formed by stacking a nitride semiconductor layer having a relatively small band gap energy and a nitride semiconductor layer having a relatively large band gap energy.

The multilayer structure includes an Al _i1 Ga _j1 In _(1-i1-j1) N (0 ≦ i1 <1, 0 <j1 ≦ 1) layer and an Al _i2 Ga _j2 In _(1-i2-j2) N (0 ≦ i2 _). <1, 0 ≦ j2 <1, j1 <j2) layers are preferably laminated alternately.

The multilayer structure is preferably formed by alternately laminating Ga _j3 In _(1-j3) N (0 <j3 <1) layers and GaN layers.

All of the nitride semiconductor layers constituting the multilayer structure preferably include an n-type impurity. The n-type dopant concentration in the nitride semiconductor layer constituting the multilayer structure is preferably lower than the n-type dopant concentration in the V pit generation layer, more preferably 7 × 10 ¹⁷ cm ⁻³ or less.

  The plurality of nitride semiconductor layers having different band gap energies are preferably undoped layers.

  It is preferable that a second multilayer structure is further provided between the n-type nitride semiconductor layer and the V pit generation layer. The second multilayer structure is preferably formed by alternately laminating doped layers and undoped layers whose dopant concentration is the same as the dopant concentration in the V pit generation layer.

  In a multilayer structure, when a nitride semiconductor layer having a relatively small band gap energy and a nitride semiconductor layer having a relatively large band gap energy are taken as one set, the multilayer structure has two or more sets of band gap energy relative to each other. It is preferable to have a small nitride semiconductor layer and a nitride semiconductor layer having a relatively large band gap energy.

  In the multilayer structure, the thickness of the nitride semiconductor layer having a relatively small band gap energy is not less than 1/5 times and not more than 1/2 times the thickness of the nitride semiconductor layer having a relatively large band gap energy. It is preferable.

  The intermediate layer is preferably a superlattice layer formed by alternately laminating a wide band gap layer and a narrow band gap layer having a smaller band gap energy than the wide band gap layer.

The narrow band gap layer constituting the superlattice layer preferably contains In in its composition. The In composition ratio in the narrow band gap layer is preferably the same as the In composition ratio in the Ga _j3 In _(1-j3) N (0 <j3 <1) layer constituting the multilayer structure.

  Of the wide band gap layer and the narrow band gap layer constituting the superlattice layer, at least two layers located on the multiple quantum well light emitting layer side preferably contain an n-type dopant, and at least two layers located on the V pit generation layer side Is preferably undoped.

  When the wide band gap layer and the narrow band gap layer are taken as one set, the superlattice layer preferably has 20 or more wide band gap layers and narrow band gap layers, and 5 sets of wide band gap layers located on the multiple quantum well light emitting layer side. The band gap layer and the narrow band gap layer preferably contain an n-type dopant.

  The method for manufacturing a nitride semiconductor light emitting device according to the present invention includes a step of forming an n-type nitride semiconductor layer at a first growth temperature, and a second step lower than the first growth temperature on the n-type nitride semiconductor layer. A step of forming a V pit generation layer at a growth temperature, and a plurality of nitride semiconductor layers having different band gap energies at a third growth temperature lower than the second growth temperature on the V pit generation layer. Forming a multilayer structure, forming an intermediate layer on the multilayer structure at a fourth growth temperature lower than the third growth temperature, a multiple quantum well light emitting layer and p-type nitriding on the intermediate layer Forming a physical semiconductor layer in order.

  The second growth temperature is preferably lower by 50 ° C. or more than the first growth temperature. The third growth temperature is preferably 600 ° C. or higher and 900 ° C. or lower. The second, third and fourth growth temperatures are preferably the same.

  According to the nitride semiconductor light emitting device according to the present invention, it is possible to prevent a decrease in light emission efficiency even at a high temperature drive or a high current drive, and to prevent an increase in defect rate due to ESD.

1 is a schematic cross-sectional view of a nitride semiconductor light emitting device according to an embodiment of the present invention. 1 is a schematic plan view of a nitride semiconductor light emitting device according to an embodiment of the present invention. It is an energy diagram which shows typically the magnitude | size of the band gap energy Eg in the nitride semiconductor layer which comprises the nitride semiconductor light-emitting device concerning one Embodiment of this invention. (A) is an AFM (Atomic Force Microscopy) observation result of the upper surface of the V pit evaluation structure without the multilayer structure, and (b) is an AFM of the upper surface of the V pit evaluation structure with the multilayer structure. It is an observation result. (A) is a graph showing the relationship between the V pit diameter Wv and the cumulative incidence of V pits, and (b) is a graph showing the V pit diameter Wv and the V pit depth dv based on the results shown in FIG. FIG. 5C is a cross-sectional view showing the positional relationship between the V pit generation layer and the starting point of the V pit based on the result shown in FIG. It is a graph which shows the relationship between the number of layers of the barrier layer in a MQW light emitting layer, and luminous efficiency (eta). It is a graph which shows the relationship between the light emission wavelength and the defect rate resulting from ESD. It is an energy diagram which shows typically the magnitude | size of the band gap energy Eg in the nitride semiconductor layer which comprises the nitride semiconductor light-emitting device concerning another embodiment of this invention. (A) is an AFM observation result of the upper surface of the V pit evaluation structure that does not include the multilayer structure, and (b) is an AFM observation result of the upper surface of the V pit evaluation structure that includes the multilayer structure. (A) is a graph showing the relationship between the V pit diameter Wv and the cumulative incidence of V pits, and (b) is a graph showing the relationship between the V pit diameter Wv and the V pit depth dv based on the results shown in FIG. FIG. 10C is a cross-sectional view showing the positional relationship between the V pit generation layer and the start point of the V pit based on the result shown in FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
In the following, “barrier layer” refers to a layer sandwiched between well layers. The layer not sandwiched between the well layers is referred to as “first barrier layer” or “last barrier layer”, and the description is different from the layer sandwiched between the well layers.

  Further, in the following embodiments, in order to represent the positional relationship, the portion described on the lower side of FIG. 1 may be expressed as the lower side, and the portion described on the upper side of FIG. 1 may be expressed as the upper side. It is different from the upper and lower determined with respect to the direction of gravity.

  In the following, the term “dopant concentration” and the term “carrier concentration”, which is the concentration of electrons and holes generated by doping with an n-type dopant or a p-type dopant, are used. To do.

  The “carrier gas” is a gas other than the group III source gas, the group V source gas, and the dopant source gas. The atoms constituting the carrier gas are not taken into the film or the like.

  Further, the present invention is not limited to the embodiment shown below. Further, in the drawings of the present invention, dimensional relationships such as length, width, and thickness are appropriately changed for the sake of clarity and simplification of the drawings, and do not represent actual dimensional relationships.

<First Embodiment>
FIG. 1 and FIG. 2 are a schematic cross-sectional view and a schematic plan view, respectively, of a nitride semiconductor light emitting device 1 according to the first embodiment of the present invention. A sectional view taken along line I-I shown in FIG. 2 corresponds to FIG. FIG. 3 is an energy diagram schematically showing the magnitude of the band gap energy Eg from the n-type nitride semiconductor layer 9 to the p-type nitride semiconductor layer 16 of the nitride semiconductor light emitting device 1 shown in FIG. It is. The vertical axis direction in FIG. 3 is the vertical direction of the nitride semiconductor light emitting device 1 shown in FIG. 1, and Eg on the horizontal axis in FIG. 3 schematically represents the magnitude of the band gap energy in each composition. In FIG. 3, the layer doped with the n-type dopant is hatched.

[Configuration of nitride semiconductor light emitting device]
In the nitride semiconductor light emitting device 1 according to this embodiment, on the upper surface of the substrate 3, the buffer layer 5, the base layer 7, the n-type nitride semiconductor layers 8 and 9, the V pit generation layer 10, and the multilayer structure. The body 121, the superlattice layer 122 as an intermediate layer, the MQW light emitting layer 14, and the p-type nitride semiconductor layers 16, 17, and 18 are laminated in this order. A part of the n-type nitride semiconductor layer 9, the V pit generation layer 10, the multilayer structure 121, the superlattice layer 122 as an intermediate layer, the MQW light emitting layer 14, and the p-type nitride semiconductor layers 16 and 17 , 18 are etched to form a mesa portion 30. Outside the mesa portion 30, a part of the upper surface of the n-type nitride semiconductor layer 9 is exposed without being covered with the V pit generation layer 10 and the superlattice layer 122, and the n-side electrode is formed on the exposed portion. 21 is provided. A p-side electrode 25 is provided on the p-type nitride semiconductor layer 18 via a transparent electrode 23. A transparent protective film 27 is provided on almost the entire top surface of the nitride semiconductor light emitting device 1 so that the p-side electrode 25 and the n-side electrode 21 are exposed. In the nitride semiconductor light emitting device, it is recognized that V pits are inevitably generated in ultra high magnification STEM (Scanning Transmission Electron Microscopy) observation of the cross section, but in this embodiment, V pits are generated as described later. The V pit 15 is controlled by providing the layer 10.

[substrate]
The substrate 3 may be an insulating substrate such as sapphire, or may be a conductive substrate such as GaN, SiC, or ZnO. The thickness of the substrate 3 at the time of growth is preferably 900 μm to 1200 μm, for example, and the thickness of the substrate 3 in the nitride semiconductor light emitting device 1 is preferably 50 μm to 300 μm, for example. The upper surface of the substrate 3 may be flat, or may have a concavo-convex shape including a convex portion 3A and a concave portion 3B as shown in FIG.

[Buffer layer]
The buffer layer 5 is preferably, for example, an Al _so Ga _to N (0 ≦ s0 ≦ 1, 0 ≦ t0 ≦ 1, s0 + t0 ≠ 0) layer, and more preferably an AlN layer or a GaN layer. However, a small part (0.5 to 2%) of N may be replaced with oxygen. Thereby, since the buffer layer 5 is formed so as to extend in the normal direction of the growth surface of the substrate 3, the buffer layer 5 made of an aggregate of columnar crystals with uniform crystal grains is obtained.

  Although the thickness of the buffer layer 5 is not specifically limited, It is preferable that they are 3 nm or more and 100 nm or less, More preferably, they are 5 nm or more and 50 nm or less.

[Underlayer]
Underlayer 7 is preferably for example, _{Al s1 Ga t1 In u1 N (} 0 ≦ s1 ≦ 1,0 ≦ t1 ≦ 1,0 ≦ u1 ≦ 1, s1 + t1 + u1 ≠ 0) layer, more preferably Al _s1 Ga _t1 N (0 ≦ s1 ≦ 1, 0 ≦ t1 ≦ 1, s1 + t1 ≠ 0) layer, more preferably a GaN layer. As a result, crystal defects (for example, dislocations) existing in the buffer layer 5 are likely to be looped near the interface between the buffer layer 5 and the base layer 7, so that the crystal defects are transferred from the buffer layer 5 to the base layer 7. Can be prevented.

  The underlayer 7 may contain an n-type dopant. However, if the underlayer 7 does not contain an n-type dopant, good crystallinity of the underlayer 7 can be maintained. Therefore, it is preferable that the underlayer 7 does not contain an n-type dopant.

  Increasing the thickness of the underlayer 7 reduces defects in the underlayer 7, but the effect of reducing defects in the underlayer 7 is saturated even if the thickness of the underlayer 7 is increased to some extent. From this, the thickness of the foundation layer 7 is preferably 1 μm or more and 8 μm or less.

[N-type nitride semiconductor layer]
In the n-type nitride semiconductor layers 8 and 9, for example, an Al _{s2 Gat2} In _u2 N (0 ≦ s2 ≦ 1, 0 ≦ t2 ≦ 1, 0 ≦ u2 ≦ 1, s2 + t2 + u2≈1) layer is doped with an n-type dopant. More preferably, Al _s2 Ga _{1 -s2} N (0 ≦ s2 ≦ 1, preferably 0 ≦ s2 ≦ 0.5, more preferably 0 ≦ s2 ≦ 0.1) layer is n-type A layer doped with a dopant.

  The n-type dopant is not particularly limited, and may be Si, P, As, Sb, or the like, and is preferably Si. This can be said also in each layer mentioned later.

The n-type dopant concentration in n-type nitride semiconductor layers 8 and 9 is not particularly limited, but is preferably 1 × 10 ¹⁹ cm ⁻³ or less.

  The resistance of the n-type nitride semiconductor layers 8 and 9 decreases as the thickness of the n-type nitride semiconductor layers 8 and 9 increases. However, if the thickness of the n-type nitride semiconductor layers 8 and 9 is increased, the manufacturing cost of the nitride semiconductor light emitting device is increased. From the balance of both, the thickness of the n-type nitride semiconductor layers 8 and 9 is practically preferably 1 μm or more and 10 μm or less, but is not particularly limited.

  In the examples described later, the n-type nitride semiconductor layers 8 and 9 are formed by two growth processes in which the growth of the n-type GaN layer is temporarily interrupted and then the same n-type GaN layer is grown again. Yes. However, the configuration of the n-type nitride semiconductor layer is not particularly limited. For example, the n-type nitride semiconductor layer may be a single layer by continuously forming the n-type nitride semiconductor layer 8 and the n-type nitride semiconductor layer 9, or the n-type nitride semiconductor layer may be three or more layers. You may have the laminated structure of. N-type nitride semiconductor layers 8 and 9 may have the same composition or different compositions. In addition, n-type nitride semiconductor layers 8 and 9 may have the same thickness or different thicknesses.

[V pit generation layer]
The V pit generation layer 10 is located closer to the n-type nitride semiconductor layer 9 than the layer (the MQW light emitting layer 14 in the present embodiment) in which the average position of the starting point of the V pit 15 effectively functions as the light emitting layer. This is a layer for forming the V pit 15 so as to be located in the layer (the superlattice layer 122 in the present embodiment). Here, the starting point of the V pit 15 means the bottom of the V pit 15 and is “VS” shown in FIG. In addition, the average position of the start point of the V pit 15 means a position obtained by averaging the start point of the V pit 15 formed in the MQW light emitting layer 14 in the thickness direction of the nitride semiconductor light emitting element. Yes.

V pit generation layer 10 is preferably a highly doped n-type GaN layer having a thickness of 25 nm, for example. Here, the high doping is significantly (for example, 1.1 times or more, preferably 1.4 times or more, more preferably 1.8 times or more) than the n-type nitride semiconductor layer 9 located under the V pit generation layer 10. It means that the n-type dopant concentration is high. Specifically, the n-type dopant concentration of the V pit generation layer 10 is preferably 5 × 10 ¹⁸ cm ⁻³ or more, more preferably 7 × 10 ¹⁸ cm ⁻³ or more, and 1 × 10 ^19. More preferably, it is cm ⁻³ or more. As a result, the film quality of the V pit generation layer 10 is lower than the film quality of the n-type nitride semiconductor layer 9, so that the V pit generation effect by the V pit generation layer 10 is effectively exhibited.

  On the other hand, if the n-type dopant concentration in the V pit generation layer 10 is too high, the light emission efficiency of the MQW light emission layer 14 formed on the V pit generation layer 10 may be reduced. Therefore, the n-type dopant concentration in the V pit generation layer 10 is preferably 10 times or less, more preferably 3 times or less than the n-type dopant concentration in the n-type nitride semiconductor layer 9.

  V pit generation layer 10 is significantly (for example, 1.1 times or more, preferably 1.4 times or more, more preferably 1.8 times or more) n-type dopant concentration than the uppermost surface of n-type nitride semiconductor layer 9. Is good. Thereby, the V pit generation effect by the V pit generation layer 10 is more effectively exhibited.

The V pit generation layer 10 is a layer in which an Al _{s3 Gat3} In _u3 N (0 ≦ s3 ≦ 1, 0 ≦ t3 ≦ 1, 0 ≦ u3 ≦ 1, s3 + t3 + u3≈1) layer is doped with an n-type dopant. _{Alternatively} , In _u3 Ga _1-u3 N (0 ≦ u3 ≦ 1, preferably 0 ≦ u3 ≦ 0.5, more preferably 0 ≦ u3 ≦ 0.15) is a layer doped with an n-type dopant. Preferably there is. Thus, when the V pit generation layer 10 contains In, the In composition ratio in the V pit generation layer 10 is preferably higher than the In composition ratio in the n-type nitride semiconductor layer 9. Also by this, since the film quality of the V pit generation layer 10 is lower than that of the n-type nitride semiconductor layer 9, the V pit generation effect by the V pit generation layer 10 is effectively exhibited.

  Such a V pit generation layer 10 preferably has a thickness of 5 nm or more, and more preferably has a thickness of 10 nm or more. Thereby, the effect that the number of V pits per unit number of threading dislocations increases can be obtained.

[Multilayer structure]
In the nitride semiconductor light emitting device shown in FIG. 1, the starting point VS of the V pit 15 is located below the MQW light emitting layer 14. Therefore, as will be described later, by increasing the number of undoped barrier layers constituting the MQW light emitting layer 14, the volume of the MQW light emitting layer 14 contributing to light emission can be increased. Therefore, it is possible to prevent a decrease in light emission efficiency during driving with a large current, and it is also possible to prevent a decrease in light emission efficiency at high temperatures. However, it has been found that increasing the volume of the MQW light-emitting layer 14 that contributes to light emission by increasing the number of undoped barrier layers constituting the MQW light-emitting layer 14 increases the defect rate due to ESD.

  On the other hand, when the number of undoped barrier layers constituting the MQW light-emitting layer 14 is increased, the interval between the V pit generation layer 10 and the MQW light-emitting layer 14 contributing to light emission becomes narrow, and as a result, the start point of the V pit 15 emits light. It is not preferable because it exists at a position close to the MQW light emitting layer 14 that contributes to the above. Therefore, in order to prevent the average position of the starting point of the V pit 15 from being present in the MQW light emitting layer 14 (at least above the MQW light emitting layer 14), the V pit generating layer 10 is separated from the MQW light emitting layer 14 as much as possible. It is preferable to do. However, if the thickness of the intermediate layer (superlattice layer) 122 between the MQW light emitting layer 14 and the V pit generation layer 10 is increased for this purpose, the quality of the MQW light emitting layer 14 may be deteriorated. In addition, the productivity of the nitride semiconductor light emitting device may be reduced.

  For the purpose of separating the V pit generation layer 10 from the MQW light emitting layer 14 as much as possible, only the n-type GaN layer is provided between the V pit generation layer 10 and the intermediate layer (superlattice layer) 122. When the film is formed thick at a temperature lower than the growth temperature, it is impossible to prevent a decrease in light emission efficiency during high temperature driving and large current driving, and the defect rate due to ESD increases. The reason is considered as follows. When the n-type GaN layer is formed thick (for example, 200 nm or more) at a temperature lower than the growth temperature of the V pit generation layer 10, the growth surface of the n-type GaN layer becomes uneven (the growth surface of the n-type GaN layer becomes cloudy). This is because the layer formed on the n-type GaN layer is adversely affected.

  As a result of intensive studies on these issues, if the multilayer structure 121 is formed between the V pit generation layer 10 and the intermediate layer (superlattice layer) 122, the light emission efficiency is reduced under high temperature and high current drive. It was found that the defect rate due to ESD can be further reduced. Hereinafter, the configuration of the multilayer structure 121 will be described.

  The multilayer structure 121 is formed by stacking a plurality of nitride semiconductor layers having different band gap energies, and includes a nitride semiconductor layer having a relatively small band gap energy and a nitride semiconductor layer having a relatively large band gap energy. It is preferable that they are laminated alternately. As a result, the size of the V pit 15 generated in the V pit generation layer 10 can be increased, and as a result, the size of the intermediate layer 122 and the MQW light emitting layer 14 thereon can be increased. Can be obtained. Therefore, an increase in the defect rate due to ESD can be prevented.

The n-type dopant concentration in the nitride semiconductor layer constituting the multilayer structure 121 is preferably set lower than the n-type dopant concentration in the V pit generation layer 10, for example, 7 × 10 ¹⁷ cm ⁻³ or less. It is preferable that Thus, when the n-type dopant concentration in the multilayer structure 121 is low, the depletion layer expands at the time of reverse bias, and thus the multilayer structure 121 can function as an electric field relaxation layer together with the intermediate layer (superlattice layer) 122. . If the driving voltage of the nitride semiconductor light emitting device does not exceed the allowable range, the nitride semiconductor layer constituting the multilayer structure 121 can be an undoped layer.

  The multilayer structure 121 is preferably formed at a temperature not higher than the growth temperature of the V pit generation layer 10, and more preferably at a temperature not higher than 900 ° C. Thereby, the effect that the size of the V pit 15 generated in the V pit generation layer 10 can be increased can be obtained. On the other hand, if the growth temperature of the multilayer structure 121 is too low, the film quality of the multilayer structure 121 may be deteriorated. Therefore, the growth temperature of the multilayer structure 121 is preferably 600 ° C. or higher, and more preferably 700 ° C. or higher.

  The reason why a nitride semiconductor layer (for example, an InGaN layer or an n-type InGaN layer) having a relatively small band gap energy is necessary in the multilayer structure 121 is not clear, but the following reasons are conceivable. Nitridation with a relatively small band gap energy during the growth of a nitride semiconductor layer (for example, a GaN layer or an n-type GaN layer) having a relatively large band gap energy at a temperature lower than the growth temperature of the V pit generation layer 10 Growing a semiconductor layer promotes two-dimensional growth of a nitride semiconductor material having a relatively large band gap energy. As a result, even if the total thickness of the multilayer structure 121 is thick, it is possible to prevent an adverse effect caused by the thick total thickness of the multilayer structure 121 from being given to the layer growing on the multilayer structure 121. In order to effectively obtain such an effect, the thickness of the nitride semiconductor layer with a relatively small band gap energy is set to be the thickness of the nitride semiconductor layer with a relatively large band gap energy constituting the multilayer structure 121. The band gap energy constituting the multilayer structure 121 is preferably 1/5 times or more and 1/2 times or less the thickness of the relatively large nitride semiconductor layer. Note that the thickness of the nitride semiconductor layer having a relatively large band gap energy is preferably 5 nm or more and 100 nm or less, and more preferably 10 nm or more and 40 nm or less.

  As an example of the multilayer structure 121, an n-type InGaN layer having a thickness of 7 nm, an n-type GaN layer having a thickness of 30 nm, and an n-type InGaN layer having a thickness of 7 nm are formed on the V pit generation layer 10. And an n-type GaN layer having a thickness of 20 nm are sequentially stacked.

The specific composition of the nitride semiconductor layer constituting the multilayer structure 121 is not limited to the above composition. For example, as a nitride semiconductor layer having a relatively large band gap energy constituting the multilayer structure 121, Al _i1 Ga _j1 In _(1-i1-j1) N (0 ≦ i1 <1, 0 <j1 ≦ 1) A GaN layer is preferable. Further, as a nitride semiconductor layer having a relatively small band gap energy constituting the multilayer structure 121, Al _i2 Ga _j2 In _(1-i2-j2) N (0 ≦ i2 <1, 0 ≦ j2 <1, j1 <j2) layer, and Ga _j3 In _(1-j3) N (0 <j3 <1) layer is preferable.

More specifically, the multilayer structure 121 includes an Al _i1 Ga _j1 In _(1-i1-j1) N (0 ≦ i1 <1, 0 <j1 ≦ 1) layer and an Al _i2 Ga _j2 In _{(1-i2- j2)} N (0 ≦ i2 <1, 0 ≦ j2 <1, j1 <j2) layers may be alternately stacked, or a GaN layer and Ga _j3 In _(1-j3) N (0 <J3 <1) layers may be alternately stacked.

When the nitride semiconductor layer constituting the multilayer structure 121 includes In, the In composition ratio in the nitride semiconductor layer constituting the multilayer structure 121 is approximately the same as the In composition ratio in the intermediate layer (superlattice layer) 122 ( ± 5%) is preferable. Thereby, when forming the intermediate | middle layer (superlattice layer) 122 after the multilayer structure 121, the effort which changes supply_amount | feed_rate of In source gas can be saved. Therefore, the productivity of the nitride semiconductor light emitting device is improved. More preferably, when the nitride semiconductor layer constituting the multilayer structure 121 is a Ga _j3 In _(1-j3) N (0 <j3 <1) layer, Ga _j3 In _(1-j3) N (0 < The In composition ratio (1-j3) in the j3 <1) layer is the same as the In composition ratio in the narrow band gap layer 122B constituting the intermediate layer (superlattice layer) 122.

  In the multilayer structure 121, the number of nitride semiconductor layers having a relatively small band gap energy and the number of nitride semiconductor layers having a relatively large band gap energy are not particularly limited. When the nitride semiconductor layer having a relatively small band gap energy and the nitride semiconductor layer having a relatively large band gap energy are taken as one set, the multilayer structure 121 has a relatively small band gap energy of two or more sets. It is preferable to have a nitride semiconductor layer and a nitride semiconductor layer having a relatively large band gap energy. Thereby, since the thickness of the multilayer structure 121 can be gained, the average position of the starting point of the V pit 15 is mostly on the side of the substrate 3 than near the center of the intermediate layer (superlattice layer) 122 in the thickness direction. It becomes. Therefore, it is possible to further prevent a decrease in light emission efficiency during high temperature driving or large current driving.

  As described above, when the multilayer structure 121 is introduced between the V pit generation layer 10 and the intermediate layer (superlattice layer) 122, the V pit generation layer 10 is formed further away from the MQW light emitting layer 14. Can do. Therefore, the average position of the starting point of the V pit 15 is in the intermediate layer (superlattice layer) 122, and most of it is closer to the substrate 3 side than the vicinity of the center in the thickness direction of the intermediate layer (superlattice layer) 122. There is also. Accordingly, it is possible to further prevent a decrease in light emission efficiency during high temperature driving or large current driving. In addition, the multilayer structure 121 is configured by alternately stacking nitride semiconductor layers having a relatively small band gap energy and nitride semiconductor layers having a relatively large band gap energy. Therefore, the effect that the size of the V pit 15 generated in the V pit generation layer 10 can be increased can be obtained. Therefore, an increase in the defect rate due to ESD can be prevented.

  It is preferable that a second multilayer structure is further provided between n-type nitride semiconductor layer 9 and V pit generation layer 10. An example of the configuration of the second multilayer structure provided between the n-type nitride semiconductor layer 9 and the V pit generation layer 10 is a structure in which doped layers and undoped layers are alternately stacked. Here, the doped layer and the undoped layer are preferably formed at the same temperature as the n-type nitride semiconductor layer 9. The n-type dopant concentration in the doped layer is preferably the same as the n-type dopant concentration in the V pit generation layer 10. Thereby, since the effect that the size of the V pit 15 generated in the V pit generation layer 10 can be increased can be obtained, an increase in the defect rate due to ESD can be further prevented.

[Intermediate layer (superlattice layer)]
An intermediate layer is provided between the V pit generation layer 10 and the MQW light emitting layer 14, and the intermediate layer in this embodiment is a superlattice layer 122.

  The superlattice layer in this specification means a layer composed of crystal lattices whose periodic structure is longer than the basic unit cell by alternately laminating very thin crystal layers. As shown in FIG. 3, in the superlattice layer 122, a wide band gap layer 122A and a narrow band gap layer 122B are alternately stacked to form a super lattice structure, and the periodic structure forms the wide band gap layer 122A. It is longer than the basic unit cell of the semiconductor material and the basic unit cell of the semiconductor material constituting the narrow band gap layer 122B. Note that the superlattice layer 122 has a superlattice structure in which one or more semiconductor layers different from the wide band gap layer 122A and the narrow band gap layer 122B, a wide band gap layer 122A, and a narrow band gap layer 122B are sequentially stacked. It may be configured. Further, the length of one cycle of the superlattice layer 122 (the sum of the thickness of the wide band gap layer 122A and the thickness of the narrow band gap layer 122B) is shorter than the length of one cycle of the MQW light-emitting layer 14 described later. Is preferably 1 nm or more and 10 nm or less.

Each wide band gap layer 122A is preferably an Al _a1 Ga _b1 In _(1-a1-b1) N (0 ≦ a1 ≦ 1, 0 <b1 ≦ 1) layer, and more preferably a GaN layer.

Each narrow band gap layer 122B preferably has a smaller band gap than, for example, the wide band gap layer 122A and a larger band gap than each well layer 14W described later. The narrow band gap layer 122B is an Al _a2 Ga _b2 In _(1-a2-b2) N (0 ≦ a2 <1, 0 <b2 <1, (1-a1-b1) <(1-a2-b2)) layer. It is preferable that there is a Ga _b2 In _(1-b2) N (0 <b2 <1) layer.

  At least one of each wide band gap layer 122A and each narrow band gap layer 122B preferably includes an n-type dopant. This is because if both the wide band gap layer 122A and the narrow band gap layer 122B are undoped, the drive voltage increases.

  If all of the nitride semiconductor layers constituting the superlattice layer 122 contain an n-type dopant, the depletion layer does not spread during reverse bias (electrons do not penetrate the superlattice layer 122), and therefore the effect of electric field relaxation is reduced. Invite. However, the superlattice layer 122 is also a layer provided for injecting electrons into the MQW light emitting layer 14. Therefore, if at least two nitride semiconductor layers located on the MQW light-emitting layer 14 side are n-type semiconductor layers and the nitride semiconductor layer located closer to the substrate 3 than the n-type semiconductor layer is an undoped layer, MQW Since the number of electrons injected into the light emitting layer 14 can be increased, the light output is improved and the voltage reduction effect is exhibited. In addition, when the thickness of the undoped layer is increased, it is necessary to apply a voltage for moving electrons, and the drive voltage may increase. In order to prevent an increase in driving voltage, it is preferable that at least two nitride semiconductor layers located on the substrate 3 side be undoped layers.

  When the wide band gap layer 122A and the narrow band gap layer 122B are taken as one set, the superlattice layer 122 preferably includes 20 sets or more of the wide band gap layer 122A and the narrow band gap layer 122B. As a result, the V pit generation layer 10 can be formed further away from the MQW light emitting layer 14, so that the average position of the starting point of the V pit 15 can be within the intermediate layer (superlattice layer) 122. .

  Further, when the superlattice layer 122 has 20 or more wide band gap layers 122A and narrow band gap layers 122B, the five sets of wide band gap layers 122A and narrow band gap layers 122B located on the MQW light emitting layer 14 side are n-type dopants. It is preferable to contain. Thereby, the number of electrons injected into the MQW light-emitting layer 14 can be increased, so that the light output is improved and the voltage reduction effect is exhibited.

  The superlattice layer 122 is a layer provided for improving the characteristics of the MQW light emitting layer 14, and is not an essential component for the nitride semiconductor light emitting device 1. However, if the superlattice layer 122 is provided between the V pit generation layer 10 and the MQW light emitting layer 14, the V pit generation layer 10 can be separated from the MQW light emitting layer 14. It is possible to prevent such a position from being present in the MQW light emitting layer 14 (at least above the MQW light emitting layer 14). Therefore, in the present invention, it is preferable to provide the superlattice layer 122 between the V pit generation layer 10 and the MQW light emitting layer 14. The thickness of the superlattice layer 122 is preferably 40 nm or more, more preferably the thickness of the superlattice layer 122 is 50 nm or more, and further preferably the thickness of the superlattice layer 122 is 60 nm or more. On the other hand, if the thickness of the superlattice layer 122 is too thick, the quality of the MQW light emitting layer 14 may be deteriorated. Therefore, the thickness of the superlattice layer 122 is preferably 100 nm or less, more preferably 80 nm or less. is there.

[MQW light emitting layer (multiple quantum well light emitting layer)]
The MQW light emitting layer 14 is partially formed with V pits 15. Here, the partial formation of the V pits 15 means that the V pits 15 are observed as dots on the upper surface of the MQW light emitting layer 14 when the upper surface of the MQW light emitting layer 14 is observed by AFM. The number density of the V pits 15 on the upper surface of the MQW light emitting layer 14 is preferably 1 × 10 ⁸ cm ⁻² or more and 1 × 10 ¹⁰ cm ⁻² or less. Conventionally, V pits are formed in the MQW light emitting layer. In this case, the density of the number of V pits on the upper surface of the MQW light emitting layer is less than 1 × 10 ⁸ cm ⁻² .

  As shown in FIG. 3, the MQW light emitting layer 14 includes the well layers 14 </ b> W and the barrier layers 14 </ b> A that are alternately stacked, whereby the barrier layers 14 </ b> A (14 </ b> A <b> 1, 14 </ b> A <b> 2,. 14W2,..., 14W8), and is provided on the superlattice layer 122 via the first barrier layer 14A ′. The last barrier layer 14A0 is provided on the well layer 14W1 located closest to the p-type nitride semiconductor layer 16 in the well layer 14W. In order to identify each barrier layer 14A and each well layer 14W, a number is assigned from the p-type nitride semiconductor layer 16 toward the superlattice layer 122, and the well layer 14W1, the barrier layer 14A1, the well layer 14W2, and the barrier layer 14A2,...

  In the MQW light emitting layer 14, one or more semiconductor layers different from the barrier layer 14A and the well layer 14W, a barrier layer 14A, and a well layer 14W may be stacked in this order. The length of one cycle of the MQW light emitting layer 14 (the sum of the thickness of the barrier layer 14A and the thickness of the well layer 14W) is, for example, not less than 5 nm and not more than 100 nm.

The composition of each well layer 14W is preferably adjusted according to the emission wavelength required for the nitride semiconductor light emitting device according to this embodiment. For example, Al _c Ga _d In _(1-cd) N (0 ≦ c < 1, 0 <d ≦ 1), and an In _e Ga _(1-e) N (0 <e ≦ 1) layer not containing Al is preferable. For example, when emitting ultraviolet light having a wavelength of 375 nm or less, it is necessary to increase the band gap energy of the MQW light emitting layer 14, and therefore the composition of each well layer 14W includes Al. The composition of each well layer 14W is preferably the same. Thereby, the wavelength of light emitted by recombination of electrons and holes in each well layer 14W can be made the same, and thus the emission spectrum width of the nitride semiconductor light emitting device 1 can be narrowed. Further, the well layer 14W located on the p-type nitride semiconductor layer 16 side preferably contains as little dopant as possible. In other words, the well layer 14W is located on the p-type nitride semiconductor layer 16 side without introducing a dopant raw material. It is preferable to grow the well layer 14W. As a result, non-radiative recombination hardly occurs in each well layer 14W, so that the light emission efficiency is improved. On the other hand, the well layer 14W located on the substrate 3 side may contain an n-type dopant. As a result, the driving voltage of the nitride semiconductor light emitting device tends to decrease.

  The thickness of each well layer 14W is not particularly limited, but is preferably the same. If the thickness of each well layer 14W is the same, the quantum level of each well layer 14W is also the same, and light of the same wavelength is generated in each well layer 14W due to recombination of electrons and holes in each well layer 14W. . Therefore, it is convenient because the emission spectrum width of the nitride semiconductor light emitting device 1 becomes narrow. On the other hand, if the composition or thickness of the well layer 14W is intentionally varied, the emission spectrum width of the nitride semiconductor light emitting device 1 can be broadened. When the nitride semiconductor light-emitting element shown in FIG. 1 is used for illumination or the like, it is preferable to intentionally vary the composition or thickness of the well layer 14W. For example, the thickness of each well layer 14W is preferably 1 nm or more and 7 nm or less. If the thickness of each well layer 14W is outside this range, the light emission efficiency may decrease.

The materials constituting each barrier layer 14A (14A1 to 14A7 shown in FIG. 3), the first barrier layer 14A ′, and the last barrier layer 14A0 each have a larger band gap energy than the material constituting each well layer 14W. Is preferred. Specifically, each barrier layer 14A (14A1 to 14A7 shown in FIG. 3), the first barrier layer 14A ′, and the last barrier layer 14A0 are made of Al _f Ga _g In _(1-fg) N (0 ≦ f < 1, 0 <g ≦ 1), more preferably In _h Ga _(1-h) N (0 <h ≦ 1, e> h) not containing Al, and the well layer 14W is formed. More preferably, it is made of Al _f Ga _g In _(1-fg) N (0 ≦ f <1, 0 <g ≦ 1) having substantially the same lattice constant as the material to be formed.

  The thickness of each barrier layer 14A is not particularly limited, but is preferably 1 nm or more and 10 nm or less, and more preferably 3 nm or more and 7 nm or less. The driving voltage decreases as the thickness of each barrier layer 14A decreases. However, if the thickness of each barrier layer 14A is extremely reduced, the light emission efficiency tends to decrease. The thickness of the first barrier layer 14A 'is not particularly limited and is preferably 1 nm or more and 10 nm or less. The thickness of the last barrier layer 14A0 is not particularly limited, but is preferably 1 nm or more and 40 nm or less.

  The n-type dopant concentration in each barrier layer 14A (14A1 to 14A7 shown in FIG. 3) and the first barrier layer 14A ′ is not particularly limited, and is preferably set as appropriate. Among the plurality of barrier layers 14A, the barrier layer 14A located on the substrate 3 side is doped with n-type dopant, and the barrier layer 14A located on the p-type nitride semiconductor layer 16 side is located on the substrate 3 side. It is preferable that an n-type dopant having a lower concentration than the barrier layer 14A is doped or not doped. Each barrier layer 14A (14A1 to 14A7 shown in FIG. 3), the first barrier layer 14A ', and the last barrier layer 14A0 may be intentionally doped with an n-type dopant. Further, each barrier layer 14A (14A1 to 14A7 shown in FIG. 3), the first barrier layer 14A ′, and the last barrier layer 14A0 include a p-type nitride semiconductor layer 16, a p-type nitride semiconductor layer 17, and p The p-type dopant may be doped by thermal diffusion during the growth of the type nitride semiconductor layer 18.

  The number of well layers 14W is not particularly limited, but is preferably 2 or more, 20 or less, more preferably 3 or more and 15 or less, and still more preferably 4 or more and 12 or less.

[P-type nitride semiconductor layer]
In the configuration shown in FIG. 1, the p-type nitride semiconductor layer has a three-layer structure of a p-type AlGaN layer 16, a p-type GaN layer 17, and a high-concentration p-type GaN layer 18. It is only an example of a physical semiconductor layer. p-type nitride semiconductor layer 16, 17 and 18, for example _{Al s4 Ga t4 In u4 N (} 0 ≦ s4 ≦ 1,0 ≦ t4 ≦ 1,0 ≦ u4 ≦ 1, s4 + t4 + u4 ≠ 0) layer on the p-type dopant Preferably it is a doped layer, more preferably Al _s4 Ga _(1-s4) N (0 <s4 ≦ 0.4, preferably 0.1 ≦ s4 ≦ 0.3) layer is doped with p-type dopant Layer.

Although a p-type dopant is not specifically limited, For example, it is preferable that it is magnesium. The carrier concentration in the p-type nitride semiconductor layers 16, 17, and 18 is preferably 1 × 10 ¹⁷ cm ⁻³ or more. Here, since the activation rate of the p-type dopant is about 0.01, the p-type dopant concentration (different from the carrier concentration) in the p-type nitride semiconductor layers 16, 17 and 18 is 1 × 10 ¹⁹ cm ^−3. The above is preferable. However, the p-type dopant concentration in the portion located on the MQW light emitting layer 14 side of the p-type nitride semiconductor layer 16 may be less than 1 × 10 ¹⁹ cm ⁻³ .

  The total thickness of the p-type nitride semiconductor layers 16, 17, and 18 is not particularly limited, but is preferably 50 nm or more and 300 nm or less. By reducing the thickness of the p-type nitride semiconductor layers 16, 17, and 18, the heating time during the growth can be shortened, so that the diffusion of the p-type dopant into the MQW light emitting layer 14 can be suppressed. it can.

[N-side electrode, transparent electrode, p-side electrode]
The n-side electrode 21 and the p-side electrode 25 are electrodes for supplying driving power to the nitride semiconductor light emitting device 1. Although the n-side electrode 21 and the p-side electrode 25 are composed of only the pad electrode portion in FIG. 2, an elongated protrusion (branch electrode) for current diffusion is connected to the n-side electrode 21 or the p-side electrode 25. May be. In addition, it is preferable that an insulating layer for preventing current from being injected into the p-side electrode 25 is provided below the p-side electrode 25. Thereby, the amount of emitted light shielded by the p-side electrode 25 is reduced.

  The n-side electrode 21 is preferably configured, for example, by laminating a titanium layer, an aluminum layer, and a gold layer in this order. Assuming the case where wire bonding is performed on the n-side electrode 21, the thickness of the n-side electrode 21 is preferably 1 μm or more.

  The p-side electrode 25 is preferably configured by, for example, a nickel layer, an aluminum layer, a titanium layer, and a gold layer laminated in this order, and may be made of the same material as the n-side electrode 21. Assuming the case where wire bonding is performed on the p-side electrode 25, the thickness of the p-side electrode 25 is preferably 1 μm or more.

  The transparent electrode 23 is preferably made of a transparent conductive film such as ITO (indium tin oxide) or IZO (indium zinc oxide), and preferably has a thickness of 20 nm to 200 nm.

[V pit start point]
In the nitride semiconductor light emitting device 1 according to this embodiment, most of the V pit start points VS are not present in the MQW light emitting layer 14 like the V pit P1 shown in FIG. That is, the starting point position of the V pit estimated from the distribution of the V pit diameter shown in FIG. 5 (a) has the distribution P1 shown in FIG. 5 (b). It is considered to exist in the lattice layer 122. Since the V pit 15 is considered to be generated due to threading dislocations, most of the threading dislocations are considered to be inside the V pit 15. Thereby, it is possible to suppress the electrons and holes injected into the MQW light emitting layer 14 from reaching the inside of the V pit 15. Therefore, it is presumed that the occurrence of non-radiative recombination due to the trapping of electrons and holes by threading dislocations is suppressed. Therefore, it is possible to prevent a decrease in luminous efficiency. This becomes conspicuous at a high temperature or during a large current drive.

  Specifically, at a high temperature, the movement of injected carriers (holes or electrons) into the MQW light-emitting layer becomes active, so that the probability that the injected carriers reach threading dislocations increases. However, in the nitride semiconductor light emitting device 1 according to this embodiment, many threading dislocations in the MQW light emitting layer 14 are covered with the V pit 15 (since many threading dislocations exist inside the V pit 15). Non-radiative recombination at threading dislocations is suppressed. Therefore, it is possible to prevent a decrease in light emission efficiency at a high temperature.

  Further, since the start point of the V pit 15 is located below the MQW light emitting layer 14, the volume of the MQW light emitting layer 14 contributing to light emission can be increased by increasing the number of undoped barrier layers. Therefore, it is possible to prevent a decrease in light emission efficiency when driving with a large current.

[About carrier concentration and dopant concentration]
The carrier concentration means the concentration of electrons or holes, and is not determined only by the amount of n-type dopant or the amount of p-type dopant. Such carrier concentration is calculated based on the result of the voltage-capacitance characteristics of the nitride semiconductor light-emitting element 1, and indicates the carrier concentration in a state where no current is injected. , The total of carriers generated from donor-generated crystal defects and acceptor-formed crystal defects.

  However, it can be considered that the n-type carrier concentration is almost the same as the n-type dopant concentration because the activation rate of Si, which is an n-type dopant, is high. The n-type dopant concentration can be easily obtained by measuring the concentration distribution in the depth direction by SIMS (Secondary Ion Mass Spectroscopy). Furthermore, the relative relationship (ratio) of the dopant concentration is almost the same as the relative relationship (ratio) of the carrier concentration. For these reasons, in the scope of claims of the present invention, the dopant concentration is actually defined as easily measured. And if the n-type dopant concentration obtained by the measurement is averaged in the thickness direction, the average n-type dopant concentration can be obtained.

[Nitride Semiconductor Light-Emitting Device Manufacturing Method]
Below, the manufacturing method of the nitride semiconductor light-emitting device shown in FIG. 1 is shown.

  First, the buffer layer 5 is formed on the substrate 3 by, for example, sputtering. Next, the base layer 7, the n-type nitride semiconductor layer 8, the n-type nitride semiconductor layer 9, the V pit generation layer 10, the multilayer structure 121, the superlattice layer 122 are formed on the buffer layer 5 by, for example, MOCVD. The MQW light emitting layer 14, the p-type nitride semiconductor layer 16, the p-type nitride semiconductor layer 17, and the p-type nitride semiconductor layer 18 are formed in this order. Then, the p-type nitride semiconductor layer 18, the p-type nitride semiconductor layer 17, the p-type nitride semiconductor layer 16, the MQW light emitting layer 14, and the superlattice layer 122 so that a part of the n-type nitride semiconductor layer 9 is exposed. The multilayer structure 121, the V pit generation layer 10, and a part of the n-type nitride semiconductor layer 9 are etched. An n-side electrode 21 is formed on the upper surface of n-type nitride semiconductor layer 9 exposed by this etching. Further, the transparent electrode 23 and the p-side electrode 25 are sequentially stacked on the upper surface of the p-type nitride semiconductor layer 18. Thereafter, a transparent protective film 27 is formed so as to cover the transparent electrode 23 and the side surface of each layer exposed by the etching. Thereby, the nitride semiconductor light emitting device shown in FIG. 1 is obtained. The composition, thickness, and the like of each layer are as described above in [Configuration of nitride semiconductor light emitting device].

  A method for forming V pit generation layer 10 is not particularly limited, but a temperature (second growth temperature) lower than the growth temperature (first growth temperature) of n-type nitride semiconductor layer 8 and n-type nitride semiconductor layer 9. Thus, it is preferable to grow the V pit generation layer 10. Specifically, (first growth temperature−second growth temperature) is preferably 50 ° C. or higher, more preferably 100 ° C. or higher. In other words, the growth temperature of the V pit generation layer 10 is preferably 920 ° C. or less, more preferably 860 ° C. or less, and further preferably 820 ° C. or less. The growth temperature of the V pit generation layer 10 is preferably 600 ° C. or higher, and more preferably 700 ° C. or higher. As a result, the film quality of the V pit generation layer 10 is lower than that of the n-type nitride semiconductor layer 9, and the V pit formation effect of the V pit generation layer 10 is increased. Therefore, the V pit 15 is formed in the MQW light emitting layer 14.

  If the growth temperature of the V pit generation layer 10 is too low, the light emission efficiency in the MQW light emitting layer 14 may decrease. Therefore, (first growth temperature−second growth temperature) is preferably set to 400 ° C. or less, and more preferably 300 ° C. or less.

  Further, the V-pit generation layer 10 may be formed with a higher n-type dopant concentration than the n-type nitride semiconductor layer 9. Even in this case, the V pit formation effect of the V pit generation layer 10 is increased. Therefore, the V pit 15 is formed in the MQW light emitting layer 14. The n-type dopant concentration is as shown in the above [V pit generation layer].

  The method of forming the multilayer structure 121 is not particularly limited, but it is preferable to grow the multilayer structure 121 at a temperature (third growth temperature) that is not higher than the growth temperature (second growth temperature) of the V pit generation layer 10. Thereby, since the effect that the size of the V pit 15 generated in the V pit generation layer 10 can be increased can be obtained, the defect rate due to ESD can be reduced. In order to effectively obtain this effect, the third growth temperature is preferably 600 ° C. or higher, and more preferably 600 ° C. or higher and 900 ° C. or lower.

  The formation method of the intermediate layer (superlattice layer) 122 is not particularly limited, but the intermediate layer (superlattice layer) 122 is not higher than the growth temperature (third growth temperature) of the multilayer structure 121 (fourth growth temperature). It is preferable to grow. Thereby, the effect that the size of the V pit 15 generated in the V pit generation layer 10 can be increased can be obtained. In order to effectively obtain this effect, the fourth growth temperature is preferably 600 ° C. or higher and 900 ° C. or lower, and the fourth growth temperature is more preferably 600 ° C. or higher and 800 ° C. or lower.

  The growth temperature of the V pit generation layer 10 (second growth temperature), the growth temperature of the multilayer structure 121 (third growth temperature), and the growth temperature of the intermediate layer (superlattice layer) 122 (fourth growth temperature) are It is preferable that they are the same. Thereby, the effect that the size of the V pit 15 generated in the V pit generation layer 10 can be increased can be obtained. In order to effectively obtain this effect, the growth temperature of the V pit generation layer 10 (second growth temperature), the growth temperature of the multilayer structure 121 (third growth temperature), and the intermediate layer (superlattice layer) 122 The growth temperature (fourth growth temperature) is preferably 600 ° C. or higher and 900 ° C. or lower, and more preferably 600 ° C. or higher and 800 ° C. or lower.

  Below, the specific Example of this embodiment is shown. In addition, this embodiment is not limited to the Example shown below.

[Nitride Semiconductor Light-Emitting Element and V-Pit Evaluation Structure in First Example]
Hereinafter, the nitride semiconductor light emitting device 1 in the first embodiment and the V pit evaluation structure created for the examination will be described along the manufacturing process. Although the manufacturing conditions of the V-pit evaluation structure and the first embodiment are slightly different, the manufacturing conditions of the nitride semiconductor light emitting device 1 are described below as representatives.

  First, a wafer made of a sapphire substrate 3 having a diameter of 100 mm having an uneven surface made of convex portions 3A and concave portions 3B on the upper surface was prepared. The convex portion 3A has an equilateral triangular cross-sectional shape, and the interval between the apexes of the adjacent convex portions 3A is 2 μm. A buffer layer 5 made of AlN was formed on the upper surface of the sapphire substrate 3 subjected to the uneven processing by a sputtering method.

Next, the wafer on which the buffer layer 5 was formed was placed in the first MOCVD apparatus. An underlayer 7 made of undoped GaN was grown on the upper surface of the buffer layer 5 by MOCVD, and an n-type nitride semiconductor layer 8 made of Si-doped n-type GaN was subsequently grown on the upper surface of the underlayer 7. At this time, the thickness of the base layer 7 was 4 μm, the thickness of the n-type nitride semiconductor layer 8 was 3 μm, and the n-type dopant concentration in the n-type nitride semiconductor layer 8 was 6 × 10 ¹⁸ cm ⁻³ .

The wafer taken out from the first MOCVD apparatus was placed in the second MOCVD apparatus. The temperature of the wafer was set to 1081 ° C. (first growth temperature), and the n-type nitride semiconductor layer 9 was grown on the upper surface of the n-type nitride semiconductor layer 8. The n-type nitride semiconductor layer 9 is an n-type GaN layer having an n-type dopant concentration of 6 × 10 ¹⁸ cm ⁻³ , and the thickness of the n-type nitride semiconductor layer 9 is 1.5 μm.

Subsequently, the temperature of the wafer was set to 801 ° C. (second growth temperature), and the V pit generation layer 10 was grown on the upper surface of the n-type nitride semiconductor layer 9. Specifically, a Si-doped GaN layer having a thickness of 25 nm was grown so that the n-type dopant concentration was 1 × 10 ¹⁹ cm ⁻³ .

Subsequently, the multilayer structure 121 was grown with the wafer temperature kept at 801 ° C. (third growth temperature). Specifically, a multilayer structure in which a Si-doped InGaN layer having a thickness of 7 nm, a Si-doped GaN layer having a thickness of 30 nm, a Si-doped InGaN layer having a thickness of 7 nm, and a Si-doped GaN layer having a thickness of 20 nm are alternately stacked. 121. The n-type dopant concentration in the multilayer structure 121 was set to 7 × 10 ¹⁷ cm ⁻³ in any layer. The In composition ratio of the InGaN layer was set to be the same as the In composition ratio of the narrow band gap layer constituting the intermediate layer (superlattice layer) 122 to be grown next.

Subsequently, the intermediate layer (superlattice layer) 122 was grown with the wafer temperature kept at 801 ° C. (fourth growth temperature). Specifically, wide band gap layers 122A made of Si-doped GaN and narrow band gap layers 122B made of Si-doped InGaN were alternately grown for 20 periods. The thickness of each wide band gap layer 122A was 1.55 nm. Each narrow band gap layer 122B had a thickness of 1.55 nm. The n-type dopant concentration in each wide band gap layer 122A is 1 × 10 ¹⁹ cm ⁻³ in five layers of the wide band gap layer 122A located on the MQW light emitting layer 14 side, and is located closer to the substrate 3 than that. In the wide band gap layer 122A, it was 0 cm ⁻³ (undoped).

The n-type dopant concentration in each narrow band gap layer 122B is 1 × 10 ¹⁹ cm ⁻³ in five layers of the narrow band gap layer 122B located on the MQW light emitting layer 14 side, and the narrow band located on the substrate 3 side than that. The gap layer 122B was 0 cm ⁻³ (undoped). Further, since the flow rate of TMI was adjusted so that the wavelength of light emitted from the well layer 14W by photoluminescence was 375 nm, the composition of each narrow band gap layer 122B was In _y Ga _{1 -y} N (y = 0.04). It was.

Next, the temperature of the wafer was lowered to 672 ° C. to grow the MQW light emitting layer 14. Specifically, barrier layers 14A and well layers 14W made of InGaN were alternately grown, and eight well layers 14W were grown. Each barrier layer 14A had a thickness of 4.2 nm. The n-type dopant concentration in the first barrier layer 14A ′ and the barrier layer 14A7 is 4.3 × 10 ¹⁸ cm ⁻³ , and the other barrier layers 14A6, 14A5,..., 14A1 are undoped.

Note that the thickness of the first barrier layer 14A ′ is set for the purpose of forming the narrow band gap layer 122B located closest to the MQW light emitting layer 14 in the superlattice layer 122 that is the intermediate layer, and the superlattice layer that is the intermediate layer. For the purpose of providing the function of the wide band gap layer 122A which is not included in the number of pairs 122, the barrier layer 14A7 may be thicker (for example, 5.05 nm). Further, the n-type dopant concentration in the first barrier layer 14A ′ is set to 1 × 10 ¹⁹ cm ^{−3 in} the upper part of the first barrier layer 14A ′ (a region separated from the upper surface of the first barrier layer 14A ′ by 1.55 nm). The lower portion of the first barrier layer 14A ′ (the portion other than the upper portion of the first barrier layer 14A ′) may be 4.3 × 10 ¹⁸ cm ⁻³ .

  Alternatively, the n-type dopant may be doped only in the lower portion of the barrier layer 14A7 (region separated from the lower surface of the barrier layer 14A7 by 3.5 nm), and the upper portion of the barrier layer 14A7 (portion other than the lower portion of the barrier layer 14A) may be undoped. . Thus, by making the upper part of the barrier layer 14A7 undoped, it is possible to prevent the injected carriers of the well layer 14W7 from being in direct contact with the n-type doped barrier layer part.

As the well layer 14W, an undoped In _x Ga _1-x N layer (x = 0.20) was grown using nitrogen gas as a carrier gas. The thickness of each well layer 14W was 2.7 nm. Also, the In composition x in the well layer 14W was set by adjusting the flow rate of TMI so that the wavelength of light emitted from the well layer 14W by photoluminescence was 448 nm.

  Next, the last barrier layer 14A0 (thickness: 10 nm) made of an undoped GaN layer was grown on the uppermost well layer 14W1. In the V pit evaluation structure described later, the growth is stopped at this point and the surface state is evaluated.

Next, the temperature of the wafer was raised to 1000 ° C., and a p-type Al _0.18 Ga _0.82 N layer 16, a p-type GaN layer 17 and a p-type contact layer 18 were grown on the upper surface of the last barrier layer 14A0.

In the MOCVD growth of each layer described above, TMG (trimethylgallium) is used as the Ga source gas, TMA (trimethylaluminum) is used as the Al source gas, and TMI (trimethylindium) is used as the In source gas. Used, NH ₃ was used as the N source gas. Further, SiH ₄ was used as a source gas for Si as an n-type dopant, and Cp ₂ Mg was used as a source gas for Mg as a p-type dopant. However, the source gas is not limited to the above gas, and any gas that can be used as a MOCVD source gas can be used without limitation. Specifically, TEG (triethylgallium) can be used as the Ga source gas, TEA (triethylaluminum) can be used as the Al source gas, and TEI (triethylindium) can be used as the In source gas. An organic nitrogen compound such as DMHy (dimethylhydrazine) can be used as the N source gas, and Si ₂ H ₆ or organic Si can be used as the Si source gas.

The p-type contact layer 18, the p-type GaN layer 17, the p-type AlGaN layer 16, the MQW light emitting layer 14, the superlattice layer 122, the multilayer structure 121, so that a part of the n-type nitride semiconductor layer 9 is exposed. Each part of V pit generation layer 10 and n-type nitride semiconductor layer 9 was etched. An n-side electrode 21 made of Au was formed on the upper surface of the n-type nitride semiconductor layer 9 exposed by this etching. A transparent electrode 23 made of ITO and a p-side electrode 25 made of Au were sequentially formed on the upper surface of the p-type contact layer 18. Further, a transparent protective film 27 made of SiO ₂ was formed so as to mainly cover the transparent electrode 23 and the side surfaces of each layer exposed by the etching.

  The obtained wafer was divided into chips of 380 × 420 μm size. Thereby, the nitride semiconductor light emitting device according to the first example was obtained.

  The obtained nitride semiconductor light emitting device was mounted on a TO-18 type stem, and the light output of the nitride semiconductor light emitting device was measured without resin sealing. When the nitride semiconductor light emitting device was driven at 85 mA in an environment of 25 ° C., an optical output P (25) = 101.5 mW (dominant wavelength 449 nm) was obtained at a driving voltage of 3.20 V. Further, when this nitride semiconductor light emitting device was driven at 85 mA in an environment of 80 ° C., an optical output P (80) = 98.9 mW was obtained. As a result, P (80) / P (25) = 97.4%.

  For comparison, a nitride semiconductor light emitting device (hereinafter referred to as nitridation in the first comparative example) is performed according to the same method as the nitride semiconductor light emitting device according to the first embodiment except that the multilayer structure 121 is not formed. (Referred to as a physical semiconductor device). When the nitride semiconductor device of the first comparative example was driven at 85 mA in an environment of 25 ° C., an optical output P (25) = 99.0 mW (dominant wavelength 449 nm) was obtained at a driving voltage of 3.22 V. Further, when the nitride semiconductor device in the first comparative example was driven at 85 mA in an environment of 80 ° C., an optical output P (80) = 95.5 mW was obtained. As a result, P (80) / P (25) = 96.5%. Thus, in the first example, both the light output at 25 ° C. and the light output at 80 ° C. increased compared to the first comparative example.

  In order to observe the state of the V pit 15, the inventors stopped the growth in the MQW light emitting layer 14 and stopped the p-type AlGaN layer 16, the p-type GaN layer 17, and the p-type contact as a basic experiment for reaching the present invention. A V pit evaluation structure (the V pit evaluation structure of the first embodiment) in which the layer 18 is not grown was produced, and the state of the V pit 15 was examined using this V pit evaluation structure.

  For comparison, a V pit evaluation structure (the V pit evaluation structure in the first comparative example) is performed according to the same method as the V pit evaluation structure of the first embodiment except that the multilayer structure 121 is not formed. Body). Then, the uppermost surfaces of the V pit evaluation structure of the first example and the V pit evaluation structure of the first comparative example were observed by AFM. FIG. 4A shows the AFM observation result for the top surface of the V pit evaluation structure of the first comparative example, and FIG. 4B shows the top surface of the V pit evaluation structure of the first embodiment. It is an AFM observation result. In both cases, the observation range was a range defined by a square of 1 μm in both length and width.

  As shown in FIGS. 4A and 4B, V pits are formed on both the uppermost surface of the V pit evaluation structure of the first comparative example and the uppermost surface of the V pit evaluation structure of the first embodiment. (Black dots in FIGS. 4 (a) and 4 (b)) were observed. The median diameter of the V pit in FIG. 4A was 61.3 mm, whereas the median diameter of the V pit in FIG. 4B was 93.9 mm. From this, it can be seen that the V pit diameter was significantly increased by providing the multilayer structure 121. The V pit diameter was obtained from the AFM observation result, and the median diameter of the V pit was obtained using the obtained V pit diameter.

In the first embodiment, the present inventors present the following (i) and (ii) as the formation conditions of the V pit generation layer 10. However, the present inventors have confirmed that the V pit generation layer 10 can be formed by only one of the following measures (i) and (ii). Specifically, the following (i) is as described in [V pit generation layer] in the first embodiment. The following (ii) is as described in [Nitride semiconductor light emitting device manufacturing method] in the first embodiment. (I): The n-type dopant concentration is higher than that of the n-type nitride semiconductor layer 9. Make it high. For example, the n-type dopant concentration in the n-type nitride semiconductor layer 9 is 6 × 10 ¹⁸ cm ^−3, and the n-type dopant concentration in the V pit generation layer 10 is 1 × 10 ¹⁹ cm ⁻³ (ii): n-type The growth temperature is set lower than that of the nitride semiconductor layer 9. For example, the growth temperature of n-type nitride semiconductor layer 9 is set to 1081 ° C., and the growth temperature of V pit generation layer 10 is set to 801 ° C.

  In addition, the inventors measured the V pit diameter on the upper surface of the V pit evaluation structure, and examined the positional relationship between the V pit generation layer 10 and the start point of the V pit 15 based on the measurement result. As a result, it was confirmed that the starting point of the V pit 15 does not exist in the V pit generation layer 10. This point will be described with reference to FIG.

  FIG. 5A is a graph showing the relationship between the V pit diameter Wv (nm) and the cumulative occurrence rate (%) of V pits. The structure P1 (the structure including the V pit generation layer 10 and the multilayer structure 121). (First Example)) and N (structure without the multilayer structure 121 (first comparative example)) are plotted with the V pit diameter Wv and the cumulative incidence of V pits. . In FIG. 5A, a vertical line passing through a point where the cumulative occurrence rate of V pits is 10% and a vertical line passing through a point where the occurrence rate is 90% are drawn. As shown in FIG. 5A, the V pit diameter Wv is 53 nm or more and 67 nm or less when the cumulative occurrence rate of V pits is 10% to 90% in the structure N, whereas the V pits in the structure P1. The V pit diameter Wv when the cumulative incidence was 10% to 90% was 81 nm or more and 102 nm or less. From these facts, it is understood that the V pit diameter Wv is significantly larger in the structure P1 than in the structure N.

  FIG. 5B is a graph showing the relationship between the V pit diameter Wv (nm) and the V pit depth dv (nm) based on the result shown in FIG. 5A. P1 shown in FIG. Indicates the relationship between the V pit diameter Wv (nm) and the V pit depth dv (nm) in the structure P1, and N in FIG. 5B indicates the V pit diameter Wv (nm) and the V pit depth in the structure N. The relationship with dv (nm) is shown. Using FIG. 5B, the V pit depth dv was obtained from the V pit diameter Wv. Specifically, if the vertex angle (θ shown in FIG. 5C) at the start point VS of the V pit 15 is 56 °, the V pit diameter (Wv) and the V pit depth (dv) are Wv / 2. The V pit depth dv was determined using the fact that the relationship = dv × Tan (56 ° / 2) is satisfied (described in Non-Patent Document 2). This relationship is consistent with the actual measurement values obtained by STEM.

  FIG. 5C is a sectional view showing the positional relationship between the V pit generation layer 10 and the start point VS of the V pit 15 based on the result shown in FIG. 5A, and P1 shown in FIG. V pits formed in the structure P1, and N shown in FIG. 5C is a V pit formed in the structure N. In FIG. 5C, the V pit P1 and the V pit N are illustrated as being formed on the same sample, but in reality, the V pit P1 and the V pit N are formed on the same sample. It is not formed, it is formed in separate samples. In FIG. 5C, TD is threading dislocation, θ is the vertex angle (56 °) at the V pit start point VS, and VS is the V pit start point.

In the case where the multilayer structure 121 is provided, the majority of the start points VS of the V pits P1 exist within the range represented by P1 _10-90 , that is, about 80 to 101 nm from the upper surface of the V pit generation layer 10. In other words, it exists on the substrate 3 side of the center of the superlattice layer 122 in the thickness direction. On the other hand, when the multilayer structure 121 is not provided, the majority of the start points VS of the V pits N are within the range represented by N _10-90 , that is, from 116 to from the upper surface of the V pit generation layer 10. It exists about 130 nm above. As described above, when the multilayer structure 121 is provided, the deeper V pits 15 can be formed as compared with the case where the multilayer structure 121 is not provided. Therefore, when the V pit generation layer 10 and the multilayer structure 121 are provided and the thickness of the superlattice layer 122 as an intermediate layer is 40 nm or more, the majority of the starting points VS of the V pits 15 are superlattice layers. 122 exists on the substrate 3 side from the vicinity of the center in the thickness direction. The thickness of the superlattice layer 122 is as shown in [Intermediate layer (superlattice layer)] in the first embodiment.

  The inventors presume the mechanism by which the characteristics of the nitride semiconductor light emitting device are improved when the multilayer structure 121 is provided as follows. When the V pit generation layer 10 is provided, the majority of the start points VS of the V pits 15 are closer to the substrate 3 than the center of the superlattice layer 122 in the thickness direction. The threading dislocation TD penetrating the MQW light emitting layer 14 from the substrate 3 side toward the upper surface of the MQW light emitting layer 14 is covered with V pits 15 in the light emitting layer 14 or in the undoped portion of the barrier layer 14A. When the temperature becomes high, the movement of carriers (holes or electrons) injected into the MQW light emitting layer 14 becomes active, so that the probability that the injected carriers reach the threading dislocation TD increases. However, in the nitride semiconductor light emitting device including the V pit generation layer 10, since most of the threading dislocations TD in the MQW light emitting layer 14 are covered with the V pits 15 as described above, non-radiative recombination at the threading dislocations TD occurs. It is suppressed. Therefore, the high temperature characteristics of the nitride semiconductor light emitting device are improved (a reduction in light emission efficiency at high temperatures is prevented). These characteristics are improved as the V pit generation layer 10 is separated from the MQW light emitting layer 14.

  Further, the number of barrier layers (Si undoped barrier layers) of the MQW light emitting layer 14 was changed, and the relationship between the number of barrier layers of the MQW light emitting layer 14 and the high temperature characteristics of the nitride semiconductor light emitting device was examined. The result is shown in FIG. In FIG. 6, the horizontal axis represents the number of barrier layers of the MQW light-emitting layer 14, the left vertical axis represents the luminous efficiency η at a drive current of 80 mA in an 80 ° C. environment, and the right vertical axis represents 25 ° C. The ratio (P (80) / P (25)) of the light output P (25) at 80 ° C. and the light output P (80) at 80 ° C. is taken. In FIG. 6, (Vpit) means that the V pit generation layer 10 is provided, and (ref) means that the V pit generation layer 10 is not provided.

  As shown in FIG. 6, in the structure in which the V pit generation layer 10 is provided, the barrier layer (Si undoped barrier layer) of the MQW light emitting layer 114 is compared with the structure in which the V pit generation layer 10 is not provided. It was found that the temperature characteristic P (80) / P (25) is particularly improved when the number is 4 or more and 6 or less. Further, by extrapolating the expected temperature line (the upper broken line in FIG. 6), good temperature characteristics can be obtained even when the number of barrier layers (Si undoped barrier layers) of the MQW light emitting layer 14 is 7 or more and 9 or less. Presumed to be obtained.

[Evaluation of defect rate due to ESD]
The structure of the first comparative example, that is, the Vpit evaluation structure manufactured according to the same method as that of the first example except that the multilayer structure 121 is not formed, The effect of reducing the defect rate due to ESD was verified by changing the number of undoped barrier layers. FIG. 7 shows the relationship between the emission wavelength and the defect rate due to ESD.

  As shown in FIG. 7, when the multilayer structure 121 is not formed (“121 not formed” described in FIG. 7), the ESD increases as the number of undoped barrier layers increases to 3, 4, and 6. The defect rate due to increased. However, when the multilayer structure 121 was formed (“121 formation” described in FIG. 7), even when the number of undoped barrier layers was six, the defect rate due to ESD was greatly reduced. The reason for this is that a reverse bias during ESD is applied, and at that time, a V pit is formed in a portion where the depletion layer spreads. Therefore, the threading dislocation at the center of the V pit is electrically connected to the MQW light emitting layer. This is thought to be due to separation. When the multilayer structure 121 was formed, the light output was equivalent or slightly improved, and the drive voltage was equivalent or slightly reduced compared to the case where the multilayer structure 121 was not formed.

<Second Embodiment>
FIG. 8 is an energy diagram schematically showing the magnitude of the band gap energy Eg from the n-type nitride semiconductor layer 9 to the p-type nitride semiconductor layer 16 in the nitride semiconductor light emitting device of the second embodiment. The vertical axis direction in FIG. 8 is the vertical direction of the nitride semiconductor light emitting device in this embodiment, and Eg on the horizontal axis in FIG. 8 schematically represents the magnitude of the band gap energy in each composition. In FIG. 8, the layer doped with the n-type dopant is hatched.

  In the nitride semiconductor light emitting device according to the present embodiment, the multilayer structure 221 includes a pair of an n-type GaN layer and an n-type InGaN layer formed at a temperature lower than the growth temperature of the V pit generation layer 10. Three sets of n-type GaN layers and n-type InGaN layers are provided. The nitride semiconductor light emitting device according to the present embodiment has the same configuration as the nitride semiconductor device according to the first embodiment with respect to other points. Even in this case, the same effect as that obtained by the nitride semiconductor device according to the first embodiment can be obtained.

  Below, the specific Example of this embodiment is shown. In addition, this embodiment is not limited to the Example shown below.

[V-pit evaluation structure in the second embodiment]
After forming the V pit generation layer 10 according to the method shown in the first embodiment, the wafer temperature is 801 ° C., the Si-doped InGaN having a thickness of 7 nm, the Si-doped GaN having a thickness of 30 nm, and the 7-nm thickness. Si-doped InGaN, Si-doped GaN with a thickness of 30 nm, Si-doped InGaN with a thickness of 7 nm, and Si-doped GaN with a thickness of 20 nm were alternately stacked to form a multilayer structure 221. The n-type dopant concentration in the multilayer structure 221 was set to 7 × 10 ¹⁷ cm ⁻³ in any layer. The In composition ratio of the InGaN layer was set to be the same as the In composition ratio of the narrow band gap layer constituting the intermediate layer (superlattice layer) 122 to be grown next.

  Then, the intermediate layer (superlattice layer) 122 and the MQW light emitting layer 14 were produced according to the method described in the first example. In this way, the V-pit evaluation structure of the second example was obtained.

  For comparison, a V pit evaluation structure was manufactured without preparing the multilayer structure 221 (this V pit evaluation structure is the same as the V pit evaluation structure of the first comparative example). And each uppermost surface of the V pit evaluation structure of the 2nd example and the V pit evaluation structure of the 1st comparative example was observed with AFM. FIG. 9A shows the AFM observation result for the top surface of the V pit evaluation structure of the first comparative example, and FIG. 9B shows the top surface of the V pit evaluation structure of the second embodiment. It is an AFM observation result. In both cases, the observation range was a range defined by a square of 1 μm in both length and width.

  As shown in FIGS. 9A and 9B, V pits are formed on both the top surface of the V pit evaluation structure of the first comparative example and the top surface of the V pit evaluation structure of the second embodiment. (Black dots in FIGS. 9A and 9B) were observed. The median diameter of the V pit in FIG. 9A was 61.3 mm, whereas the median diameter of the V pit in FIG. 9B was 112.1 mm. From this, it can be seen that the V pit diameter was significantly increased by providing the multilayer structure 121. The V pit diameter was obtained from the AFM observation result, and the median diameter of the V pit was obtained using the obtained V pit diameter.

  FIG. 10A is a graph showing the relationship between the V pit diameter Wv (nm) and the cumulative occurrence rate (%) of V pits. The structure P2 (the structure including the V pit generation layer 10 and the multilayer structure 221). (Second Example)) and V-pit diameter Wv and the cumulative occurrence rate of V-pits in structure N (structure not provided with multilayer structure 121 (first comparative example)) are plotted. . Further, in FIG. 10A, a vertical line passing through a point where the cumulative occurrence rate of V pits is 10% and a vertical line passing through a point where this occurrence rate is 90% are drawn. As shown in FIG. 10A, the V pit diameter Wv is 53 nm to 67 nm in the structure N when the cumulative occurrence rate of V pits is 10% to 90% in the structure N, whereas the V pits in the structure P2 When the cumulative occurrence rate was 10% to 90%, the V pit diameter Wv was 97 nm to 120 nm. From these, it can be seen that the V pit diameter Wv is significantly larger in the structure P2 than in the structure N.

  FIG. 10B is a graph showing the relationship between the V pit diameter Wv (nm) and the V pit depth dv (nm) based on the result shown in FIG. 10A, and P2 shown in FIG. Represents the relationship between the V pit diameter Wv (nm) and the V pit depth dv (nm) in the structure P2, and N in FIG. 10B represents the V pit diameter Wv (nm) and the V pit depth in the structure N. The relationship with dv (nm) is shown. In accordance with the method described in the first embodiment, the V pit depth dv was obtained from the V pit diameter Wv using FIG. 10B.

  FIG. 10C is a sectional view showing the positional relationship between the V pit generation layer 10 and the starting point VS of the V pit 15 based on the result shown in FIG. 10A, and P2 shown in FIG. V pits formed in the structure P2, and N shown in FIG. 10C is a V pit formed in the structure N. In FIG. 10C, the V pit P2 and the V pit N are illustrated as being formed on the same sample, but in reality, the V pit P2 and the V pit N are formed on the same sample. It is not formed, it is formed in separate samples. Further, TD, θ and VS in FIG. 10C are as shown in the first embodiment.

In the case where the multilayer structure 221 is provided, the majority of the start points VS of the V pits P2 exist within the range represented by P2 _10-90 , that is, about 63 to 85 nm from the upper surface of the V pit generation layer 10. In other words, it exists on the substrate 3 side of the center of the superlattice layer 122 in the thickness direction. On the other hand, when the multilayer structure 221 is not provided, the majority of the starting points VS of the V pits N are within the range represented by N _10-90 , that is, 116 to 116 from the upper surface of the V pit generation layer 10. It exists about 130 nm above. Thus, when the multilayer structure 221 is provided, the deeper V pit 15 can be formed compared with the case where the multilayer structure 221 is not provided. Therefore, when the V pit generation layer 10 and the multilayer structure 221 are provided and the thickness of the superlattice layer 122 as an intermediate layer is 40 nm or more, the majority of the starting points VS of the V pits 15 are superlattice layers. 122 exists on the substrate 3 side from the vicinity of the center in the thickness direction. Further, since the thickness of the multilayer structure 221 is thicker than the thickness of the multilayer structure 121 of the first embodiment, the majority of the starting points VS of the V pits P2 are closer to the substrate 3 than the first embodiment. Will exist. The thickness of the superlattice layer 122 is as shown in [Intermediate layer (superlattice layer)] in the first embodiment.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  DESCRIPTION OF SYMBOLS 1 Nitride semiconductor light-emitting device, 3 board | substrate, 3A convex part, 3B recessed part, 5 buffer layer, 7 Underlayer, 8 n-type nitride semiconductor layer, 9 n-type nitride semiconductor layer, 10 V pit generating layer, 14 MQW light emission Layer, 14A barrier layer, 14W well layer, 15 V pit, 16 p-type nitride semiconductor layer, 17 p-type nitride semiconductor layer, 18 p-type nitride semiconductor layer, 21 n-side electrode, 23 transparent electrode, 25 p-side Electrode, 27 Transparent protective film, 30 mesa portion, 121,221 multilayer structure, 122 superlattice layer, 122A wide band gap layer, 122B narrow band gap layer.

Claims (17)

A nitride semiconductor light emitting device in which a substrate, an n-type nitride semiconductor layer, a V pit generation layer, an intermediate layer, a multiple quantum well light emitting layer, and a p type nitride semiconductor layer are provided in this order. And
The substrate is composed of a sapphire substrate having an uneven shape on the upper surface,
The multiple quantum well light emitting layer is a layer formed by alternately laminating a barrier layer and a well layer having a smaller band gap energy than the barrier layer,
In the multiple quantum well light emitting layer, V pits are partially formed,
Between the V pit generation layer and the intermediate layer is provided a multilayer structure in which a plurality of nitride semiconductor layers having different band gap energies are laminated,
The multilayer structure is formed by alternately laminating nitride semiconductor layers having relatively small band gap energy and nitride semiconductor layers having relatively large band gap energy,
A nitride semiconductor layer having a relatively small band gap energy and a nitride semiconductor layer having a relatively large band gap energy are provided in this order in contact with the V pit generation layer,
The average position of the starting point of the V pit is in the intermediate layer, and is located closer to the V pit generation layer than near the center in the thickness direction of the intermediate layer,
The nitride semiconductor light emitting element whose n-type dopant density | concentration of the said V pit generation | occurrence | production layer is 5 * 10 < ¹⁸ > cm < ^-3 > or more. The multilayer structure includes an Al _i1 Ga _j1 In _(1-i1-j1) N (0 ≦ i1 <1, 0 <j1 ≦ 1) layer and an Al _i2 Ga _j2 In _(1-i2-j2) N (0 ≦ i2 <1,0 ≦ j2 <1, j1 <j2) nitride according the to claim 1 formed by alternately stacking layers semiconductor light-emitting device. 2. The nitride semiconductor light emitting device according to claim 1 , wherein the multilayer structure is formed by alternately laminating Ga _j3 In _(1-j3) N (0 <j3 <1) layers and GaN layers. Each of the nitride semiconductor layers constituting the multilayer structure includes an n-type impurity,
The n-type dopant concentration in the nitride semiconductor layer constituting the multilayer structure are both nitride semiconductor light-emitting device according to any one of the V pit generation 1 lower claim than the n-type dopant concentration in the layer 3 . 5. The nitride semiconductor light-emitting element according to claim 4 , wherein the n-type dopant concentration in the nitride semiconductor layer constituting the multilayer structure is 7 × 10 ¹⁷ cm ⁻³ or less. Wherein the plurality of nitride semiconductor layers having different band gap energies, nitride semiconductor light emitting device according to any one of claims 1 to 3 which is an undoped layer. A second multilayer structure is further provided between the n-type nitride semiconductor layer and the V pit generation layer,
The nitride according to any one of claims 1 to 6 , wherein the second multilayer structure is formed by alternately laminating doped layers and undoped layers having a dopant concentration equal to the dopant concentration in the V pit generation layer. Semiconductor light emitting device. In the multilayer structure, when the nitride semiconductor layer having a relatively small band gap energy and the nitride semiconductor layer having a relatively large band gap energy are taken as one set, the multilayer structure has two or more sets of the band gap energy. the nitride semiconductor light emitting device according to any one of claims 1 to 7 but relatively small nitride semiconductor layer and said band gap energy has a relatively large nitride semiconductor layer. In the multilayer structure, the thickness of the nitride semiconductor layer having a relatively small band gap energy is not less than 1/5 times and not more than 1/2 times the thickness of the nitride semiconductor layer having a relatively large band gap energy. The nitride semiconductor light emitting device according to any one of claims 1 to 8 . The intermediate layer, according to any one of claims 1 to 9 which is a superlattice layer formed by laminating a smaller narrow bandgap layer band gap energy alternately than the wide band gap layer and the wide band gap layer Nitride semiconductor light emitting device. The narrow band gap layer constituting the superlattice layer includes In in its composition,
11. The nitride according to claim 10 , wherein an In composition ratio in the narrow band gap layer is the same as an In composition ratio in a Ga _j3 In _(1-j3) N (0 <j3 <1) layer constituting the multilayer structure. Semiconductor light emitting device. Among the wide band gap layer and the narrow band gap layer constituting the superlattice layer,
At least two layers located on the multiple quantum well light emitting layer side include an n-type dopant,
The nitride semiconductor light emitting device according to claim 10 or 11 , wherein at least two layers located on the V pit generation layer side are undoped. When the wide band gap layer and the narrow band gap layer are set as one set, the superlattice layer has 20 sets or more of the wide band gap layer and the narrow band gap layer,
13. The nitride semiconductor light emitting device according to claim 12 , wherein the five sets of the wide band gap layer and the narrow band gap layer located on the multiple quantum well light emitting layer side include an n-type dopant. A substrate, an n-type nitride semiconductor layer, a V pit generation layer having an n-type dopant concentration of 5 × 10 ¹⁸ cm ⁻³ or more, an intermediate layer, a multiple quantum well light emitting layer, a p-type nitride semiconductor layer, Is a method of manufacturing a nitride semiconductor light emitting device provided in this order,
Forming the n-type nitride semiconductor layer at a first growth temperature on a sapphire substrate having an uneven shape on an upper surface ;
Forming the V pit generation layer on the n-type nitride semiconductor layer at a second growth temperature lower than the first growth temperature;
On the V pit generation layer, a nitride semiconductor layer having a relatively small band gap energy at a third growth temperature lower than the second growth temperature, and a nitride semiconductor layer having a relatively large band gap energy, A step of forming a multilayer structure in which a plurality is provided in this order ;
Forming the intermediate layer on the multilayer structure at a fourth growth temperature lower than the third growth temperature;
Forming the multi-quantum well light-emitting layer and the p-type nitride semiconductor layer in order on the intermediate layer. The method for manufacturing a nitride semiconductor light-emitting element according to claim 14 , wherein the second growth temperature is lower by 50 ° C. or more than the first growth temperature. The third growth temperature for fabrication of a nitride semiconductor light emitting device according to claim 14 or 15 is 600 ° C. or higher 900 ° C. or less. The method for manufacturing a nitride semiconductor light emitting element according to any one of claims 14 to 16 , wherein the second, third and fourth growth temperatures are the same.