JP7281976B2 - semiconductor light emitting device - Google Patents

Description

The present invention relates to a semiconductor light emitting device.

Patent Document 1 discloses a semiconductor light emitting element as an example of a semiconductor light emitting device. This semiconductor light emitting device includes a sapphire substrate, a lower GaN clad layer formed on the sapphire substrate, a GaN/InGaN-MQW layer formed on the lower GaN clad layer, and a GaN/InGaN-MQW layer formed on the GaN/InGaN-MQW layer. including a formed upper GaN cladding layer.

JP-A-2001-257379

One embodiment of the present invention provides a semiconductor light emitting device capable of suppressing fluctuations in emission wavelength caused by fluctuations in current.

An embodiment of the present invention includes a first semiconductor layer of a first conductivity type, a first well layer containing In _X Ga _(1−X) N having an In composition ratio X (0<X<1), and first barrier layers containing GaN doped with first conductivity type impurities are alternately stacked, and the pair of first well layers and first barrier layers have a stacked structure having a first total thickness; a first MQW structure formed on the first semiconductor layer; and a second well including In _Y Ga _(1−Y) N having an In composition ratio Y exceeding the In composition ratio X (X<Y≦1). and a second barrier layer comprising undoped GaN are alternately stacked, and the paired second well layer and the second barrier layer have a second total thickness less than the first total thickness. a second MQW structure formed on the first MQW structure; and a second conductivity type second semiconductor layer formed on the second MQW structure. offer.

According to this semiconductor light-emitting device, it is possible to suppress fluctuations in emission wavelength caused by fluctuations in current.

FIG. 1 is a plan view showing a semiconductor light emitting device according to a first embodiment of the invention. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. FIG. 3 is a cross-sectional view taken along line III-III shown in FIG. FIG. 4 is a cross-sectional view schematically showing the structure of the active layer. FIG. 5 is an enlarged view of a recess formed on the main surface of the second MQW structure. FIG. 6 is a schematic perspective view for explaining recesses formed on the main surface of the second MQW structure. 7 is an enlarged plan view of the barrier electrode of the n-side electrode shown in FIG. 1. FIG. 8 is an enlarged plan view of the barrier electrode of the p-side electrode shown in FIG. 1. FIG. FIG. 9 is a graph obtained by actual measurement of the relationship between the emission wavelength and the forward current. FIG. 10 is a graph obtained by actual measurement of the relationship between the maximum amount of change in emission wavelength and the thickness of the second barrier layer. FIG. 11 is an enlarged view of a region corresponding to FIG. 5, and is an enlarged view partially showing the semiconductor light emitting device according to the second embodiment of the present invention. FIG. 12 is an enlarged view of a region corresponding to FIG. 5, and is an enlarged view partially showing the semiconductor light emitting device according to the third embodiment of the present invention. FIG. 13 is a cross-sectional view of a region corresponding to FIG. 3, showing a semiconductor light-emitting device according to a fourth embodiment of the present invention. FIG. 14 is a sectional view of a region corresponding to FIG. 3, showing a semiconductor light emitting device according to a fifth embodiment of the present invention.

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
FIG. 1 is a plan view showing a semiconductor light emitting device 1 according to a first embodiment of the invention. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. FIG. 3 is a cross-sectional view taken along line III-III shown in FIG. FIG. 4 is a cross-sectional view schematically showing the structure of the light emitting layer 23. As shown in FIG.
FIG. 5 is an enlarged view of the recess 41 formed in the major surface 42 of the second MQW structure 32. As shown in FIG. FIG. 6 is a schematic perspective view for explaining the recess 41 formed in the main surface 42 of the second MQW structure 32. FIG. FIG. 7 is an enlarged plan view of the barrier electrode 75 of the n-side electrode 61 shown in FIG. FIG. 8 is an enlarged plan view of the barrier electrode 95 of the p-side electrode 81 shown in FIG.

1 to 3, a semiconductor light emitting device 1 includes a chip body 2. As shown in FIG. The chip body 2 has a first chip main surface 3 on one side, a second chip main surface 4 on the other side, and chip side surfaces 5A, 5B, 5C connecting the first chip main surface 3 and the second chip main surface 4. , 5D. Chip side surfaces 5A to 5D more specifically include a first chip side surface 5A, a second chip side surface 5B, a third chip side surface 5C and a fourth chip side surface 5D. The first chip main surface 3 and the second chip main surface 4 are formed in a quadrangular shape when viewed from above in the normal direction N (hereinafter simply referred to as "plan view").

The first chip side surface 5A and the second chip side surface 5B extend along the first direction A in plan view and face each other in a second direction B intersecting the first direction A. As shown in FIG. The third chip side surface 5C and the fourth chip side surface 5D extend along the second direction B and face each other in the first direction A in plan view. The second direction B is, more specifically, orthogonal to the first direction A. The chip side surfaces 5A to 5D extend two-dimensionally along the normal direction N. As shown in FIG.

More specifically, chip body 2 has a laminated structure including substrate 6 and semiconductor light emitting layer 7 . The substrate 6 forms part of the second chip main surface 4 of the chip body 2 and chip side surfaces 5A to 5D. The semiconductor light emitting layer 7 forms part of the first chip main surface 3 and chip side surfaces 5A to 5D of the chip body 2 .
The substrate 6 has a first substrate main surface 8 on one side, a second substrate main surface 9 on the other side, and substrate side surfaces 10A, 10B, 10C connecting the first substrate main surface 8 and the second substrate main surface 9, respectively. including 10D. The substrate side surfaces 10A-10D more specifically include a first substrate side surface 10A, a second substrate side surface 10B, a third substrate side surface 10C and a fourth substrate side surface 10D.

The first substrate main surface 8 and the second substrate main surface 9 are formed in a square shape in plan view. The second substrate main surface 9 forms the second chip main surface 4 . The substrate side surfaces 10A to 10D form part of the chip side surfaces 5A to 5D of the chip body 2, respectively.
The substrate 6 consists of a light transmissive substrate. In this embodiment, the substrate 6 is made of an impurity-free hexagonal crystal substrate as an example of a light-transmissive substrate. The hexagonal substrate may be a sapphire substrate, GaN substrate, ZnO substrate, AlN substrate or SiC substrate. The substrate 6 consists of a sapphire substrate in this embodiment.

The first substrate main surface 8 of the substrate 6 may have an off-angle inclined at an angle of 0.1° or more and 1° or less in the m-axis direction with respect to the c-plane of the hexagonal crystal. The off angle in the m-axis direction is also the angle between the normal direction N of the first substrate main surface 8 and the c-axis of the hexagonal crystal. The off angle in the m-axis direction is 0.1° or more and 0.2° or less, 0.2° or more and 0.4° or less, 0.4° or more and 0.6° or less, 0.6° or more and 0.8°. or less, or 0.8° or more and 1° or less.

The off angle in the m-axis direction is preferably 0.2° or more and 0.5° or less. More preferably, the off angle in the m-axis direction is 0.3° or more and 0.4° or less. The off angle of the a-axis direction with respect to the c-plane on the first substrate main surface 8 is preferably 0°.
The thickness of the substrate 6 may be 50 μm or more and 350 μm or less. The thickness of the substrate 6 may be 50 μm to 100 μm, 100 μm to 150 μm, 150 μm to 200 μm, 200 μm to 250 μm, 250 μm to 300 μm, or 300 μm to 350 μm.

On the first substrate main surface 8 of the substrate 6, in this embodiment, an uneven structure 11 is formed. The uneven structure 11 diffusely reflects the light generated in the semiconductor light emitting layer 7 toward the first chip main surface 3 of the chip body 2 . As a result, the extraction efficiency of light generated in the semiconductor light emitting layer 7 is enhanced.
The uneven structure 11 includes a plurality of protrusions 12 that form unevenness with respect to the first substrate main surface 8 of the substrate 6 in this embodiment. The plurality of protruding portions 12 are arranged on the first substrate main surface 8 at intervals. The plurality of protrusions 12 may be arranged in a matrix or in a zigzag pattern in plan view. The plurality of protrusions 12 are formed in a frustum shape, a dome shape, or a hemispherical shape. The plurality of protrusions 12 may be formed in a truncated cone shape or n (n≧3) truncated pyramid shape as an example of the truncated pyramid shape.

The multiple protrusions 12 each include an insulator in this embodiment. The plurality of protrusions 12 may each contain silicon oxide or silicon nitride as an example of an insulator. The multiple protrusions 12 are made of silicon nitride in this embodiment.
The semiconductor light emitting layer 7 is laminated on the first substrate main surface 8 of the substrate 6 . In this embodiment, the semiconductor light emitting layer 7 generates light having a dominant wavelength WL (emission wavelength) in the range of 480 nm to 550 nm. More specifically, the dominant wavelength WL of the semiconductor light emitting layer 7 is 480 nm or more and 510 nm or less. That is, the semiconductor light emitting layer 7 generates light in the blue-green region. Turquoise blue, cyan blue, and the like are examples of light colors in the blue-green region. Light generated by the semiconductor light emitting layer 7 is extracted from the first chip main surface 3 of the chip body 2 .

The semiconductor light emitting layer 7 includes a semiconductor main surface 13 and semiconductor side surfaces 14A, 14B, 14C and 14D. Semiconductor sides 14A-14D more specifically include first semiconductor side 14A, second semiconductor side 14B, third semiconductor side 14C and fourth semiconductor side 14D.
The semiconductor main surface 13 is formed in a square shape in plan view. The semiconductor main surface 13 is a light extraction surface. The semiconductor main surface 13 forms the first chip main surface 3 . The semiconductor side surfaces 14A-14D are continuous with the substrate side surfaces 10A-10D. The semiconductor side surfaces 14A-14D are formed flush with the substrate side surfaces 10A-10D. The semiconductor side surfaces 14A to 14D form part of the chip side surfaces 5A to 5D of the chip body 2, respectively.

The semiconductor light emitting layer 7 consists of a group III nitride semiconductor layer. The semiconductor light emitting layer 7 is formed on the first substrate main surface 8 of the substrate 6 by epitaxial growth. Therefore, the crystal plane (semiconductor main surface 13 ) of the semiconductor light emitting layer 7 matches the crystal plane of the first substrate main surface 8 .
The semiconductor light-emitting layer 7 has a laminated structure including a buffer layer 21, an n-type semiconductor layer 22, a light-emitting layer 23, and a p-type semiconductor layer 24 which are laminated in this order from the first substrate main surface 8 side of the substrate 6. . The light emitting layer 23 is heterojunction with the n-type semiconductor layer 22 . The p-type semiconductor layer 24 is heterojunction with the light emitting layer 23 . Thus, a double heterostructure including the n-type semiconductor layer 22, the light emitting layer 23, and the p-type semiconductor layer 24 is formed.

When a forward voltage VF is applied between the n-type semiconductor layer 22 and the p-type semiconductor layer 24 , electrons are supplied from the n-type semiconductor layer 22 to the light-emitting layer 23 and forward from the p-type semiconductor layer 24 to the light-emitting layer 23 . A hole is provided. The electrons and holes supplied to the light emitting layer 23 combine in the light emitting layer 23 . Thereby, light is generated in the light emitting layer 23 .
The buffer layer 21 contains undoped GaN. A plurality of protrusions 12 are covered on the first substrate main surface 8 of the substrate 6 . The thickness of the buffer layer 21 may be 0.1 μm or more and 5 μm or less. The thickness of the buffer layer 21 is 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, or It may be 4 μm or more and 5 μm or less.

The buffer layer 21 contains a plurality of holes 25 in this form. A plurality of holes 25 are formed on the tops of the plurality of protrusions 12, respectively. The plurality of holes 25 are formed starting from the plurality of protrusions 12 , and are formed in a one-to-one correspondence with the tops of the plurality of protrusions 12 . The plurality of holes 25 are formed in a line shape extending along the normal direction N from the tops of the plurality of projecting portions 12 toward the semiconductor main surface 13 in a cross-sectional view.

Buffer layer 21 includes a plurality of (two or more) buffer layers laminated on first substrate main surface 8 of substrate 6 in this embodiment. The number of laminations of the buffer layer is arbitrary, and is not limited to a specific number of laminations. In this embodiment, the buffer layer 21 includes a first buffer layer 26, a second buffer layer 27 and a third buffer layer 28 laminated in this order from the first substrate main surface 8 side. The first buffer layer 26, the second buffer layer 27 and the third buffer layer 28 each contain undoped GaN.

The first buffer layer 26 covers the first substrate major surface 8 of the substrate 6 . The first buffer layer 26 contains GaN crystal-grown in the form of a film on the first substrate main surface 8 . The first buffer layer 26 is formed in a region on the first substrate main surface 8 side of the substrate 6 with respect to the tops of the plurality of protrusions 12 .
A second buffer layer 27 is formed on the first buffer layer 26 . The second buffer layer 27 contains GaN crystal-grown three-dimensionally on the first buffer layer 26 . The second buffer layer 27 is tapered from the first buffer layer 26 toward the semiconductor main surface 13 . The second buffer layer 27 has a base and a top.

The base of the second buffer layer 27 is positioned on the first substrate main surface 8 side of the substrate 6 with respect to the tops of the plurality of protrusions 12 . The top of the second buffer layer 27 protrudes toward the semiconductor main surface 13 with respect to the tops of the protrusions 12 . The second buffer layer 27 is formed so as to expose at least the tops of the plurality of protrusions 12 . The second buffer layer 27 exposes a portion of the tops and sidewalls of the plurality of protrusions 12 in this form.

A third buffer layer 28 is formed on the second buffer layer 27 . The third buffer layer 28 contains GaN crystal-grown two-dimensionally on the second buffer layer 27 . A third buffer layer 28 covers the second buffer layer 27 and the plurality of protrusions 12 . The third buffer layer 28 partitions a plurality of holes 25 with the tops of the plurality of protrusions 12 .
The n-type semiconductor layer 22 is formed on the buffer layer 21 . The n-type semiconductor layer 22 has a laminated structure including an n-type contact layer 29 and an n-type clad layer 30 in this embodiment.

The n-type contact layer 29 comprises, in this form, GaN doped with n-type impurities. The n-type contact layer 29 may contain silicon as an example of n-type impurities. The n-type impurity concentration of the n-type contact layer 29 may be 5×10 ¹⁷ cm ⁻³ or more and 5×10 ¹⁹ cm ⁻³ or less. The n-type impurity concentration of the n-type contact layer 29 is approximately 5×10 ¹⁸ cm ⁻³ in this embodiment.

The thickness of the n-type contact layer 29 may be 0.1 μm or more and 10 μm or less. The thickness of the n-type contact layer 29 may be 0.1 μm to 1 μm, 1 μm to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, or 8 μm to 10 μm.
The n-type cladding layer 30 includes GaN doped with n-type impurities in this form. The n-type cladding layer 30 may contain silicon as an example of n-type impurities. The n-type impurity concentration of the n-type cladding layer 30 may be equal to or lower than the n-type impurity concentration of the n-type contact layer 29 . The n-type impurity concentration of the n-type cladding layer 30 is preferably less than the n-type impurity concentration of the n-type contact layer 29 . The n-type impurity concentration of the n-type cladding layer 30 may be 5×10 ¹⁷ cm ⁻³ or more and 5×10 ¹⁹ cm ⁻³ or less. The n-type impurity concentration of the n-type cladding layer 30 is approximately 3×10 ¹⁸ cm ⁻³ in this embodiment.

The thickness of the n-type cladding layer 30 may be 50 nm or more and 500 nm or less. The thickness of the n-type clad layer 30 is 50 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or less, 200 nm or more and 250 nm or less, 250 nm or more and 300 nm or less, 300 nm or more and 350 nm or less, 350 nm or more and 400 nm or less, 400 nm or more and 450 nm or less. Alternatively, it may be 450 nm or more and 500 nm or less. The thickness of the n-type cladding layer 30 is approximately 200 nm in this embodiment.

2 to 4, light emitting layer 23 is formed on n-type semiconductor layer 22. As shown in FIG. The light emitting layer 23 has a multiple quantum well structure in which a plurality of well layers and a plurality of barrier layers are alternately laminated. Hereinafter, the multiple quantum well structure is simply referred to as "MQW (Multiple Quantum Well) structure". Light-emitting layer 23 more specifically includes first MQW structure 31 , second MQW structure 32 and buffer MQW structure 33 .

A first MQW structure 31 is formed on the n-type semiconductor layer 22 . The first MQW structure 31 has a laminated structure in which first well layers 34 and first barrier layers 35 are alternately laminated. The first MQW structure 31 includes four first well layers 34 and five first barrier layers 35 in this form. The bottom and top layers of the first MQW structure 31 are each formed in this form by a first barrier layer 35 .

The number and order of lamination of the first well layers 34 and the first barrier layers 35 are arbitrary. Therefore, the bottom layer and/or top layer of the first MQW structure 31 may be formed by the first well layer 34 . The first well layers 34 and the first barrier layers 35 may be alternately laminated with a period of 2 or more and 10 or less, for example.
The first well layer 34 contains impurity-free In _X Ga _(1−X) N having an In composition ratio X (0<X<1). The first well layer 34 is formed as a blue light emitting layer that generates blue light having a peak emission wavelength in the range of 410 nm or more and less than 480 nm.

The In composition ratio X may be 0.01 or more and 0.2 or less. In composition ratio X is 0.01 or more and 0.025 or less, 0.025 or more and 0.05 or less, 0.05 or more and 0.075 or less, 0.075 or more and 0.1 or less, 0.1 or more and 0.125 or less , 0.125 to 0.15, 0.15 to 0.175, or 0.175 to 0.2. The In composition ratio X is preferably 0.04 or more and 0.18 or less.

The plurality of first well layers 34 may have the same In composition ratio X, or may have the In composition ratio X different from each other. That the In composition ratios X are equal to each other means that the plurality of first well layers 34 are formed under the condition that the In composition ratios X are equal. An error of about ±10% may occur between the In composition ratios X.
In this embodiment, the plurality of first well layers 34 are stacked such that the In composition ratio X gradually increases in the direction away from the n-type semiconductor layer 22 . The plurality of first well layers 34 are preferably stacked in such a manner that the In composition ratio X gradually increases at a constant rate. As an example, the plurality of first well layers 34 have an In composition ratio X of 0.04, 0.08, 0.12, 0 from the bottom first well layer 34 to the top first well layer 34 . 0.16 may be stacked.

The first barrier layer 35 includes GaN doped with n-type impurities. The first barrier layer 35 may contain silicon as an example of n-type impurities. The impurity concentration of the first barrier layer 35 may be 5×10 ¹⁶ cm ⁻³ or more and 5×10 ²⁰ cm ⁻³ or less.
The first barrier layer 35 captures holes supplied from the p-type semiconductor layer 24 by n-type impurities. As a result, the number of holes supplied to the first well layer 34 is reduced, thereby suppressing the generation of light in the first well layer 34 . The peak emission wavelength of light generated in the first well layer 34 is weak (noise level). The blue light generated in the first well layer 34 hardly contributes to the dominant wavelength WL (light color) of light extracted from the semiconductor light emitting layer 7 .

That is, the first MQW structure 31 has an inactive structure in which light generation in the first well layer 34 is suppressed by the n-type impurities of the first barrier layer 35 . The first MQW structure 31 is formed as a stress relaxation structure that suppresses changes in lattice size caused by indium.
One first well layer 34 and one first barrier layer 35 paired in the stacking direction have a first total thickness T1. The first total thickness T1 is the sum of the thickness TW1 of the first well layer 34 and the thickness TB1 of the first barrier layer 35 (T1=TW1+TB1).

The thickness TW1 of the first well layer 34 may be 2 nm or more and 4 nm or less. The thickness TW1 may be 2 nm or more and 2.5 nm or less, 2.5 nm or more and 3 nm or less, 3 nm or more and 3.5 nm or less, or 3.5 nm or more and 4 nm or less. The thickness TW1 is preferably 2.5 nm or more and 3.5 nm or less.
The multiple first well layers 34 may have the same thickness TW1, or may have different thicknesses TW1. The plurality of first well layers 34 are preferably formed with the same thickness TW1. That the thicknesses TW1 are equal to each other means that the plurality of first well layers 34 are formed under the condition that the thicknesses TW1 are equal. An error of about ±10% may occur between the thicknesses TW1.

The thickness TB1 of the first barrier layer 35 exceeds the thickness TW1 of the first well layer 34 (TW1<TB1). The thickness TB1 may be 5 nm or more and 20 nm or less. The thickness TB1 is 5 nm or more and 7.5 nm or less, 7.5 nm or more and 10 nm or less, 10 nm or more and 12.5 nm or less, 12.5 nm or more and 15 nm or less, 15 nm or more and 17.5 nm or less, or 17.5 nm or more and 20 nm or less. may The thickness TB1 is preferably 8 nm or more and 16 nm or less.

The multiple first barrier layers 35 may have the same thickness TB1, or may have different thicknesses TB1. That the thicknesses TB1 are equal to each other means that the plurality of first barrier layers 35 are formed under the condition that the thicknesses TB1 are equal. An error of about ±10% may occur between the thicknesses TB1.
The plurality of first barrier layers 35 are formed such that the thickness TB1 of the uppermost first barrier layer 35 is less than the thickness TB1 of the other first barrier layers 35 in this embodiment. The thickness TB1 of the uppermost first barrier layer 35 is approximately 10 nm in this embodiment. The thickness TB1 of the other first barrier layer 35 is approximately 15 nm in this embodiment. Such a structure is effective in relieving stress in the light emitting layer 23 in relation to the second MQW structure 32 .

A second MQW structure 32 is formed on the first MQW structure 31 . The second MQW structure 32 has a laminated structure in which second well layers 36 and second barrier layers 37 are alternately laminated. The second MQW structure 32 includes three second well layers 36 and two second barrier layers 37 in this form. The bottom layer of the second MQW structure 32 is formed by a second well layer 36 in this embodiment. The second MQW structure 32 includes a top barrier layer 38 that forms the top layer of the second MQW structure 32 in this form.

The number and order of lamination of the second well layers 36 and the second barrier layers 37 are arbitrary. Therefore, the bottom layer of the second MQW structure 32 may be formed by the second barrier layer 37 . Also, the top layer of the second MQW structure 32 may be formed by a second well layer 36 . The second well layers 36 and the second barrier layers 37 may be alternately laminated with a period of 2 or more and 10 or less, for example. However, the number of layers of the second well layers 36 and the second barrier layers 37 is preferably less than the number of layers of the first well layers 34 and the first barrier layers 35 .

The second well layer 36 contains impurity-free In _Y Ga _(1−Y) 3 having an In composition ratio Y (X<Y≦1) exceeding the In composition ratio X of the first well layer 34 . The second well layer 36 is formed as a blue-green light-emitting layer that generates blue-green light having a peak emission wavelength in the range of 480 nm to 550 nm. More specifically, the peak emission wavelength of the second well layer 36 is 480 nm or more and 510 nm or less. The blue-green light generated in the first well layer 34 contributes to the dominant wavelength WL (light color) of light extracted from the semiconductor light emitting layer 7 .

The In composition ratio Y may be 0.1 or more and 0.3 or less. In composition ratio Y is 0.1 or more and 0.125 or less, 0.125 or more and 0.15 or less, 0.15 or more and 0.175 or less, 0.175 or more and 0.2 or less, 0.2 or more and 0.225 or less. , 0.225 to 0.25, 0.25 to 0.275, or 0.275 to 0.3. The In composition ratio Y is preferably 0.15 or more and 0.25 or less.

The plurality of second well layers 36 are laminated in such a manner that the In composition ratio Y is constant. Thereby, variations in the peak emission wavelength of the second well layer 36 can be appropriately suppressed. As an example, the plurality of second well layers 36 may be stacked such that the In composition ratio Y of all of them is 0.18.
That the In composition ratio Y is constant means that the plurality of second well layers 36 are formed under the condition that the In composition ratio Y is constant. An error of about ±10% may occur between the In composition ratios Y. The error of the In composition ratio Y is preferably ±5% or less.

The plurality of second well layers 36 may have In composition ratios Y different from each other. However, in this case, it should be noted that the peak emission wavelengths of the plurality of second well layers 36 vary. The plurality of second well layers 36 may be stacked such that the In composition ratio Y gradually increases in the direction away from the first MQW structure 31 .
In this case, the plurality of second well layers 36 may be stacked such that the In composition ratio Y gradually increases at a constant rate. As an example, the plurality of second well layers 36 have an In composition ratio Y of 0.18, 0.2, and 0.22 from the bottom second well layer 36 to the top second well layer 36. It may be laminated as follows.

The second barrier layer 37 includes undoped GaN. The second barrier layer 37 allows holes supplied from the p-type semiconductor layer 24 to pass therethrough. As a result, consumption (capture) of holes in the second barrier layer 37 is suppressed, so that light is efficiently generated in the second well layer 36 . Therefore, the second MQW structure 32 has an active structure that produces light in the second well layer 36 .

The second barrier layer 37 has an In composition ratio Y exceeding the In composition ratio X of the first barrier layer 35 of the first MQW structure 31 . Therefore, when the second MQW structure 32 is formed directly on the n-type semiconductor layer 22, the stress in the light emitting layer 23 increases due to the abrupt change in lattice size. A stress generated in the second MQW structure 32 is relaxed by the first MQW structure 31 .

One second well layer 36 and one second barrier layer 37 paired in the stacking direction have a second total thickness T2. The second total thickness T2 is the sum of the thickness TW2 of the second well layer 36 and the thickness TB2 of the second barrier layer 37 (T2=TW2+TB2). The second total thickness T2 is less than the first total thickness T1 of the first MQW structure 31 (T2<T1).
The thickness TW2 of the second well layer 36 is less than the thickness TW1 of the first well layer 34 (TW2<TB1). The thickness TW2 may be 1 nm or more and 2 nm or less. The thickness TW2 may be 1 nm or more and 1.25 nm or less, 1.25 nm or more and 1.5 nm or less, 1.5 nm or more and 1.75 nm or less, or 1.75 nm or more and 2 nm or less. The thickness TW2 is preferably 1.5 nm or more and 2 nm or less. The thickness TW2 is preferably less than 2 nm.

The multiple second well layers 36 may have the same thickness TW2, or may have different thicknesses TW2. The plurality of second barrier layers 37 are preferably formed with the same thickness TW2. That the thicknesses TW2 are equal to each other means that the plurality of second well layers 36 are formed under the condition that the thicknesses TW2 are equal. An error of about ±10% may occur between the thicknesses TW2.

The thickness TB2 of the second barrier layer 37 exceeds the thickness TW2 of the second well layer 36 (TW2<TB2). The thickness TB2 of the second barrier layer 37 is less than the thickness TB1 of the first barrier layer 35 (TB2<TB1). The thickness TB2 of the second barrier layer 37 is preferably less than or equal to half the thickness TB1 of the first barrier layer 35 (TB2<TB1/2).
The thickness TB2 may be 3 nm or more and 6 nm or less. The thickness TB2 is 3 nm or more and 3.5 nm or less, 3.5 nm or more and 4 nm or less, 4 nm or more and 4.5 nm or less, or 4.5 nm or more and 5 nm or less, 5 nm or more and 5.5 nm or less, or 5.5 nm or more and 6 nm or less. may be The thickness TB2 is preferably 4 nm or more and 5 nm or less. Thickness TB2 is preferably less than 5 nm.

The multiple second barrier layers 37 may have the same thickness TB2, or may have different thicknesses TB2. That the thicknesses TB2 are equal to each other means that the plurality of second barrier layers 37 are formed under the condition that the thicknesses TB2 are equal. An error of about ±10% may occur between the thicknesses TB2.
The top barrier layer 38 is formed in the same manner as the second barrier layer 37 except that it has a thickness TBtop different from the thickness TB2 of the second barrier layer 37 . The thickness TBtop of the top barrier layer 38 exceeds the thickness TB2 of the second barrier layer 37 (TB2<TBtop). The top layer of the second MQW structure 32 may be formed by a second barrier layer 37 instead of the top barrier layer 38 .

A buffer MQW structure 33 is interposed in the region between the first MQW structure 31 and the second MQW structure 32 . The buffer MQW structure 33 has a laminated structure in which a buffer well layer 39 and a buffer barrier layer 40 are laminated.
Buffer MQW structure 33 includes one buffer well layer 39 and one buffer barrier layer 40 in this form. The bottom layer of the buffer MQW structure 33 is formed by a buffer well layer 39 in this form. The top layer of the buffer MQW structure 33 is formed by a buffer barrier layer 40 in this form.

The number of stacks of buffer well layers 39 and buffer barrier layers 40 is arbitrary. The buffer well layers 39 and the buffer barrier layers 40 may be alternately laminated with a period of 2 or more and 10 or less, for example. The stacking order of the buffer well layers 39 and the buffer barrier layers 40 is adjusted according to the top layer of the first MQW structure 31 and the bottom layer of the second MQW structure 32 .
When the top layer of the first MQW structure 31 is formed by the first well layer 34 , the bottom layer of the buffer MQW structure 33 is formed by the buffer barrier layer 40 . When the top layer of the first MQW structure 31 is formed by the first barrier layer 35 , the bottom layer of the buffer MQW structure 33 is formed by the buffer well layer 39 .

When the bottom layer of the second MQW structure 32 is formed by the second well layer 36 , the top layer of the buffer MQW structure 33 is formed by the buffer barrier layer 40 . When the bottom layer of the first MQW structure 31 is formed by the second barrier layer 37 , the top layer of the buffer MQW structure 33 is formed by the buffer well layer 39 .
The buffer well layer 39 contains impurity-free In _Z Ga _(1-Z) N having an In composition ratio Z (X<Z≦1) exceeding the In composition ratio X of the first well layer 34 . The In composition ratio Z of the buffer well layer 39 is less than or equal to the In composition ratio Y of the second well layer 36 (X<Z≦Y).

In this embodiment, the In composition ratio Z is equal to the In composition ratio Y (Z=Y). That the In composition ratio Z is equal to the In composition ratio Y means that the buffer well layer 39 is formed under the condition that the In composition ratio Z is equal to the In composition ratio Y. The In composition ratio Z may have an error of about ±10% with respect to the In composition ratio Y.
The buffer well layer 39 is formed as a blue-green light-emitting layer that generates blue-green light having a peak emission wavelength in the range of 480 nm to 550 nm. More specifically, the peak emission wavelength of the buffer well layer 39 is 480 nm or more and 510 nm or less.

The In composition ratio Z may be 0.1 or more and 0.3 or less. In composition ratio Z is 0.1 or more and 0.125 or less, 0.125 or more and 0.15 or less, 0.15 or more and 0.175 or less, 0.175 or more and 0.2 or less, 0.2 or more and 0.225 or less. , 0.225 to 0.25, 0.25 to 0.275, or 0.275 to 0.3. The In composition ratio Z is preferably 0.15 or more and 0.25 or less.

Between the first well layers 34 and the buffer well layers 39 adjacent to each other in the stacking direction, the increase ratio between the In composition ratio X and the In composition ratio Z is the increase ratio of the In composition ratio X of the plurality of first well layers 34. is preferably equal to As a result, sudden changes in the In composition ratio X and the In composition ratio Z between the first MQW structure 31 and the buffer MQW structure 33 are suppressed.
That the rate of increase between the In composition ratio X and the In composition ratio Z is equal to the rate of increase of the In composition ratio X means that the rate of increase between the In composition ratio X and the In composition ratio Z is the same as the rate of increase of the In composition ratio X. It means that the buffer well layer 39 is formed under equal conditions. The rate of increase between the In composition ratio X and the In composition ratio Z may have an error of about ±10% of the rate of increase of the In composition ratio X.

The buffer barrier layer 40 comprises GaN doped with n-type impurities. The buffer barrier layer 40 may contain silicon as an example of n-type impurities. The impurity concentration of the buffer barrier layer 40 may be 5×10 ¹⁶ cm ⁻³ or more and 5×10 ²⁰ cm ⁻³ or less.
The buffer barrier layer 40 captures holes supplied from the p-type semiconductor layer 24 by n-type impurities. As a result, the number of holes supplied to the buffer well layer 39 is reduced, so that the generation of light in the buffer well layer 39 is suppressed. Moreover, since the number of holes supplied to the first MQW structure 31 is also reduced, the generation of light in the first MQW structure 31 is also suppressed.

The peak emission wavelength of light generated in the buffer well layer 39 is weak (noise level). Also, the peak emission wavelength generated by the buffer well layer 39 is equal to the peak emission wavelength generated by the second MQW structure 32 (second well layer 36). Therefore, the light generated in the buffer well layer 39 does not affect the dominant wavelength WL (light color) of the light extracted from the semiconductor light emitting layer 7. FIG.

One buffer well layer 39 and one buffer barrier layer 40 paired in the stacking direction have a third total thickness T3. The third total thickness T3 is the sum of the thickness TW3 of the buffer well layer 39 and the thickness TB3 of the buffer barrier layer 40 (T3=TW3+TB3).
The third total thickness T3 is less than or equal to the first total thickness T1 (T3≦T1) of the first MQW structure 31 . The third total thickness T3 is greater than or equal to the second total thickness T2 of the second MQW structure 32 (T2≦T3). In this embodiment, the third total thickness T3 is greater than the second total thickness T2 and less than the first total thickness T1 (T2<T3<T1).

The thickness TW3 of the buffer well layer 39 exceeds the thickness TW2 of the second well layer 36 (TW2<TW3). The thickness TW3 of the buffer well layer 39 is preferably equal to or less than the thickness TW1 of the first well layer 34 (TW3≤TW1). The thickness TW3 of the buffer well layer 39 is equal to the thickness TW1 of the first well layer 34 in this embodiment (TW3=TW1).
That the thickness TW3 is equal to the thickness TW1 means that the buffer well layer 39 is formed under the condition that the thickness TW3 is equal to the thickness TW1. The thickness TW3 may have an error of about ±10% of the thickness TW1.

The thickness TW3 may be 2 nm or more and 4 nm or less. The thickness TW3 may be 2 nm or more and 2.5 nm or less, 2.5 nm or more and 3 nm or less, 3 nm or more and 3.5 nm or less, or 3.5 nm or more and 4 nm or less. The thickness TW3 is preferably 2.5 nm or more and 3.5 nm or less.
The thickness TB3 of the buffer barrier layer 40 exceeds the thickness TW3 of the buffer well layer 39 (TW3<TB3). The thickness TB3 of the buffer barrier layer 40 is equal to or less than the thickness TB1 of the first barrier layer 35 (TB3≤TB1). The thickness TB3 of the buffer barrier layer 40 is preferably less than the thickness TB1 of the first barrier layer 35 (TB3<TB1). More preferably, the thickness TB3 of the buffer barrier layer 40 is less than or equal to half the thickness TB1 of the first barrier layer 35 (TB3<TB1/2).

The thickness TB3 of the buffer barrier layer 40 may be less than or equal to the thickness TB2 of the second barrier layer 37 (TB3≦TB2). The thickness TB3 of the buffer barrier layer 40 is in this embodiment equal to the thickness TB2 of the second barrier layer 37 (TB3=TB2).
That thickness TB3 is equal to thickness TB2 means that buffer well layer 39 is formed under the condition that thickness TB3 is equal to thickness TB2. The thickness TB3 may have an error of about ±10% of the thickness TB2.

The thickness TB3 may be 3 nm or more and 6 nm or less. The thickness TB3 is 3 nm or more and 3.5 nm or less, 3.5 nm or more and 4 nm or less, 4 nm or more and 4.5 nm or less, 4.5 nm or more and 5 nm or less, 5 nm or more and 5.5 nm or less, or 5.5 nm or more and 6 nm or less. may The thickness TB3 is preferably 4 nm or more and 5 nm or less. Thickness TB3 is preferably less than 5 nm.

Thus, buffer MQW structure 33 has both the function of first MQW structure 31 and the function of second MQW structure 32 . Interposing the buffer MQW structure 33 in the region between the first MQW structure 31 and the second MQW structure 32 appropriately suppresses the generation of light in the first MQW structure 31 and appropriately generates light in the second MQW structure 32. can be done. Also, rapid changes in lattice size between the first MQW structure 31 and the second MQW structure 32 can be suppressed.

When a plurality of buffer well layers 39 are formed, the plurality of buffer well layers 39 may have the same In composition ratio Z, or may have different In composition ratios Z from each other. That the In composition ratios Z are equal to each other means that the plurality of buffer well layers 39 are formed under the condition that the In composition ratios Z are equal. An error of about ±10% may occur between the In composition ratios Z.

The plurality of buffer well layers 39 may be stacked in such a manner that the In composition ratio Z is constant, similar to the second MQW structure 32 . As an example, all the buffer well layers 39 may be stacked with an In composition ratio Z equal to the In composition ratio Y of the second well layers 36 .
The plurality of buffer well layers 39 may be stacked such that the In composition ratio Z gradually increases from the first MQW structure 31 toward the second MQW structure 32 . The plurality of buffer well layers 39 are preferably stacked in such a manner that the In composition ratio Z gradually increases at a constant rate.

In this case, between the first well layers 34 and the buffer well layers 39 adjacent to each other in the stacking direction, the increase rate between the In composition ratio X and the In composition ratio Z is the In composition ratio X of the plurality of first well layers 34 is preferably equal to the increase rate of
That the rate of increase between the In composition ratio X and the In composition ratio Z is equal to the rate of increase of the In composition ratio X means that the rate of increase between the In composition ratio X and the In composition ratio Z is the same as the rate of increase of the In composition ratio X. It means that the buffer well layer 39 is formed under equal conditions. The rate of increase between the In composition ratio X and the In composition ratio Z may have an error of about ±10% of the rate of increase of the In composition ratio X.

In addition, between the second well layers 36 and the buffer well layers 39 adjacent to each other in the stacking direction, the rate of increase between the In composition ratio Y and the In composition ratio Z is the increase in the In composition ratio Z of the plurality of buffer well layers 39. It is preferably equal to the percentage.
That the rate of increase between the In composition ratio Y and the In composition ratio Z is equal to the rate of increase of the In composition ratio Z means that the rate of increase between the In composition ratio Y and the In composition ratio Z is the same as the rate of increase of the In composition ratio Z. This means that the second well layer 36 is formed under equal conditions. The rate of increase between the In composition ratio Y and the In composition ratio Z may have an error of about ±10% of the rate of increase of the In composition ratio Z.

The multiple buffer well layers 39 may have the same thickness TW3, or may have different thicknesses TW3. The multiple buffer barrier layers 40 may have the same thickness TB3, or may have different thicknesses TB3.
3, 5 and 6, the second MQW structure 32 in this embodiment has a main surface 42 in which a plurality of recesses 41 recessed toward the first MQW structure 31 are formed. A plurality of recesses 41 are formed on the major surface 42 of the second MQW structure 32 at intervals. A plurality of recesses 41 are formed in an irregular pattern in plan view. The plurality of recesses 41 are formed at a density of 1×10 ⁷ cm ⁻² or more and 1×10 ¹⁰ cm ^{−2 or} less per unit area.

It is preferable that the plurality of recesses 41 be spaced apart from each other on the second MQW structure 32 side with respect to the first MQW structure 31 . The plurality of recesses 41 preferably have a depth that traverses at least one second well layer 36 with respect to the normal direction N. As shown in FIG. A plurality of recesses 41 are formed with a depth across all the second well layers 36 included in the second MQW structure 32 with respect to the normal direction N in this embodiment.

A plurality of recesses 41 consist of V-pits 43 introduced in the second MQW structure 32 in this configuration. The V-pit 43 is also called a V-defect. The V pit 43 is formed starting from, for example, a threading dislocation from the substrate 6 or a crystal defect (more specifically, any well layer) in the light emitting layer 23 .
The V pits 43 are formed in an inverted hexagonal pyramidal shape corresponding to the hexagonal (GaN) crystal plane. Since the V pits 43 are actually accompanied by variations in crystal growth, they are formed in an inverted cone shape or an inverted hexagonal pyramid shape close to an inverted cone shape.

The apex angle θV of the V pit 43 may be 50° or more and 60° or less. The apex angle θV is the apex angle that appears when the V pit 43 is cut along the diagonal line. The apex angle θV may be 50° or more and 52° or less, 52° or more and 54° or less, 54° or more and 56° or less, 56° or more and 58° or less, or 58° or more and 60° or less. The apex angle θV is 55° or more and 57° or less in this embodiment.

The V-pit 43 includes six inclined facet surfaces 44A, 44B, 44C, 44D, 44E, and 44F inclined downward toward the first MQW structure 31 with respect to the main surface 42 of the second MQW structure 32 . The inclined facets 44A to 44F are planes other than the hexagonal c-plane.
More specifically, the inclined facet surfaces 44A to 44F are formed by hexagonal semipolar surfaces. A hexagonal crystal has 6-fold symmetry and has equivalent crystal planes and equivalent crystal directions every 60°. Therefore, each inclined facet 44A-44F has the crystal symmetry exhibited by the hexagonal crystal.

Each inclined facet 44A-44F may include any of (1-101), (1-102), (11-22) and (20-21) planes. That is, each of the inclined facet planes 44A to 44F has a crystal plane equivalent to the (1-101) plane, a crystal plane equivalent to the (1-102) plane, a crystal plane equivalent to the (11-22) plane, and a (20- 21) may include any of the equivalent crystal planes.

V-pits 43 include base V-pits 45 , middle V-pits 46 and top V-pits 47 . The base V pit 45 serves as an introduction starting point for the V pit 43 . A base V-pit 45 is formed in the buffer MQW structure 33 in this form. More specifically, the base V pit 45 is formed in the buffer barrier layer 40 starting from the buffer well layer 39 .
The middle V pit 46 is formed in the second well layer 36 and the second barrier layer 37 starting from the base V pit 45 . The second well layer 36 and the second barrier layer 37 are crystal-grown in a film shape following the main surface of the buffer barrier layer 40 and the inclined facet plane of the base V pit 45 . Thereby, a middle V pit 46 is formed in the second well layer 36 and the second barrier layer 37 starting from the base V pit 45 .

The top V-pit 47 forms the slanted facets 44A-44F of the V-pit 43. As shown in FIG. A top V pit 47 is formed in the top barrier layer 38 of the second MQW structure 32 . The uppermost barrier layer 38 is crystal-grown as a film following the main surface of the second well layer 36 and the inclined facet surfaces of the middle V pits 46 . Thereby, a top V pit 47 is formed in the uppermost barrier layer 38 starting from the middle V pit 46 .

Referring to FIGS. 2 and 3 again, p-type semiconductor layer 24 is formed on light emitting layer 23 . More specifically, the p-type semiconductor layer 24 fills the plurality of recesses 41 and covers the main surface 42 of the second MQW structure 32 . The p-type semiconductor layer 24 supplies holes to the second MQW structure 32 from regions inside and outside the plurality of recesses 41 .
That is, the p-type semiconductor layer 24 supplies holes to the second MQW structure 32 from the main surface 42 of the second MQW structure 32 and the inclined facet surfaces 44A to 44F of the V pits 43 . The p-type semiconductor layer 24 has a laminated structure including a p-type clad layer 48 and a p-type contact layer 49 in this embodiment.

A p-type cladding layer 48 is formed on the main surface 42 of the second MQW structure 32 . More specifically, the p-type cladding layer 48 fills the plurality of recesses 41 and covers the main surface 42 of the second MQW structure 32 . The p-type cladding layer 48 has a flat main surface. The p-type cladding layer 48 supplies holes to the second MQW structure 32 from regions inside and outside the plurality of recesses 41 . That is, the p-type cladding layer 48 supplies holes to the second MQW structure 32 from the main surface 42 of the second MQW structure 32 and the inclined facet surfaces 44A to 44F of the V pits 43 .

The p-type cladding layer 48 in this form comprises GaN doped with p-type impurities. The p-type cladding layer 48 may contain magnesium as an example of p-type impurities. The p-type impurity concentration of the p-type cladding layer 48 may be 5×10 ¹⁸ cm ⁻³ or more and 5×10 ²⁰ cm ⁻³ or less. The p-type impurity concentration of the p-type cladding layer 48 is approximately 5×10 ¹⁹ cm ⁻³ in this embodiment.

The thickness of the p-type cladding layer 48 may be 10 nm or more and 50 nm or less. The thickness of the p-type cladding layer 48 may be 10 nm or more and 20 nm or less, 20 nm or more and 30 nm or less, 30 nm or more and 40 nm or less, or 40 nm or more and 50 nm or less. The thickness of the p-type cladding layer 48 is approximately 30 nm in this embodiment.
A p-type contact layer 49 is formed on the p-type clad layer 48 . The p-type contact layer 49, in this form, comprises GaN doped with p-type impurities. The p-type contact layer 49 may contain magnesium as an example of p-type impurities. The p-type impurity concentration of the p-type contact layer 49 may be 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²² cm ⁻³ or less. The p-type impurity concentration of the p-type contact layer 49 is approximately 2×10 ²⁰ cm ⁻³ in this embodiment.

The thickness of the p-type contact layer 49 may be 50 nm or more and 500 nm or less. The thickness of the p-type clad layer 48 is 50 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or less, 200 nm or more and 250 nm or less, 250 nm or more and 300 nm or less, 300 nm or more and 350 nm or less, 350 nm or more and 400 nm or less, 400 nm or more and 450 nm or less. Alternatively, it may be 450 nm or more and 500 nm or less. The thickness of the p-type clad layer 48 is approximately 200 nm in this embodiment.

FIG. 9 is a graph obtained by actual measurement of the relationship between the dominant wavelength WL (light emission wavelength) and the forward current IF. In FIG. 9, the vertical axis indicates the dominant wavelength WL [nm] extracted from the semiconductor light emitting layer 7, and the horizontal axis indicates the forward current IF [mA].
FIG. 9 shows a first characteristic S1 (see broken line) and a second characteristic S2 (see solid line). A first characteristic S1 indicates the characteristic of the light emitting layer 23 according to the reference example. A second characteristic S2 indicates the characteristic of the light-emitting layer 23 according to this form. In the light emitting layer 23 according to the reference example, the thickness TW2 of the second well layer 36 in the second MQW structure 32 is set to 2 nm or more.

Referring to the first characteristic S1, in the light-emitting layer 23 according to the reference example, the dominant wavelength WL varied from 507 nm to 500 nm when the forward current IF was changed from 0 mA to 200 mA. In the light-emitting layer 23 according to the reference example, the maximum amount of change ΔWL in the dominant wavelength WL when the forward current IF was changed from 0 mA to 200 mA exceeded 5 nm. The maximum amount of change ΔWL is an absolute value (same below).

In the light-emitting layer 23 according to the reference example, the change rate of the dominant wavelength WL exceeds 1% when the forward current IF is changed from 0 mA to 200 mA. More specifically, the rate of change of dominant wavelength WL exceeds 1.3%.
An increase in forward current IF means an increase in holes supplied to light emitting layer 23 . In the light-emitting layer 23 according to the reference example, holes reaching the first MQW structure 31 cannot be sufficiently reduced depending on the second MQW structure 32 and the buffer MQW structure 33 . Therefore, as the forward current IF increased, the dominant wavelength WL largely shifted from the blue-green region toward the blue region.

Since light in the bluish-green region of 480 nm to 550 nm (more specifically, 480 nm to 510 nm) has excellent color discrimination, it is also applied to color barrier-free. Therefore, the change of the dominant wavelength WL from the bluish-green region to the blue region side means a decrease in color distinguishability, and is not preferable from the viewpoint of color barrier-free.
On the other hand, referring to the second characteristic S2, in the light-emitting layer 23 according to this embodiment, the dominant wavelength WL varied from 506 nm to 504 nm when the forward current IF was changed from 0 mA to 200 mA. In the light-emitting layer 23 according to this embodiment, the maximum amount of change ΔWL in the dominant wavelength WL when the forward current IF was changed from 0 mA to 200 mA was more than 0 nm and less than 5 nm (more specifically, less than 3 nm). .

In addition, in the light-emitting layer 23 according to this embodiment, the change rate of the dominant wavelength WL was 1% or less when the forward current IF was changed from 0 mA to 200 mA. More specifically, the rate of change of dominant wavelength WL was less than 0.5%.
In other words, in the light-emitting layer 23 according to this embodiment, the dominant wavelength WL has a thickness such that the maximum change amount ΔWL of is less than 5 nm (more specifically, less than 3 nm).

Further, the second well layer 36 has a rate of change of 1% or less in the dominant wavelength WL when the forward current IF flowing between the n-type semiconductor layer 22 and the p-type semiconductor layer 24 is changed from 0 mA to 200 mA. have a thickness.
FIG. 10 is a graph obtained by actual measurement of the relationship between the maximum variation ΔWL of the dominant wavelength WL and the thickness TB2 of the second barrier layer 37. In FIG. In FIG. 10, the vertical axis indicates the maximum variation .DELTA.WL [nm] of the dominant wavelength WL of light extracted from the semiconductor light emitting layer 7, and the horizontal axis indicates the thickness TB2 [nm] of the second barrier layer 37. FIG.

FIG. 10 shows a first plotted point P1, a second plotted point P2 and a third plotted point P3. A first plotted point P1 indicates the maximum variation .DELTA.WL when the thickness TB2 of the second barrier layer 37 is set to 10 nm and the forward current IF is varied from 5 mA to 20 mA.
A second plotted point P2 indicates the maximum variation .DELTA.WL when the thickness TB2 of the second barrier layer 37 is set to 7 nm and the forward current IF is varied from 5 mA to 20 mA. A third plotted point P3 indicates the maximum variation .DELTA.WL when the thickness TB2 of the second barrier layer 37 is set to 4.5 nm and the forward current IF is varied from 5 mA to 20 mA.

Referring to the first plotted point P1, when the thickness TB2 was set to 10 nm, the maximum amount of change .DELTA.WL was 6.6 nm. Referring to the second plotted point P2, when the thickness TB2 was set to 6 nm, the maximum amount of change .DELTA.WL was 6.3 nm. Referring to the third plotted point P3, when the thickness TB2 was set to 4.5 nm, the maximum amount of change .DELTA.WL was 5.3 nm.
Thus, by reducing the thickness TB2 of the second barrier layer 37, the maximum variation .DELTA.WL was reduced. In order to secure the function of the second barrier layer 37 and at the same time reduce the maximum variation ΔWL, the thickness TB2 of the second barrier layer 37 is preferably 3 nm or more and 6 nm or less. In this case, the maximum amount of change ΔWL can be suppressed within a range of 4 nm or more and 6.5 nm or less.

In other words, the second barrier layer 37 has a maximum change amount ΔWL of the dominant wavelength WL of 6.5 mA when the forward current IF flowing between the n-type semiconductor layer 22 and the p-type semiconductor layer 24 is changed from 5 mA to 20 mA. It preferably has a thickness TB2 of 5 nm or less.
1 to 3, the semiconductor main surface 13 of the semiconductor light emitting layer 7 is formed with a high band portion 51, a low band portion 52 and a connecting portion 53. As shown in FIG. The high band portion 51 , the low band portion 52 and the connection portion 53 are formed by cutting the semiconductor light emitting layer 7 . The high band portion 51 , the low band portion 52 and the connection portion 53 form a plateau-shaped mesa structure 54 .

The high region 51 is positioned relatively high with respect to the thickness direction (stacking direction) of the semiconductor light emitting layer 7 . The high band portion 51 is formed by the p-type semiconductor layer 24 . More specifically, the high region 51 is formed by the p-type contact layer 49 . In this embodiment, the high-pass portion 51 is formed in the central portion of the semiconductor light-emitting layer 7 at intervals from the semiconductor side surfaces 14A to 14D in plan view.

The high band portion 51 has four sides extending in parallel along the semiconductor side surfaces 14A to 14D in plan view. The planar shape of the high band portion 51 is arbitrary, and is not limited to a specific shape. The high band portion 51 may be formed in a polygonal shape, a circular shape, an elliptical shape, or the like in plan view.
The low band portion 52 is positioned lower than the high band portion 51 with respect to the thickness direction (stacking direction) of the semiconductor light emitting layer 7 . The low-pass portion 52 is formed by the n-type semiconductor layer 22 . More specifically, the low-pass portion 52 is formed by the n-type contact layer 29 . The low frequency band portion 52 extends in a belt shape along the periphery of the high frequency band portion 51 in plan view. In this embodiment, the low frequency band portion 52 is formed in an endless shape (annular shape) surrounding the high frequency band portion 51 in plan view.

The connecting portion 53 connects the high frequency portion 51 and the low frequency portion 52 . The connection portion 53 is formed by a portion of the n-type semiconductor layer 22 (n-type contact layer 29 ), the light emitting layer 23 and the p-type semiconductor layer 24 . The connecting portion 53 has four sides extending parallel to the semiconductor side surfaces 14A to 14D in plan view. The connecting portion 53 extends in a plane along the normal direction N. As shown in FIG. The connection portion 53 may slope downward from the high frequency portion 51 toward the low frequency portion 52 .

An insulating layer 55 covering the connection portion 53 is formed on the semiconductor main surface 13 . The insulating layer 55 may include a silicon oxide layer or a silicon nitride layer, or a laminated structure including a silicon oxide layer and a silicon nitride layer. The insulating layer 55 has a single-layer structure made of a silicon nitride layer in this embodiment.
The insulating layer 55 surrounds the high frequency portion 51 in plan view. The insulating layer 55 covers the entire connection portion 53 . Insulating layer 55 includes an overlap portion covering high frequency portion 51 via an edge portion connecting high frequency portion 51 and connecting portion 53 . Insulating layer 55 includes an overlap portion covering low frequency band portion 52 via an edge portion connecting low frequency band portion 52 and connecting portion 53 .

1 to 3, an n-side electrode 61 is formed on semiconductor main surface 13. As shown in FIG. The n-side electrode 61 is arranged in the low frequency band portion 52 . The n-side electrode 61 is formed in a region along at least one of the semiconductor side surfaces 14A to 14D in the low-pass portion 52. As shown in FIG.
In this embodiment, the n-side electrode 61 is arranged in a region along the corner connecting the first semiconductor side surface 14A and the fourth semiconductor side surface 14D in the low band portion 52 . The n-side electrode 61 is electrically connected to the n-type semiconductor layer 22 (n-type contact layer 29).

The n-side electrode 61 more specifically includes a light transmissive electrode 62 . The light transmissive electrode 62 includes an ITO (indium tin oxide) layer. The light transmissive electrode 62 has a single layer structure made of an ITO layer in this embodiment. The light-transmissive electrode 62 covers the semiconductor main surface 13 (low-band portion 52) and allows the light generated in the semiconductor light-emitting layer 7 to pass therethrough. The light transmissive electrode 62 is formed on the n-type semiconductor layer 22 (n-type contact layer 29). The light transmissive electrode 62 is electrically connected to the n-type semiconductor layer 22 (n-type contact layer 29).

The light transmissive electrode 62 has a first area Sn1 in plan view. The light-transmitting electrode 62 faces the plurality of projections 12 along the normal direction N. As shown in FIG. Also, the light-transmitting electrode 62 faces the plurality of holes 25 formed in the buffer layer 21 along the normal direction N. As shown in FIG.
The light-transmissive electrode 62 includes a body portion 63 and a wiring portion 64 in this embodiment. In this form, the body portion 63 is formed in a circular shape in plan view. The planar shape of the main body portion 63 is arbitrary and is not limited to a specific shape. The body portion 63 may be formed in a polygonal shape in plan view, or may be formed in an elliptical shape.

The wiring portion 64 is a strip-like portion pulled out from the main body portion 63 . In this embodiment, the wiring portion 64 is drawn out from the main body portion 63 to a region along the first semiconductor side surface 14A in the low frequency band portion 52 . The wiring portion 64 may be formed along two, three, or four of the semiconductor side surfaces 14A to 14D so as to partition the high frequency portion 51 from two, three, or four directions in plan view. good.

The thickness of the light transmissive electrode 62 may be 10 nm or more and 500 nm or less. The thickness of the light transmissive electrode 62 may be 10 nm or more and 100 nm or less, 100 nm or more and 200 nm or less, 200 nm or more and 300 nm or less, 300 nm or more and 400 nm or less, or 400 nm or more and 500 nm or less. The thickness of the light transmissive electrode 62 is 50 nm or more and 150 nm or less in this embodiment.

The n-side electrode 61 includes a terminal electrode 65 formed on the light transmissive electrode 62 . The terminal electrode 65 has a second area Sn2 less than the first area Sn1 of the light transmissive electrode 62 (Sn2<Sn1) in plan view. The terminal electrode 65 is formed spaced inwardly from the periphery of the light transmissive electrode 62 .
The entire area of the terminal electrode 65 overlaps the light transmissive electrode 62 in plan view. The terminal electrode 65 faces the plurality of protrusions 12 along the normal direction N. As shown in FIG. In addition, the terminal electrode 65 faces the plurality of holes 25 formed in the buffer layer 21 along the normal direction N. As shown in FIG.

Terminal electrode 65 includes main body portion 66 and wiring portion 67 . The body portion 66 is a portion to which a conductive joining member such as a bonding wire is connected. The body portion 66 is arranged on the body portion 63 of the light transmissive electrode 62 . In this form, the body portion 66 is formed in a circular shape in a plan view. The planar shape of the main body portion 66 is arbitrary and is not limited to a specific shape. The body portion 66 may be formed in a polygonal shape in plan view, or may be formed in an elliptical shape.

The wiring portion 67 is a strip-like portion drawn out from the main body portion 66 . The wiring portion 67 is arranged on the wiring portion 64 of the light transmissive electrode 62 . By adjusting the drawing mode of the wiring portion 67, the forward voltage VF and the like of the semiconductor light emitting device 1 are adjusted.
The wiring portion 67 is drawn out from the main body portion 66 to a region in the low-frequency portion 52 along the first semiconductor side surface 14A. The wiring portion 67 may be formed along two, three, or four of the semiconductor side surfaces 14A to 14D so as to partition the high frequency portion 51 from two, three, or four directions in plan view. good.

The terminal electrode 65 is formed in a trapezoidal shape having a top portion 68 , a base portion 69 , and side walls 70 inclined downward from the top portion 68 toward the base portion 69 when viewed in cross section. The terminal electrode 65 has a bulging portion 71 projecting outward at an edge portion connecting the top portion 68 and the side wall 70 .
The bulging portion 71 protrudes in the normal direction N and in a direction along the top portion 68 . The bulging portion 71 is formed in an annular shape extending along the periphery of the top portion 68 in plan view. The bulging portion 71 defines a region of the body portion 66 to which a conductive joining member such as a bonding wire is connected.

In this form, the terminal electrode 65 has a laminated structure including an Al electrode 72, a Ti electrode 73 and an Au electrode 74 laminated in this order from the light transmissive electrode 62 side.
The Al electrode 72 contains Al (aluminum). The Al electrode 72 is made of pure Al or an Al alloy. The Al alloy may be an AlCu alloy, an AlSi alloy, an AlSiCu alloy, or the like. The Al electrode 72 is made of pure Al in this form.

The Al electrode 72 is formed as a light reflecting electrode that reflects light generated by the semiconductor light emitting layer 7 . The Al electrode 72 is formed in a trapezoidal shape when viewed in cross section. A side wall of the Al electrode 72 has a first inclination angle θn1. The first tilt angle θn1 is the angle formed by the sidewall of the Al electrode 72 within the Al electrode 72 with respect to the semiconductor principal surface 13 .
The thickness of the Al electrode 72 may be 100 nm or more and 1500 nm or less. The thickness of the Al electrode 72 may be 100 nm or more and 250 nm or less, 250 nm or more and 500 nm or less, 500 nm or more and 750 nm or less, 750 nm or more and 1000 nm or less, 1000 nm or more and 1250 nm or less, or 1250 nm or more and 1500 nm or less. The thickness of the Al electrode 72 is 250 nm or more and 350 nm or less in this embodiment. The thicker the Al electrode 72, the higher the reflectance of light.

The Ti electrode 73 contains Ti (titanium). The Ti electrode 73 is formed as an adhesive layer that enhances the adhesion of the Au electrode 74 to the Al electrode 72 . The Ti electrode 73 covers almost the entire area of the Al electrode 72 . The Ti electrode 73 is formed in a trapezoidal shape when viewed in cross section. The sidewall of the Ti electrode 73 covers the sidewall of the Al electrode 72 .
The sidewall of the Ti electrode 73 has a second tilt angle θn2 (θn1<θn2) that exceeds the first tilt angle θn1 of the Al electrode 72 . The second tilt angle θn2 is the angle formed by the sidewall of the Ti electrode 73 within the Ti electrode 73 with respect to the semiconductor main surface 13 .

The thickness of the Ti electrode 73 may be 100 nm or more and 500 nm or less. The thickness of the Ti electrode 73 may be 100 nm or more and 200 nm or less, 200 nm or more and 300 nm or less, 300 nm or more and 400 nm or less, or 400 nm or more and 500 nm or less. The thickness of the Ti electrode 73 is 150 nm or more and 250 nm or less in this embodiment.
The Au electrode 74 contains Au (gold). The Au electrode 74 covers almost the entire Ti electrode 73 . The Au electrode 74 is formed in a trapezoidal shape when viewed in cross section. The Au electrode 74 forms the outer surface of the terminal electrode 65 . The side walls of the Au electrode 74 cover the side walls of the Ti electrode 73 .

The sidewall of the Au electrode 74 has a third tilt angle θn3 (θn1<θn2<θn3) that exceeds the second tilt angle θn2 of the Ti electrode 73 . The third tilt angle θn3 is the angle formed by the side wall of the Au electrode 74 within the Au electrode 74 with respect to the semiconductor main surface 13 .
The thickness of the Au electrode 74 may be 1 μm or more and 5 μm or less. The thickness of the Au electrode 74 may be 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, or 4 μm or more and 5 μm or less. The thickness of the Au electrode 74 is 1.5 μm or more and 2.5 μm or less in this embodiment.

2 and 7, n-side electrode 61 includes a barrier electrode 75 interposed in a region between light transmitting electrode 62 and terminal electrode 65 (Al electrode 72). The barrier electrode 75 is formed as a protective electrode that suppresses galvanic corrosion that occurs in the light transmissive electrode 62 due to Al in the Al electrode 72 . As a result, a decrease in light extraction efficiency due to galvanic corrosion can be suppressed. Therefore, light from the second MQW structure 32 can be properly extracted.

Barrier electrode 75 includes at least one of a TiN layer and a Cr layer. The barrier electrode 75 preferably has a single layer structure consisting of a TiN layer or a Cr layer. The Cr layer has a smaller light transmittance than the TiN layer. Therefore, barrier electrode 75 is preferably made of a TiN layer having a relatively high light transmittance.
The thickness of the barrier electrode 75 is less than the thickness of the light transmissive electrode 62 . The thickness of the barrier electrode 75 is less than the thickness of the Al electrode 72 . The thickness of the barrier electrode 75 may be 1 nm or more and 5 nm or less. The thickness of the barrier electrode 75 may be 1 nm or more and 2 nm or less, 2 nm or more and 3 nm or less, 3 nm or more and 4 nm or less, or 4 nm or more and 5 nm or less. The thickness of the barrier electrode 75 is 1.5 nm or more and 2.5 nm or less in this embodiment.

The barrier electrode 75 is formed over the entire area of the light transmissive electrode 62 facing the terminal electrode 65 in plan view. In other words, the barrier electrode 75 includes the body portion 76 and the wiring portion 77 . The main body portion 76 of the barrier electrode 75 is interposed in a region between the main body portion 63 of the light transmissive electrode 62 and the main body portion 66 of the terminal electrode 65 . The wiring portion 77 of the barrier electrode 75 is interposed in a region between the wiring portion 64 of the light transmissive electrode 62 and the wiring portion 67 of the terminal electrode 65 .

The peripheral edge of the barrier electrode 75 may be located inside the terminal electrode 65 with respect to the peripheral edge of the terminal electrode 65 in plan view. The peripheral edge of the barrier electrode 75 may be flush with the peripheral edge of the terminal electrode 65 . The peripheral edge of the barrier electrode 75 may be positioned outside the terminal electrode 65 with respect to the peripheral edge of the terminal electrode 65 in plan view. That is, the barrier electrode 75 may be drawn out to a region outside the terminal electrode 65 in plan view.

The barrier electrode 75 faces the plurality of protrusions 12 along the normal direction N. As shown in FIG. Also, the barrier electrode 75 faces the plurality of holes 25 formed in the buffer layer 21 along the normal direction N. As shown in FIG.
1 to 3, p-side electrode 81 is formed on semiconductor main surface 13 . The p-side electrode 81 is arranged in the high frequency region 51 . The p-side electrode 81 is electrically connected to the p-type semiconductor layer 24 (p-type contact layer 49).

The p-side electrode 81 more specifically includes a light transmissive electrode 82 . The light transmissive electrode 82 includes an ITO (indium tin oxide) layer. The light transmissive electrode 82 has a single layer structure made of an ITO layer in this embodiment. The light-transmitting electrode 82 covers the semiconductor main surface 13 (high-frequency region 51 ) and transmits light generated in the semiconductor light-emitting layer 7 . The light transmissive electrode 82 is formed on the p-type semiconductor layer 24 (p-type contact layer 49). The light transmissive electrode 82 is electrically connected to the p-type semiconductor layer 24 (p-type contact layer 49).

The light-transmitting electrode 82 covers the inner area of the high-frequency portion 51 at a distance from the periphery of the high-frequency portion 51 . A peripheral edge of the light-transmissive electrode 82 extends along a peripheral edge of the high-frequency portion 51 . The light transmissive electrode 82 has a first area Sp1 in plan view. The light-transmitting electrode 82 faces the plurality of projections 12 along the normal direction N. As shown in FIG. Also, the light-transmissive electrode 82 faces the plurality of holes 25 formed in the buffer layer 21 along the normal direction N. As shown in FIG.

The thickness of the light transmissive electrode 82 may be 10 nm or more and 500 nm or less. The thickness of the light transmissive electrode 82 may be 10 nm or more and 100 nm or less, 100 nm or more and 200 nm or less, 200 nm or more and 300 nm or less, 300 nm or more and 400 nm or less, or 400 nm or more and 500 nm or less.
The thickness of the light transmissive electrode 82 is 50 nm or more and 150 nm or less in this embodiment. The thickness of the light transmissive electrode 82 is preferably equal to the thickness of the light transmissive electrode 62 of the n-side electrode 61 . The expression that the thickness of the light-transmitting electrode 82 is equal to the thickness of the light-transmitting electrode 62 means that the light-transmitting electrode 82 is formed under the condition that the thickness of the light-transmitting electrode 82 is equal to the thickness of the light-transmitting electrode 62 . means. The thickness of the light transmissive electrode 82 may have an error of about ±10% of the thickness of the light transmissive electrode 62 .

The p-side electrode 81 includes a terminal electrode 85 formed on the light transmissive electrode 82 . The terminal electrode 85 has a second area Sp2 (Sp2<Sp1) that is less than the first area Sp1 of the light transmissive electrode 82 in plan view. The terminal electrode 85 is formed spaced inwardly from the periphery of the light transmissive electrode 82 .
The terminal electrode 85 is formed on the light transmissive electrode 82 in such a manner that the area of the exposed portion of the light transmissive electrode 82 is greater than or equal to the area of the hidden portion of the light transmissive electrode 82 in plan view. As a result, the entire area of the terminal electrode 85 overlaps the light transmissive electrode 82 in plan view. The terminal electrode 85 faces the plurality of protrusions 12 along the normal direction N. As shown in FIG. Also, the terminal electrode 85 faces the plurality of holes 25 formed in the buffer layer 21 along the normal direction N. As shown in FIG.

Terminal electrode 85 includes main body portion 86 and wiring portion 87 . The body portion 86 is a portion to which a conductive joining member such as a bonding wire is connected. In this form, the body portion 86 is formed in a circular shape in a plan view. The planar shape of the main body portion 86 is arbitrary and is not limited to a specific shape. The body portion 86 may be formed in a polygonal shape in plan view, or may be formed in an elliptical shape.

The wiring portion 87 is a strip-like portion pulled out from the main body portion 86 . The forward voltage VF and the like of the semiconductor light emitting device 1 are adjusted by adjusting the drawing mode of the wiring portion 87 . In this embodiment, the wiring portion 87 is drawn out from a portion of the body portion 86 facing the n-side electrode 61 .
In this form, the wiring portion 87 is formed in an arcuate shape curved in a direction away from the main body portion 86 in plan view, and circumscribes the main body portion 86 . The wiring portion 87 more specifically includes a plurality of portions having different radii of curvature. The multiple portions include a first wiring portion 87a and a second wiring portion 87b.

The first wiring portion 87 a extends in an arc shape centering on the body portion 66 of the n-side electrode 61 (terminal electrode 65 ) in plan view, and is circumscribed by the body portion 86 . The second wiring portion 87b extends in an arc around the tip of the wiring portion 67 of the n-side electrode 61 (terminal electrode 65) in plan view, and is connected to the first wiring portion 87a.
The terminal electrode 85 is formed in a trapezoidal shape having a top portion 88 , a base portion 89 , and side walls 90 inclined downward from the top portion 88 toward the base portion 89 in a cross-sectional view. The terminal electrode 85 has a bulging portion 91 at an edge portion connecting the top portion 88 and the side wall 90 .

The bulging portion 91 protrudes in the normal direction N and in the direction along the top portion 88 . The bulging portion 91 is formed in an annular shape extending along the periphery of the top portion 88 in plan view. The bulging portion 91 defines a region of the body portion 86 to which a conductive joining member such as a bonding wire is connected.
In this form, the terminal electrode 85 has a laminated structure including an Al electrode 92, a Ti electrode 93 and an Au electrode 94 laminated in this order from the light transmissive electrode 82 side.

The Al electrode 92 contains Al (aluminum). The Al electrode 92 may consist of pure Al or an Al alloy. The Al alloy may be an AlCu alloy, an AlSi alloy, an AlSiCu alloy, or the like. The Al electrode 92 is preferably made of the same electrode material as the Al electrode 72 of the n-side electrode 61 . The Al electrode 92 is made of pure Al in this form.
The Al electrode 92 is formed as a light reflecting electrode that reflects light generated by the semiconductor light emitting layer 7 . The Al electrode 92 is formed in a trapezoidal shape when viewed in cross section. A side wall of the Al electrode 92 has a first inclination angle θp1. The first tilt angle θp1 is an angle formed by the sidewall of the Al electrode 92 within the Al electrode 92 with respect to the semiconductor main surface 13 .

The thickness of the Al electrode 92 may be 100 nm or more and 1500 nm or less. The thickness of the Al electrode 92 may be 100 nm or more and 250 nm or less, 250 nm or more and 500 nm or less, 500 nm or more and 750 nm or less, 750 nm or more and 1000 nm or less, 1000 nm or more and 1250 nm or less, or 1250 nm or more and 1500 nm or less.
The thickness of the Al electrode 92 is 250 nm or more and 350 nm or less in this embodiment. The thicker the Al electrode 92, the higher the reflectance of light. The thickness of the Al electrode 92 is preferably equal to the thickness of the Al electrode 72 of the n-side electrode 61 . That the thickness of the Al electrode 92 is equal to the thickness of the Al electrode 72 means that the Al electrode 92 is formed under the condition that the thickness of the Al electrode 92 is equal to the thickness of the Al electrode 72 . The thickness of the Al electrode 92 may have an error of about ±10% of the thickness of the Al electrode 72 .

The Ti electrode 93 contains Ti (titanium). The Ti electrode 93 is formed as an adhesive layer that enhances the adhesion of the Au electrode 94 to the Al electrode 92 . The Ti electrode 93 covers almost the entire area of the Al electrode 92 . The Ti electrode 93 is formed in a trapezoidal shape when viewed in cross section. The sidewalls of the Ti electrode 93 cover the sidewalls of the Al electrode 92 .
The side wall of the Ti electrode 93 has a second tilt angle θp2 (θp1<θp2) that exceeds the first tilt angle θp1 of the Al electrode 92 . The second tilt angle θp2 is the angle formed by the sidewall of the Ti electrode 93 within the Ti electrode 93 with respect to the semiconductor main surface 13 .

The thickness of the Ti electrode 93 may be 100 nm or more and 500 nm or less. The thickness of the Ti electrode 93 may be 100 nm or more and 200 nm or less, 200 nm or more and 300 nm or less, 300 nm or more and 400 nm or less, or 400 nm or more and 500 nm or less.
The thickness of the Ti electrode 93 is 150 nm or more and 250 nm or less in this embodiment. The thickness of the Al electrode 92 is preferably equal to the thickness of the Ti electrode 73 of the n-side electrode 61 . That the thickness of the Ti electrode 93 is equal to the thickness of the Ti electrode 73 means that the Ti electrode 93 is formed under the condition that the thickness of the Ti electrode 93 is equal to the thickness of the Ti electrode 73 . The thickness of the Ti electrode 93 may have an error of about ±10% of the thickness of the Ti electrode 73 .

The Au electrode 94 contains Au (gold). The Au electrode 94 covers almost the entire Ti electrode 93 . The Au electrode 94 is formed in a trapezoidal shape when viewed in cross section. The Au electrode 94 forms the outer surface of the terminal electrode 85 . The side walls of the Au electrode 94 cover the side walls of the Ti electrode 93 .
The sidewall of the Au electrode 94 has a third tilt angle θp3 (θp1<θp2<θp3) that exceeds the second tilt angle θp2 of the Ti electrode 93 . The third tilt angle θp3 is the angle formed by the sidewall of the Au electrode 94 within the Au electrode 94 with respect to the semiconductor main surface 13 .

The thickness of the Au electrode 94 may be 1 μm or more and 5 μm or less. The thickness of the Au electrode 94 may be 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, or 4 μm or more and 5 μm or less.
The thickness of the Au electrode 94 is 1.5 μm or more and 2.5 μm or less in this embodiment. The thickness of the Au electrode 94 is preferably equal to the thickness of the Au electrode 74 of the n-side electrode 61 . That the thickness of the Au electrode 94 is equal to the thickness of the Au electrode 74 means that the Au electrode 94 is formed under the condition that the thickness of the Au electrode 94 is equal to the thickness of the Au electrode 74 . The thickness of the Au electrode 94 may have an error of about ±10% of the thickness of the Au electrode 74 .

3 and 8, p-side electrode 81 includes a barrier electrode 95 interposed in a region between light transmitting electrode 82 and terminal electrode 85 (Al electrode 92). The barrier electrode 95 is formed as a protective electrode that suppresses galvanic corrosion that occurs in the light transmissive electrode 82 due to Al in the Al electrode 92 . As a result, a decrease in light extraction efficiency due to galvanic corrosion can be suppressed. Therefore, light from the second MQW structure 32 can be properly extracted.

Barrier electrode 95 includes at least one of a TiN layer and a Cr layer. The barrier electrode 95 preferably has a single layer structure consisting of a TiN layer or a Cr layer. The Cr layer has a smaller light transmittance than the TiN layer. Therefore, barrier electrode 95 is preferably made of a TiN layer having a relatively high light transmittance.
The thickness of the barrier electrode 95 is less than the thickness of the light transmissive electrode 82 . The thickness of the barrier electrode 95 is less than the thickness of the Al electrode 92 . The thickness of the barrier electrode 95 may be 1 nm or more and 5 nm or less. The thickness of the barrier electrode 95 may be 1 nm or more and 2 nm or less, 2 nm or more and 3 nm or less, 3 nm or more and 4 nm or less, or 4 nm or more and 5 nm or less.

The thickness of the barrier electrode 95 is 1.5 nm or more and 2.5 nm or less in this embodiment. The thickness of the barrier electrode 95 is preferably equal to the thickness of the barrier electrode 75 of the n-side electrode 61 . That the thickness of the barrier electrode 95 is equal to the thickness of the barrier electrode 75 means that the barrier electrode 95 is formed under the condition that the thickness of the barrier electrode 95 is equal to the thickness of the barrier electrode 75 . The thickness of the barrier electrode 95 may have an error of about ±10% of the thickness of the barrier electrode 75 .

The barrier electrode 95 is formed over the entire area of the light transmissive electrode 82 facing the terminal electrode 85 in plan view. In other words, the barrier electrode 95 includes a body portion 96 and a wiring portion 97 . The main body portion 96 of the barrier electrode 95 is interposed in the region between the light transmissive electrode 82 and the main body portion 86 of the terminal electrode 85 . The wiring portion 97 of the barrier electrode 95 is interposed in the region between the light transmissive electrode 62 and the wiring portion 87 of the terminal electrode 85 .

The peripheral edge of the barrier electrode 95 may be located inside the terminal electrode 85 with respect to the peripheral edge of the terminal electrode 85 in plan view. The peripheral edge of the barrier electrode 95 may be flush with the peripheral edge of the terminal electrode 85 . The peripheral edge of the barrier electrode 95 may be located outside the terminal electrode 85 with respect to the peripheral edge of the terminal electrode 85 in plan view. That is, the barrier electrode 95 may be drawn out to a region outside the terminal electrode 85 in plan view.

The barrier electrode 95 faces the plurality of protrusions 12 along the normal direction N. As shown in FIG. Also, the barrier electrode 95 faces the plurality of holes 25 formed in the buffer layer 21 along the normal direction N. As shown in FIG.
As described above, the semiconductor light-emitting device 1 has a double heterostructure including the n-type semiconductor layer 22 , the light-emitting layer 23 and the p-type semiconductor layer 24 . Light-emitting layer 23 includes a first MQW structure 31 having an inactive structure and a second MQW structure 32 having an active structure. As a result, light generation in the first MQW structure 31 can be suppressed, and light can be generated in the second MQW structure 32 .

More specifically, the first MQW structure 31 includes a first well layer 34 containing In _X Ga _(1−X) N having an In composition ratio X (0<X<1) and an n-type impurity doped It has a laminated structure in which first barrier layers 35 containing GaN are alternately laminated. One first well layer 34 and one first barrier layer 35 paired in the stacking direction have a first total thickness T1.
On the other hand, the second MQW structure 32 includes a second well layer 36 containing In _Y Ga _(1−Y) N having an In composition ratio Y (X<Y≦1) exceeding the In composition ratio X, and an impurity-free It has a laminated structure in which second barrier layers 37 containing GaN are alternately laminated. One second well layer 36 and one second barrier layer 37 paired in the stacking direction have a second total thickness T2 (T2<T1) less than the first total thickness T1.

As a result, the efficiency of supplying holes to the second MQW structure 32 can be increased, and at the same time, the number of holes supplied to the first MQW structure 31 can be reduced. As a result, light generation in the first MQW structure 31 can be suppressed, and light can be efficiently generated in the second MQW structure 32 . Therefore, fluctuations in the dominant wavelength WL (light emission wavelength) due to fluctuations in the forward current IF can be suppressed.

The second well layer 36 preferably has a thickness TW2 that is less than the thickness TW1 of the first well layer 34 (TW2<TW1). The second barrier layer 37 preferably has a thickness TB2 that is less than the thickness TB1 of the first barrier layer 35 (TW2<TB1).
The first barrier layer 35 preferably has a thickness TB1 greater than the thickness TW1 of the first well layer 34 (TW1<TB1). The second barrier layer 37 preferably has a thickness TB2 greater than the thickness TW2 of the second well layer 36 (TW2<TB2). These structures are effective in appropriately suppressing fluctuations in dominant wavelength WL caused by fluctuations in forward current IF.

In this case, the first well layer 34 preferably has a thickness of 2 nm or more and 4 nm or less, and the second well layer 36 preferably has a thickness of 1 nm or more and less than 2 nm. The first barrier layer 35 preferably has a thickness of 5 nm or more and 20 nm or less, and the second barrier layer 37 preferably has a thickness of 3 nm or more and less than 5 nm.
The plurality of first well layers 34 are preferably stacked such that the In composition ratio X gradually increases in the direction away from the n-type semiconductor layer 22 . As a result, the change in lattice size due to indium can be suppressed, so the stress in the first MQW structure 31 can be relaxed.

The plurality of second well layers 36 are preferably stacked such that the In composition ratio Y is constant. As a result, variations in peak emission wavelength in the plurality of second well layers 36 can be suppressed, so that light having a desired dominant wavelength WL can be appropriately extracted.
The second barrier layer 37 has an In composition ratio Y exceeding the In composition ratio X of the first barrier layer 35 of the first MQW structure 31 . Therefore, when the second MQW structure 32 is formed directly on the n-type semiconductor layer 22, stress increases due to the abrupt change in lattice size.

A stress generated between the second MQW structure 32 and the n-type semiconductor layer 22 is relieved by the first MQW structure 31 . Thereby, the introduction of lattice defects in the second MQW structure 32 can be appropriately suppressed. As a result, light having a desired peak emission wavelength can be appropriately generated in the second MQW structure 32 .
Semiconductor light emitting device 1 further includes a buffer MQW structure 33 interposed in a region between first MQW structure 31 and second MQW structure 32 . Buffer MQW structure 33 has an inactive structure. The buffer MQW structure 33 more specifically has both the function of the first MQW structure 31 and the function of the second MQW structure 32 .

More specifically, the buffer MQW structure 33 includes a buffer well layer 39 containing In _Z Ga _(1−Z) N having an In composition ratio Z exceeding the In composition ratio X (X<Z≦1), and n It has a layered structure including a buffer barrier layer 40 comprising doped GaN. One buffer well layer 39 and one buffer barrier layer 40 paired in the stacking direction have a third total thickness T3 (T2<T3) exceeding the second total thickness T2.

Light generated in the buffer well layer 39 is weak. Also, the peak emission wavelength of the buffer well layer 39 is approximately equal to the peak emission wavelength of the second well layer 36 . Therefore, the light generated in the buffer well layer 39 does not affect the dominant wavelength WL (light color) of the light extracted from the semiconductor light emitting layer 7. FIG.
The buffer MQW structure 33 can suppress rapid changes in lattice size between the first MQW structure 31 and the second MQW structure 32 . Further, according to the buffer MQW structure 33, the generation of light in the first MQW structure 31 can be suppressed appropriately.

In this case, the buffer well layer 39 preferably has a thickness TW3 that exceeds the thickness TW2 of the second well layer 36 (TW2<TW3). Also, the buffer barrier layer 40 preferably has a thickness TB3 that is less than the thickness TB1 of the first barrier layer 35 (TB3<TB1).
Also, in the semiconductor light emitting device 1 , the second MQW structure 32 includes a recess 41 recessed toward the first MQW structure 31 . The p-type semiconductor layer 24 fills the recess 41 to cover the second MQW structure 32 and is electrically connected to the second MQW structure 32 in regions inside and outside the recess 41 . Thereby, holes can be efficiently supplied to the second MQW structure 32 . As a result, light having a desired peak emission wavelength can be appropriately generated in the second MQW structure 32 .

The recess 41 preferably crosses at least one second well layer 36 with respect to the stacking direction of the second MQW structure 32 . More preferably, the recess 41 crosses all the second well layers 36 in the stacking direction of the second MQW structure 32 . These structures can appropriately increase the efficiency of supplying holes to the second well layer 36 .
The recess 41 is preferably formed on the second MQW structure 32 side with respect to the first MQW structure 31 . According to such a structure, the supply of holes to the first MQW structure 31 can be suppressed, and at the same time, the efficiency of supplying holes to the second MQW structure 32 can be enhanced. Therefore, in the structure in which the recess 41 is formed, fluctuations in the dominant wavelength WL due to fluctuations in the forward current IF can be suppressed appropriately.

Further, according to the semiconductor light-emitting device 1, the substrate 6 is made of a hexagonal substrate, and the first substrate 6 has an off-angle inclined at an angle of 0.1° or more and 1° or less in the m-axis direction with respect to the c-plane of the hexagonal crystal. It includes a substrate major surface 8 . The semiconductor light emitting layer 7 is made of a Group III nitride semiconductor layer and formed on the main surface 8 of the first substrate. Thereby, the semiconductor light-emitting layer 7 made of high-quality crystals can be formed. As a result, the light emission efficiency of the light emitting layer 23 (more specifically, the second MQW structure 32) can be enhanced.

FIG. 11 is an enlarged view of a region corresponding to FIG. 5 and partially showing a semiconductor light emitting device 101 according to the second embodiment of the present invention. In the following, structures corresponding to the structures described for the semiconductor light emitting device 1 are denoted by the same reference numerals, and descriptions thereof are omitted.
Referring to FIG. 11, the plurality of recesses 41 are formed with a depth in the normal direction N up to a midpoint in the depth direction of the second MQW structure 32 in this embodiment. That is, the recesses 41 are formed on the second MQW structure 32 side with respect to the buffer MQW structure 33 . A plurality of recesses 41 are formed by V pits 43 .

A base V-pit 45 of V-pit 43 is formed in the second MQW structure 32 in this embodiment. More specifically, the base V pit 45 is formed in the lowermost second barrier layer 37 starting from the lowermost second well layer 36 .
A middle V pit 46 of the V pit 43 is formed in the second well layer 36 and the second barrier layer 37 located below the uppermost barrier layer 38 with the base V pit 45 as a starting point. The second well layer 36 and the second barrier layer 37 are crystal-grown in a film shape following the main surface of the buffer barrier layer 40 and the inclined facet plane of the base V pit 45 . Thereby, a middle V pit 46 is formed in the second well layer 36 and the second barrier layer 37 starting from the base V pit 45 .

A top V-pit 47 of V-pit 43 is formed by top barrier layer 38 of second MQW structure 32 . The uppermost barrier layer 38 is crystal-grown as a film following the main surface of the second well layer 36 and the inclined facet surfaces of the middle V pits 46 . Thereby, a top V pit 47 is formed in the uppermost barrier layer 38 starting from the middle V pit 46 .
As described above, the semiconductor light emitting device 101 can also achieve the same effects as those described for the semiconductor light emitting device 1 . Further, according to the semiconductor light emitting device 101 , the plurality of recesses 41 are formed on the second MQW structure 32 side with respect to the buffer MQW structure 33 . Thereby, generation of light in the first MQW structure 31 and the buffer MQW structure 33 can be suppressed appropriately. Therefore, fluctuations in the dominant wavelength WL due to fluctuations in the forward current IF can be suppressed appropriately.

FIG. 12 is an enlarged view of a region corresponding to FIG. 5 and partially showing a semiconductor light emitting device 111 according to the third embodiment of the present invention. In the following, structures corresponding to the structures described for the semiconductor light emitting device 1 are denoted by the same reference numerals, and descriptions thereof are omitted.
Referring to FIG. 12, a plurality of recesses 41 extend across the second MQW structure 32 and the buffer MQW structure 33 to the first MQW structure 31 with respect to the normal direction N in this embodiment. A plurality of recesses 41 are formed by V pits 43 .

A base V-pit 45 of the V-pit 43 is formed in the surface layer portion of the first MQW structure 31 in this embodiment. The base V pit 45 is formed in the uppermost first barrier layer 35 starting from the uppermost first well layer 34 in this embodiment.
The base V pit 45 of the V pit 43 may be formed starting from the first well layer 34 that is two, three, or four layers below the uppermost first well layer 34 . However, from the viewpoint of reducing the hole injection area, the base V pit 45 is formed in the uppermost first well layer 34 or the first well layer 2 or 3 layers below the uppermost first well layer 34 . It is preferable that the layer 34 be the starting point.

Middle V pit 46 of V pit 43 is formed in buffer well layer 39 , buffer barrier layer 40 , second well layer 36 and second barrier layer 37 starting from base V pit 45 . The buffer well layer 39, the buffer barrier layer 40, the second well layer 36 and the second barrier layer 37 are film-like following the main surface of the uppermost first barrier layer 35 and the inclined facet surface of the base V pit 45, respectively. crystal growth. Thereby, a middle V pit 46 is formed in the buffer well layer 39 , the buffer barrier layer 40 , the second well layer 36 and the second barrier layer 37 starting from the base V pit 45 .

Top V-pit 47 is formed by top barrier layer 38 of second MQW structure 32 . The uppermost barrier layer 38 is crystal-grown as a film following the main surface of the second well layer 36 and the inclined facet surfaces of the middle V pits 46 . Thereby, a top V pit 47 is formed in the uppermost barrier layer 38 starting from the middle V pit 46 .
As described above, according to the semiconductor light emitting device 111, the same effects as those described for the semiconductor light emitting device 1 can be obtained. Further, according to the semiconductor light emitting device 111 , the recesses 41 cross the second MQW structure 32 and the buffer MQW structure 33 to reach the surface layer of the first MQW structure 31 .

As a result, the efficiency of supplying holes to the second MQW structure 32 can be reliably increased. However, it should be noted that in the semiconductor light emitting device 111, the number of holes supplied to the first MQW structure 31 and the buffer MQW structure 33 increases.
FIG. 13 is a sectional view of a region corresponding to FIG. 3, showing a semiconductor light emitting device 121 according to the fourth embodiment of the present invention. In the following, structures corresponding to the structures described for the semiconductor light emitting device 1 are denoted by the same reference numerals, and descriptions thereof are omitted.

Referring to FIG. 13, buffer layer 21 in semiconductor light emitting device 121 does not have holes 25 . As described above, according to the semiconductor light emitting device 121, the same effects as those described for the semiconductor light emitting device 1 can be obtained. The buffer layer 21 according to the fourth embodiment can also be applied to the buffer layers 21 according to the above-described second and third embodiments.
FIG. 14 is a sectional view of a region corresponding to FIG. 3, showing a semiconductor light emitting device 131 according to the fifth embodiment of the present invention. In the following, structures corresponding to the structures described for the semiconductor light emitting device 1 are denoted by the same reference numerals, and descriptions thereof are omitted.

Referring to FIG. 14 , uneven structure 11 according to semiconductor light emitting device 131 includes a plurality of protrusions 132 formed from a portion of substrate 6 instead of protrusions 12 in this embodiment. The plurality of protrusions 132 are formed by selectively digging down the first substrate main surface 8 of the substrate 6 toward the second substrate main surface 9 by an etching method. The etching method may be a wet etching method and/or a dry etching method.

The plurality of protrusions 132 are formed in a frustum shape, a dome shape, or a hemispherical shape. The plurality of projecting portions 132 may be formed in a truncated cone shape or n (n≧3) truncated pyramid shape as an example of the truncated pyramid shape. The plurality of protruding portions 132 are formed on the first substrate main surface 8 at intervals. The plurality of protrusions 132 may be formed in a matrix or zigzag pattern in plan view.

As described above, according to the semiconductor light emitting device 131, the same effects as those described for the semiconductor light emitting device 1 can be obtained. The concave-convex structure 11 according to the fifth embodiment can also be applied to the concave-convex structure 11 according to the above-described second, third, and fourth embodiments.
The invention can also be implemented in other forms.
In each of the embodiments described above, an example in which a plurality of recesses 41 (V pits 43) are formed in the main surface 42 of the second MQW structure 32 has been described. However, a second MQW structure 32 that does not have a plurality of recesses 41 (V-pits 43) may be employed.

In each of the above-described embodiments, an example in which the terminal electrode 65 related to the n-side electrode 61 includes the main body portion 66 and the wiring portion 67 has been described. However, a terminal electrode 65 that does not have the wiring portion 67 may be employed. In this case, the wiring portion 77 of the barrier electrode 75 may be removed.
In each of the above-described embodiments, an example in which the terminal electrode 85 related to the p-side electrode 81 includes the main body portion 86 and the wiring portion 87 has been described. However, a terminal electrode 85 that does not have the wiring portion 87 may be employed. In this case, the wiring portion 97 of the barrier electrode 95 may be removed.

In each of the above-described embodiments, an example in which the terminal electrode 65 related to the n-side electrode 61 has a laminated structure including the Al electrode 72, the Ti electrode 73 and the Au electrode 74 has been described. However, the terminal electrode 65 may have a single layer structure consisting of the Al electrode 72 .
In each of the above-described embodiments, the structure on the Al electrode 72 is arbitrary, and the Ti electrode 73 and the Au electrode 74 do not necessarily have to be laminated. For example, a Pt (platinum) layer or a W (tungsten) layer may be formed on the Al electrode 72 instead of the Ti electrode 73 and the Au electrode 74 .

In each of the above-described embodiments, an example in which the terminal electrode 85 related to the p-side electrode 81 has a laminated structure including the Al electrode 92, the Ti electrode 93 and the Au electrode 94 has been described. However, the terminal electrode 85 may have a single layer structure consisting of the Al electrode 92 .
In each of the above-described embodiments, the structure on the Al electrode 92 is arbitrary, and the Ti electrode 93 and the Au electrode 94 do not necessarily have to be laminated. For example, a Pt (platinum) layer or a W (tungsten) layer may be formed on the Al electrode 92 instead of the Ti electrode 93 and the Au electrode 94 .

In each of the above-described embodiments, an example in which the uneven structure 11 is formed on the main surface 8 of the first substrate has been described. However, in the first to fifth embodiments, a configuration in which the first substrate main surface 8 does not have the concave-convex structure 11 may be employed.
In each of the above-described embodiments, a structure in which the conductivity type of each semiconductor portion is reversed may be employed. That is, the p-type portion may be formed to be n-type, and the n-type portion may be formed to be p-type.

This specification does not limit any combination of features shown in the first to fifth embodiments. The first to fifth embodiments can be combined in any manner and in any form among them. In other words, a semiconductor light-emitting device in which the features shown in the first to fifth embodiments are combined in any manner and in any form may be employed.
Although the embodiments of the present invention have been described in detail, these are merely specific examples used to clarify the technical content of the present invention, and the present invention should be construed as being limited to these specific examples. should not, the scope of the invention is limited only by the appended claims.

1 semiconductor light emitting device 22 n-type semiconductor layer 24 p-type semiconductor layer 31 first MQW structure 32 second MQW structure 33 buffer MQW structure 34 first well layer 35 first barrier layer 36 second well layer 37 second barrier layer 39 buffer well layer 40 buffer barrier layer 41 recess 101 semiconductor light emitting device 111 semiconductor light emitting device 121 semiconductor light emitting device 131 semiconductor light emitting device T1 first total thickness T2 second total thickness T3 third total thickness TB1 first barrier layer thickness TB2 2 Barrier layer thickness TB3 Buffer barrier layer thickness TW1 First well layer thickness TW2 Second well layer thickness TW3 Buffer well layer thickness WL Dominant wavelength X In composition ratio Y In composition ratio Z In composition ratio

Claims (19)

a first semiconductor layer of a first conductivity type;
Alternating first well layers containing In _X Ga _(1−X) N having an In composition ratio X (0<X<1) and first barrier layers containing GaN doped with first conductivity type impurities a first MQW structure formed on the first semiconductor layer, the stacked first well layer and the first barrier layer forming a pair having a stacked structure having a first total thickness;
A second well layer containing In _Y Ga _(1−Y) N having an In composition ratio Y (X<Y≦1) exceeding the In composition ratio X, and a second barrier layer containing GaN with no impurity added. A stacked structure in which the second well layers and the second barrier layers are alternately stacked to form a pair and have a second total thickness less than the first total thickness, and are formed on the first MQW structure. a second MQW structure;
a second conductivity type second semiconductor layer formed on the second MQW structure;
A buffer well layer containing In _Z Ga _(1-Z) N having an In composition ratio Z (X<Z≦1) exceeding the In composition ratio X, and a buffer containing GaN doped with first conductivity type impurities a stacked structure including barrier layers, wherein the buffer well layer paired with the buffer barrier layer has a third total thickness greater than the second total thickness, and between the first MQW structure and the second MQW structure; a buffer MQW structure intervening in the region of
The first MQW structure includes a plurality of first well layers stacked such that the In composition ratio X gradually increases in a direction away from the first semiconductor layer,
The second MQW structure includes a plurality of second well layers stacked such that the In composition ratio Y is constant,
Between the first well layers and the buffer well layers adjacent to each other in the stacking direction, the rate of increase between the In composition ratio X and the In composition ratio Z is equal to the In composition ratio X of the plurality of first well layers. A semiconductor light-emitting device equal to the increasing rate of . 2. The semiconductor light emitting device according to claim 1, wherein said In composition ratio Z of said buffer well layer is equal to or less than said In composition ratio Y of said second well layer (X<Z≤Y). 3. The buffer MQW structure according to claim 1, wherein said buffer MQW structure includes a plurality of said buffer well layers stacked such that said In composition ratio Z gradually increases at a constant rate from said first MQW structure toward said second MQW structure. The semiconductor light emitting device described. 4. The first MQW structure according to any one of claims 1 to 3 , wherein the first MQW structure has an inactive structure in which light generation in the first well layer is suppressed by the first conductivity type impurity in the first barrier layer. 10. The semiconductor light-emitting device according to claim 1 . 5. The semiconductor light emitting device according to claim 1, wherein said second well layer has a thickness less than that of said first well layer. 6. The semiconductor light emitting device according to claim 1, wherein said second barrier layer has a thickness less than that of said first barrier layer. 7. The semiconductor light emitting device according to claim 1, wherein said first barrier layer has a thickness exceeding the thickness of said first well layer. 8. The semiconductor light emitting device according to claim 1, wherein said second barrier layer has a thickness exceeding the thickness of said second well layer. 9. The semiconductor light emitting device according to claim 1, wherein said buffer well layer has a thickness exceeding the thickness of said second well layer. 10. The semiconductor light emitting device according to claim 1 , wherein said buffer barrier layer has a thickness less than the thickness of said first barrier layer. the first well layer has a thickness of 2 nm or more and 4 nm or less;
11. The semiconductor light emitting device according to claim 1, wherein said second well layer has a thickness of 1 nm or more and 2 nm or less. the first barrier layer has a thickness of 5 nm or more and 20 nm or less;
12. The semiconductor light emitting device according to claim 1 , wherein said second barrier layer has a thickness of 3 nm or more and 6 nm or less. The In composition ratio X of the first well layer is 0.01 or more and 0.2 or less,
13. The semiconductor light emitting device according to claim 1, wherein said In composition ratio Y of said second well layer is 0.1 or more and 0.3 or less. said second MQW structure having a recess recessed towards said first MQW structure;
14. The second semiconductor layer according to claim 1, wherein said second semiconductor layer fills said recess to cover said second MQW structure, and is electrically connected to said second MQW structure in regions inside and outside said recess. 1. The semiconductor light emitting device according to item 1. 15. The semiconductor light emitting device according to claim 14 , wherein said recess crosses at least one said second well layer with respect to the stacking direction of said second MQW structure. The recess is formed on the second MQW structure side with respect to the first MQW structure,
16. The semiconductor light emitting device according to claim 14 or 15 . the first well layer generates light having a wavelength of 410 nm or more and less than 480 nm;
17. The semiconductor light emitting device according to claim 1, wherein said second well layer generates light having a wavelength of 480 nm or more and 550 nm or less. further comprising a substrate;
18. The semiconductor light emitting device according to claim 1, wherein said first semiconductor layer is formed on said substrate. The substrate is made of a hexagonal crystal substrate and includes a main surface of the substrate having an off angle inclined at an angle of 0.1° or more and 1° or less in the m-axis direction with respect to the c-plane of the hexagonal crystal,
19. The semiconductor light emitting device according to claim 18 , wherein said first semiconductor layer is formed on said main surface of said substrate.

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