WO2016158111A1

WO2016158111A1 - Semiconductor light emitting element and method for manufacturing same

Info

Publication number: WO2016158111A1
Application number: PCT/JP2016/055617
Authority: WO
Inventors: 研片岡
Original assignee: ウシオ電機株式会社
Priority date: 2015-03-31
Filing date: 2016-02-25
Publication date: 2016-10-06

Abstract

To achieve a semiconductor light emitting element having a high yield. This semiconductor light emitting element has: a substrate; a first semiconductor layer, an active layer, and a second semiconductor layer, which are formed on an upper layer of the substrate; and a first electrode. The active layer and/or the first semiconductor layer includes, in the direction parallel to the surface of the substrate, an uneven surface in a first region, and a second region different from the first region is configured from a flat surface. In the second region, the first electrode is formed in contact with the first semiconductor layer, and in a state of being insulated from the active layer and the second semiconductor layer. In the second region, the active layer and the second semiconductor layer are not formed on the upper layer of the first semiconductor layer, said upper layer being positioned in a region in contact with the first electrode.

Description

Semiconductor light emitting device and method of manufacturing the same

The present invention relates to a semiconductor light emitting device and a method of manufacturing the same.

As one of the device structures of semiconductor light emitting devices, development of a so-called via structure type semiconductor light emitting device has been advanced. For example, in Patent Document 1 below, by adopting a semiconductor light emitting element of a via structure type, the distance in which the current should be spread in the lateral direction becomes smaller in the semiconductor, the series resistance can be reduced, and high current drive is achieved. It describes what can be achieved.

JP, 2004-047988, A

The inventors of the present invention have found a unique problem that the yield is deteriorated when manufacturing the above-described via structure type semiconductor light emitting device, and the present invention has been achieved.

The semiconductor light emitting device according to the present invention is
A substrate,
A first semiconductor layer formed of an n-type or p-type nitride semiconductor formed in the upper layer of the substrate;
An active layer formed of a nitride semiconductor, formed on the upper layer of the first semiconductor layer;
A second semiconductor layer formed of a nitride semiconductor of a conductivity type different from the first semiconductor layer, formed in the upper layer of the active layer;
And a first electrode formed in contact with the first semiconductor layer,
At least one of the active layer and the first semiconductor layer includes an uneven surface in a first region in a direction parallel to the surface of the substrate, and a second region different from the first region is a flat surface.
The first electrode is formed in the second region so as to be in contact with the first semiconductor layer and to have insulation with respect to the active layer and the second semiconductor layer.
In the second region, the active layer and the second semiconductor layer are not formed on the upper layer of the first semiconductor layer located in the region in contact with the first electrode.

The following two configurations are assumed as the above element. First, the first configuration will be described, and the second configuration will be described later.

In the first configuration, the active layer is configured such that the surface located on the side of the first semiconductor layer in the first region includes an uneven surface, while the surface of the first semiconductor layer in the second region is The surface located in the side is comprised by the flat surface.

In the above element, the first electrode is formed to be in contact with the first semiconductor layer in a region where the active layer and the second semiconductor layer do not exist. In the first electrode, the surface located on the side of the first semiconductor layer of the active layer is not included in the first region including the uneven surface, but the surface located on the side of the first semiconductor layer of the active layer is It is provided in the 2nd area | region comprised by the flat surface.

In order to form a region in which the active layer and the second semiconductor layer do not exist, the second semiconductor layer and the active layer located in the region are formed, for example, by performing etching or the like. Here, it is assumed that the first electrode is formed in the first region in which the active layer is formed including the uneven surface. Even if the first semiconductor layer is exposed at a portion where the surface of the active layer on the first semiconductor layer side is recessed toward the first semiconductor layer as the etching progresses, on the first semiconductor layer side in the vicinity thereof At a location where the surface of the active layer is convex toward the first semiconductor layer, it is assumed that the active layer still exists and the first semiconductor layer is not exposed. That is, in order to form the first electrode, etching is performed until the first semiconductor layer is completely exposed at the portion where the surface of the active layer on the first semiconductor layer side is convex toward the first semiconductor layer. It is necessary to advance.

On the other hand, when the first electrode is formed in the second region in which the active layer is formed to be flat, there is no need to pay attention to the above, and only the film thickness equivalent of the active layer is required. By advancing the etching, the first semiconductor layer can be exposed. That is, the amount of etching can be reduced as compared with the case where the first electrode is formed in the first region.

An increase in the amount of etching means an increase in the amount of energy applied at the time of etching. From the viewpoint of suppressing the adverse effect on the electrical characteristics of the light emitting element as much as possible, it is preferable to reduce the amount of energy applied at the time of etching. Therefore, according to the above configuration, even in the case where the concavo-convex surface is formed in the semiconductor layer, it can be realized by inserting the first electrode into the hole portion formed by the etching to the flat surface. A semiconductor light emitting device of via type structure with high yield can be realized because the electrical characteristics between the devices can be made uniform.

The semiconductor light emitting device can be a flip chip structure as well as a via structure.

In the second region, it has a hole which penetrates at least the second semiconductor layer and the active layer and reaches the first semiconductor layer,
The first electrode may be inserted into the hole in a state in which an insulating state is maintained with respect to the active layer and the second semiconductor layer, and may be formed to be in contact with the first semiconductor layer. I do not care. As a result, a semiconductor light emitting device of via type structure with high yield is realized.

In the above configuration,
In the first region, the surface on the side of the first semiconductor layer and the surface on the side of the second semiconductor layer include concavo-convex surfaces in the first region, while in the second region Both the surface on the semiconductor layer side and the surface on the second semiconductor layer side may be flat.

According to the above configuration, when forming the first electrode, the upper surface of the first semiconductor layer can be exposed to the active layer by etching the film thickness of the active layer. Thereby, the controllability of the etching process becomes easy, and the yield of the manufactured element is improved.

Here, the uneven surface of the active layer in the first region is composed of a nonpolar surface of a nitride semiconductor, and the flat surface of the active layer in the second region is composed of a polar surface of a nitride semiconductor It does not matter if you

In the semiconductor light emitting element made of a nitride semiconductor, there is another problem that the luminous efficiency is lowered due to the internal electric field. Conventionally, a semiconductor light emitting device using a nitride semiconductor has been manufactured by c-plane growth. Here, “c-plane growth” means epitaxial growth along a direction perpendicular to the c-plane, that is, along the c-axis.

In the c-axis direction, Ga atoms and N atoms are arranged asymmetrically. At this time, on the c-plane, which is the growth surface of the GaN layer, the Ga atomic surface containing only Ga atoms is slightly charged negatively, while the N atomic surface containing only N atoms is slightly negatively charged, as a result Spontaneous polarization occurs in the c-axis direction. In addition, when hetero-epitaxially growing a dissimilar semiconductor layer on a GaN crystal layer, compressive strain or tensile strain occurs in the GaN crystal due to the difference in lattice constant between the two, and piezoelectric polarization (piezoelectric polarization) in the c-axis direction in the GaN crystal Occurs.

The active layer generally has a quantum well structure. The above heteroepitaxial growth is required to form a quantum well structure. Therefore, when a semiconductor layer including an active layer is grown with the c-plane as a growth plane, an internal electric field due to spontaneous polarization or piezoelectric polarization is generated in the c-axis direction in the quantum well. As a result, the recombination probability of electrons and holes is lowered, and the light emission efficiency is lowered.

On the other hand, according to the above-described semiconductor light emitting device, the active layer is formed of nonpolar planes in the first region, so the internal electric field is reduced compared to the case where all active layers are formed of polar planes. And the recombination probability is improved.

Further, in the second region, the active layer is formed of a polar surface, so that a flat surface is formed in the region. Then, since the first electrode is formed in the second region formed by the flat surface, as described above, the dimensions of the adjacent first electrodes are made uniform, and between the elements in the case of manufacturing a plurality of elements. The dimensions of the first electrode can be made uniform, and thus the electrical characteristics between the elements can be made uniform.

In the second semiconductor layer, the surface located on the opposite side to the active layer in the first region includes a rough surface, and the surface located on the opposite side to the active layer in the second region May be configured as a flat surface.

In this case, when forming the first electrode, if the etching progresses and the second semiconductor layer is first exposed, the etching should proceed by the film thickness of the second semiconductor layer and the film thickness of the active layer. , And the first semiconductor layer can be exposed. Thereby, the controllability of the etching process becomes easy, and the yield of the manufactured element is improved.

The second semiconductor layer may have a flat surface on the side opposite to the active layer in the first area and the second area.

Conversely, the second semiconductor layer may be configured such that the surface opposite to the active layer in the first region and the second region includes an uneven surface. This uneven surface can be, for example, a surface intended to improve the light extraction efficiency.

In the second region, even if the surface of the second semiconductor layer opposite to the active layer is configured to include the uneven surface, as described above, the surface of the active layer on the first semiconductor layer side is Since the flat surface is formed, the etching amount is reduced as compared with the case where the first electrode is formed in the first region in which the surface on the first semiconductor layer side of the active layer is formed by the uneven surface. The effects that can be done are still played. That is, according to this configuration, an element with an improved yield can be realized while improving the light extraction efficiency.

Further, the semiconductor light emitting device is
A second electrode in contact with the second semiconductor layer,
The first electrode may be in contact with the first semiconductor layer in a state in which an insulating state is maintained with respect to the second electrode.

The present invention is also a method of manufacturing a semiconductor light emitting device,
Preparing a substrate (a);
In the upper layer of the substrate, in the first region, at least a nonpolar surface is a crystal growth surface, and in a second region different from the first region, a polar surface is a crystal growth surface, n-type or p-type nitridation Growing a first semiconductor layer made of a semiconductor semiconductor (b);
(C) growing an active layer made of a nitride semiconductor on the first semiconductor layer;
Growing a second semiconductor layer made of a nitride semiconductor of a conductivity type different from that of the first semiconductor layer on the active layer;
Etching the second semiconductor layer and the active layer in at least a part of the second region to expose the first semiconductor layer on the bottom surface;
And (f) forming the first electrode on at least a portion of the top surface of the first semiconductor layer exposed in a state of being electrically insulated from the second semiconductor layer and the active layer. .

According to this method, the device according to the first configuration is manufactured.

In the step (b), the first semiconductor layer is grown with the nonpolar plane as the crystal growth plane at least in the first region, and the first semiconductor layer is grown with the polar plane as the crystal growth plane in the second region. Thereby, in a state where the step (b) is completed, the unevenness is formed on the surface of the first semiconductor layer in the first region, while the surface of the first semiconductor layer becomes flat in the second region.

Thereafter, by performing step (c) after step (b), the surface located on the side of the first semiconductor layer in the first region is configured to include an uneven surface, while the surface different from the first region is It is possible to grow an active layer in which the surface located on the side of the first semiconductor layer in the two regions is a flat surface. Therefore, as described above, at the time of etching in step (e), the amount of etching required to expose the first semiconductor layer can be reduced, and a device with high yield can be realized.

Further, according to the above method, an active layer having a nonpolar plane as a crystal growth plane can be grown at least in the first region. Therefore, in the semiconductor light emitting device manufactured by the present method, the internal electric field is relaxed and the light emission efficiency is improved as compared with the semiconductor light emitting device having only the active layer whose crystal growth surface is the polar surface.

Various methods can be adopted as a method for realizing the step (b) described above.

For example, after the step (a), a third semiconductor layer made of a nitride semiconductor is grown on the upper surface of the substrate, and then the third semiconductor layer is stretched in a predetermined direction in the first region. A step (b1) of forming a groove (hereinafter referred to as a "first groove") is performed. The first groove has a depth within a range in which the surface of the substrate is not exposed.

After execution of the step (b1), the step (b2) of growing the third semiconductor layer again is performed. Before the step (b2) is performed, the uneven surface is formed by the presence of the first groove in the first region, and the third semiconductor layer is grown on the uneven surface to form the inside of the first region. In the above, the third semiconductor layer is formed with the growth surface at least a nonpolar surface. On the other hand, in the second region, a third semiconductor layer having a polar plane as a growth surface is formed.

After execution of the step (b2), the step (b3) of growing the first semiconductor layer is performed. The first semiconductor layer is formed on the growth surface of the third semiconductor layer so that at least the nonpolar surface is formed as the growth surface in the first region, and the polar surface is formed as the growth surface in the second region. Be done. The step (b) can be realized by the steps (b1) to (b3).

As another example, the step (b) may be realized by performing the step (b3) of growing the first semiconductor layer after the step (b1) is performed. That is, before the step (b3) is performed, the uneven surface is formed by the presence of the first groove in the first region, and the first semiconductor layer is grown on the uneven surface. In the region, a first semiconductor layer having at least a nonpolar surface as a growth surface is formed. On the other hand, in the second region, a first semiconductor layer having a polar surface as a growth surface is grown.

As still another example, after the step (a), the third semiconductor layer made of a nitride semiconductor is grown on the upper surface of the substrate, and then the step (b4) of growing the first semiconductor layer is performed. Thereafter, in the first region, a step (b5) of forming a groove extending in a predetermined direction is performed on the first semiconductor layer. Then, after the step (b5) is performed, the step (b6) of growing the first semiconductor layer is performed again. Before the step (b6) is performed, the uneven surface is formed by the presence of the first groove in the first region, and the first semiconductor layer is grown on the uneven surface to form the inside of the first region. In the second semiconductor layer, the first semiconductor layer having the nonpolar plane as the growth plane is formed, and in the second region, the first semiconductor layer having the polar plane as the growth plane is formed. The step (b) can be realized by the steps (b4) to (b6).

The step (e) is a step of etching the second semiconductor layer and the active layer in at least a part of the second region to form a groove in the bottom surface of which the first semiconductor layer is exposed. Yes,
The step (f) may be a step of filling the groove with a conductive material in a state of being electrically insulated from the second semiconductor layer and the active layer to form the first electrode. .

According to this method, the first electrode is filled in a groove penetrating the second semiconductor layer and the active layer (hereinafter referred to as “second groove” as appropriate), so a so-called semiconductor light emitting element of via structure type is obtained. To be realized. Thereby, the uniformity of the current distribution density is improved, and a semiconductor light emitting device suitable for high current driving is realized.

The step (e) may be a step of etching a plane parallel to the c-plane of the layer made of nitride semiconductor. Here, in the present specification, "a plane parallel to c-plane" refers to a c-plane and a plane substantially corresponding to c-plane, and a plane substantially corresponding to c-plane is inclined to c-plane The angle is in the range of 5 ° or less.

In the above method, after the step (d) is completed, before the start of the step (e), a step (g) may be formed to form a concavo-convex shape on the upper surface of the second semiconductor layer.

According to this method, an element with an improved yield can be realized while improving the light extraction efficiency.

In the above method, after the step (d) is completed, before the start of the step (e), a step (h) of forming a second electrode on the upper layer of the second semiconductor layer in the first region. Have
The step (f) may be a step of forming the first electrode in a state of being electrically insulated from the second electrode.

According to the above method, in the semiconductor light emitting device having the uneven shape on the surface of the active layer, the etching amount can be minimized when forming the first electrode, and a semiconductor light emitting device with high yield can be realized. Ru.

Next, the second configuration will be described.
In the second configuration, the surface opposite to the active layer in the first region is configured to include an uneven surface, while the surface opposite to the active layer is in the second region. The surface is composed of a flat surface.

According to the above-described semiconductor light emitting device, since the second semiconductor layer has the concavities and convexities formed on the surface opposite to the active layer, the amount of light capable of extracting the light emitted from the active layer to the outside of the device Increases to improve the light extraction efficiency.

The first electrode is formed to be in contact with the first semiconductor layer in a region where the active layer and the second semiconductor layer are not present. In the first electrode, the surface of the second semiconductor layer opposite to the active layer is not in the first region including the uneven surface, but opposite to the active layer of the second semiconductor layer. The surface located on the side is provided in a second area which is constituted by a flat surface.

In order to form a region in which the active layer and the second semiconductor layer do not exist, the second semiconductor layer and the active layer located in the region are formed, for example, by etching or the like. Since the upper surface of the second semiconductor layer is a flat surface, energy given at the time of etching can be uniformly given to the target portion. For this reason, when forming a plurality of first electrodes in the same element, etching regions for forming the first electrodes can be formed with the same dimensions. Therefore, the electrical characteristics between the manufactured devices can be made uniform, and a semiconductor light emitting device with high yield can be realized.

In the above element, the active layer may be made of a nitride semiconductor having a nonpolar plane as a crystal plane.

On the other hand, according to the above-described semiconductor light emitting device, since the active layer is formed of a nonpolar surface, the internal electric field is reduced as compared with the case where all the active layers are formed of polar surfaces, The probability is improved.

In the above configuration, both the surface located on the side of the first semiconductor layer and the surface located on the side of the second semiconductor layer across the first region and the second region are uneven. It does not matter as what is comprised including.

In another aspect, the active layer is flat over both the first region and the second region, and a surface located on the side of the first semiconductor layer and a surface located on the side of the second semiconductor layer It does not matter as what is comprised by the surface.

Also, the present invention is
Preparing a substrate (a);
Growing a first semiconductor layer made of an n-type or p-type nitride semiconductor on the upper layer of the substrate (b)
(C) growing an active layer made of a nitride semiconductor on the first semiconductor layer;
Growing a second semiconductor layer made of a nitride semiconductor of a conductivity type different from that of the first semiconductor layer on the active layer;
Forming a concavo-convex shape on at least a part of the upper surface of the second semiconductor layer located in the first region among the upper surfaces of the second semiconductor layer;
Etching the second semiconductor layer and the active layer in at least a part of the second region different from the first region to expose the first semiconductor layer on the bottom surface;
And (g) forming the first electrode on at least a portion of the top surface of the first semiconductor layer exposed in a state of being electrically insulated from the second semiconductor layer and the active layer. .

According to this method, the device according to the second configuration is manufactured.

According to the above method, a semiconductor light emitting device with improved light extraction efficiency is manufactured while achieving uniform dimensions among the devices.

In the above method, the step (b) may be a step of growing the first semiconductor layer with a nonpolar plane as a crystal growth plane. As a result, a semiconductor light emitting device in which the internal electric field is reduced and the recombination probability is improved is realized.

By the way, various methods can be adopted as a method for realizing the above-described step (b).

As an example, after the step (a), a third semiconductor layer made of a nitride semiconductor is grown on the upper surface of the substrate, and then a groove extending in a predetermined direction with respect to the third semiconductor layer (hereinafter Step (b1) of forming a single groove portion) is performed. The first groove has a depth within a range in which the surface of the substrate is not exposed.

After execution of the step (b1), the step (b2) of growing the third semiconductor layer again is performed. Before the step (b2) is performed, the uneven surface is formed by the presence of the first groove, and the third semiconductor layer is grown on the uneven surface to form a third semiconductor layer with at least a nonpolar surface as a growth surface. A semiconductor layer is formed.

After execution of the step (b2), the step (b3) of growing the first semiconductor layer is performed. The first semiconductor layer is formed on at least the nonpolar surface as the growth surface because the first semiconductor layer is to be continuously grown on the growth surface of the third semiconductor layer. The step (b) can be realized by the steps (b1) to (b3).

As another example, the step (b) may be realized by performing the step (b3) of growing the first semiconductor layer after the step (b1) is performed. That is, before the step (b3) is performed, the uneven surface is formed by the presence of the first groove portion, and the first semiconductor layer is grown on the uneven surface to form at least the nonpolar surface as the growth surface. The first semiconductor layer is formed.

As still another example, after the step (a), the third semiconductor layer made of a nitride semiconductor is grown on the upper surface of the substrate, and then the step (b4) of growing the first semiconductor layer is performed. Thereafter, a step (b5) of forming a groove extending in a predetermined direction is performed on the first semiconductor layer. Then, after the step (b5) is performed, the step (b6) of growing the first semiconductor layer is performed again. Before execution of the step (b6), the uneven surface is formed by the presence of the first groove portion, and the first semiconductor layer is grown on the uneven surface, so that at least the nonpolar surface is the growth surface. One semiconductor layer is formed. The step (b) can be realized by the steps (b4) to (b6).

The step (f) is a step of etching the second semiconductor layer and the active layer in at least a part of the second region to form a groove in the bottom surface of which the first semiconductor layer is exposed. Yes,
The step (g) may be a step of filling the groove with a conductive material in a state of being electrically insulated from the second semiconductor layer and the active layer to form the first electrode. .

The step (b) may be a step of growing the first semiconductor layer using a nonpolar surface as a crystal growth surface over the first region and the second region.

In the above method, after the step (d) is completed, before the start of the step (f), a step (h) of forming a second electrode on the upper layer of the second semiconductor layer in the first region. Have
The step (g) may be a step of forming the first electrode in a state of being electrically insulated from the second electrode.

According to the present invention, a semiconductor light emitting device with high yield can be realized.

It is drawing which shows typically the structure of the semiconductor light-emitting device of one Embodiment of 1st structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of one Embodiment of 1st structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of one Embodiment of 1st structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of one Embodiment of 1st structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of one Embodiment of 1st structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of one Embodiment of 1st structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of one Embodiment of 1st structure. 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It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of one Embodiment of 1st structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of one Embodiment of 1st structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of one Embodiment of 1st structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of one Embodiment of 1st structure. FIG. 17 is a diagram for describing the difference between the case where the etching is performed in the second region 104 and the case where the etching is performed in the first region 103 in step S9. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of another embodiment of a 1st structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of another embodiment of a 1st structure. It is drawing which shows typically another structure of the semiconductor light-emitting device of another embodiment of a 1st structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of another embodiment of a 1st structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of another embodiment of a 1st structure. It is drawing which shows typically another structure of the semiconductor light-emitting device of another embodiment of a 1st structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of another embodiment of 1st structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of another embodiment of a 1st structure. It is drawing which shows typically another structure of the semiconductor light-emitting device of another embodiment of a 1st structure. It is drawing which shows typically the structure of the semiconductor light-emitting device of 1st embodiment of 2nd structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment of 2nd structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment of 2nd structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment of 2nd structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment of 2nd structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment of 2nd structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment of 2nd structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment of 2nd structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment of 2nd structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment of 2nd structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment of 2nd structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment of 2nd structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment of 2nd structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment of 2nd structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment of 2nd structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment of 2nd structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment of 2nd structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of 1st embodiment of 2nd structure. It is drawing which shows typically the structure of the semiconductor light-emitting device of 2nd embodiment of 2nd structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of 2nd embodiment of 2nd structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of 2nd embodiment of 2nd structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of 2nd embodiment of 2nd structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of 2nd embodiment of 2nd structure. It is a process drawing which shows the manufacturing process of the semiconductor light-emitting device of 2nd embodiment of 2nd structure. It is another drawing which shows typically the structure of the semiconductor light-emitting device of 2nd embodiment of 2nd structure.

The semiconductor light emitting device of the present invention and the method of manufacturing the same will be described with reference to the drawings. In each of the drawings, the dimensional ratio of the drawings and the actual dimensional ratio do not necessarily coincide.

[First configuration]
The first configuration of the present invention will be described.

<Construction>
FIG. 1 is a drawing schematically showing the structure of a semiconductor light emitting element, and corresponds to an element called a so-called “via structure type”. In FIG. 1, (a) is a schematic plan view as viewed from the side opposite to the light extraction surface, and (b) is a schematic cross section when cut along line AA in (a). FIG. 10 is a diagram, and corresponds to a schematic cross-sectional view when cut by a plane formed in the [0001] direction and the [1-100] direction here.

In the present specification, the symbol “−” attached immediately before the numeral in parentheses indicating the Miller index indicates the inversion of the index, and is the same as “bar” in the drawings. Further, in the present specification, the {1-101} plane means a (1-101) plane and a plane that is crystallographically equivalent to the (1-101) plane, that is, a (10-11) plane, (01 It is a concept including a -11) plane, a (0-111) plane, a (-1101) plane, and a (-1011) plane. In the present specification, the <11-20> direction is the [11-20] direction and a direction crystallographically equivalent to the [11-20] direction, that is, the [1-210] direction, 2110] A concept including a [-1 120] direction, a [-12-10] direction, and a [2-1-10] direction.

Further, in the present specification, the term “AlGaN” simply means that the semiconductor is a nitride semiconductor containing Al and Ga, and the description of the composition ratio of Al and Ga is simply omitted. It is not intended to limit the case where the composition ratio of Al and Ga is 1: 1. The same applies to the notation of InGaN or AlInGaN.

The semiconductor light emitting device 101 includes a substrate 111, a first semiconductor layer 115, an active layer 117, a second semiconductor layer 119, and a first electrode 141. The first semiconductor layer 115 is formed in the upper layer of the substrate 111, the active layer 117 is formed in the upper layer of the first semiconductor layer 115, and the second semiconductor layer 119 is formed in the upper layer of the active layer 117. The semiconductor light emitting device 101 further includes a first electrode 141 and a second electrode 121.

Here, for convenience of explanation, as shown in FIG. 1B, the semiconductor light emitting device 101 is divided into two regions of a first region 103 and a second region 104. The second region 104 corresponds to the region where the first electrode 141 is formed and the region in the vicinity thereof, and the first region 103 is farther from the position where the first electrode 141 is disposed in the semiconductor light emitting device 101 than the second region 104. Corresponds to the area.

In the present embodiment, the active layer 117 is formed to include an uneven surface in the first region 103, while a flat surface is formed in the second region 104. The semiconductor light emitting element 101 has a hole 107 in the second region 104, and the first electrode 141 is formed so as to be inserted into the hole 107.

Hereinafter, an example of a detailed configuration of each element will be described.

(Substrate 111, Element Substrate 112)
The substrate 111 is made of, for example, a sapphire substrate. Further, the element substrate 112 is configured by providing a wiring pattern on a conductive substrate of CuW, W, Mo or the like, a semiconductor substrate of Si or the like, or an insulating substrate such as AlN. Note that, as shown in FIG. 1B, in the element substrate 112, insulation is provided between the region electrically connected to the first electrode 141 and the region electrically connected to the second electrode 121. Is secured. Although various methods can be adopted as a method for securing this insulation property, an example can be realized by patterning.

(Bonding layer 143)
The bonding layer 143 is made of, for example, Au-Sn, Au-In, Au-Cu-Sn, Cu-Sn, Pd-Sn, Sn or the like. The bonding layer 143 functions as a layer for securing the adhesion between the substrate 111 and the element substrate 112 when bonding the substrate 111 and the element substrate 112.

(Protective layer 142)
The protective layer 142 is made of, for example, a Pt-based metal (an alloy of Ti and Pt), W, Mo, Ni or the like. At the time of bonding via the bonding layer 143, the material constituting the bonding layer 143 diffuses to the second electrode 121 side, and the function of preventing a decrease in light extraction efficiency due to a decrease in reflectance at the second electrode 121 is performed. Play.

Note that as shown in FIG. 1B, a protective layer 142 may be provided on the upper surface of the first electrode 141 for the purpose of preventing the material constituting the bonding layer 143 from diffusing to the first electrode 141 side. Absent.

(First electrode 141)
The first electrode 141 is made of, for example, Cr-Au. As shown to Fig.1 (a), the semiconductor light-emitting device 101 of this embodiment is the structure which has the some 1st electrode 141 arrange | positioned discretely.

The first electrode 141 is formed by being inserted into the hole 107 which penetrates the second semiconductor layer 119 and the active layer 117 in the second region 104 and reaches the first semiconductor layer 115. In the present embodiment, the first semiconductor layer 115 is an n-type semiconductor layer, and the second semiconductor layer 119 is a p-type semiconductor layer. At this time, the first electrode 141 corresponds to the n-side electrode.

(Second electrode 121)
The second electrode 121 is formed on the surface of the second semiconductor layer 119, and can be made of, for example, a metal material containing an Ag-based metal (an alloy of Ni and Ag), Al, Rh, or the like. These materials are conductive materials capable of reflecting the light emitted from the active layer 117. With this configuration, light emitted from the active layer 117 toward the element substrate 112 can be reflected by the second electrode 121 and guided to the extraction surface side (substrate 111 side). , High light extraction efficiency is realized. In the present embodiment, the second electrode 121 corresponds to a p-side electrode.

(Insulating layer 154)
As described above, the insulating layer 154 has an insulating property between the first electrode 141 and the second electrode 121, an insulating property between the first electrode 141 and the second semiconductor layer 119, and the first electrode 141 and the active layer. It is provided for the purpose of securing insulation between it and 117. In the present embodiment, the insulating layer 154 is provided on a part of the outer surface of the first electrode 141 and a part of the surface of the second electrode 121 on the element substrate 112 side. The formation location and formation mode of the insulating layer 154 can be appropriately changed within the range that can be realized. The insulating layer 154 may be made of SiO ₂ , SiN, Zr ₂ O _3, Al ₂ O ₃ or the like.

(First semiconductor layer 115)
In the present embodiment, the first semiconductor layer 115 is composed of an n-type AlN layer. Incidentally, other AlN, general formula _{_{_{Al x2 Ga y2 In 1-x2}}} -y2 N may be composed of (0 ≦ x2 ≦ 1,0 ≦ y2 ≦ 1) n -type nitride semiconductor layer defined by. Further, in the present embodiment, as described later with reference to FIG. 2E etc., the first semiconductor layer 115 has a growth surface 115a parallel to a nonpolar surface (for example, {1-101} surface) and a polar surface (for example, Growth surface 115 b parallel to the {0001} plane).

(Active layer 117)
In the present embodiment, the active layer 117 has a configuration in which Al _{x 3} Ga _{1-x 3} N (0 <x 3 ≦ 1) / AlN is stacked in one cycle or multiple cycles. As an example, a light emitting layer made of Al _0.8 Ga _0.2 N and a barrier layer made of AlN are repeatedly formed in multiple cycles. The configuration of the active layer 117 is appropriately selected according to the light emission wavelength. Further, in the present embodiment, as in the first semiconductor layer 115, in the active layer 117, the growth surface 117a parallel to the nonpolar plane (eg {1-101} plane) and the polar plane (eg {0001} plane) are used. It has parallel growth surfaces 117b (see FIG. 2F described later). In the active layer 117, two types of nitride semiconductor layers (AlGaN or AlInGaN) having a difference in band gap energy by making the Al composition different may be stacked in one cycle or multiple cycles.

(Second semiconductor layer 119)
In the present embodiment, the second semiconductor layer 119 includes a p _- type cladding layer formed of p-type Al _{x 4} Ga _{1 -x 4} N (0 <x 4 ≦ 1) and p ⁺ -type GaN formed on the p-type cladding layer. And a p-type contact layer. The second electrode 121 is formed to be in contact with the p-type contact layer. The p-type contact layer may be made of p ⁺ -type Al _{x 5} Ga ₁ _-x ₅ N (0 <x5 ≦ 1).

(Third semiconductor layer 113)
In the present embodiment, the semiconductor light emitting device 101 includes the third semiconductor layer 113, and the first semiconductor layer 115 is formed on the third semiconductor layer 113. The first semiconductor layer 115 is a layer formed by epitaxial growth on the upper layer of the third semiconductor layer 113.

In the present embodiment, the third semiconductor layer 113 is formed of an AlN layer. In addition to AlN, a nitride semiconductor layer defined by the general formula Al _x ₁ Ga _{y 1} In _{1-x 1-y} N (0 ≦ x 1 ≦ 1, 0 ≦ y 1 ≦ 1) can be used. Incidentally, the emission wavelength from the _{_{_{Al x1 Ga y1 In 1-x1}}} -y1 N the In composition is preferably 1% or less, _{_{_{Al x1 Ga y1 In 1-x1}}} -y1 N Al composition, the active layer 117 It is appropriately selected accordingly.

The third semiconductor layer 113 has a groove (concave portion) 114 extending along a predetermined direction (here, the [11-20] direction) in the first region 103, while the second semiconductor layer 113 The groove portion 114 is not provided in the region 104. In the present embodiment, although the stretching direction of the groove portion 114 is the [11-20] direction, the stretching direction is a crystallographically equivalent direction to the [11-20] direction, that is, <11-20>. It may be a direction, or may be another direction.

According to this configuration, since the active layer 117 has the growth surface 117a (see FIG. 2F described later) parallel to the nonpolar surface, the influence of the internal electric field is suppressed, and the light emitting element with high light emission efficiency Is realized.

Further, in the via-structure-type semiconductor light emitting device, as shown in FIG. 1A, a plurality of via electrodes (corresponding to the first electrode 141 in this case) are generally formed on the same device. The second semiconductor layer 119 and the active layer 117 have a flat surface in the second region 104 in which the hole 107 in which the first electrode 141 is inserted is formed. As will be described later, the holes 107 are formed by etching, but the etching target surface is formed flat as described above, so that etching energy is uniformly applied to the surfaces of the second semiconductor layer 119 and the active layer 117. Can be given to Therefore, since the hole 107 for inserting the first electrode 141 can be formed with the same size, the electrical characteristics among the manufactured semiconductor light emitting devices 101 can be made uniform, and a high yield can be realized.

<Production method>
The method of manufacturing the semiconductor light emitting device 101 will be described with reference to FIGS. 1 and 2A to 2Q. 2A to 2G, 2N to 2Q, and 2H (b) to 2M (b) among the following drawings, as in FIG. 1 (b), at each time point This corresponds to a schematic cross-sectional view when the element is cut at a location corresponding to the line AA in FIG. 1 (a). 2H (a) to 2M (a) correspond to schematic plan views when the device at each time point is viewed from the side opposite to the light extraction surface, as in FIG. 1 (a).

(Step S1)
The substrate 111 is prepared (see FIG. 2A). As the substrate 111, a sapphire substrate having a (0001) plane can be used as an example.

As a preparation process, the substrate 111 is cleaned. As a more specific example of this cleaning, the growth substrate 111 is disposed in the processing furnace of a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, and hydrogen at a flow rate of, for example, 10 slm is disposed in the processing furnace. It is carried out by raising the temperature in the furnace to, for example, 1150 ° C. while flowing a gas.

This step S1 corresponds to the step (a).

(Step S2)
As shown in FIG. 2B, the third semiconductor layer 113 made of, for example, AlN is formed on the (0001) plane of the substrate 111. As an example of the specific method, while the furnace temperature of the MOCVD apparatus is set to a temperature of 900 ° C. to 1600 ° C., nitrogen gas and hydrogen gas are flowed as a carrier gas, and trimethylaluminum (TMA) and ammonia are treated as source gases Supply into the furnace. By setting the flow rate ratio (V / III ratio) of TMA and ammonia to a value of 10 or more and 4,000 or less, setting the growth pressure to a value of 1 kPa or more and 70 kPa or less, and adjusting the supply time appropriately, AlN of a desired film thickness is formed. Ru. Here, the third semiconductor layer 113 made of AlN and having a film thickness of 600 nm was formed.

In the case where Al _x ₁ Ga _{y 1} In _{1-x 1-y 1} N (0 <x1 ≦ 1, 0 ≦ y1 ≦ 1) is formed as the third semiconductor layer 113, trimethylgallium (in addition to TMA and ammonia TMG) and trimethylindium (TMI) may be supplied at predetermined flow rates according to the composition.

(Step S3)
As shown in FIG. 2C, in the third semiconductor layer 113, a groove (first groove) 114 along a predetermined, for example, <11-20> direction is applied to at least a part of the first region 103. Form. At this time, no groove is formed in the second region 104. As a result, the groove 114 is formed in the first region 103 and the groove 114 is not formed in the second region 104 on the top surface of the third semiconductor layer 113. In addition, it is preferable to control so that the groove part 114 is formed in the bottom of the groove part 114 in the depth in the range which the board | substrate 111 does not expose.

As an example of a specific method, the wafer obtained by performing to step S2 is taken out of the processing furnace, and <11-20 of the third semiconductor layer 113 is formed by photolithography and reactive ion etching (RIE). A plurality of grooves parallel to the direction are formed at predetermined intervals. In FIG. 2C, the groove 114 is stretched in the [11-20] direction which is one direction that is crystallographically equivalent to the <11-20> direction.

In the present step S3, as shown in FIG. 2D, the entire upper surface of the second region 104 may be made flat by etching the entire region of the second region 104 to form the groove portion 114a. Absent. Below, only when advancing a process from the state of FIG. 2C, it demonstrates.

This step S2-S3 corresponds to the step (b1).

(Step S4)
As shown in FIG. 2E, the first semiconductor layer 115 is formed on the upper surface of the third semiconductor layer 113 in which the groove portion 114 is formed along the <11-20> direction. As an example of the specific method, the wafer after completion of step S3 is again put into the furnace of the MOCVD apparatus, the furnace temperature of the MOCVD apparatus is set to a temperature of 900.degree. C. or more and 1600.degree. While flowing hydrogen gas, TMA, ammonia, tetraethylsilane as an n-type dopant, etc. are supplied into the processing furnace as source gases. By setting the flow rate ratio (V / III ratio) of TMA and ammonia to a value of 10 or more and 4,000 or less, setting the growth pressure to a value of 1 kPa or more and 70 kPa or less, and adjusting the supply time appropriately, AlN of a desired film thickness is formed. Ru. Here, the first semiconductor layer 115 made of n-type AlN having a film thickness of 3000 nm was formed.

Incidentally, as the first semiconductor layer 115, the case of forming the n-type _{_{_{Al x2 Ga y2 In 1-x2}}} -y2 N (0 <x2 ≦ 1,0 ≦ y2 ≦ 1) is, TMA, ammonia, a tetra ethyl silane In addition, TMG and TMI may be supplied at predetermined flow rates according to the composition.

By growing a crystal on the upper surface of the third semiconductor layer 113 in which the groove 114 having a depth to which the upper surface of the substrate 111 is not exposed is formed, a nonpolar surface (here, as an example) A first semiconductor layer 115 having a growth surface 115a parallel to the {1-101} plane is formed. In addition, the first semiconductor layer 115 has a growth surface 115 b parallel to the polar surface (here, {0001} as an example) in the second region 104, the upper surface of which is constituted only by the flat surface. Grow on. In the configuration shown in FIG. 2E, in the first region 103, the first semiconductor layer 115 has the growth surface 115b parallel to the polar plane at a part of the portion, but in the first region 103, The first semiconductor layer 115 may have only the growth surface 115 a parallel to the nonpolar plane.

This step S4 corresponds to the step (b3). Steps S2-S4 correspond to step (b).

(Step S5)
As shown in FIG. 2F, a first semiconductor layer having a growth surface 115a parallel to the nonpolar plane (here, {1-101} plane) and a growth plane 115b parallel to the polar plane (here, {0001} plane) An active layer 117 is grown on top of the surface 115. As a specific example of the method, the furnace temperature of the MOCVD apparatus is set to a temperature of 900 ° C. or more and 1600 ° C. or less, and nitrogen gas and hydrogen gas are flowed as a carrier gas, while TMA and ammonia as a source gas are filmed in the processing furnace. A step of supplying a predetermined time according to the thickness and a step of supplying TMA, TMG and ammonia as source gases into the processing furnace for a predetermined time according to the film thickness are repeated a predetermined number of times according to the number of cycles. Thereby, an active layer 117 made of multi-period Al _{x 3} Ga _{1-x 3} N (0 <x 3 ≦ 1) / AlN is formed.

Incidentally, as the active layer _{_{_{117, Al x3 Ga y3 In 1}}} -x3-y3 N (0 <x3 ≦ 1,0 ≦ y3 ≦ 1) / Al x4 Ga y4 In 1-x4-y4 N (0 <x4 ≦ 1, In the case of forming 0 ≦ y4 ≦ 1), TMA, ammonia, TMG and TMI may be supplied as source gases at predetermined flow rates according to the composition.

Since the first semiconductor layer 115 having the growth surface 115 a parallel to the nonpolar surface and the growth surface 115 b parallel to the polar surface is formed in step S 4, the epitaxial growth is performed in this step S 5 in this state. As shown in FIG. 2F, an active layer 117 having a growth surface 117a parallel to the nonpolar plane and a growth surface 117b parallel to the polar plane is formed. In particular, in the first region 103, an active layer 117 having a growth surface 117a parallel to the nonpolar plane and in the second region 104 a growth surface 117b parallel to the polar surface is formed. As shown in FIG. 2F, the active layer 117 may have a growth surface 117b parallel to the nonpolar plane in the first region 103.

This step S5 corresponds to the step (c).

(Step S6)
As shown in FIG. 2G, the second semiconductor layer 119 is grown on the upper surface of the active layer 117. As an example of a specific method, a bis-cyclopentan for forming a p-type impurity in addition to ammonia, TMA and TMG as source gases with an in-furnace pressure of 100 kPa and an in-furnace temperature of 830 ° C. in the MOCVD apparatus Further grow with dienyl magnesium (Cp ₂ Mg). As a result, the second semiconductor layer 119 formed of p-type Al _{x 4} Ga _{1 -x 4} N (0 <x4 ≦ 1) is formed on the active layer 117. The flow rate of the source gas may be further changed to form the p ⁺ -type GaN layer on the upper layer. In this case, the second semiconductor layer 119 is configured by the p-type Al _{x 4} Ga _{1 -x 4} N (0 <x 4 ≦ 1) and the p ⁺ -type GaN layer. Also, the p ⁺ -type GaN layer may be made of p ⁺ -type Al _{x 5} Ga ₁ _-x ₅ N (0 <x5 ≦ 1).

In the present embodiment, at the time when step S6 is completed, the upper surface of the second semiconductor layer 119 is configured by the uneven surface in the first region 103, and is configured by only the flat surface in the second region 104. .

This step S6 corresponds to the step (d).

(Step S7)
An activation process is performed on the wafer obtained through steps S1-S6. More specifically, activation treatment is performed at 650 ° C. for 15 minutes in a nitrogen atmosphere using an RTA (Rapid Thermal Anneal: rapid heating) apparatus.

(Step S8)
As shown in FIG. 2H, the second electrode 121 is formed on the top surface of the second semiconductor layer 119. Specifically, the second electrode 121 is selectively formed on the region other than the one or more island regions 124 on the upper surface of the second semiconductor layer 119. The wafer having undergone this step S8 has, on the upper surface, a region 124 in which the second semiconductor layer 119 is exposed in an island shape and a region in which the second electrode 121 is exposed. Here, the island region 124 is formed in the second region 104.

The specific formation method of the second electrode 121 is, for example, as follows.

First, a resist is applied by patterning to the region of the upper surface of the second semiconductor layer 119 corresponding to the region where the second electrode 121 is not formed. The area to which the resist is applied corresponds to an area where the first electrode 141 is to be formed later and an area close to the first electrode 141 where current tends to be concentrated. After that, Ag with a film thickness of 150 nm and Ni with a film thickness of 30 nm are formed on the entire surface including the upper surface of the resist by using, for example, a sputtering apparatus. Note that, as the material film, Ni having a film thickness of about 1.5 nm may be formed under the Ag layer in order to enhance the adhesion to the second semiconductor layer 119.

Next, after lifting off the resist, the second electrode is subjected to a contact annealing treatment at 400 ° C. to 550 ° C. (eg 400 ° C.) for 60 seconds to 300 seconds in a dry air or inert gas atmosphere using an RTA device or the like. Form 121. When annealing is performed in an inert gas atmosphere, the diffusion of Ag to the second semiconductor layer 119 side due to migration can be reduced, so the Schottky effect can be further enhanced than in the case of a dry air atmosphere.

This step S8 corresponds to the step (h).

(Step S9)
As shown in FIG. 2I, the surface of the second semiconductor layer 119 located in the second region 104 exposed through the step S8 is etched to expose the upper surface of the first semiconductor layer 115.

Specifically, a resist 151 is applied by patterning to the upper surface of the second electrode 121 formed at the end of step S8. Thereafter, using the resist 151 as a mask, the second semiconductor layer 119 and the active layer 117 are removed by dry etching using an ICP apparatus until a partial upper surface of the first semiconductor layer 115 is exposed. In the step S9, the first semiconductor layer 115 may be partially etched away. The groove part 107 is formed by this step S9. The groove portion 107 corresponds to the “second groove portion”.

In this step S9, etching is performed on the second semiconductor layer 119 and the active layer 117 in the second region 104 formed of a flat surface, so that the first semiconductor can be etched with the same size for adjacent portions as well. Layer 115 can be exposed. This point will be described with reference to FIG.

FIG. 3 is a diagram for explaining the difference between the case where the portion to be etched is in the second region 104 and the case in the first region 103 in the present step S9. FIG. 3A corresponds to the drawing when the first semiconductor layer 115 is exposed by etching the second semiconductor layer 119 and the active layer 117 in the first region 103 in step S9. FIG. 3 (b) corresponds to the drawing of FIG. 2I.

In the case of FIG. 3A, the second semiconductor layer 119 and the active layer 117 present in the etching target region each have an uneven surface. At this time, in a portion where the active layer 117 forms a recess toward the second semiconductor layer 119, the active layer 117 is active layer as compared to a portion forming a protrusion toward the second semiconductor layer 119. The contact surface between the semiconductor layer 117 and the first semiconductor layer 115 exists near the substrate 111. This is because, for example, in a portion where the upper surface of the second semiconductor layer 119 constitutes a convex, the active layer 117 is still present even if the etching proceeds until the upper surface of the first semiconductor layer 115 is exposed. Suggests exposure.

The groove portion 107 formed in step S9 later becomes a space for embedding the first electrode 141 for supplying a current to the first semiconductor layer 115. For this reason, in step S7, it is necessary to advance the etching until the upper surface of the first semiconductor layer 115 is exposed in the entire region of the bottom surface of the groove portion 107. In all the elements, the pitch and the height of the concavo-convex portion formed in the active layer 117 do not necessarily have the same dimension. Therefore, as shown in FIG. 3A, when the groove portion 107 is to be formed in the first region 103, it is necessary to secure a large etching amount d1, and the etching energy to be supplied is increased. There is a fear.

On the other hand, in the case of forming the groove portion 107 by etching the inside of the second region 104 as in the present embodiment, the film is formed regardless of the pitch or the height of the uneven portion formed in the active layer 117. The first semiconductor layer 115 can be exposed by advancing it by the etching amount d2 assumed in advance depending on the film thickness of each layer (117, 119). Further, in the present embodiment, the amount of etching d2 required to expose the upper surface of the first semiconductor layer 115 can be made smaller than the amount of etching d1 shown in FIG. The amount can be reduced.

This step S9 corresponds to step (e).

(Step S10)
Next, after lifting off the resist 151 formed in step S9, as shown in FIG. 2J, a resist 153 is formed on the central portion of the bottom of the groove 107 and the upper surface of the second electrode 121 by patterning. That is, the upper surface of the first semiconductor layer 115 is exposed to the outer periphery of the resist 153 at the bottom of the groove portion 107. Thereafter, the insulating layer 154 is formed on the entire surface. The insulating layer 154 can be used _{_{SiO 2, SiN, Zr 2 O}} 3, AlN, Al 2 O 3 or the like.

Thereafter, the resist 153 is lifted off as shown in FIG. 2K. At this time, the insulating layer 154 is formed on the inner side surface of the groove portion 107 and the partial upper surface of the second electrode 121.

(Step S11)
A resist 155 is formed on the upper surface of the second electrode 121 by patterning. Thereafter, a conductive material is deposited to form the first electrode 141 so as to fill the groove 107 (see FIG. 2K) (see FIG. 2L). As an example of a method of forming the first electrode 141, after Cr having a film thickness of 100 nm and Au having a film thickness of 0.5 to 3 μm are vapor deposited, annealing is performed at 250 ° C. for about 1 minute in a nitrogen atmosphere. Thereafter, the resist 155 is lifted off (see FIG. 2M).

By the steps S10 to S11, the first electrode 141 is formed in the groove portion 107 in a state of being electrically insulated from the second electrode 121. Steps S10 to S11 correspond to step (f).

(Step after)
The protective layer 142 and the bonding layer 143 are formed on the exposed upper surfaces of the first electrode 141 and the second electrode 121, and the element substrate 112 is bonded via the bonding layer 143 (see FIG. 1). A specific example is as follows.

The protective layer 142 is formed by forming Ti and Pt three cycles with an electron beam vapor deposition apparatus (EB apparatus), and then Ti and Au-Sn solder are vapor deposited on the upper surface (Pt surface) of the protective layer 142 Thus, the bonding layer 143 is formed. Then, an element substrate 112 for applying a voltage to each of the electrodes (141, 121) is bonded to each other through the bonding layer 143. As the element substrate 112, as described above, a conductive substrate of CuW, W, Mo or the like, a semiconductor substrate of Si or the like, or an insulating substrate of AlN or the like provided with a wiring pattern can be used.

<Another manufacturing method>
In the method described above, step (b) is performed by steps S2-S4, but step (b) can be realized in various ways. In addition, since step S5 and subsequent steps are the same as the above-mentioned contents, they are omitted.

The first method is a method of growing the first semiconductor layer 115 in the same manner as step S4, after performing the step (b2) of growing the third semiconductor layer 113 again from the state shown in FIG. 2C (FIG. 2N) reference). Before the step (b2) is performed, the uneven surface is formed by the presence of the groove 114 in the first region 103, and the third semiconductor layer 113 is grown on the uneven surface to form the first region. In 103, the third semiconductor layer 113 having at least a nonpolar surface as a growth surface is formed. On the other hand, in the second region 104, the third semiconductor layer 113 having a polar plane as a growth surface is formed. Therefore, by subsequently growing the first semiconductor layer 115, as shown in FIG. 2O, the first semiconductor layer 115 having the growth surface 115a parallel to the nonpolar plane is formed in the first region 103, and In the two regions 104, a first semiconductor layer 115 having a growth surface 115b parallel to the polar plane is formed.

In the second method, after the step (b4) of growing the first semiconductor layer 115 from the state shown in FIG. 2B, a groove is formed in a first region, for example, along a predetermined <11-20> direction. (B) is performed (see FIG. 2P). Then, after the step (b5) is performed, the step (b6) of growing the first semiconductor layer 115 is performed again. Before the step (b6) is performed, the uneven surface is formed by the presence of the groove in the first region 103, and the first semiconductor layer 115 is grown on the uneven surface, as shown in FIG. 2Q. As described above, while the first semiconductor layer 115 having at least a nonpolar surface as a growth surface is formed in the first region 103, the first semiconductor layer 115 having a polar surface as a growth surface in the second region 104 is formed. It is formed.

[Another embodiment]
Hereinafter, another embodiment regarding the first configuration will be described.

<1> In the above embodiment, as described with reference to FIG. 2G, after the step S6 is performed, the second semiconductor layer 119 has the concavo-convex formed on the upper surface in the first region 103, The upper surface is formed flat in the region 104. However, as shown in FIG. 4A, depending on the film forming conditions of the second semiconductor layer 119, the upper surface may be formed flat over both the first region 103 and the second region 104 after step S6 is performed. Absent.

Even in such a configuration, at the time of the etching according to step S9, as shown in FIG. 4B, the active layer 117 and the first semiconductor layer 115 are formed as flat surfaces in the second region 104, so The first semiconductor layer 115 can be exposed with an etching amount of the same size.

After the state of FIG. 4B, the semiconductor light emitting device 101 shown in FIG. 4C is manufactured by performing the steps after step S10 described above. In the above, FIG. 4A and FIG. 4B correspond to schematic cross-sectional views when cut at a point corresponding to the line AA in FIG. 4C (a) at each time point, and FIG. The semiconductor light emitting device 101 according to the embodiment is schematically shown following FIG.

<2> In the above another embodiment <1>, after the state of FIG. 4A, the upper surface of the exposed second semiconductor layer 119 is subjected to asperity processing before the start of the second electrode 121 forming step according to step S8. It does not matter (see FIG. 5A). This corresponds to step (g).

In FIG. 5A, the concavo-convex shape 105 is provided only in the first region 103 of the top surface of the second semiconductor layer 119. Such a configuration is, by way of example, the surface of the second semiconductor layer 119, with the second semiconductor layer 119 in the second region 104 masked, the second region in the first region 103 exposed. This is realized by immersing an alkaline solution such as KOH in the second semiconductor layer 119.

Even in such a configuration, at the time of the etching according to step S9, as shown in FIG. 5B, since the active layer 117 and the first semiconductor layer 115 are formed as flat surfaces in the second region 104, they are adjacent to each other. The first semiconductor layer 115 can be exposed with an etching amount of the same size. After the state of FIG. 5B, the semiconductor light emitting device 101 shown in FIG. 5C is manufactured by performing the steps after step S10 described above. According to the semiconductor light emitting device 101 shown in FIG. 5C, since the concavo-convex shape 105 is provided on a part of the surface of the second semiconductor layer 119, the light extraction efficiency to the outside can be improved.

Although the concavo-convex shape 105 is applied only to the first region 103 in FIG. 5A, as shown in FIG. 6A, the concavo-convex shape 105 may be applied to the entire top surface of the second semiconductor layer 119 in this step. Absent. Even in this case, since the active layer 117 is formed to have a flat surface in the second region 104, the first semiconductor layer can be etched with the same size to the adjacent portion during the etching according to step S9. 115 can be exposed (see FIG. 6B). After the state of FIG. 6B, the semiconductor light emitting device 101 shown in FIG. 6C is manufactured by performing the steps after step S10 described above.

<3> In the above embodiments, the first semiconductor layer 115 is described as an n-type semiconductor layer, and the second semiconductor layer 119 is described as a p-type semiconductor layer, but this is merely an example, and the configuration of the above embodiment It is not intended to exclude from the present invention a semiconductor light emitting device in which n-type and p-type are inverted.

<4> In the first embodiment, although the case where the extending direction of the groove portion 114 is the <11-20> direction has been described as an example, this is merely an example, and the active layer 117 is in the first region 103. The extending direction of the groove 114 may be another direction as long as growth can be performed with the growth surface 117a parallel to the nonpolar plane.

<5> In each of the above embodiments, the semiconductor light emitting device 101 of the via type structure in which the first electrode 141 is formed in the hole portion 107 has been described. However, for example, by using the second region 104 as the end region of the substrate 111, it is possible to realize the horizontal and flip chip type semiconductor light emitting device 101 with high yield.

[Second configuration]
The second configuration of the present invention will be described.

First Embodiment
A first embodiment of the present invention will be described.

<Construction>
FIG. 7 is a drawing schematically showing the structure of the semiconductor light emitting device of the second configuration, and corresponds to a device called a “via structure type”. In FIG. 7, (a) is a schematic plan view as viewed from the side opposite to the light extraction surface, and (b) is a schematic cross section when cut along the line AA in (a). FIG. 10 is a diagram, and corresponds to a schematic cross-sectional view when cut by a plane formed in the [0001] direction and the [1-100] direction here.

The semiconductor light emitting device 201 includes a substrate 211, a first semiconductor layer 215, an active layer 217, a second semiconductor layer 219, and a first electrode 241. The first semiconductor layer 215 is formed in the upper layer of the substrate 211, the active layer 217 is formed in the upper layer of the first semiconductor layer 215, and the second semiconductor layer 219 is formed in the upper layer of the active layer 217. The semiconductor light emitting device 201 further includes a first electrode 241 and a second electrode 221.

Here, for convenience of explanation, as shown in FIG. 7B, the semiconductor light emitting device 201 is divided into two regions of a first region 203 and a second region 204. The second region 204 corresponds to the region where the first electrode 241 is formed and the region in the vicinity thereof, and the first region 203 is farther from the position where the first electrode 241 is disposed in the semiconductor light emitting element 201 than the second region 204 Corresponds to the area.

In the present embodiment, the second semiconductor layer 219 is configured such that the surface located on the opposite side to the active layer 217 in the first region 203 includes an uneven surface, while the second semiconductor layer 219 includes the active layer 217 in the second region 204. The surface on the opposite side is composed of a flat surface. The semiconductor light emitting element 201 has a hole 207 in the second region 204, and the first electrode 241 is formed so as to be inserted into the hole 207.

(Substrate 211, element substrate 212)
The substrate 211 is made of, for example, a sapphire substrate. The element substrate 212 is configured by providing a wiring pattern on a conductive substrate of CuW, W, Mo or the like, a semiconductor substrate of Si or the like, or an insulating substrate of AlN or the like. As shown in FIG. 7B, in the element substrate 212, insulation is provided between a region electrically connected to the first electrode 241 and a region electrically connected to the second electrode 221. Is secured. Although various methods can be adopted as a method for securing this insulation property, an example can be realized by patterning. In the semiconductor light emitting device 201 shown in FIG. 7, the side of the substrate 211 constitutes a light extraction surface.

(Bonding layer 243)
The bonding layer 243 is made of, for example, Au-Sn, Au-In, Au-Cu-Sn, Cu-Sn, Pd-Sn, Sn or the like. The bonding layer 243 functions as a layer for securing the adhesion between the substrate 211 and the element substrate 212 when bonding the substrate 211 and the element substrate 212.

(Protective layer 242)
The protective layer 242 is made of, for example, a Pt-based metal (an alloy of Ti and Pt), W, Mo, Ni or the like. At the time of bonding via the bonding layer 243, the material constituting the bonding layer 243 is diffused to the second electrode 221 side, and the function of preventing a decrease in light extraction efficiency due to a decrease in reflectance at the second electrode 221 is performed. Play.

As shown in FIG. 7B, a protective layer 242 may be provided on the upper surface of the first electrode 241 for the purpose of preventing the material forming the bonding layer 243 from diffusing to the first electrode 241 side. Absent.

(First electrode 241)
The first electrode 241 is made of, for example, Cr-Au. As shown to Fig.7 (a), the semiconductor light-emitting device 201 of this embodiment is the structure which has the some 1st electrode 241 arrange | positioned discretely.

The first electrode 241 penetrates the second semiconductor layer 219 and the active layer 217 in the second region 204 and is formed by being inserted into the hole 207 reaching the first semiconductor layer 215. In the present embodiment, the first semiconductor layer 215 is an n-type semiconductor layer and the second semiconductor layer 219 is a p-type semiconductor layer. At this time, the first electrode 241 corresponds to an n-side electrode.

(Second electrode 221)
The second electrode 221 is formed on the surface of the second semiconductor layer 219, and can be made of, for example, a metal material containing an Ag-based metal (an alloy of Ni and Ag), Al, Rh, or the like. These materials are conductive materials capable of reflecting the light emitted from the active layer 217. With this configuration, light emitted from the active layer 217 toward the element substrate 212 can be reflected by the second electrode 221 and guided to the extraction surface side (the substrate 211 side). , High light extraction efficiency is realized. In the present embodiment, the second electrode 221 corresponds to a p-side electrode.

(Insulating layer 254)
As described above, the insulating layer 254 has the insulation between the first electrode 241 and the second electrode 221, the insulation between the first electrode 241 and the second semiconductor layer 219, and the first electrode 241 and the active layer. It is provided for the purpose of securing insulation between it and 217. In the present embodiment, the insulating layer 254 is provided on part of the outer surface of the first electrode 241 and part of the surface of the second electrode 221 on the element substrate 212 side, but the above-described object is The formation location and the formation mode of the insulating layer 254 can be appropriately changed within the range that can be realized. Note that the insulating layer 254 may be made of SiO ₂ , SiN, Zr ₂ O _3, Al ₂ O ₃ or the like.

(First semiconductor layer 215)
In the present embodiment, the first semiconductor layer 215 is composed of an n-type AlN layer. Incidentally, other AlN, general formula _{_{_{Al x2 Ga y2 In 1-x2}}} -y2 N may be composed of (0 ≦ x2 ≦ 1,0 ≦ y2 ≦ 1) n -type nitride semiconductor layer defined by. In the present embodiment, as described later with reference to FIG. 8D and the like, the first semiconductor layer 215 includes a growth surface 215a parallel to the nonpolar surface (for example, {1-101} surface) and a polar surface (for example, Growth surface 215 b parallel to the {0001} plane).

(Active layer 217)
In the present embodiment, the active layer 217 has a configuration in which Al _{x 3} Ga _{1-x 3} N (0 <x 3 ≦ 1) / AlN is stacked in one cycle or multiple cycles. As an example, a light emitting layer made of Al _0.8 Ga _0.2 N and a barrier layer made of AlN are repeatedly formed in multiple cycles. The configuration of the active layer 217 is appropriately selected according to the light emission wavelength. Further, in the present embodiment, as described later with reference to FIG. 8E and the like, the active layer 217 is a growth surface parallel to a nonpolar surface (for example, {1-101} surface), like the first semiconductor layer 215. 217a and a growth surface 217b parallel to a polar surface (eg, {0001} surface). In the active layer 217, two types of nitride semiconductor layers (AlGaN or AlInGaN) having a difference in band gap energy by making the Al composition different may be stacked in one cycle or multiple cycles.

(Second semiconductor layer 219)
In the present embodiment, the second semiconductor layer 219 is a p ⁺ -type GaN formed on the p-type cladding layer and a p-type cladding layer made of p-type Al _{x 4} Ga ₁ -X ₄ N (0 <x4 ≦ 1). And a p-type contact layer. The second electrode 221 is formed to be in contact with the p-type contact layer. The p-type contact layer may be made of p ⁺ -type Al _{x 5} Ga ₁ _-x ₅ N (0 <x5 ≦ 1).

(Third semiconductor layer 213)
In the present embodiment, the semiconductor light emitting device 201 includes the third semiconductor layer 213, and the first semiconductor layer 215 is formed on the third semiconductor layer 213. The first semiconductor layer 215 is a layer formed by epitaxial growth on the upper layer of the third semiconductor layer 213.

In the present embodiment, the third semiconductor layer 213 is formed of an AlN layer. In addition to AlN, a nitride semiconductor layer defined by the general formula Al _x ₁ Ga _{y 1} In _{1-x 1-y} N (0 ≦ x 1 ≦ 1, 0 ≦ y 1 ≦ 1) can be used. Incidentally, the emission wavelength from the _{_{_{Al x1 Ga y1 In 1-x1}}} -y1 N the In composition is preferably 1% or _{_{_{less, Al x1 Ga y1 In 1-}}} x1-y1 Al composition of N, the active layer 217 It is appropriately selected accordingly.

The third semiconductor layer 213 has a groove (concave portion) 214 extending along a predetermined direction (here, the [11-20] direction). In the present embodiment, although the stretching direction of the groove portion 214 is the [11-20] direction, the stretching direction is a crystallographically equivalent direction with respect to the [11-20] direction, that is, <11-20>. It may be a direction, or may be another direction.

According to this configuration, since the active layer 217 has the growth surface 217a (see FIG. 8E described later) parallel to the nonpolar surface, the influence of the internal electric field is suppressed, and the light emitting element with high light emission efficiency Is realized.

Further, in the via-structure-type semiconductor light emitting device, as shown in FIG. 7A, a plurality of via electrodes (corresponding to the first electrode 241 in this case) are usually formed on the same device. Then, in the second region 204 in which the hole portion 207 in which the first electrode 241 is inserted is formed, as described above, the upper surface of the second semiconductor layer 219 is configured to be a flat surface. As will be described later, the holes 207 are formed by etching. By thus forming the surface to be etched as a flat surface, etching energy can be uniformly applied to the active layer 217. Therefore, since the hole 207 for inserting the first electrode 241 can be formed with the same size, the electrical characteristics among the manufactured semiconductor light emitting elements 201 can be equalized, and a high yield can be realized.

<Production method>
The method of manufacturing the semiconductor light emitting device 201 according to the first embodiment will be described with reference to FIGS. 7 and 8A to 8Q. Of the following drawings, in each of FIGS. 8A to 8G, 8N to 8Q, and 8H (b) to 8M (b), as in FIG. 7 (b), at each time point This corresponds to a schematic cross-sectional view when the element is cut at a location corresponding to the line AA in FIG. 7A. Further, FIGS. 8H (a) to 8M (a) correspond to schematic plan views when the device at each time point is viewed from the side opposite to the light extraction surface, as in FIG. 7 (a).

(Step S21)
The substrate 211 is prepared (see FIG. 8A). As the substrate 211, a sapphire substrate having a (0001) plane can be used as an example.

As a preparation step, the substrate 211 is cleaned. As a more specific example of this cleaning, the growth substrate 211 is disposed in the processing furnace of a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, and hydrogen at a flow rate of, for example, 10 slm is provided in the processing furnace. It is carried out by raising the temperature in the furnace to, for example, 1150 ° C. while flowing a gas.

This step S21 corresponds to the step (a).

(Step S22)
As shown in FIG. 8B, a third semiconductor layer 213 made of, for example, AlN is formed on the (0001) plane of the substrate 211. As an example of the specific method, while the furnace temperature of the MOCVD apparatus is set to a temperature of 900 ° C. to 1600 ° C., nitrogen gas and hydrogen gas are flowed as a carrier gas, and trimethylaluminum (TMA) and ammonia are treated as source gases Supply into the furnace. By setting the flow rate ratio (V / III ratio) of TMA and ammonia to a value of 10 or more and 4,000 or less, setting the growth pressure to a value of 1 kPa or more and 70 kPA or less, and adjusting the supply time appropriately, AlN of a desired film thickness is formed. Ru. Here, the third semiconductor layer 213 made of AlN and having a film thickness of 600 nm was formed.

As the third semiconductor layer 213, when forming the _{_{_{Al x1 Ga y1 In 1-x1}}} -y1 N (0 <x1 ≦ 1,0 ≦ y1 ≦ 1) is, TMA, in addition to ammonia, trimethyl gallium ( TMG) and trimethylindium (TMI) may be supplied at predetermined flow rates according to the composition.

(Step S23)
As shown in FIG. 8C, a groove (first groove) 214 is formed in the third semiconductor layer 213 along, for example, a predetermined <11-20> direction. It is preferable to control so that the groove part 214 is formed in the bottom of the groove part 214 by the depth in the range which the board | substrate 211 does not expose.

As an example of the specific method, the wafer obtained by performing up to step S22 is taken out of the processing furnace, and <11-20 of the third semiconductor layer 213 is formed by photolithography and reactive ion etching (RIE). A plurality of grooves parallel to the direction are formed at predetermined intervals. In FIG. 8C, the groove portion 214 is stretched in the [11-20] direction which is one direction that is crystallographically equivalent to the <11-20> direction.

The present steps S22 to S23 correspond to the step (b1).

(Step S24)
As shown in FIG. 8D, the first semiconductor layer 215 is formed on the upper surface of the third semiconductor layer 213 in which the groove 214 is formed along the <11-20> direction. As an example of the specific method, the wafer after completion of step S23 is again put into the furnace of the MOCVD apparatus, the furnace temperature of the MOCVD apparatus is set to a temperature of 900.degree. C. to 1600.degree. While flowing hydrogen gas, TMA, ammonia, tetraethylsilane as an n-type dopant, etc. are supplied into the processing furnace as source gases. By setting the flow rate ratio (V / III ratio) of TMA and ammonia to a value of 10 or more and 4,000 or less, setting the growth pressure to a value of 1 kPa or more and 70 kPa or less, and adjusting the supply time appropriately, AlN of a desired film thickness is formed. Ru. Here, the first semiconductor layer 215 made of n-type AlN having a film thickness of 3000 nm was formed.

Incidentally, as the first semiconductor layer 215, the case of forming the n-type _{_{_{Al x2 Ga y2 In 1-x2}}} -y2 N (0 <x2 ≦ 1,0 ≦ y2 ≦ 1) is, TMA, ammonia, a tetra ethyl silane In addition, TMG and TMI may be supplied at a predetermined flow rate according to the composition.

By growing a crystal on the upper surface of the third semiconductor layer 213 in which the groove portion 214 having a depth to which the upper surface of the substrate 211 is not exposed is formed, a nonpolar surface (here, {1-101} as an example) is formed. A first semiconductor layer 215 having parallel growth surfaces 215a is formed. In the configuration shown in FIG. 8D, although the first semiconductor layer 215 has the growth surface 215b parallel to the polar surface at a part of the part, the growth surface parallel to the nonpolar surface is the first semiconductor layer 215. It may be a configuration having only 215a.

This step S24 corresponds to the step (b3). Steps S22 to S24 correspond to step (b).

(Step S25)
As shown in FIG. 8E, a first semiconductor layer having a growth surface 215a parallel to the nonpolar plane (here, {1-101} plane) and a growth plane 215b parallel to the polar plane (here, {0001} plane) An active layer 217 is grown on top of 215. As a specific example of the method, the furnace temperature of the MOCVD apparatus is set to a temperature of 900 ° C. or more and 1600 ° C. or less, and nitrogen gas and hydrogen gas are flowed as a carrier gas, while TMA and ammonia as a source gas are filmed in the processing furnace. A step of supplying a predetermined time according to the thickness and a step of supplying TMA, TMG and ammonia as source gases into the processing furnace for a predetermined time according to the film thickness are repeated a predetermined number of times according to the number of cycles. Thus, an active layer 217 made of multi-period Al _{x 3} Ga _{1-x 3} N (0 <x 3 ≦ 1) / AlN is formed.

Incidentally, as the active layer _{_{_{217, Al x3 Ga y3 In 1}}} -x3-y3 N (0 <x3 ≦ 1,0 ≦ y3 ≦ 1) / Al x4 Ga y4 In 1-x4-y4 N (0 <x4 ≦ 1, In the case of forming 0 ≦ y4 ≦ 1), TMA, ammonia, TMG, and TMI may be supplied as source gases at a predetermined flow rate according to the composition.

Since the first semiconductor layer 215 having the growth surface 215a parallel to the nonpolar surface and the growth surface 215b parallel to the polar surface is formed in step S24, the epitaxial growth is performed in this step S25 in this state. As shown in 8E, an active layer 217 is formed having a growth surface 217a parallel to the nonpolar plane and a growth surface 217b parallel to the polar plane. If the first semiconductor layer 215 has only the growth surface 215a parallel to the nonpolar plane in step S24, only the growth surface 217a parallel to the nonpolar plane is active in step S25. It may be configured to have

Step S25 corresponds to step (c).

(Step S26)
As shown in FIG. 8F, the second semiconductor layer 219 is grown on the upper surface of the active layer 217. As an example of a specific method, a bis-cyclopentan for forming a p-type impurity in addition to ammonia, TMA and TMG as source gases with an in-furnace pressure of 100 kPa and an in-furnace temperature of 830 ° C. in the MOCVD apparatus Further grow with dienyl magnesium (Cp ₂ Mg). Thus, the second semiconductor layer 219 formed of p-type Al _{x 4} Ga _{1 -x 4} N (0 <x4 ≦ 1) is formed in the upper layer of the active layer 217. The flow rate of the source gas may be further changed to form the p ⁺ -type GaN layer on the upper layer. In this case, the second semiconductor layer 219 is configured by the p-type Al _{x 4} Ga _{1 -x 4} N (0 <x 4 ≦ 1) and the p ⁺ -type GaN layer. Also, the p ⁺ -type GaN layer may be made of p ⁺ -type Al _{x 5} Ga ₁ _-x ₅ N (0 <x5 ≦ 1).

In the present embodiment, as shown in FIG. 8F, the upper surface of the second semiconductor layer 219 is formed to be a flat surface. By appropriately setting the film formation conditions of the second semiconductor layer 219, it is possible to make the upper surface of the second semiconductor layer 219 flat as described above.

This step S26 corresponds to the step (d).

(Step S27)
The activation process is performed on the wafer obtained through steps S21 to S26. More specifically, activation treatment is performed at 650 ° C. for 15 minutes in a nitrogen atmosphere using an RTA (Rapid Thermal Anneal: rapid heating) apparatus.

(Step S28)
Next, with respect to the second semiconductor layer 219 in the first region 203 exposed in the state where the second semiconductor layer 219 in the second region 204 is masked among the surfaces of the second semiconductor layer 219, Soak an alkaline solution such as KOH. As a result, as shown in FIG. 8G, the concavo-convex shape 205 is formed on the upper surface of the second semiconductor layer 219 only in the first region 203.

This step S28 corresponds to the step (e). Note that this step S28 may be performed before step S27.

(Step S29)
As shown in FIG. 8H, the second electrode 221 is formed on the top surface of the second semiconductor layer 219. Specifically, the second electrode 221 is selectively formed on a region other than the one or more island regions 224 on the upper surface of the second semiconductor layer 219. The wafer having undergone this step S29 has, on the upper surface, a region 224 in which the second semiconductor layer 219 is exposed in an island shape and a region in which the second electrode 221 is exposed. Here, the island region 224 is formed in the second region 204.

The specific formation method of the second electrode 221 is, for example, as follows.

First, a resist is applied by patterning to the region of the upper surface of the second semiconductor layer 219 corresponding to the region where the second electrode 221 is not formed. The region to which the resist is applied corresponds to a region where the first electrode 241 is to be formed later and a region near the first electrode 241 where current tends to be concentrated. After that, Ag with a film thickness of 150 nm and Ni with a film thickness of 30 nm are formed on the entire surface including the upper surface of the resist by using, for example, a sputtering apparatus. As the material film, Ni may be formed to a film thickness of about 1.5 nm under the Ag layer in order to enhance the adhesion to the second semiconductor layer 219.

Next, after lifting off the resist, the second electrode is subjected to a contact annealing treatment at 400 ° C. to 550 ° C. (eg 400 ° C.) for 60 seconds to 300 seconds in a dry air or inert gas atmosphere using an RTA device or the like. Form 221 When annealing is performed in an inert gas atmosphere, the diffusion of Ag to the second semiconductor layer 219 side due to migration can be reduced, so the Schottky effect can be further enhanced compared to the case of a dry air atmosphere.

This step S29 corresponds to step (h).

(Step S30)
As shown in FIG. 8I, the surface of the second semiconductor layer 219 located in the second region 204 and exposed through the step S29 is etched to expose the top surface of the first semiconductor layer 215.

Specifically, a resist 251 is applied to the upper surface of the second electrode 221 formed at the end of step S29 by patterning. Thereafter, using the resist 251 as a mask, the second semiconductor layer 219 and the active layer 217 are removed by dry etching using an ICP apparatus until a partial upper surface of the first semiconductor layer 215 is exposed. In the step S30, the first semiconductor layer 215 may be partially etched away. The groove portion 207 is formed by the present step S30. The groove portion 207 corresponds to the “second groove portion”.

The groove portion 207 formed in step S30 later becomes a space for embedding the first electrode 241 for supplying a current to the first semiconductor layer 215. Therefore, in step S30, it is necessary to advance the etching until the surface of the first semiconductor layer 215 is exposed in the entire region of the bottom surface of the groove portion 207.

Here, a case where this step S30 is performed on the surface of the second semiconductor layer 219 on which the concavo-convex shape 205 is formed in step S28 will be examined. Since the wet etching process performed in step S28 has poor controllability compared to dry etching, the pitch and height of the concavo-convex shape 205 formed on the surface of the second semiconductor layer 219 are randomly determined. As a result, in the present step S30, it is assumed that the etching amount required to expose the surface of the first semiconductor layer 215 in the entire region of the bottom surface of the groove portion 207 differs from element to element. For this reason, in order to reliably expose the surface of the first semiconductor layer 215 in the entire region of the bottom surface of the groove portion 207 in each element to be manufactured, it is necessary to secure a large etching amount in the etching step. . As a result, the supplied etching energy may be increased.

In addition, since the concavo-convex shape 205 is formed on the surface of the semiconductor layer at the start of etching, the etching energy to be introduced is easily dispersed in the plane direction parallel to the substrate 211, and the etching is difficult to progress at the beginning of the etching The etching energy supplied may be increased.

On the other hand, when the inside of the second region 204 is etched to form the groove portion 207 as in the present embodiment, the upper surface of the second semiconductor layer 219 relating to the etching target region is formed flat. The shape of the active layer 217 can be controlled by the thickness of the first semiconductor layer 215 and the pitch and depth of the grooves 207. That is, based on the information such as the thickness of the first semiconductor layer 215 and the pitch and depth of the groove portion 207 set in the step prior to the step S29, the etching is advanced to what depth in the step S30. Then, it can be estimated in advance whether the surface of the first semiconductor layer 215 can be exposed. That is, with the method according to the present embodiment, the amount of energy to be applied at the time of etching can be made smaller than when etching the inside of the first region 203.

Step S30 corresponds to step (f).

(Step S31)
Next, after lifting off the resist 251 formed in step S30, as shown in FIG. 8J, a resist 253 is formed on the central portion of the bottom of the groove portion 207 and the upper surface of the second electrode 221 by patterning. That is, the upper surface of the first semiconductor layer 215 is exposed to the outer periphery of the resist 253 on the bottom surface of the groove portion 207. After that, the insulating layer 254 is formed over the entire surface. As the insulating layer 254, SiO _2, SiN, Zr ₂ O ₃ , AlN, Al ₂ O ₃ or the like can be used.

Thereafter, the resist 253 is lifted off as shown in FIG. 8K. At this time, the insulating layer 254 is formed on the inner side surface of the groove portion 207 and the partial upper surface of the second electrode 221.

(Step S32)
A resist 255 is formed on the upper surface of the second electrode 221 by patterning. Thereafter, a conductive material is deposited to form the first electrode 241 so as to fill the groove portion 207 (see FIG. 8L). As an example of a method of forming the first electrode 241, after Cr having a film thickness of 100 nm and Au having a film thickness of 0.5 to 3 μm are deposited, annealing is performed at 250 ° C. for about 1 minute in a nitrogen atmosphere. Thereafter, the resist 255 is lifted off (see FIG. 8M).

By the steps S31 to S32, the first electrode 241 is formed in the groove portion 207 in a state of being electrically insulated from the second electrode 221. Steps S31 to S32 correspond to step (g).

(Step after)
The protective layer 242 and the bonding layer 243 are formed on the exposed upper surfaces of the first electrode 241 and the second electrode 221, and the element substrate 212 is bonded via the bonding layer 243 (see FIG. 7). A specific example is as follows.

The protective layer 242 is formed by forming Ti and Pt three cycles with an electron beam vapor deposition apparatus (EB apparatus), and then Ti and Au-Sn solder are vapor deposited on the upper surface (Pt surface) of the protective layer 242 Thus, the bonding layer 243 is formed. Then, an element substrate 212 for applying a voltage to each electrode (41, 21) is bonded to each other through the bonding layer 243. As the element substrate 212, as described above, a conductive substrate of CuW, W, Mo or the like, a semiconductor substrate of Si or the like, or an insulating substrate of AlN or the like provided with a wiring pattern can be used.

<Another manufacturing method>
In the above-described method, step (b) is performed by steps S22 to S24, but step (b) can be realized by various methods. In addition, since step S25 and subsequent steps are the same as the contents described above, they are omitted.

The first method is a method of growing the first semiconductor layer 215 in the same manner as step S24 after performing the step (b2) of growing the third semiconductor layer 213 again from the state shown in FIG. 8C (FIG. 8N). reference). Before the step (b2) is performed, the uneven surface is formed by the presence of the groove 214 in the first region 203, and the third semiconductor layer 213 is grown on the uneven surface to at least a nonpolar surface. The third semiconductor layer 213 having the surface 213a as a growth surface is formed. Therefore, by subsequently growing the first semiconductor layer 215, as shown in FIG. 8O, the first semiconductor layer 215 having the growth surface 215a at least parallel to the nonpolar plane is formed.

In the second method, after the step (b4) of growing the first semiconductor layer 215 from the state shown in FIG. 8B, the step (b5) of forming a groove along a predetermined <11-20> direction is performed. It is the method to implement (refer FIG. 8P). Then, after the step (b5) is performed, the step (b6) of growing the first semiconductor layer 215 is performed again. Before execution of the step (b6), the first semiconductor layer 215 has an uneven surface, and the first semiconductor layer 215 is regrown on the uneven surface, as shown in FIG. 8Q. A first semiconductor layer 215 is formed having a growth surface 215a parallel to the polar plane.

Second Embodiment
A second embodiment of the present invention will be described. In the present embodiment, the elements common to the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

<Construction>
FIG. 9 is a drawing schematically showing the structure of the semiconductor light emitting device of the second embodiment of the second configuration. FIG. 9 is a schematic plan view as seen from the side opposite to the light extraction surface, as in FIG. 7, and (b) is taken along the line AA in (a) It is a typical sectional view of the time. The same reference numerals are given to elements common to the first embodiment. Note that, since the semiconductor light emitting element 201a of this embodiment does not have a structure in which the nonpolar surface is a growth surface, unlike the first embodiment, the Miller index is not displayed in the drawing.

Also in the semiconductor light emitting device 201a of the present embodiment, as in the first embodiment, the second semiconductor layer 219 is configured such that the surface located on the opposite side to the active layer 217 in the first region 203 is an uneven surface. On the other hand, the surface opposite to the active layer 217 in the second region 204 is a flat surface. The semiconductor light emitting element 201 has a hole 207 in the second region 204, and the first electrode 241 is formed so as to be inserted into the hole 207.

Also in the semiconductor light emitting device 201a of the present embodiment, the island-shaped region 224 is formed by etching as in the first embodiment. As shown in FIG. 9, the etching target surface is formed to be a flat surface, so that etching energy can be uniformly applied to the active layer 217. Therefore, since the hole 207 for inserting the first electrode 241 can be formed with the same size, the electrical characteristics among the manufactured semiconductor light emitting devices 201a can be made uniform, and a high yield can be realized.

<Production method>
The method of manufacturing the semiconductor light emitting device 201a according to the second embodiment will be described with reference to FIGS. 9 and 10A to 10E. In each of FIGS. 10A to 10B and 10C (b) to 10E (b), as in FIG. 9 (b), the elements at each time point are taken along AA in FIG. 9 (a). It corresponds to a schematic cross-sectional view when cut at a portion corresponding to a line. 10C (a) to 10E (a) correspond to schematic plan views when the device at each time point is viewed from the side opposite to the light extraction surface, as in FIG. 9A. In addition, description is omitted about the part common to 1st embodiment.

(Step S41)
As in step S21, the substrate 211 is prepared. As the substrate 211, a sapphire substrate having a (0001) plane can be used as an example. Step S41 corresponds to step (a).

(Steps S42 to S44)
As shown in FIG. 10A, the first semiconductor layer 215, the active layer 217, and the second semiconductor layer 219 are formed on the substrate 211. An example of a specific method is as follows.

(Step S42)
First, a low temperature buffer layer made of GaN is formed on the surface of the substrate 211, and an underlayer made of GaN is formed thereon. These low temperature buffer layers and underlayers correspond to the undoped layer 236. A specific method of forming the undoped layer 236 is, for example, as follows. First, the pressure in the furnace of the М CVD apparatus is 100 kPa, and the temperature in the furnace is 480 ° C. Then, while flowing nitrogen gas and hydrogen gas each having a flow rate of 5 slm as a carrier gas in the processing furnace, TMG having a flow rate of 50 μmol / min and ammonia having a flow rate of 250,000 μmol / min as a source gas for 68 seconds in the processing furnace Supply. Thereby, a low temperature buffer layer of 20 nm thick made of GaN is formed on the surface of the substrate 211.

Next, the temperature in the furnace of the MOCVD apparatus is raised to 1150 ° C. Then, while flowing nitrogen gas having a flow rate of 20 slm and hydrogen gas having a flow rate of 15 slm as a carrier gas in the processing furnace, TMG having a flow rate of 100 μmol / min and ammonia having a flow rate of 250000 μmol / min as a source gas in the processing furnace Feed for 30 minutes. Thereby, an underlayer of 1.7 μm in thickness made of GaN is formed on the surface of the low temperature buffer layer.

Then, the first semiconductor layer 215 is formed on the undoped layer 236. Subsequently, with the temperature in the furnace being 1150 ° C., the pressure in the furnace of the MOCVD apparatus is 30 kPa. Then, while flowing nitrogen gas having a flow rate of 20 slm and hydrogen gas having a flow rate of 15 slm as carrier gas, TMG having a flow rate of 94 μmol / min, TMA having a flow rate of 6 μmol / min, and a flow rate of 250,000 μmol / min as a carrier gas. Ammonia of min and tetraethylsilane with a flow rate of 0.013 μmol / min are fed into the processing furnace for 60 minutes. Thereby, a first semiconductor layer 215 having a composition of Al _0.06 Ga _0.94 N, a Si concentration of 5 × 10 ¹⁹ / cm ³ , and a thickness of 2 μm is formed on the upper layer of the undoped layer 236.

After that, the supply of TMA is stopped, and the source gas other than that is supplied for 6 seconds, thereby providing a protective layer made of n-type GaN having a thickness of about 5 nm on the upper layer of the n-type AlGaN layer. The semiconductor layer 215 may be realized.

In the above description, the n-type impurity contained in the first semiconductor layer 215 is Si, but Ge, S, Se, Sn, Te, or the like can be used as the n-type impurity in addition to Si. .

This step S42 corresponds to the step (b).

(Step S43)
Next, in the upper layer of the first semiconductor layer 215, an active layer 217 in which a light emitting layer composed of, for example, InGaN and a barrier layer composed of n-type AlGaN are periodically repeated is formed.

Specifically, first, the pressure in the furnace of the MOCVD apparatus is 100 kPa, and the temperature in the furnace is 830.degree. Then, while flowing nitrogen gas having a flow rate of 15 slm and hydrogen gas having a flow rate of 1 slm as carrier gas in the processing furnace, TMG having a flow rate of 10 μmol / min and TMI having a flow rate of 12 μmol / min and a flow rate of 300000 μmol / min as source gases. The step of supplying min ammonia for 48 seconds into the processing furnace is performed. Thereafter, a step of supplying TMG with a flow rate of 10 μmol / min, TMA with a flow rate of 1.6 μmol / min, tetraethylsilane with a 0.002 μmol / min and ammonia with a flow rate of 300000 μmol / min into the treatment furnace for 120 seconds. Hereinafter, by repeating these two steps, the active layer 217 in which the light emitting layer made of InGaN and the barrier layer made of n-type AlGaN having a thickness of 7 nm are repeated 15 cycles is repeated by repeating the two steps. Formed in the upper layer of

This step S43 corresponds to the step (c).

(Step S44)
Next, the second semiconductor layer 219 made of, for example, AlGaN is formed on the active layer 217. The specific formation method of the second semiconductor layer 219 is, for example, as follows.

Specifically, the pressure in the furnace of the MOCVD apparatus is maintained at 100 kPa, and the temperature in the furnace is raised to 1025 ° C. while flowing nitrogen gas with a flow rate of 15 slm and hydrogen gas with a flow rate of 25 slm into the processing furnace as carrier gas. Do. Thereafter, as source gases, TMG with a flow rate of 35 μmol / min, TMA with a flow rate of 20 μmol / min, Cp ₂ Mg with a flow rate of 0.1 μmol / min for doping ammonia with a flow rate of 250000 μmol / min Supply to the processing furnace for 60 seconds. Thereby, on the surface of the active layer 33, a hole supply layer having a composition of Al _0.3 Ga _0.7 N having a thickness of 20 nm is formed. Thereafter, the flow rate of TMA is changed to 4 μmol / min and the source gas is supplied for 360 seconds to form a hole supply layer having a composition of Al _0.13 Ga _0.87 N with a thickness of 120 nm. The second semiconductor layer 219 is formed by these hole supply layers.

After that, while stopping the supply of TMA and changing the flow rate of Cp ₂ Mg to 0.2 μmol / min and supplying the source gas for 20 seconds, the thickness is about 5 nm and the p-type impurity concentration is 1 × A p-type contact layer of about 10 ²⁰ / cm ³ may be formed. In this case, the second semiconductor layer 219 also includes this p-type contact layer.

This step S44 corresponds to the step (d).

(Step S45)
An activation process is performed on the wafer. More specifically, activation treatment is performed at 650 ° C. for 15 minutes in a nitrogen atmosphere using an RTA (Rapid Thermal Anneal: rapid heating) apparatus.

(Step S46)
Next, with respect to the second semiconductor layer 219 in the first region 203 exposed in the state where the second semiconductor layer 219 in the second region 204 is masked among the surfaces of the second semiconductor layer 219, Soak an alkaline solution such as KOH. As a result, as shown in FIG. 10B, the concavo-convex shape 205 is formed on the top surface of the second semiconductor layer 219 only in the first region 203.

This step S46 corresponds to the step (e). The present step S26 may be performed before step S45.

(Step S47)
As shown in FIG. 10C, the second electrode 221 is formed as in step S29. Step S47 corresponds to step (h).

(Step S48)
As shown in FIG. 10D, as in step S30, the upper surface of the first semiconductor layer 215 is etched by etching the surface of the second semiconductor layer 219 located in the second region 204 exposed through step S47. Expose the In this step S48, as in step S30 in the first embodiment, the etching is performed on the second semiconductor layer 219 in the second region 204 and the active layer 217 below the second region 204, the upper surface of which is formed as a flat surface. Therefore, the first semiconductor layer 215 can be exposed to the adjacent portion with the same amount of etching amount.

Step S48 corresponds to step (f).

(Step S49)
As shown in FIG. 10E, the insulating layer 254 and the first electrode 241 are formed in the same manner as in steps S31 to S32. Step S49 corresponds to step (g).

(Step after)
After that, the semiconductor light emitting device 201a as shown in FIG. 9 is realized through the same steps as the first embodiment.

Note that after this, a step of peeling the substrate 211 may be performed. As a more specific example, with the substrate 211 facing up and the element substrate 212 facing downward, a KrF excimer laser is irradiated from the substrate 211 side to decompose the interface between the substrate 211 and the epitaxial layer. Peel 211. Thereafter, the GaN (undoped layer 236) remaining on the wafer is removed by wet etching using hydrochloric acid or the like or dry etching using an ICP apparatus to expose the first semiconductor layer 215. Through this process, the semiconductor light emitting device 201a shown in FIG. 11 is realized. FIG. 11 is a schematic plan view when (a) is viewed from the light extraction surface side (the first semiconductor layer 215 side), and (b) is a cut along line AA in (a) of the element 201a. It is typical sectional drawing at the time of.

[Another embodiment]
Hereinafter, another embodiment of the second configuration will be described.

<1> In the configuration of the first embodiment, the case where the active layer 217 has the growth surface 217a parallel to the nonpolar plane in both the first region 203 and the second region 204 has been described. However, the active layer 217 may have a growth surface 217 a parallel to the nonpolar surface in at least a part of the area.

<2> In the first embodiment, the case where the extending direction of the groove portion 214 is the <11-20> direction has been described as an example, but this is merely an example, and the active layer 217 is parallel to the nonpolar surface The extending direction of the groove portion 214 may be another direction as long as growth can be performed with the growth surface 217a.

<3> In the above embodiments, the first semiconductor layer 215 is described as an n-type semiconductor layer, and the second semiconductor layer 219 is described as a p-type semiconductor layer, but this is merely an example, and the configuration of the above embodiment It is not intended to exclude from the present invention a semiconductor light emitting device in which n-type and p-type are inverted.

<4> In each of the above embodiments, the semiconductor light emitting device 201 having the via type structure in which the first electrode 241 is formed in the hole portion 207 has been described. However, for example, by using the second region 204 as the end region of the substrate 211, it is possible to realize the horizontal or flip chip type semiconductor light emitting device 201 with high yield.

101: Semiconductor light emitting element 103: First region 104: Second region 105: Irregular shape 107: Hole / groove (second groove)
111: Substrate 112: Element substrate 113: Third semiconductor layer 114: Groove (first groove)
114a: Groove (first groove)
115: first semiconductor layer 117: active layer 119: second semiconductor layer 121: second electrode 124: island-like region 141: first electrode 142: protective layer 143: bonding layer 151: resist 153: resist 154: insulating layer 155 : Resist 201, 201a: Semiconductor light emitting element 203: First region 204: Second region 205: Irregular shape 207: Hole / groove (second groove)
211: Substrate 212: Element substrate 213: Third semiconductor layer 214: Groove (first groove)
215: first semiconductor layer 215a: nonpolar surface of first semiconductor layer 215b: polar surface of first semiconductor layer 217: active layer 217a: nonpolar surface of active layer 217b: polar surface of active layer 219: second semiconductor layer 221: second electrode 224: island region 236: undoped layer 241: first electrode 242: protective layer 243: bonding layer 251: resist 253: resist 254: insulating layer 255: resist

Claims

A substrate,
A first semiconductor layer formed of an n-type or p-type nitride semiconductor formed in the upper layer of the substrate;
An active layer formed of a nitride semiconductor, formed on the upper layer of the first semiconductor layer;
A second semiconductor layer formed of a nitride semiconductor of a conductivity type different from the first semiconductor layer, formed in the upper layer of the active layer;
And a first electrode formed in contact with the first semiconductor layer,
At least one of the active layer and the first semiconductor layer includes an uneven surface in a first region in a direction parallel to the surface of the substrate, and a second region different from the first region is a flat surface.
The first electrode is formed in the second region so as to be in contact with the first semiconductor layer and to have insulation with respect to the active layer and the second semiconductor layer.
In the second region, the active layer and the second semiconductor layer are not formed on the upper layer of the first semiconductor layer located in the region in contact with the first electrode. element.
The active layer is configured such that the surface located on the side of the first semiconductor layer in the first region includes an uneven surface, and the surface located on the side of the first semiconductor layer in the second region is The semiconductor light emitting device according to claim 1, wherein the semiconductor light emitting device is constituted by a flat surface.
In the second region, it has a hole which penetrates at least the second semiconductor layer and the active layer and reaches the first semiconductor layer,
The first electrode is inserted into the hole in a state in which an insulating state is maintained with respect to the active layer and the second semiconductor layer, and the first electrode is formed to be in contact with the first semiconductor layer. The semiconductor light emitting device according to claim 2.
The uneven surface of the active layer in the first region is composed of a nonpolar surface of a nitride semiconductor, and the flat surface of the active layer in the second region is composed of a polar surface of a nitride semiconductor The semiconductor light emitting device according to claim 2 or 3, characterized in that
In the second semiconductor layer, the surface located on the opposite side to the active layer in the first region includes a rough surface, and the surface located on the opposite side to the active layer in the second region The semiconductor light emitting device according to any one of claims 2 to 4, characterized in that
The second semiconductor layer is characterized in that a surface opposite to the active layer in the first region and the second region includes an uneven surface. The semiconductor light-emitting device according to any one of 4.
The second semiconductor layer is characterized in that a surface located on the opposite side to the active layer in the first region and the second region is a flat surface. The semiconductor light-emitting device according to any one of the above.
A second electrode in contact with the second semiconductor layer,
The semiconductor according to any one of claims 2 to 7, wherein the first electrode is in contact with the first semiconductor layer in a state in which an insulating state is maintained with respect to the second electrode. Light emitting element.
The method of manufacturing a semiconductor light emitting device according to claim 2,
Preparing the substrate (a);
In the upper layer of the substrate, at least a nonpolar surface is a crystal growth surface in the first region, and a polar surface is a crystal growth surface in the second region different from the first region, n-type or p-type Growing the first semiconductor layer comprising a nitride semiconductor of
Growing the active layer of nitride semiconductor on top of the first semiconductor layer (c);
Growing the second semiconductor layer made of a nitride semiconductor of a conductivity type different from that of the first semiconductor layer on the active layer;
Etching the second semiconductor layer and the active layer in at least a part of the second region to expose the first semiconductor layer on the bottom surface;
And (f) forming the first electrode on at least a portion of the top surface of the first semiconductor layer exposed in a state of being electrically insulated from the second semiconductor layer and the active layer. Method of manufacturing a semiconductor light emitting device
The step (e) is a step of etching the second semiconductor layer and the active layer in at least a part of the second region to form a groove in the bottom surface of which the first semiconductor layer is exposed. Yes,
The step (f) is a step of filling the groove with a conductive material in a state of being electrically insulated from the second semiconductor layer and the active layer to form the first electrode. A method of manufacturing a semiconductor light emitting device according to claim 9.
11. The method of manufacturing a semiconductor light emitting device according to claim 9, wherein the step (e) is a step of etching a plane parallel to the c plane of the layer made of a nitride semiconductor.
12. The method according to any one of claims 9 to 11, further comprising the step (g) of forming a concavo-convex shape on the upper surface of the second semiconductor layer after the end of the step (d) and before the start of the step (e). A method of manufacturing a semiconductor light emitting device according to any one of the preceding items.
After the completion of the step (d), before the start of the step (e), there is a step (h) of forming a second electrode on the upper layer of the second semiconductor layer in at least the first region,
The semiconductor light emitting device according to any one of claims 9 to 12, wherein the step (f) is a step of forming the first electrode in a state of being electrically insulated from the second electrode. Manufacturing method.
The second semiconductor layer is configured such that the surface opposite to the active layer in the first region includes an uneven surface, while the second semiconductor layer is opposite to the active layer in the second region. The semiconductor light emitting device according to claim 1, wherein the surface to be formed is a flat surface.
In the second region, it has a hole which penetrates at least the second semiconductor layer and the active layer and reaches the first semiconductor layer,
The first electrode is inserted into the hole in a state in which an insulating state is maintained with respect to the active layer and the second semiconductor layer, and the first electrode is formed to be in contact with the first semiconductor layer. The semiconductor light-emitting device according to claim 14.
16. The semiconductor light emitting device according to claim 14, wherein the active layer is made of a nitride semiconductor having a nonpolar plane as a crystal plane.
In the active layer, both the surface located on the side of the first semiconductor layer and the surface located on the side of the second semiconductor layer across the first region and the second region include an uneven surface. The semiconductor light emitting device according to claim 16,
In the active layer, both the surface located on the side of the first semiconductor layer and the surface located on the side of the second semiconductor layer are configured to be flat across the first region and the second region. The semiconductor light emitting device according to claim 14 or 15, characterized in that
A second electrode in contact with the second semiconductor layer,
The semiconductor according to any one of claims 14 to 18, wherein the first electrode is in contact with the first semiconductor layer in a state in which an insulating state is maintained with respect to the second electrode. Light emitting element.
15. A method of manufacturing a semiconductor light emitting device according to claim 14.
Preparing the substrate (a);
Growing the first semiconductor layer made of an n-type or p-type nitride semiconductor on the upper layer of the substrate (b)
Growing the active layer of nitride semiconductor on top of the first semiconductor layer (c);
Growing the second semiconductor layer made of a nitride semiconductor of a conductivity type different from that of the first semiconductor layer on the active layer;
Forming a concavo-convex shape on at least a part of the upper surface of the second semiconductor layer located in the first region among the upper surfaces of the second semiconductor layer;
Etching the second semiconductor layer and the active layer in at least a part of the second region different from the first region to expose the first semiconductor layer on the bottom surface;
And (g) forming the first electrode on at least a portion of the top surface of the first semiconductor layer exposed in a state of being electrically insulated from the second semiconductor layer and the active layer. Method of manufacturing a semiconductor light emitting device
The step (f) is a step of etching the second semiconductor layer and the active layer in at least a part of the second region to form a groove in the bottom surface of which the first semiconductor layer is exposed. Yes,
The step (g) is a step of filling the groove with a conductive material in a state of being electrically insulated from the second semiconductor layer and the active layer to form the first electrode. A method of manufacturing a semiconductor light emitting device according to claim 20.
22. The method of manufacturing a semiconductor light emitting device according to claim 20, wherein the step (b) is a step of growing the first semiconductor layer with a nonpolar surface as a crystal growth surface.
The semiconductor light emission according to claim 22, wherein the step (b) is a step of growing the first semiconductor layer using a nonpolar surface as a crystal growth surface over the first region and the second region. Method of manufacturing a device
After the completion of the step (d), before the start of the step (f), there is a step (h) of forming a second electrode on the upper layer of the second semiconductor layer in at least the first region,
The semiconductor light-emitting device according to any one of claims 20 to 23, wherein the step (g) is a step of forming the first electrode in a state of being electrically insulated from the second electrode. Manufacturing method.