CN112397374B - Growth method of low threading dislocation density silicon-based gallium arsenide layer based on nano-cavity - Google Patents
Growth method of low threading dislocation density silicon-based gallium arsenide layer based on nano-cavity Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 76
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 76
- 239000010703 silicon Substances 0.000 title claims abstract description 76
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 title claims abstract description 52
- 229910001218 Gallium arsenide Inorganic materials 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 238000000137 annealing Methods 0.000 claims abstract description 25
- 229910000673 Indium arsenide Inorganic materials 0.000 claims abstract description 22
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 239000002096 quantum dot Substances 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 13
- 238000005566 electron beam evaporation Methods 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 claims description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 32
- 150000001875 compounds Chemical class 0.000 description 4
- 239000002210 silicon-based material Substances 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 238000001534 heteroepitaxy Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000002360 explosive Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02601—Nanoparticles
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02658—Pretreatments
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention specifically discloses a growth method of a silicon-based gallium arsenide layer with low threading dislocation density based on nanometer cavity, which comprises the following steps: s1, conveying a silicon substrate into an MBE cavity to remove a surface oxide layer; s2, growing a first epitaxial layer on the silicon substrate from which the surface oxide layer is removed, and annealing; s3, carrying out indium arsenide nano dot growth after annealing in the step S2; s4, growing a second epitaxial layer after the indium arsenide nano dots in the step S3 grow, and annealing again; and S5, annealing again in the step S4 and growing a layer of gallium arsenide buffer layer, so that the silicon-based gallium arsenide substrate with low threading dislocation density based on the nano cavity is obtained. The invention greatly reduces the threading dislocation density on the silicon substrate by adopting the nanometer-sized cavity, and can effectively avoid the micro-crack problem caused by using excessive superlattice dislocation filter layers in the subsequent gallium arsenide growth of the silicon substrate, thereby improving the performance of devices on the silicon-based gallium arsenide substrate.
Description
Technical Field
The invention relates to the technical field of semiconductor substrates, in particular to a growth method of a silicon-based gallium arsenide layer with low threading dislocation density based on nanometer holes.
Background
With the vigorous development of the fields of big data, cloud computing, internet of things, 5G communication, artificial intelligence and the like, the data flow is expected to increase to a compound annual average growth rate of more than 25% and more than one hundred gigabyte in 2021 worldwide. This explosive growth in traffic demand poses significant challenges to the existing data communication arts. Under the large background, the silicon-based photonic integrated circuit is utilized to realize high-speed low-power-consumption optical interconnection in the data center, so that the optical interconnection becomes a break in the field of new-generation communication. Because silicon materials are indirect bandgap semiconductor materials, the low luminous efficiency of the silicon materials has become the most significant bottleneck in achieving efficient silicon-based light sources. The most mature method is to integrate mature III-V compound photoelectric devices on a silicon substrate by adopting a heteroepitaxy and heterointegration method, so that a high-efficiency silicon-based light source is realized. Heteroepitaxy is considered a more efficient integration method with higher throughput and lower production costs than heterointegration.
A technical difficulty with heteroepitaxy is that the crystal properties of III-V materials and silicon materials do not match. Because of lattice mismatch between the III-V compound material and the silicon substrate, high-density threading dislocations are generated when III-V is epitaxially grown on the silicon material, and the threading dislocations form non-radiative recombination centers of a large number of carriers and propagate to an active layer of a silicon-based light source, so that the luminous efficiency and the service life of the device are greatly reduced. Threading dislocations will only end up propagating when they either cross the entire crystal structure or when two threading dislocations with opposite berkovich vector directions meet. Molecular beam epitaxial growth (Molecular Beam Epitaxy, MBE) on silicon substrates is now primarily dependent on superlattice dislocation filter layers for achieving low threading dislocation density group III-V compound materials. This approach requires a high thickness III-V buffer layer to accommodate enough superlattice dislocation filter layers to effectively reduce threading dislocation densities to<10 6 cm -2 . Because of the different thermal expansion coefficients of III-V and IV, an excessively thick epitaxial layer can generate a large number of microcracks during cooling thermal annealing, and the productivity of the laser is greatly reduced.
In view of this, how to realize a low thickness low threading dislocation density III-V buffer layer will directly determine whether high yield low cost silicon-based photonic integrated circuits are successful or not.
Disclosure of Invention
The invention aims to provide a growth method of a silicon-based gallium arsenide layer with low threading dislocation density based on nano-cavity, which utilizes MBE equipment to prepare a silicon epitaxial layer on a silicon substrate and combines a gallium arsenide buffer layer to reduce threading dislocation.
In order to solve the technical problems, the invention provides a growth method of a silicon-based gallium arsenide layer with low threading dislocation density based on nano-cavity, which comprises the following steps:
s1, conveying a silicon substrate into an MBE cavity, and removing a surface oxide layer of the silicon substrate by utilizing high temperature in the MBE cavity;
s2, growing a first epitaxial layer on the silicon substrate from which the surface oxide layer is removed, and performing primary annealing in the MBE cavity;
s3, carrying out indium arsenide nano dot growth after the first annealing in the step S2;
s4, growing a second epitaxial layer after the indium arsenide nanodots in the step S3 grow, and then performing second annealing in the MBE cavity to form nano cavities in the second epitaxial layer;
and S5, growing gallium arsenide materials after the second annealing in the step S4 to form a gallium arsenide buffer layer, thereby obtaining the low-threading dislocation density silicon-based gallium arsenide substrate based on the nano-cavity.
Preferably, the specific implementation manner of the step S1 is: and (3) feeding the silicon substrate into an MBE cavity with the temperature of 950-1200 ℃ and keeping for 10-40min, so as to remove the surface oxide layer of the silicon substrate.
Preferably, the specific implementation manner of the step S2 is: and growing a first epitaxial layer with the thickness of 50-100nm on the silicon substrate with the surface oxide layer removed by utilizing an MBE cavity and silicon electron beam evaporation technology, and then maintaining the temperature in the MBE cavity between 900-1200 ℃ for 10-20min to finish the first annealing in the MBE cavity.
Preferably, the first epitaxial layer is a silicon epitaxial layer.
Preferably, the specific implementation manner of the step S3 is: and (3) reducing the temperature in the MBE cavity to 300-500 ℃ and maintaining, and then growing the indium arsenide nano-dots to obtain the indium arsenide nano-dots.
Preferably, the growth rate of the indium arsenide nanodots is 0.1-0.3 atomic layers per second.
Preferably, the specific implementation manner of the step S4 is: and (3) maintaining the temperature in the MBE cavity between 300 and 500 ℃ and growing a second epitaxial layer with the thickness of 10 to 20nm, and then raising the temperature in the MBE cavity to between 700 and 750 ℃ for a second annealing in the MBE cavity to generate high-density nano-voids in the second epitaxial layer.
Preferably, the material used for the growth of the second epitaxial layer is silicon.
Preferably, the specific implementation manner of the step S5 is: and (3) reducing the temperature in the MBE cavity to 550-610 ℃, and then growing gallium arsenide material to grow a gallium arsenide buffer layer with the thickness of 200-500nm, so as to obtain the low threading dislocation density silicon-based gallium arsenide substrate based on nano holes.
Preferably, the growth rate of the gallium arsenide buffer layer is 0.1-1.0 atomic layer per second.
Compared with the prior art, the method has the advantages that the MBE equipment is firstly utilized to prepare a first epitaxial layer on the silicon substrate, then annealing is carried out, then high-quality indium arsenide nanodots are grown on the first epitaxial layer, a second epitaxial layer barrier is formed on the periphery of the indium arsenide nanodots, then annealing is carried out again, so that high-density nano holes are generated in the second epitaxial layer, finally, the gallium arsenide buffer layer is combined to reduce the threading dislocation density of the silicon substrate, and the method can effectively avoid the problem of microcrack caused by the fact that excessive superlattice dislocation filter layers are used in the subsequent growth process, so that the device performance on the silicon-based gallium arsenide substrate is improved.
Drawings
Figure 1 is a flow chart of the growth method of the low threading dislocation density silicon-based gallium arsenide layer based on nano-holes,
fig. 2 is a block diagram of a low threading dislocation density gallium arsenide silicon substrate in accordance with the present invention.
Detailed Description
In order to make the technical scheme of the present invention better understood by those skilled in the art, the present invention will be further described in detail with reference to the accompanying drawings.
FIG. 1 shows a flow chart of a growth method of a silicon-based gallium arsenide layer with low threading dislocation density based on nano-voids.
Fig. 2 shows a structure diagram of a gallium arsenide silicon substrate with medium and low threading dislocation density according to the present invention. As shown in fig. 2, the semiconductor device comprises a silicon substrate 1, a first epitaxial layer 2, a second epitaxial layer 3 and a gallium arsenide buffer layer 4.
As shown in fig. 1-2, a low threading dislocation density silicon-based gallium arsenide layer growth method based on nano-cavity comprises the following steps:
s1, conveying a silicon substrate 1 into an MBE (Molecular Beam Epitaxy ) cavity, and removing a surface oxide layer of the silicon substrate 1 by utilizing high temperature in the MBE cavity;
s2, growing a first epitaxial layer 2 on the silicon substrate 1 with the surface oxide layer removed, and performing primary annealing in the MBE cavity;
s3, carrying out indium arsenide nano-dot growth after the first annealing in the step S2 to obtain indium arsenide nano-dots;
s4, growing a second epitaxial layer 3 after the indium arsenide nano-dots in the step S3 grow, and then performing second annealing in the MBE cavity to form nano-voids in the second epitaxial layer 3;
and S5, growing gallium arsenide materials after the second annealing in the step S4 to form a gallium arsenide buffer layer 4, thereby obtaining the low-threading dislocation density silicon-based gallium arsenide substrate based on the nano-cavity.
In this embodiment, a first epitaxial layer 2 is first prepared on a silicon substrate 1 by using MBE equipment, indium arsenide nano dots are grown on the first epitaxial layer 2, then a second epitaxial layer 3 barrier is formed around the indium arsenide nano dots to generate high-density nano holes in the second epitaxial layer 3, and finally the second epitaxial layer 3 is combined with a gallium arsenide buffer layer 4 to reduce the threading dislocation density of the silicon substrate, so that the problem of microcrack caused by using excessive layers of superlattice dislocation filter layers in the subsequent gallium arsenide growth process can be effectively avoided, and the performance of devices on the silicon gallium arsenide substrate is improved.
The specific implementation manner of the step S1 is as follows: and (3) feeding the silicon substrate 1 into an MBE cavity with the temperature of 950-1200 ℃ and keeping for 10-40min, so as to remove the surface oxide layer of the silicon substrate 1.
The specific implementation manner of the step S2 is as follows: and growing a first epitaxial layer 2 with the thickness of 50-100nm on the silicon substrate 1 with the surface oxide layer removed by utilizing an MBE cavity and silicon electron beam evaporation technology, and then maintaining the temperature in the MBE cavity between 900-1200 ℃ for 10-20min to finish the first annealing in the MBE cavity. In this embodiment, the first epitaxial layer 2 is a silicon epitaxial layer.
The specific implementation manner of the step S3 is as follows: and (3) reducing the temperature in the MBE cavity to 300-500 ℃ and maintaining, and then growing the indium arsenide nano-dots to obtain the indium arsenide nano-dots.
Wherein the growth rate of the indium arsenide nano-dots is 0.1-0.3 atomic layer per second.
The specific implementation manner of the step S4 is as follows: the temperature in the MBE cavity is kept between 300 and 500 ℃ and a second epitaxial layer 3 with the thickness of 10 to 20nm is grown, and then the temperature in the MBE cavity is increased to between 700 and 750 ℃ for a second annealing in the MBE cavity to generate high-density nano-voids in the second epitaxial layer 3. In this embodiment, the material used for the second epitaxial layer 3 is silicon. Since the high-density nano-voids are generated in the second epitaxial layer 3, threading dislocations formed on the surface of the second epitaxial layer 3 can propagate into the high-density nano-voids and be terminated.
The specific implementation manner of the step S5 is as follows: the temperature in the MBE cavity is reduced to 550-610 ℃, and then gallium arsenide material growth is carried out to grow a gallium arsenide buffer layer 4 with the thickness of 200-500nm, so that the low threading dislocation density silicon-based gallium arsenide substrate based on nano holes is obtained. In this embodiment, the thickness of the gaas buffer layer 4 may be adjusted accordingly according to the polishing control accuracy.
Wherein the growth rate of the gallium arsenide buffer layer 4 is 0.1-1.0 atomic layer per second.
The low threading dislocation density silicon-based gallium arsenide layer growth method based on the nano-cavity is described in detail. The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the core concepts of the invention. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the invention can be made without departing from the principles of the invention and these modifications and adaptations are intended to be within the scope of the invention as defined in the following claims.
Claims (8)
1. The low threading dislocation density silicon-based gallium arsenide layer growth method based on the nano-cavity is characterized by comprising the following steps:
s1, conveying a silicon substrate into an MBE cavity, and removing a surface oxide layer of the silicon substrate by utilizing high temperature in the MBE cavity;
s2, growing a first epitaxial layer on the silicon substrate from which the surface oxide layer is removed, and performing primary annealing in the MBE cavity;
s3, carrying out indium arsenide nano dot growth after the first annealing in the step S2; the specific implementation manner of the step S3 is as follows: the temperature in the MBE cavity is reduced to 300-500 ℃ and kept, and then indium arsenide nano-dots are grown to obtain indium arsenide nano-dots;
s4, growing a second epitaxial layer after the indium arsenide nanodots in the step S3 grow, and then performing second annealing in the MBE cavity to form nano cavities in the second epitaxial layer; the specific implementation manner of the step S4 is as follows: maintaining the temperature in the MBE cavity between 300 and 500 ℃ and growing a second epitaxial layer with the thickness of 10 to 20nm, and then raising the temperature in the MBE cavity to between 700 and 750 ℃ for a second annealing in the MBE cavity to generate high-density nano-voids in the second epitaxial layer;
and S5, growing gallium arsenide materials after the second annealing in the step S4 to form a gallium arsenide buffer layer, thereby obtaining the low-threading dislocation density silicon-based gallium arsenide substrate based on the nano-cavity.
2. The growth method of the silicon-based gallium arsenide layer with low threading dislocation density based on nano-cavity as claimed in claim 1, wherein the specific implementation manner of the step S1 is as follows: and (3) feeding the silicon substrate into an MBE cavity with the temperature of 950-1200 ℃ and keeping for 10-40min, so as to remove the surface oxide layer of the silicon substrate.
3. The growth method of the silicon-based gallium arsenide layer with low threading dislocation density based on nano-cavity as claimed in claim 2, wherein the specific implementation manner of the step S2 is as follows: and growing a first epitaxial layer with the thickness of 50-100nm on the silicon substrate with the surface oxide layer removed by utilizing an MBE cavity and silicon electron beam evaporation technology, and then maintaining the temperature in the MBE cavity between 900-1200 ℃ for 10-20min to finish the first annealing in the MBE cavity.
4. The method for growing a low threading dislocation density silicon-based gallium arsenide layer based on nano-holes according to claim 3, wherein the first epitaxial layer is a silicon epitaxial layer.
5. The growth method of the silicon-based gallium arsenide layer with low threading dislocation density based on nano holes according to claim 4, wherein the growth rate of the indium arsenide nano dots is 0.1-0.3 atomic layer per second.
6. The method for growing a low threading dislocation density silicon-based gallium arsenide layer based on nano-holes according to claim 5, wherein the material used for the growth of the second epitaxial layer is silicon.
7. The growth method of the silicon-based gallium arsenide layer with low threading dislocation density based on nano-cavity as claimed in claim 6, wherein the specific implementation manner of the step S5 is as follows: and (3) reducing the temperature in the MBE cavity to 550-610 ℃, and then growing gallium arsenide material to grow a gallium arsenide buffer layer with the thickness of 200-500nm, so as to obtain the low threading dislocation density silicon-based gallium arsenide substrate based on nano holes.
8. The growth method of the silicon-based gallium arsenide layer with low threading dislocation density based on nano-cavity according to claim 7, wherein the growth rate of the gallium arsenide buffer layer is 0.1-1.0 atomic layer per second.
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