CN111540671A - III-V group compound material growth method based on CMOS technology compatible with silicon substrate - Google Patents
III-V group compound material growth method based on CMOS technology compatible with silicon substrate Download PDFInfo
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- CN111540671A CN111540671A CN202010415449.XA CN202010415449A CN111540671A CN 111540671 A CN111540671 A CN 111540671A CN 202010415449 A CN202010415449 A CN 202010415449A CN 111540671 A CN111540671 A CN 111540671A
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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Abstract
The invention specifically discloses a III-V group compound material growth method compatible with a silicon substrate based on a CMOS technology, which comprises the following steps: s1, conveying the silicon substrate without the corner cut into the MBE cavity to remove the oxide layer on the surface of the silicon substrate without the corner cut; s2, growing a silicon epitaxial layer on the silicon substrate without the corner cut and with the surface oxide layer removed, and annealing in an MBE cavity; and S3, growing III-V compound materials on the annealed non-corner-cut silicon substrate to form a III-V compound buffer layer. According to the invention, a silicon epitaxial layer is grown on a silicon substrate without a corner cut by using MBE equipment, and then the reverse domain is terminated in the III-V compound buffer layer by combining with the III-V compound buffer layer grown on the silicon epitaxial layer, so that the reverse domain is effectively prevented from appearing in an active region of a silicon-based light source, and the problem of a large amount of reverse domains generated when the III-V compound grows to a nonpolar silicon substrate in an epitaxial manner is solved.
Description
Technical Field
The invention relates to the technical field of semiconductor substrates, in particular to a III-V group compound material growth method compatible with a silicon substrate based on a CMOS (complementary metal oxide semiconductor) technology.
Background
Today, the realization of high-density silicon-based photonic integrated circuits is the core technology of the next generation of high-speed low-price optical interconnects. And it has the characteristics of compatibility with the present CMOS (Complementary Metal Oxide Semiconductor) technology, and can be prepared by using the established silicon-based integrated circuit process line, thereby greatly reducing the cost. However, due to the poor light emitting characteristics of silicon materials, efficient silicon-based light sources become the most important bottleneck of silicon-based photonic integrated circuits. At present, the most successful method is to adopt a heteroepitaxy and heterointegration method to mix and integrate mature III-V compound photoelectric devices on a silicon substrate, thereby realizing a high-efficiency silicon-based light source. Due to the limited throughput of heterogeneous integration methods, although heterogeneous integration has been successfully commercialized, heteroepitaxy is considered to be a more efficient integration method.
The technical difficulty with heteroepitaxy is that the III-V material does not match the crystalline properties of the silicon material. Due to the polar nature of crystals of III-V compound materials, a large number of inversion domains are created when epitaxially grown to a non-polar silicon substrate. The inversion domain boundary generates a large number of non-radiative recombination centers of carriers and spreads to the active layer of the silicon-based light source to strongly weaken the light source performance. The inverted domains can be terminated only when they meet in the crystal. At present, the realization of the Molecular Beam Epitaxy growth (MBE) of III-V group compound materials based on a silicon substrate is mainly limited to selecting a deflection angle substrate, but has the defect of incompatibility with a CMOS technology process, and the feasibility of silicon-based photoelectron integration is determined by the CMOS compatible technology. Therefore, the direct growth of group III-V compound materials for MBE on CMOS technology compatible silicon substrates is critical to the success of high density low cost silicon-based photonic integrated circuits.
Disclosure of Invention
The invention aims to prepare a III-V compound material growth method based on a CMOS (complementary metal oxide semiconductor) technology compatible silicon substrate. According to the method, a silicon epitaxial layer is grown on a silicon substrate without a corner cut by MBE equipment, and the III-V compound buffer layer is combined to terminate the reverse domain in the III-V compound buffer layer, so that the reverse domain is effectively prevented from appearing in an active region of a silicon-based light source, and the problem that a large amount of reverse domains are generated when III-V compounds grow to a nonpolar silicon substrate in an epitaxial mode is solved.
In order to solve the above technical problem, the present invention provides a method for growing a III-V compound material based on a CMOS technology compatible silicon substrate, the method comprising the steps of:
s1, conveying the silicon substrate without the corner cut into the MBE cavity to remove the oxide layer on the surface of the silicon substrate without the corner cut;
s2, growing a silicon epitaxial layer on the silicon substrate without the corner cut and with the surface oxide layer removed, and annealing in an MBE cavity;
and S3, growing III-V compound materials on the annealed non-corner-cut silicon substrate to form a III-V compound buffer layer.
Preferably, the step S1 is specifically implemented as follows: and (3) conveying the silicon substrate without the corner cut into an MBE chamber with the temperature of 950-1200 ℃ and keeping the temperature for 30-40min, thereby removing the oxide layer on the surface of the silicon substrate without the corner cut.
Preferably, the step S2 is specifically implemented as follows: growing a silicon epitaxial layer with the thickness of 10-300nm on the silicon substrate without the corner cut and with the surface oxide layer removed, and then annealing at the temperature of 900-1200 ℃ in the MBE cavity for 10-30 min.
Preferably, the specific implementation manner of step S3 includes:
s31, reducing the temperature in the MBE cavity to between 300 and 350 ℃, and then growing a first III-V compound buffer layer with the thickness of 20-300nm on the annealed non-corner silicon substrate, wherein the growth rate of the first III-V compound buffer layer is 0.1-0.2 atomic layer per second;
s32, raising the temperature in the MBE cavity to 380-500 ℃, and then growing a second III-V compound buffer layer with the thickness of 200-300nm, wherein the growth rate of the second III-V compound buffer layer is 0.5-0.6 atomic layer per second;
s33, raising the temperature in the MBE cavity to between 500 and 610 ℃, and finally growing a third III-V compound buffer layer with the thickness of 300 and 500nm, wherein the growth rate of the third III-V compound buffer layer is 0.6-1.0 atomic layer per second.
Preferably, the III-V compound is gallium arsenide.
Preferably, the chamfer angle of the silicon substrate without chamfer angle is less than +/-0.5 degrees.
Compared with the prior art, the method firstly utilizes MBE equipment to remove the oxide layer on the surface of the silicon substrate without the corner cut at high temperature, generate a single-atom step silicon epitaxial layer with ordered single direction, and then grow the III-V group compound buffer layer on the silicon epitaxial layer, so that a large number of reverse domains generated when the III-V group compound grows to the nonpolar silicon substrate in an epitaxial manner can be terminated in the III-V group compound buffer layer, the reverse domains are effectively prevented from appearing in the active region of the silicon-based light source, and the use of the corner cut silicon substrate is also avoided.
Drawings
Figure 1 is a flow chart of the method of growing III-V compound material based on CMOS technology compatible silicon substrates of the present invention,
FIG. 2 is a flow chart of a method of growing a III-V compound buffer layer on a non-corner-cut silicon substrate according to the present invention,
FIG. 3 is a schematic structural diagram of a III-V compound buffer layer grown on a silicon substrate without corner cut in the present invention,
fig. 4 is a schematic view of a silicon substrate without corner cuts after growth of gallium arsenide material in the present invention under a transmission electron microscope.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention is further described in detail below with reference to the accompanying drawings.
Fig. 1 shows a flow chart of a method for growing a III-V compound material based on a CMOS technology compatible silicon substrate according to the present invention.
FIG. 2 is a flow chart showing a method for growing a III-V compound buffer layer on a silicon substrate without corner cuts in the invention.
FIG. 3 is a schematic structural diagram of a III-V compound buffer layer grown on a silicon substrate without corner cut in the present invention. As shown in fig. 3, the epitaxial layer comprises a silicon epitaxial layer 1, a first III-V compound buffer layer 2, a second III-V compound buffer layer 3, a third III-V compound buffer layer 4, a reverse domain 5 and a silicon substrate 6.
As shown in fig. 1 to 3, a method for growing a III-V compound material based on a CMOS technology compatible silicon substrate, the method comprising the steps of:
s1, feeding the silicon substrate 6 without the corner cut into an MBE cavity to remove an oxide layer on the surface of the silicon substrate 6 without the corner cut;
s2, growing a silicon epitaxial layer 1 on the silicon substrate 6 without the corner cut and with the surface oxide layer removed, and annealing in an MBE cavity;
and S3, growing III-V compound materials on the annealed non-corner-cut silicon substrate 6 to form a III-V compound buffer layer.
In the embodiment, firstly, an oxide layer on the surface of the silicon substrate 6 without the corner cut is removed by MBE equipment to generate a silicon epitaxial layer 1, and then III-V group compound material growth is carried out on the generated silicon epitaxial layer 1 to obtain a III-V group compound buffer layer, so that a large number of reverse domains 5 generated when the III-V group compound grows to the nonpolar silicon substrate in an epitaxial growth mode are terminated in the III-V group compound buffer layer, the reverse domains 5 are effectively prevented from appearing in an active region of a silicon-based light source, and the use of the corner cut silicon substrate is also avoided.
The method comprises the following specific steps of removing an oxide layer on the surface of the silicon substrate 6 without the corner cut: and (3) delivering the silicon substrate 6 without the corner cut into an MBE chamber with the temperature of 950-1200 ℃ and keeping the temperature for 30-40min, and further removing the oxide layer on the surface of the silicon substrate 6 without the corner cut. In this embodiment, the oxide layer on the surface of the silicon substrate 6 without corner cut is removed by high temperature in the MBE chamber.
The specific steps for generating the silicon epitaxial layer 1 on the silicon substrate 6 without the corner cut are as follows: growing a silicon epitaxial layer 1 with the thickness of 10-300nm on the silicon substrate 6 without the corner cut and with the surface oxide layer removed, and then annealing at the temperature of 900-1200 ℃ in the MBE cavity for 10-30 min. In this embodiment, by forming a silicon surface epitaxial layer with a single-direction ordered monoatomic step on the silicon substrate 6 without a corner cut, the generation position of the reverse domain 5 (i.e., the monoatomic step) can be guided in order to easily eliminate the reverse domain 5.
The method specifically comprises the following steps of growing the III-V compound buffer layer:
s31, reducing the temperature in the MBE cavity to between 300 and 350 ℃, and then growing a first III-V group compound buffer layer 2 with the thickness of 20-300nm on the annealed non-corner silicon substrate 6, wherein the growth rate of the first III-V group compound buffer layer 2 is 0.1-0.2 atomic layer per second; in the present embodiment, growing the first III-V compound buffer layer 2 by keeping low temperature and low growth rate can effectively confine the propagation direction of the inversion domain 5 to the vertical direction (the vertical direction refers to the direction upward of the vertical paper and downward of the vertical paper in fig. 3), and also can suppress the formation of a three-dimensional surface.
S32, raising the temperature in the MBE cavity to 380-500 ℃, and then growing a second III-V compound buffer layer 3 with the thickness of 200-300nm, wherein the growth rate of the second III-V compound buffer layer 3 is 0.5-0.6 atomic layer per second; in this embodiment, since the temperature in the MBE cavity changes after the first III-V group compound buffer layer 2 is grown, the propagation direction of the reverse domains 5 is bent, and the reverse domains 5 may converge and cancel each other out.
S33, raising the temperature in the MBE cavity to between 500 and 610 ℃, and finally growing a third III-V compound buffer layer 4 with the thickness of 300 and 500nm, wherein the growth rate of the third III-V compound buffer layer 4 is 0.6-1.0 atomic layer per second. In this embodiment, the temperature in the MBE cavity is continuously increased after the second III-V compound buffer layer 3 is grown to accelerate the bending of the reverse domains 5, so that the reverse domains 5 are more efficiently offset and are all terminated in the third III-V compound buffer layer 4, thereby ensuring that the reverse domains 5 do not spread to the surface of the crystal and eliminating a large number of reverse domains 5 generated when the III-V compound is epitaxially grown on the nonpolar silicon substrate.
Wherein the III-V compound is gallium arsenide. In this embodiment, the selected III-V compound is gallium arsenide, and in other embodiments, other III-V compounds such as indium phosphide and gallium nitride can be used.
Wherein the chamfer angle of the silicon substrate 6 without chamfer angle is less than +/-0.5 degrees. In this embodiment, the angle of the corner cut of the silicon substrate 6 without the corner cut is less than ± 0.5 °, and the smaller the angle of the corner cut of the silicon substrate 6 without the corner cut is, the more advantageous the silicon-based photonic integration is.
In order to better understand the working principle and the beneficial technical effects of the present invention, the following description will take the growth of gallium arsenide material as an example to illustrate the specific implementation of the present invention.
Firstly, taking a silicon substrate 6 without a cutting angle smaller than +/-0.5 degrees, and sending the silicon substrate into an MBE equipment cavity with the temperature of 950-;
secondly, growing a silicon epitaxial layer 1 on the surface of the silicon substrate 6 without the corner cut, from which the surface oxide layer is removed, and ensuring the thickness of the silicon epitaxial layer 1 to be 10-300nm, and then annealing the silicon substrate 6 without the corner cut for 10-30min by keeping the temperature in the MBE cavity between 900 and 1200 ℃, wherein a layer of silicon epitaxial layer 1 with single-direction ordered monoatomic steps grows on the silicon substrate 6 without the corner cut;
thirdly, reducing the temperature in the MBE cavity to be between 300 and 350 ℃, growing a first gallium arsenide buffer layer with the thickness of 20-300nm on the annealed silicon substrate 6 without the corner cut, wherein the growth rate of the first gallium arsenide buffer layer is kept to be 0.1-0.2 atomic layer per second (namely the growth rate is 0.028-0.056 nm/s);
fourthly, raising the temperature in the MBE cavity to 380-500 ℃, growing a second gallium arsenide buffer layer with the thickness of 200-300nm, and ensuring that the growth rate of the second gallium arsenide buffer layer is 0.5-0.6 atomic layer per second (namely the growth rate is 0.14-0.168 nm/s);
fifthly, the temperature in the MBE cavity is continuously increased to 610 ℃ of 500-, thereby completing the growth of gallium arsenide material based on CMOS technology compatible silicon substrate, as shown in figure 4, fig. 4 is a schematic view of the silicon substrate without corner cut after the growth of the gallium arsenide material in this embodiment under a transmission electron microscope (with a resolution of 250nm), and it can be seen from fig. 4 that the reverse domains 5 on the silicon substrate without corner cut 6 are effectively eliminated, which illustrates that the technical solution in the present invention can effectively eliminate the reverse domains 5 in the silicon substrate without corner cut 6, therefore, the use of the silicon substrate with the cut corner in actual application can be avoided, and the silicon substrate has wide industrial and commercial values.
The method for growing the III-V compound material based on the CMOS compatible silicon substrate is described in detail above. The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the core concepts of the present invention. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Claims (6)
1. A method for growing a III-V compound material based on a CMOS technology compatible silicon substrate, the method comprising the steps of:
s1, conveying the silicon substrate without the corner cut into the MBE cavity to remove the oxide layer on the surface of the silicon substrate without the corner cut;
s2, growing a silicon epitaxial layer on the silicon substrate without the corner cut and with the surface oxide layer removed, and annealing in an MBE cavity;
and S3, growing III-V compound materials on the annealed non-corner-cut silicon substrate to form a III-V compound buffer layer.
2. The method for growing a III-V compound material based on a CMOS technology compatible silicon substrate according to claim 1, wherein the step S1 is implemented in a manner that: and (3) conveying the silicon substrate without the corner cut into an MBE chamber with the temperature of 950-1200 ℃ and keeping the temperature for 30-40min, thereby removing the oxide layer on the surface of the silicon substrate without the corner cut.
3. The method for growing a III-V compound material based on a CMOS technology compatible silicon substrate according to claim 2, wherein the step S2 is implemented in a manner that: growing a silicon epitaxial layer with the thickness of 10-300nm on the silicon substrate without the corner cut and with the surface oxide layer removed, and then annealing at the temperature of 900-1200 ℃ in the MBE cavity for 10-30 min.
4. The method for growing a III-V compound material based on a CMOS compatible silicon substrate as claimed in claim 3, wherein said step S3 comprises:
s31, reducing the temperature in the MBE cavity to between 300 and 350 ℃, and then growing a first III-V compound buffer layer with the thickness of 20-300nm on the annealed non-corner silicon substrate, wherein the growth rate of the first III-V compound buffer layer is 0.1-0.2 atomic layer per second;
s32, raising the temperature in the MBE cavity to 380-500 ℃, and then growing a second III-V compound buffer layer with the thickness of 200-300nm, wherein the growth rate of the second III-V compound buffer layer is 0.5-0.6 atomic layer per second;
s33, raising the temperature in the MBE cavity to between 500 and 610 ℃, and finally growing a third III-V compound buffer layer with the thickness of 300 and 500nm, wherein the growth rate of the third III-V compound buffer layer is 0.6-1.0 atomic layer per second.
5. The method of growing a III-V compound material based on a CMOS technology compatible silicon substrate of claim 1, wherein the III-V compound is gallium arsenide.
6. The method of growing a group III-V compound material based on a CMOS technology compatible silicon substrate according to claim 5, wherein the corner cut of the corner-free silicon substrate is less than ± 0.5 °.
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| CN112397374A (en) * | 2020-11-17 | 2021-02-23 | 湖南汇思光电科技有限公司 | Low threading dislocation density silicon-based gallium arsenide layer growth method based on nano-cavities |
| CN112951940A (en) * | 2021-04-23 | 2021-06-11 | 湖南汇思光电科技有限公司 | InGaAs detector structure based on InPOI substrate and preparation method |
| CN113178771A (en) * | 2021-04-23 | 2021-07-27 | 湖南汇思光电科技有限公司 | InAs quantum dot laser structure based on GaAsOI substrate and preparation method |
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