KR101476143B1 - Compound semiconductor epitaxial wafer and process for producing the same - Google Patents

Compound semiconductor epitaxial wafer and process for producing the same Download PDF

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KR101476143B1
KR101476143B1 KR1020107005269A KR20107005269A KR101476143B1 KR 101476143 B1 KR101476143 B1 KR 101476143B1 KR 1020107005269 A KR1020107005269 A KR 1020107005269A KR 20107005269 A KR20107005269 A KR 20107005269A KR 101476143 B1 KR101476143 B1 KR 101476143B1
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후미타카 구메
마사유키 시노하라
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신에쯔 한도타이 가부시키가이샤
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Abstract

The present invention, the <100> and the orientation to the reference direction, the off-angle on the GaAs single crystal substrate 1 having a 20 ° or less major axis over 10 °, including the Ⅲ group elements of two or more (Al x Ga 1 by -x) y in 1 -y P (However, 0≤x≤1, 0 <a light emitting layer portion (24, consisting of y≤1)), the 1GaP layer (organic metal vapor-phase growth method, 7a) in order to And second GaP layers 7b and 7c are formed on the first GaP layer 7a by hydride vapor phase epitaxy. The second GaP layers 7b and 7c are two-stage growth of the low-speed growth region 7b at the first growth rate and the high-speed growth region 7c at the second growth rate higher than the first growth rate, 10 m / hr to 40 m / hr in the entire growth process. Thereby providing a compound semiconductor epitaxial wafer in which the height of the hillocks generated when the thick window layer is formed by using the hydride vapor phase growth method, and a method of manufacturing the same.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor epitaxial wafer,

The present invention relates to a compound semiconductor epitaxial wafer and a manufacturing method thereof.

(Al x Ga 1 -x ) y In 1 - y P mixed crystal (0? X? 1, 0 <y? 1: hereinafter referred to as AlGaInP hybrid crystal or simply AlGaInP) The light emitting device having a light emitting layer portion is formed by laminating a thin AlGaInP active layer on a p-type AlGaInP cladding layer sandwiched between an n-type AlGaInP cladding layer (clad layer) having a larger band gap and a double heterostructure (DH structure), it is possible to realize a device with high luminance.

For example, an AlGaInP light emitting device is formed by laminating an n-type GaAs buffer layer, an n-type AlGaInP cladding layer, an AlGaInP active layer, and a p-type AlGaInP cladding layer in this order on a n-type GaAs substrate in a hetero- . Energization to the light emitting layer portion is made through a metal electrode formed on the surface of the element. Here, since the metal electrode acts as a light shielding body, it is formed, for example, in such a manner as to cover only the central portion of the main surface of the light emitting layer portion, and light (light) is taken out from the electrode non- .

In this case, it is advantageous from the viewpoint of improving the light extraction efficiency because the area of the metal electrode is made as small as possible because the area of the light leakage region formed around the electrode can be made large. Although attempts have been made to increase the amount of light output by effectively expanding the current in the device by studying the shape of the electrode in the past, the increase of the electrode area is also difficult to avoid anyway, It is in a dilemma that the volume of extraction is limited. Further, the carrier concentration of the dopant in the cladding layer, and hence the conductivity, is somewhat lowered in order to optimize the light emission recombination of the carriers in the active layer, and the current tends to be difficult to expand in the in-plane direction. This results in a concentration of current density in the electrode covering region and a substantial decrease in the amount of light output in the light leakage region.

Thus, a method is known in which a conductive transparent window layer (current diffusion layer: hereinafter simply referred to as a window layer) is provided between the light emitting layer portion and the electrode so that the current density is minimized (Patent Document 1). In order to efficiently form the current diffusion layer, a thin light emitting layer portion is formed by a metalorganic vapor phase epitaxy (MOVPE) method, while a thick current diffusion layer is formed by hydride vapor deposition Phase epitaxial growth method (hereinafter, also referred to as HVPE method) is known (Patent Document 2).

On the other hand, it has been conventionally known that when an epitaxial layer is grown on a compound semiconductor single crystal substrate, a crystal defect (crystal defect) having a concave-convex shape called a Hillock is likely to occur on the surface. For example, in Patent Document 3, a hillock having a height of about 6 占 퐉 formed when a GaP buffer layer of 0.5 占 퐉 and an AlGaInP lower cladding layer of about 3 占 퐉 are grown on a GaP substrate by MOVPE method is planarized by a polish, And the crystal growth of the double hetero-structure moiety is performed again by the MOVPE method. However, when the substrate material, the plane direction, the layer structure, the growth temperature, etc. are changed, the hillock occurrence situation changes.

US Patent Publication No. 5,008,718 Japanese Patent Application Laid-Open No. 2004-047960 Japanese Patent Application Laid-Open No. 07-240372

If a GaP layer to be a window layer is formed thick on an AlGaInP double hetero structure formed on a GaAs substrate, a hillock tends to be formed on the surface of the GaP layer. When such an epitaxial wafer having a window layer made of a GaP layer is provided for device manufacture, the surface of the window layer is polished and planarized according to a photolithography process or the like. However, If a hillock having a concavo-convex shape is formed, it is necessary to increase the polishing value by the height of the hillock, which results in a problem of poor efficiency.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and it is an object of the present invention to provide a compound semiconductor epitaxial wafer in which the height of a hillock generated when a thick window layer is formed by using the hydride vapor phase growth method, do.

In order to solve the above-described problems, the first compound semiconductor epitaxial wafer of the present invention is a compound semiconducting epitaxial wafer having a <100> direction as a reference direction and a main axis having an off angle of 10 ° to 20 ° (Al x Ga 1 -x ) y In 1 -y P (where 0? X? 1, 0? Y? 1 ) containing two or more Group III elements is formed on a GaAs single crystal substrate (GaAs single crystal substrate) (y? 1) and a GaP layer having a thickness of 50 占 퐉 or more and 250 占 퐉 or less are laminated in this order. The GaP layer has a non-polished surface, And a height of a Hillock formed on the uncured surface is 10 占 퐉 or less.

When a monocrystal substrate having no off-angle is used in the case of growing the light-emitting layer portion by the MOVPE method, Group III atoms are not randomly distributed in the light-emitting layer portion, and unevenness of the atomic arrangement or uneven distribution occurs have. Since the region where the regularization or the shifting occurs is different from the band gap energy originally expected, the band gap energy is generated in the entire light emitting layer portion, resulting in a deviation of the emission spectrum profile or the central wavelength . However, by imparting appropriate off-angles to the single crystal substrate, the above-described regularization or shaking of Group III elements is greatly reduced, and a light emitting device having no deviation in emission spectrum profile or central wavelength can be obtained. Further, when a single crystal substrate to which an off-angle is imparted is used, a facet is hardly generated on the surface of the finally obtained window layer, and a window layer having a good smoothness can be obtained.

(Al x Ga 1 -x ) y In 1 - y P, the monocrystalline substrate has a <100> direction as a reference direction and an off-angle with respect to the reference direction of 10 ° or more and 20 ° or less A GaAs single crystal substrate can be obtained. By using the GaAs single crystal having such a high angle off angle, the effect of smoothing the surface of the finally obtained GaP window layer in the second vapor phase growth by the HVPE method can be further enhanced. When a single crystal substrate having an off-angle of 1 deg. Or more and less than 10 deg. Is used, on the surface of the window layer obtained by the HVPE method, the amplitude is small like the facet and the formation of the same concavity and convexity is effectively prevented. However, And may lead to defects such as erroneous detection in a wire bonding process or the like. However, when the off-angle is set to be in the range of 10 DEG to 20 DEG, occurrence of such protruding crystal defects can be effectively suppressed.

Since the GaP layer formed by the HVPE method has a thickness variation of 50 占 퐉 or more, it is necessary to polish the GaP layer by 10 占 퐉 or more to planarize the surface of the GaP layer. Therefore, by setting the height of the hillocks formed on the surface of the GaP layer before polishing to 10 m or less, the surface of the GaP layer can be planarized without leaving hillock even if the polishing value is not substantially increased. When the height of the hillocks is 1 占 퐉 or less, it is completely contained in the range of the polishing value, so there is no need to worry about the presence of hillock at the time of polishing.

In order to obtain the first compound semiconductor epitaxial wafer of the present invention, the first method of manufacturing the light emitting device of the present invention is a method of manufacturing a compound semiconductor epitaxial wafer,

(Al x Ga 1 -x ) y In 1 - x Ga 1 -x Al y Ga 1 -x Al y Ga 1 -x Al y Ga 1 -x Al y Ga 1- y P (0? x? 1, 0 < y? 1), and a first GaP layer are formed in this order on the first GaP layer, and a second GaP layer is formed on the first GaP layer A hydride vapor phase growth process,

The growth rate of the second GaP layer is set to a first growth rate in a predetermined period of time at the beginning of growth and a second growth rate higher than the first growth rate after the elapse of the period, hr or more and 40 占 퐉 / hr or less.

In the first method for producing a compound semiconductor epitaxial wafer of the present invention, for example, (Al x Ga 1 -x ) y In 1 -y P (where 0? X? 1 and 0 < y &amp;le; 1: therefore, &quot; including two or more Group III elements &quot; means &quot; comprising at least one of Al and Ga and In &quot;) is formed on a single crystal substrate Is grown using an organic metal vapor phase growth method (MOVPE method) (organic metal vapor phase growth process). On the other hand, it is effective to form the second GaP layer, which is a window layer necessary to set the layer thickness to a certain large extent, by using the hydride vapor phase growth method (hydride vapor phase growth step). In the HVPE method, Ga (gallium) having a low vapor pressure in a quartz reaction furnace substituted with hydrogen gas is converted into GaCl which is easily vaporized by reaction with hydrogen chloride, and the GaCl- Gas is reacted with Ga to vapor-phase-grow the III-V group compound semiconductor layer. According to the HVPE method, the layer growth rate can be made faster than the MOVPE method, and since the second GaP layer requiring a certain thickness can be formed with a very high efficiency, the raw material cost can be controlled to be much lower than that of the MOVPE method. In addition, in the HVPE method, the mixing ratio of the group V element source (AsH 3 , PH 3, etc.) to the group III element source can be made to be much smaller without using the expensive organic metal as the group III element source For example, about 1/3 times), which is advantageous in terms of cost.

However, when GaCl is supplied at a high concentration to achieve high-speed growth of the second GaP layer, hillock tends to occur. Therefore, when the growth of the second GaP layer starts in the initial stage of the hydride vapor phase growth process, the growth is slowed at the first growth rate to suppress the occurrence of hillocks. When the growth rate is increased to the second growth rate, the occurrence of hillock can be suppressed even when the growth rate is 10 m / hr (hr) or more and 40 m / hr (hr) or less in the entire growth process.

When the growth rate of the entire growth process is less than 10 탆 / hr, the difference from the growth rate obtained by the MOVPE method becomes small, so that the effect of using the HVPE method is hardly obtained. When the growth rate of the entire growth process exceeds 40 占 퐉 / hr, it is difficult to suppress the height of the generated hillock to 10 占 퐉 or less, so that it is preferably 40 占 퐉 / hr or less.

The height of the hillock generated when the growth rate of the second GaP layer is started, that is, the first growth rate is, for example, 10 占 퐉 / hr or less can be suppressed to 10 占 퐉 or less. In particular, the height of the hillocks generated when the first growth rate is set to, for example, 5 占 퐉 / hr or less can be suppressed to 1 占 퐉 or less. The lower limit value of the first growth rate is, for example, about 1 占 퐉 / hr.

The sum of the thicknesses of the first GaP layer and the second GaP layer is preferably set to 50 m or more in the non-polishing step in order to obtain the effect as a window layer. However, if the sum of the thickness exceeds 250 탆, it becomes difficult to suppress the height of the hillocks to 10 탆 or less.

When the GaP layer is vapor-grown by the HVPE method at a temperature higher than 800 ° C, the quartz reaction furnace wall is etched by hydrogen or hydrogen chloride, and silicon is easily liberated, So that a large amount of silicon impurities are introduced. Further, when the second GaP layer is vapor-grown at a temperature lower than 650 deg. C, it is difficult to form a single crystal layer (single crystal layer). Therefore, when the second GaP layer is formed by the HVPE method, it is preferable to grow at a temperature of 650 ° C or more and 800 ° C or less.

In addition, in the case of adopting the manufacturing method of the present invention, the compound semiconductor epitaxial wafer of the present invention is formed by forming the GaP layer on the light emitting layer portion by the first GaP layer by the MOVPE method and the second GaP layer by the HVPE method And a dopant is added to each of the GaP layers. In the MOVPE method and the HVPE method, since the dopant concentration to be added does not usually coincide, both GaP layers can be identified.

Next, a second example of the compound semiconductor epitaxial wafer of the present invention is formed by epitaxial growth on a GaAs single crystal substrate having a <100> direction as a reference direction and a main axis having an off-angle of 10 ° to 20 ° (Al x Ga 1 -x ) y In 1 -y P (where 0? X? 1, 0 <y? 1) containing two or more Group III elements,

(Main surface) located on the side opposite to the side of the light emitting layer portion grown on the GaAs single crystal substrate facing the GaAs single crystal substrate is a main surface and a main surface on the side facing the GaAs single crystal substrate is a main surface A main surface side GaP layer having a thickness of 50 mu m or more and 250 mu m or less and being epitaxially grown on the main surface of the light emitting layer portion,

And a main back side GaP layer having a thickness of 50 탆 or more and 250 탆 or less epitaxially grown on the main back surface of the light emitting layer portion appearing by removing the GaAs single crystal substrate,

Wherein the main surface side GaP layer and the main back side GaP layer all have a non-polished surface and a height of a hillock formed on the non-polished surface is 10 m or less.

In order to obtain the second compound semiconductor epitaxial wafer of the present invention, the second method of manufacturing the light emitting device of the present invention is a method for manufacturing a compound semiconductor epitaxial wafer of the present invention, wherein the <100> direction is a reference direction and a major axis whose off- (Al x Ga 1 -x ) y In 1 -y P (where 0? X? 1, 0 <y? 1) containing two or more Group III elements on a GaAs single crystal substrate, And a first GaP layer are sequentially formed on the first GaN layer;

A first hydride vapor phase growth step of forming a second GaP layer on the first GaP layer,

A GaAs single crystal substrate removing step of removing the GaAs single crystal substrate from the light emitting layer portion,

A second hydride vapor phase growth step of forming a third Ga.sub.AP layer on the main back surface of the light emitting layer portion by removal of the GaAs single crystal substrate;

Are carried out in this order, and

The growth rate of the second GaP layer and the growth rate of the third GaP layer is set to a first growth rate in a predetermined period of time at the beginning of growth and a second growth rate higher than the first growth rate after the lapse of the period, To 10 m / hr and not more than 40 m / hr.

In the second aspect of the present invention, the combination of the first GaP layer and the second GaP layer is a main surface side GaP layer corresponding to the same concept as the first GaP layer in the present invention. In the second aspect of the present invention, in the first aspect of the present invention, the GaAs single crystal substrate remaining on the main back surface of the light emitting layer part is removed, and the third GaAp layer formed by the hydride vapor phase growth method is epitaxially It grows. If the third GaP layer is the main layer, it becomes a side GaP layer. Unlike the first aspect of the present invention, the final compound semiconductor epitaxial wafer does not include a GaAs single crystal substrate as a constituent requirement, but it is preferable that the first GaP layer and the second GaP layer (main surface side GaP layer) Whether or not the GaP layer is epitaxially grown on the <100> surface of the GaAs single crystal to which the off-angle is imparted is determined by whether the main surface side GaP layer has a <100> major surface in the same manner, It is possible to easily confirm whether or not an off-angle of the vehicle is generated.

Since the light emitting layer portion is also formed by forming the off-angle of not less than 10 DEG and not more than 20 DEG on the main axis, the light emitting layer portion is formed by epitaxially growing the main surface Side GaP layer (third GaP layer) also has a <100> main surface and an off-angle of 10 ° or more and 20 ° or less is formed on the main axis.

By applying the same concept as the first aspect of the present invention to the main back side GaP layer, it is possible to grow at a low growth rate at a first growth rate when the growth of the third GaP layer is started by the hydride vapor phase growth process, It is possible to suppress the occurrence of hillocks in the same manner.

Here, the growth rate at the start of growth of the third GaAp layer, that is, the first growth rate, is preferably 10 占 퐉 / hr or less, preferably 5 占 퐉 / hr or less as in the case of the main surface side GaP layer. The thickness of the third GaInAs layer (i.e., the main back GaP layer) is preferably 50 mu m or more and 250 mu m or less. When the third GaP layer is formed by the HVPE method, it preferably grows at a temperature of 650 ° C or more and 800 ° C or less.

1 is a schematic diagram showing a first example of a compound semiconductor wafer of the present invention in a laminated structure.
Fig. 2 is an explanatory diagram showing a manufacturing process of the compound semiconductor wafer of Fig. 1;
Fig. 3 is an explanatory diagram subsequent to Fig. 2. Fig.
4 is a schematic diagram showing a second example of the compound semiconductor wafer of the present invention in a laminated structure.
Fig. 5 is an explanatory view showing a manufacturing process of the compound semiconductor wafer of Fig. 4;
FIG. 6 is an explanatory diagram subsequent to FIG. 5; FIG.
Fig. 7 is an explanatory diagram subsequent to Fig. 6; Fig.
8 is a diagram showing the relationship between the growth rate of the second GaP layer low-growth region and the hillock height generated on the surface of the second GaP layer.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 is a conceptual diagram showing an example of a compound semiconductor epitaxial wafer 100 according to the first aspect of the present invention. The compound semiconductor epitaxial wafer 100 has a light emitting layer portion 24 formed on a main surface of an n-type GaAs single crystal substrate 1 (hereinafter simply referred to as a substrate) In other words, the substrate 1 is located on the main back surface of the light emitting layer portion 24). The substrate 1 is provided with a main axis having a <100> direction as a reference direction and an off angle with respect to the reference direction of 10 ° or more and 20 ° or less. An n-type GaAs buffer layer 2 is formed so as to be in contact with the main surface of the substrate 1, and a light emitting layer portion 24 is formed on the buffer layer 2. The main surface side GaP layer 7 is formed on the light emitting layer portion 24.

Consisting of y P (stage, 0≤x≤0.55, 0.45≤y≤0.55) mixed crystal (mixed crystal), - a light emitting layer section 24, non-doped (doping非) (Al x Ga 1 -x) y In 1 The active layer 5 is formed by stacking a p-type clad layer 6 (p-type clad layer) 6 made of p-type (Al z Ga 1 -z ) y In 1 -y P (where x < Al z Ga 1 -z ) y In 1-y P (where x <z? 1). "Undoped" referred to here is "not actively adding a dopant (dopant)" is a means, the conventional example containing (for example, the dopant components inevitably incorporated during the manufacturing process 10 13 ~10 16 / cm 3 degree The upper limit is not excluded).

The main surface side GaP layer 7 is formed as a p-type GaP layer. The thickness of the main surface-side GaP layer 7 is, for example, 50 占 퐉 or more and 250 占 퐉 or less. The main surface side GaP layer 7 is formed by a first GaP layer 7a formed by an organic metal vapor phase growth method and a second GaP layer low growth region 7b and a second GaP layer high growth region 7b formed by a hydride vapor phase growth method 7c are stacked in this order. The carrier concentration of the second GaP low-speed growth region 7b and the second GaP high-speed growth region 7c is 1 × 10 17 / cm 3 or more and 2 × 10 18 / cm 3 or less.

Hereinafter, a method of manufacturing the compound semiconductor epitaxial wafer 100 of FIG. 1 will be described. First, as shown in FIG. 2, a GaAs single crystal substrate 1 having a <100> direction as a reference direction and a main axis having an off-angle of 10 ° to 20 ° is prepared. As shown in steps 1 and 2, on the main surface of the substrate 1, an n-type GaAs buffer layer 2 is formed to a thickness of, for example, 0.5 탆, and then a (Al x Ga 1 -x ) y in 1 - n-type cladding layer (4) (n-type dopant for 1㎛ consisting y p is Si), an 0.6㎛ of the active layer (non-doped) 5 and 1㎛ of the p-type cladding layer 6 , a p-type first GaP layer 7a (p-type dopant is Mg: C in the organic metal molecule can also contribute as a p-type dopant) are sequentially epitaxially grown (organometallic vapor phase growth step). The epitaxial growth of each of these layers is performed by the well-known MOVPE method. As the source gas to be each of the constituent sources of Al, Ga, In (indium) and P (phosphorus), the following materials can be used;

Al source gas: trimethyl aluminum (TMAl), triethyl aluminum (TEAl) and the like;

· Ga source gas: trimethyl gallium (TMGa), triethyl gallium (TEGa) and the like;

· In source gas: trimethyl indium (TMIn), triethyl indium (TEIn) and the like;

P source gas: trimethyl phosphorus (TMP), triethyl phosphorus (TEP), tertiary butyl phosphine (TBP), phosphine (PH 3 ) and the like.

In step 3, the second GaP layers 7b and 7c are grown on the p-type first GaP layer 7a by the HVPE method at a temperature of 650 ° C to 800 ° C (hydride vapor phase growth step) to form the first GaP layer 7a ) And the thickness of the second GaP layer 7b (7c) is set to 50 mu m or more and 250 mu m or less.

The second GaP layer is formed by forming a second GaP layer low-growth region 7b by adopting a first growth rate at a low growth rate at the start of growth, and thereafter forming a second GaP layer 7b at a second growth rate higher than the first growth rate The high-speed growth region 7c is formed, and the entire growth process is performed at 10 mu m / hr or more and 40 mu m / hr or less. More specifically, when the growth rate (first growth rate) of the second GaP low-speed growth region 7b is 10 占 퐉 / hr or less, the height of the Hillock after the formation of the second GaP layer is 10 占 퐉 or less, (100) can be obtained. Further, when the first growth rate is 5 占 퐉 / hr or less, a compound semiconductor wafer 100 having a hillock height of 1 占 퐉 or less after the formation of the second GaP layer can be obtained. The second GaP low-speed growth region 7b is preferably maintained at a low growth rate due to the first growth rate until the thickness becomes, for example, 0.5 mu m or more and 20 mu m or less, from the viewpoint of suppressing the hillock height Do. The relationship between the growth rate (first growth rate) of the second GaP low-speed growth region 7b and the hillock height occurring on the surface of the second GaP layer when the growth to the second GaP high-speed growth region 7c is completed 8.

When the above process is completed, the surface of the second GaP high-speed growth region 7c is polished by 10 탆 or more to flatten the layer thickness and remove the hillock. The first electrode 9 and the second electrode 20 are formed on the planarized second GaP layer fast growing region 7c and the respective surfaces of the substrate 1 by a vacuum evaporation method, A bonding pad 16 is disposed on the substrate 9 and baking is performed for fixing the electrode at an appropriate temperature. After dicing, the second electrode 20 is fixed to a terminal electrode (not shown) also serving as a support by using a conductive paste such as Ag paste, and the bonding pad 16 and the other terminal electrode The light emitting element 200 can be obtained by bonding the wire 17 made of Au in the form of a resin mold.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

4 is a conceptual diagram showing an example of the compound semiconductor epitaxial wafer 300 according to the second aspect of the present invention. The compound semiconductor epitaxial wafer 300 is obtained by removing the substrate 1 from the main back side of the light emitting layer portion 24 in the structure of the compound semiconductor epitaxial wafer 100 according to the first aspect of the present invention , And thus the main back side GaP layer 8 is formed on the main back surface of the exposed light emitting layer 24 (the same reference numerals are given to the parts common to the compound semiconductor epitaxial wafer 100 in Fig. 1 And a detailed description thereof will be omitted).

The main back side GaP layer 8 is formed as an n-type GaP layer. The thickness of the main back side GaP layer 8 is, for example, 50 占 퐉 or more and 250 占 퐉 or less. The main back GaP layer 8 is a third GaAp layer 8 formed by hydride vapor phase epitaxy (hereinafter referred to as a 3GaP layer 8), and the third GaAp layer low growth region 8b and the third GaAp layer high- (8c) are stacked in this order. The carrier concentrations of the third 3GaP layer low-rate growth region 8b and the third 3GaP layer fast-growing region 8c are also in the range of 1 × 10 17 / cm 3 to 2 × 10 18 / cm 3 .

Hereinafter, a method of manufacturing the compound semiconductor epitaxial wafer 300 of FIG. 4 will be described. Steps 1 to 3 shown in Figs. 5 and 6 are basically the same as the steps 1 to 3 shown in Figs. 2 and 3 as a step of growing the light emitting layer portion 24 and the main surface side GaP layer 7 A first organometallic vapor phase growth process and a second hydride vapor phase growth process). The GaAs buffer layer 2 is grown on the substrate 1 by the organic metal vapor phase growth method and then the etch stop layer 3 made of AlAs is grown and then the light emitting layer portion 24 is grown 2 and Fig. The thickness of the release layer 3 is, for example, 0.5 占 퐉.

Next, the wafer is immersed in an etching solution composed of, for example, a 10% hydrofluoric acid solution to selectively etch the AlAs release layer 3 formed between the buffer layer 2 and the light emitting layer portion 24, And the Si substrate 7 joined to the substrate 1 is removed. In addition, an etch stop layer made of AlInP is formed in place of the AlAs release layer 3, and a substrate made of GaAs is formed by using a first etchant (for example, an ammonia / hydrogen peroxide mixture solution) 1) and the buffer layer 2 are removed by etching, and then a second etchant (for example, hydrochloric acid: hydrofluoric acid may be added for removal of the Al oxide layer) having selectivity to AlInP is used to etch the etch stop layer May be removed by etching.

The third 3GaP layer 8 is formed on the main back surface of the light emitting layer portion 24 exposed by the removal of the substrate 1 by the HVPE method at a temperature of 650 占 폚 or higher (Second hydride vapor phase growth process), and the thickness of the third GaInAs layer 8 is set to 50 mu m or more and 250 mu m or less.

The 3GaP layer 8 forms a 3GaP low-speed growth region 8b by employing a first growth rate at a low growth rate at the start of growth, and thereafter, at a second growth rate higher than the first growth rate The third GaP layer high-speed growth region 8c is formed, and the entire growth process is performed at 10 mu m / hr or more and 40 mu m / hr or less. More specifically, when the growth rate (first growth rate) of the 3GaP low-speed growth region 8b is set to 10 占 퐉 / hr or less, the height of the hillocks after the formation of the 3GaP layer 8 is 10 占 퐉 or less, (300) can be obtained. Further, when the first growth rate is 5 占 퐉 / hr or less, a compound semiconductor wafer 300 having a hillock height of 1 占 퐉 or less after the formation of the 3GaP layer can be obtained. It is preferable from the viewpoint of suppressing the hill height that the low-speed growth due to the first growth rate is maintained until the thickness of the third GaP-Plow low-speed growth region 8b becomes, for example, 0.5 탆 or more and 20 탆 or less Do. The growth rate (first growth rate) of the third 3GaP layer low-speed growth region 8b and the height of the hillock generated on the surface of the third 3GaP layer 8 when the growth to the third 3GaP layer fast- Is substantially the same as the result shown in Fig. 8 for the main front-surface-side GaP layer 7.

When the above process is completed, the main surface of the second GaP high-speed growth region 7c and the main backside of the third GaAP-layer high-speed growth region 8c are each polished by 10 탆 or more to flatten the layer thickness and remove the hillocks . The first electrode 9 and the second electrode 20 are formed on the main surface of the flattened second GaP layer fast growing region 7c and the main back surface of the third GaPP fast growing region 8c by the vacuum evaporation method, respectively , The bonding pad 16 is disposed on the first electrode 9, and baking is performed for fixing the electrode at an appropriate temperature. After the dicing, the second electrode 20 is fixed to a terminal electrode (not shown) serving also as a support by using a conductive paste such as an Ag paste, The light emitting element 400 can be obtained by bonding the wire 17 and further forming a resin mold.

[Example]

(Example 1)

The compound semiconductor wafer 100 shown in Fig. 1 is formed so that each layer has a thickness of the following.

N-type AlGaInP cladding layer 4 = 1 占 퐉;

AlGaInP active layer 5 = 0.6 mu m (light emission wavelength 650 nm);

P-type AlGaInP cladding layer 6 = 1 占 퐉;

First GaP layer 7a = 3 占 퐉;

The second GaP layer low growth region 7b = about 15 占 퐉;

The second GaP layer fast growing region 7c = about 150 占 퐉

Further, the GaAs single crystal substrate uses a <100> direction as a reference direction and an off-angle of about 15 ° with respect to the reference direction. the n-type AlGaInP cladding layer 4, the AlGaInP active layer 5, the p-type AlGaInP cladding layer 6 and the first GaP layer 7a are formed using an MOVPE apparatus (an organometallic vapor phase growth step) The compound semiconductor wafer 100 is formed by forming the growth region 7b and the second GaP layer fast growth region 7c by using a hydride vapor phase growth apparatus in a hydrogen atmosphere at 650 DEG C or more and 800 DEG C or less (hydride vapor phase growth process) Can be obtained. The growth rate (first growth rate) of the second GaP low-speed growth region 7b is about 9.5 占 퐉 / hr, the growth rate (second growth rate) of the second GaP layer fast growing region 7c is about 38 占 퐉 / The overall growth rate of the hydride vapor phase growth process is about 30 탆 / hr.

The height of hillocks generated on the main surface of the compound semiconductor wafer 100 obtained under the above conditions, that is, the surface of the second GaP layer fast growing region 7c was observed with a laser microscope and found to be about 8 mu m.

(Example 2)

The organic metal vapor phase growth process and the hydride vapor phase growth process were performed under the same conditions as in Example 1 except that the growth rate (first growth rate) of the second GaP low-speed growth region 7b was set to about 5 탆 / hr, The height of the hillock generated on the surface of the 2GaP layer fast growing region 7c was observed with a laser microscope and found to be about 1 mu m.

(Example 3)

The substrate 1 is removed from the compound semiconductor wafer 100 of Embodiment 1 and a third GaAp layer 8 is formed on the main back surface of the exposed light emitting layer portion 24 so that each layer has the following thickness.

Third GaP layer low growth region 8b = about 15 占 퐉;

The third GaP layer high-speed growth region 8c = about 150 mu m.

The 3GaP low-speed growth region 8b and the 3GaP high-speed growth region 8c are formed by using a hydride vapor phase growth apparatus in a hydrogen atmosphere at 650 ° C to 800 ° C (hydride vapor phase growth step) A semiconductor wafer 300 can be obtained. The growth rate (first growth rate) of the 3GaP layer low-speed growth region 8b is about 9.5 占 퐉 / hr, the growth rate (second growth rate) of the 3GaP layer fast growing region 8c is about 38 占 퐉 / The overall growth rate of the hydride vapor phase growth process is about 30 탆 / hr.

As a result of observing the height of hillocks generated on the surface of the compound semiconductor wafer 400 obtained under the above conditions, that is, on the surface of the third GaP high-speed growth region 8c with a laser microscope, the second GaP layer fast growing region 7c, Lt; / RTI &gt;

(Example 4)

The organometallic vapor phase growth process and the hydride vapor phase growth process were carried out under the same conditions as in Example 3 except that the growth rate (third growth rate) of the 3GaP low-speed growth region 8b was set to about 5 탆 / hr, The height of the hillocks generated on the surface of the 3GaP-layer high-speed growth region 8c was observed with a laser microscope and was found to be about 1 탆.

Claims (13)

A GaAs single crystal substrate (GaAs single crystal substrate) having a <100> direction as a reference direction and a main axis having an off angle of 10 ° or more and 20 ° or less includes two or more Group III elements (Light emitting layer portion) composed of (Al x Ga 1 -x ) y In 1 -y P (0? X? 1, 0 <y? 1) Layers are laminated in order,
Wherein the GaP layer has a non-polished surface and a height of a Hillock formed on the unpolished surface is 10 μm or less. 2. The compound semiconductor epitaxial wafer according to claim 1,
(Al x Ga 2 O 3), which is formed by epitaxial growth on a GaAs single crystal substrate having a <100> direction as a reference direction and a main axis having an off-angle of 10 ° or more and 20 ° or less, 1- x ) y In 1 -y P (0? X? 1, 0 <y? 1)
(Main surface) located on the side opposite to the side of the light emitting layer portion grown on the GaAs single crystal substrate facing the GaAs single crystal substrate is a main surface and a main surface on the side facing the GaAs single crystal substrate is a main surface A main surface side GaP layer having a thickness of 50 mu m or more and 250 mu m or less and being epitaxially grown on the main surface of the light emitting layer portion,
And a main back side GaP layer having a thickness of 50 탆 or more and 250 탆 or less epitaxially grown on the main back surface of the light emitting layer portion appearing by removing the GaAs single crystal substrate,
Wherein the main surface side GaP layer and the main back side GaP layer all have a non-polished surface and a height of a hillock formed on the unpolished surface is 10 m or less. A single wafer.
3. The method according to claim 1 or 2,
Wherein the height of the hillocks is 1 占 퐉 or less.
(Al x Ga 1-x ) y In 1- (Al x Ga 1-x ) y 1- y containing two or more Group III elements on a GaAs single crystal substrate having a <100> direction as a reference direction and a main axis having an off- y P (0? x? 1, 0 < y? 1), and a first GaP layer are sequentially formed on the first GaP layer; and a second GaP layer is formed on the first GaP layer And a hydride vapor phase growth step of growing the hydride vapor phase,
Wherein the growth rate of the first 2GaP layer, at the beginning of the growing period previously determined at a first growth rate, and in the first second growth rate higher than the growth rate after the expiration of said period, and also in the entire growth process Wherein the rate of growth of the second GaP layer on the average is 10 占 퐉 / hr or more and 40 占 퐉 / hr or less.
5. The method of claim 4,
Wherein the first growth rate is set to 10 占 퐉 / hr or less.
5. The method of claim 4,
Wherein the first growth rate is set to 5 占 퐉 / hr or less.
5. The method of claim 4,
Wherein the sum of the thicknesses of the first GaP layer and the second GaP layer is set in a range from 50 占 퐉 to 250 占 퐉.
8. The method according to any one of claims 4 to 7,
Wherein the second GaP layer is grown at a temperature of 650 ° C to 800 ° C.
(Al x Ga 1-x ) y In 1- (Al x Ga 1-x ) y 1- y containing two or more Group III elements on a GaAs single crystal substrate having a <100> direction as a reference direction and a main axis having an off- y P (0? x? 1, 0 <y? 1), and a first GaP layer,
A first hydride vapor phase growth step of forming a second GaP layer on the first GaP layer,
A GaAs single crystal substrate removing step of removing the GaAs single crystal substrate from the light emitting layer part;
A second hydride vapor phase growth step of forming a third GaP layer on the main back surface of the light emitting layer portion, which is caused by removal of the GaAs single crystal substrate;
Are carried out in this order, and
The growth rate of the second GaP layer and the growth rate of the third GaP layer is set to a first growth rate for a predetermined period of time at the start of growth and a second growth rate higher than the first growth rate after the lapse of the period, Wherein the rate of growth of the second GaP layer and the third GaP layer on the average is 10 占 퐉 / hr or more and 40 占 퐉 / hr or less in the entire growth process.
10. The method of claim 9,
Wherein the first growth rate is set to 10 占 퐉 / hr or less.
10. The method of claim 9,
Wherein the first growth rate is set to 5 占 퐉 / hr or less.
10. The method of claim 9,
Wherein the sum of the thicknesses of the first GaP layer and the second GaP layer and the thickness of the third GaP layer are 50 占 퐉 or more and 250 占 퐉 or less, respectively.
13. The method according to any one of claims 9 to 12,
Wherein the second GaP layer and the third GaP layer are grown at a temperature of 650 ° C or higher and 800 ° C or lower, respectively.
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