JP2001156002A - Semiconductor base material and method of manufacturing the same - Google Patents

Semiconductor base material and method of manufacturing the same

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Publication number
JP2001156002A
JP2001156002A JP33642199A JP33642199A JP2001156002A JP 2001156002 A JP2001156002 A JP 2001156002A JP 33642199 A JP33642199 A JP 33642199A JP 33642199 A JP33642199 A JP 33642199A JP 2001156002 A JP2001156002 A JP 2001156002A
Authority
JP
Japan
Prior art keywords
substrate
crystal
semiconductor
growth
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP33642199A
Other languages
Japanese (ja)
Other versions
JP3471687B2 (en
Inventor
Hiroaki Okagawa
広明 岡川
Kazuyuki Tadatomo
一行 只友
Yoichiro Ouchi
洋一郎 大内
Masahiro Koto
雅弘 湖東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Cable Industries Ltd
Original Assignee
Mitsubishi Cable Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP33642199A priority Critical patent/JP3471687B2/en
Application filed by Mitsubishi Cable Industries Ltd filed Critical Mitsubishi Cable Industries Ltd
Priority to US09/936,683 priority patent/US6940098B1/en
Priority to EP04022766A priority patent/EP1501118B1/en
Priority to PCT/JP2000/001588 priority patent/WO2000055893A1/en
Priority to EP00909660A priority patent/EP1184897B8/en
Priority to KR1020017011785A priority patent/KR100677683B1/en
Priority to DE60043122T priority patent/DE60043122D1/en
Priority to DE60030279T priority patent/DE60030279T2/en
Publication of JP2001156002A publication Critical patent/JP2001156002A/en
Application granted granted Critical
Publication of JP3471687B2 publication Critical patent/JP3471687B2/en
Priority to US10/842,777 priority patent/US7115486B2/en
Priority to US11/529,905 priority patent/US7504324B2/en
Priority to US11/541,201 priority patent/US7589001B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To avoid various problems caused by ELO growth using ordinary mask layers and, in addition, to simplify the manufacturing process of a semiconductor base material. SOLUTION: In this method of manufacturing a semiconductor base material, a substrate 1 having a growing surface made on an uneven surface and masks 3 formed on the recessed surface 12 of the growing surface as shown in Fig. (a) is used. When vapor growth is made by using the substrate 1, crystal growth occurs only from the tops of the projecting sections 11 of the growing surface due to the masks 3. At starting the crystal growth, therefore, crystal units 20 only occur as shown in Fig. (b), when the crystal growth is continued, films grown in the lateral direction from the tops of the projecting section 11 are joined together, and finally, cover the uneven surface of the substrate 1 by leaving cavity sections 13 as they are, in the recessed sections 12 as shown in Fig. (c). In this case, low dislocation areas are formed in the laterally grown sections, namely, above the recessed sections 12, and the quality of the formed film is improved.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、半導体基材及びその作
製方法に関し、特に転位欠陥が生じ易い半導体材料を用
いる場合に有用な構造及び方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate and a method for manufacturing the same, and more particularly to a structure and a method useful when a semiconductor material in which dislocation defects easily occur is used.

【0002】[0002]

【従来の技術】GaN系材料を結晶成長する場合、Ga
N系材料は格子整合する基板がないためにサファイア、
SiC、スピネル、最近ではSiなどの格子整合しない
基板を用いている。しかしながら、格子整合しないこと
に起因し作製したGaNの膜中には1010個/cm2
の転位が存在している。近年高輝度の発光ダイオード、
半導体レーザーなどが実現されているが、特性向上を図
るためには転位密度の低減が望まれている。
2. Description of the Related Art When a GaN-based material is crystal-grown, Ga
N-type materials have no lattice-matched substrate, so sapphire,
A substrate that does not lattice match, such as SiC, spinel, or recently Si, is used. However, as many as 10 10 dislocations / cm 2 exist in the GaN film produced due to lack of lattice matching. In recent years, high brightness light emitting diodes,
Although a semiconductor laser or the like has been realized, a reduction in dislocation density is desired to improve characteristics.

【0003】[0003]

【発明が解決しようとする課題】この転位密度低減を図
る方法としては、例えばGaN系半導体結晶等を、サフ
ァイア基板上にバッファ層、GaN層を成長しこれを下
地基板とし、前記基板上に部分的なマスクを設けて選択
成長する事でラテラル方向の結晶成長を行わせ、転位密
度を低減した高品質な結晶を得る方法が提案されている
(例えば特開平10−312971号公報)。
As a method for reducing the dislocation density, for example, a GaN-based semiconductor crystal or the like is grown on a sapphire substrate by growing a buffer layer and a GaN layer on a sapphire substrate, and using the GaN layer as an undersubstrate. A method has been proposed in which a crystal is grown in the lateral direction by providing a selective mask and performing selective growth to obtain a high-quality crystal with reduced dislocation density (for example, JP-A-10-312971).

【0004】しかしながら上記の方法によれば、マスク
層上にラテラル方向成長された部分において、ラテラル
成長方向にc軸が微小量ながら傾斜するといった問題が
生じ、これにより結晶品質が低下するという新たな問題
が有ることが判明した(MSR1998 Fall 、Meeti
ng 予稿集G3・1)。これは、X線ロッキングカーブ
測定(XRC)の入射方位依存性を測定(¢スキャン)
することでも確認できる。即ち、ラテラル成長方向から
の入射X線によるX線ロッキングカーブの半値全幅(F
WHM)は、マスク層のストライプ方向からのX線によ
るFWHM値より大きくなっており、C軸の微小傾斜
(チルティング)に方位依存性がある事を示している。
この事は、マスク上のラテラル成長の合体部分に新たな
欠陥を多数誘起する可能性を示唆している。
However, according to the above-mentioned method, a problem arises in that the c-axis is tilted in the lateral growth direction with a small amount in the laterally grown portion on the mask layer, thereby deteriorating the crystal quality. It turned out to be a problem (MSR 1998 Fall, Meeti
ng Proceedings G3.1). This measures the incident azimuth dependence of X-ray rocking curve measurement (XRC) (¢ scan)
You can also confirm by doing. That is, the full width at half maximum (F) of the X-ray rocking curve due to the incident X-rays from the lateral growth direction.
WHM) is larger than the FWHM value of the mask layer by X-rays from the stripe direction, indicating that the slight tilt (tilting) of the C-axis has an orientation dependency.
This suggests that many new defects may be induced in the merged portion of the lateral growth on the mask.

【0005】このような問題を解消する試みとして、S
iCのベース基板上にバッファ層及びGaN層を設けた
基板に対して、SiC層にまで至るストライプ溝加工を
施して凸部を形成し、この凸部の上方部に位置すること
になるGaN層から結晶成長させる方法が提案されてい
る(MRS1998 Fall Meeting予稿集G3.38)。
この方法によればSiO2マスク層無しで選択成長させ
る事も出来、上述のSiO2マスクを用いることに起因
する各種の問題を解消することが可能となる。
As an attempt to solve such a problem, S
A substrate provided with a buffer layer and a GaN layer on an iC base substrate is subjected to stripe groove processing up to the SiC layer to form a convex portion, and the GaN layer located above the convex portion (MRS 1998 Fall Meeting Proceedings G3.38) has been proposed.
According to this method, selective growth can be performed without the SiO 2 mask layer, and various problems caused by using the above-described SiO 2 mask can be solved.

【0006】上記方法は、ベース基板としてサファイア
基板を使用する事ができその方法も開示されている(例
えば、特開平11−191659号公報)。しかしなが
ら上記方法では、サファイアベース基板上にバッファ層
材料ならびにGaN系材料を結晶成長させ、一旦成長炉
から取り出し溝加工を施し、その後再び結晶成長を行う
というステップが必要となることから、製造プロセスが
複雑化するという新たな不都合が発生し、作業工程が多
くなりコストがかかるなどの問題を有していた。
In the above method, a sapphire substrate can be used as a base substrate, and a method thereof is also disclosed (for example, JP-A-11-191659). However, the above-described method requires a step of growing a buffer layer material and a GaN-based material on a sapphire base substrate, crystallizing the buffer layer once, removing the groove from the growth furnace, and then performing crystal growth again. There has been a problem that new inconvenience such as complication occurs, the number of work steps increases, and the cost increases.

【0007】また(応用物理学会99秋予稿集2P−W
−8)ではGaN基板に段差をつけ埋め込み成長をする
ことで低転位密度領域を得る試みも開示されている。こ
こでは埋め込んだ層の一部に低転位密度領域が形成され
ている。しかしながら上記方法では低転位密度領域を得
るためには、凸部の間隔を広げる必要、もしくは凹部の
深さを深くする必要があった。このようにするため埋め
込みに時間をかけ厚く成長をする必要があり、厚膜化に
伴うクラックの発生、時間がかかるためコストがかか
る、など種々の問題を内在していた。
[0007] (Applied Physics Society 99 Autumn Proceedings 2P-W
-8) also discloses an attempt to obtain a low dislocation density region by growing a GaN substrate with a step and performing burying growth. Here, a low dislocation density region is formed in a part of the buried layer. However, in the above method, in order to obtain a low dislocation density region, it is necessary to increase the interval between the convex portions or to increase the depth of the concave portions. In order to achieve this, it is necessary to take a long time to bury the film and to grow it thickly, and there are various problems such as the occurrence of cracks due to the thickening of the film and the cost of taking time.

【0008】またSi基板上にGaN系材料を結晶成長
する試みもなされているが、GaN系結晶を成長すると
熱膨張係数差に起因した反りやクラックが発生し良質の
結晶成長を行えない問題があった。
Attempts have also been made to grow a GaN-based material on a Si substrate. However, when a GaN-based crystal is grown, warpage and cracks are generated due to a difference in thermal expansion coefficient, so that a high-quality crystal cannot be grown. there were.

【0009】従って本発明は上記問題に鑑み、通常のマ
スク層を用いるELO成長に起因する種々の問題を回避
し、かつ製造工程の簡略化を図ることを目的としてい
る。またマスクを持たない段差構造の埋め込み成長に起
因した問題を解決する事を目的としている。さらにSi
基板等を用いた場合の反りやクラックの発生を押さえる
ことを目的としている。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to avoid various problems caused by ELO growth using a normal mask layer and to simplify the manufacturing process. It is another object of the present invention to solve the problem caused by the buried growth of the step structure having no mask. Furthermore, Si
It is intended to suppress the occurrence of warpage and cracks when using a substrate or the like.

【0010】[0010]

【課題を解決するための手段】本発明の半導体基材は、
基板と該基板上に気相成長された半導体結晶とからなる
半導体基材であって、前記基板の結晶成長面が凹凸面と
され、凹部はその層からは実質的に結晶成長し得ないマ
スクで覆われ、前記半導体結晶は該凹凸面における凸部
の上方部から専ら結晶成長されたものであることを特徴
とするものである。この場合、上記半導体結晶がInG
aAlNであることが望ましい。
The semiconductor substrate of the present invention comprises:
A semiconductor substrate comprising a substrate and a semiconductor crystal vapor-grown on the substrate, wherein the crystal growth surface of the substrate is an uneven surface, and the concave portion is substantially incapable of crystal growth from the layer. And the semiconductor crystal is formed by crystal growth exclusively from the upper part of the projection on the uneven surface. In this case, the semiconductor crystal is InG
aAlN is desirable.

【0011】上記基板の結晶成長面の凸部を、平行なス
トライプ形状からなる凸部とすることが好ましい。さら
に、上記半導体結晶がInGaAlNであって、かつス
トライプの長手方向が該InGaAlN結晶の(1−1
00)面と垂直であるストライプとすることがより好ま
しい。
It is preferable that the projection on the crystal growth surface of the substrate is a projection having a parallel stripe shape. Further, the semiconductor crystal is InGaAlN, and the longitudinal direction of the stripe is (1-1) of the InGaAlN crystal.
More preferably, the stripe is perpendicular to the (00) plane.

【0012】本発明にかかるより具体的な半導体基材
は、基板と該基板上に気相成長された半導体結晶とから
なる半導体基材であって、前記基板の結晶成長面が凹凸
面とされ、凹部はその層からは実質的に結晶成長し得な
いマスクで覆われ、前記半導体結晶は該凹凸面における
凸部の上方部から専ら結晶成長された半導体基材におい
て、前記凹凸面が成長された半導体結晶で覆われてお
り、この半導体結晶層と前記凹凸面における凹部との間
には空洞部が形成されていることを特徴とするものであ
る。
A more specific semiconductor substrate according to the present invention is a semiconductor substrate comprising a substrate and a semiconductor crystal grown by vapor deposition on the substrate, wherein the crystal growth surface of the substrate has an uneven surface. The concave portion is covered with a mask that cannot substantially grow crystals from the layer, and the semiconductor crystal is grown on the semiconductor substrate exclusively crystal-grown from above the convex portion on the concave-convex surface. And a cavity portion is formed between the semiconductor crystal layer and the concave portion on the uneven surface.

【0013】また、当該半導体基材を、基板の結晶成長
面を凹凸面とし、凹部をその層からは実質的に結晶成長
し得ないマスクで覆い、気相成長法により前記凹凸面に
おける凸部の上方部から専ら結晶成長されることで形成
された第一の半導体結晶と、この第一の半導体結晶の表
面を凹凸面とし、同様に凹部をその層からは実質的に結
晶成長し得ないマスクで覆い、その凸部の上方部から専
ら結晶成長されることで形成された第二の半導体結晶と
からなる構成とすることもできる。
Further, the semiconductor base material has an uneven surface on the crystal growth surface of the substrate, the concave portion is covered with a mask that cannot substantially grow crystals from the layer, and the convex portion on the uneven surface is formed by a vapor phase growth method. A first semiconductor crystal formed by exclusively growing a crystal from the upper part of the first semiconductor crystal, and the surface of the first semiconductor crystal has an uneven surface, and similarly, a concave portion cannot be substantially grown from the layer. A configuration including a second semiconductor crystal formed by covering with a mask and exclusively performing crystal growth from above the convex portion may be employed.

【0014】さらに、上記半導体基材における第二の半
導体結晶の表面を凹凸面とし、凹部をその層からは実質
的に結晶成長し得ないマスクで覆い、その上に同様に気
相成長法により形成された第3の半導体層乃至は同様の
工程を繰り返すことで多重的に形成された複数の半導体
層を具備させるようにしても良い。
Further, the surface of the second semiconductor crystal in the semiconductor substrate is made uneven, and the recess is covered with a mask that cannot substantially grow crystals from the layer. A plurality of semiconductor layers formed in a multiplexed manner by repeating the formed third semiconductor layer or similar steps may be provided.

【0015】本発明の半導体基材の作製方法は、基板上
に半導体結晶を気相成長させるにあたり、予め基板表面
に凹凸面加工を施し、該凹凸面における凹部をその層か
らは実質的に結晶成長し得ないマスクで覆い、次いで該
基板に対して原料ガスを供給し、前記凹凸面における凸
部の上方部から専ら結晶成長される半導体結晶にて前記
基板の凹凸面を覆うことを特徴とする。
According to the method of manufacturing a semiconductor substrate of the present invention, when a semiconductor crystal is vapor-phase grown on a substrate, the surface of the substrate is subjected to a roughening process in advance, and the concave portion on the rough surface is substantially crystallized from the layer. Covering with a mask that cannot grow, then supplying a source gas to the substrate, and covering the uneven surface of the substrate with a semiconductor crystal that is exclusively crystal-grown from above the convex portion in the uneven surface. I do.

【0016】[0016]

【作用】本発明は、バッファ層等すら形成していない状
態の基板に対して凹凸面を設け、凹部にその層からは実
質的に成長し得ないマスクで覆うことで、結晶成長当初
から実質的に低転位密度領域を形成可能なラテラル成長
を起こす素地面を予め提供しておく点に特徴を有する。
即ち、気相成長させた場合、成長初期には基板表面全体
に原料が拡散するが、凹部マスク上では結晶成長が生じ
難いため、凸部での成長が優位となり、ひいては凸部か
ら成長した層に覆われるというものである。
According to the present invention, an uneven surface is provided on a substrate in which even a buffer layer or the like is not formed, and the concave portion is covered with a mask which cannot substantially grow from the layer, so that the substrate can be substantially grown from the beginning of crystal growth. It is characterized in that a substrate for lateral growth capable of forming a low dislocation density region is provided in advance.
That is, in the case of vapor phase growth, the raw material diffuses over the entire substrate surface in the initial stage of growth, but since crystal growth is unlikely to occur on the concave mask, the growth in the convex portion becomes dominant, and thus the layer grown from the convex portion. It is covered with.

【0017】この凸部の成長ではC軸と垂直方向のいわ
ゆるラテラル成長が起き、低転位密度領域の形成が達成
されることになる。このように低転位密度領域を有する
結晶基材の成長が、一回行うだけで可能となり、その後
の成長工程を連続して行うことができるものである。ま
た凹部での成長を抑えることができるため、ラテラル成
長の効率が良くなるものである。
In the growth of the projections, so-called lateral growth in the direction perpendicular to the C axis occurs, and a low dislocation density region is formed. Thus, the growth of the crystal base material having the low dislocation density region can be performed only once, and the subsequent growth process can be performed continuously. In addition, since growth in the concave portion can be suppressed, the efficiency of lateral growth is improved.

【0018】[0018]

【発明の実施の態様】以下図面に基いて、本発明の実施
態様につき詳細に説明する。図1(a)乃至(c)は本
発明に係る半導体基材の結晶成長状態を説明するための
断面図である。図において、1は基板であり、2は該基
板1上に気相成長された半導体結晶をそれぞれ示してい
る。基板1の結晶成長面には凸部11及び凹部12が形
成されており、前記凸部11の上方部から専ら結晶成長
が行われるよう構成されている。また凹部12は、その
層からは実質的に成長し得ないマスク3で覆われてい
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings. 1A to 1C are cross-sectional views for explaining a crystal growth state of a semiconductor substrate according to the present invention. In the drawing, reference numeral 1 denotes a substrate, and 2 denotes a semiconductor crystal grown on the substrate 1 by vapor phase. A convex portion 11 and a concave portion 12 are formed on the crystal growth surface of the substrate 1, and the crystal growth is performed exclusively from above the convex portion 11. The recess 12 is covered with a mask 3 that cannot substantially grow from the layer.

【0019】本発明でいう基板とは、各種の半導体結晶
層を成長させるためのベースとなる基板であって、格子
整合のためのバッファ層等も未だ形成されていない状態
のものを言う。このような基板としては、サファイア
(C面、A面、R面)、SiC(6H、4H、3C)、
GaN、Si、スピネル、ZnO,GaAs,NGOな
どを用いることができるが、発明の目的に対応するなら
ばこのほかの材料を用いてもよい。またこれら基板から
offしたものを用いてもよい。
The substrate referred to in the present invention is a substrate serving as a base for growing various semiconductor crystal layers, in which a buffer layer or the like for lattice matching has not been formed yet. Such substrates include sapphire (C plane, A plane, R plane), SiC (6H, 4H, 3C),
GaN, Si, spinel, ZnO, GaAs, NGO, and the like can be used, but other materials may be used as long as they correspond to the object of the invention. In addition, those off from these substrates may be used.

【0020】基板1上に成長される半導体結晶としては
種々の半導体材料を用いることができ、AlxGa1-x-y
InyN(0≦x≦1,0≦y≦1)ではx、yの組成
比を変化させたGaN、Al0.5Ga0.05N、In0.5
0.05Nなどが例示できる。
Various semiconductor materials can be used for the semiconductor crystal grown on the substrate 1, and Al x Ga 1-xy
In In y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), GaN, Al 0.5 Ga 0.05 N, and In 0.5 G in which the composition ratio of x and y is changed
a 0.05 N and the like.

【0021】基板1の結晶成長面に形成される凸部11
は、その上方部から専ら結晶成長が行われるような形状
とすると有効である。「上方部から専ら結晶成長が行わ
れる」とは、凸部11の頂点ないし頂面及びその近傍で
の結晶成長が優勢に行い得る状態をいい、成長初期には
凹部での成長が生じてもよいが最終的には凸部11の結
晶成長が優勢となることを指す。
Convex portion 11 formed on the crystal growth surface of substrate 1
It is effective to make the shape such that crystal growth is performed exclusively from above. The phrase “crystal growth is performed exclusively from the upper part” refers to a state in which crystal growth can be predominantly performed at the apex or top surface of the convex part 11 and in the vicinity thereof. Good, but ultimately indicates that the crystal growth of the convex portion 11 becomes dominant.

【0022】また、凹部12上に作製するマスク3は、
その層からは実質的に結晶成長し得ない作用を果たして
いればよい。「その層からは実質的に成長し得ない」と
は結晶成長が生じ難い状態のことをいい、成長初期には
凹部マスク上での成長が生じてもよいが最終的には凸部
11の結晶成長が優勢となることを指す。つまり上方部
を起点としたラテラル成長により低転位密度領域が形成
されれば、従来のマスクを要するELOと同様の効果が
ある。これが本発明では基板の加工のみで、結晶成長一
回で低転位密度領域を形成できる点に特徴がある。以
下、この点についての説明を、図1、図2に基づいて行
う。
The mask 3 formed on the recess 12 is
It suffices if the layer does not substantially grow crystals. The phrase "can not substantially grow from that layer" means a state in which crystal growth is unlikely to occur. In the initial stage of growth, growth on the concave mask may occur. Refers to the predominance of crystal growth. That is, if a low dislocation density region is formed by lateral growth starting from the upper part, the same effect as that of the conventional ELO requiring a mask can be obtained. This is a feature of the present invention in that a low dislocation density region can be formed by a single crystal growth only by processing the substrate. Hereinafter, this point will be described with reference to FIGS.

【0023】図1、図2は凸部をストライプ状に形成し
たものの横断面図である。先ず、図1では、(a)図に示
すように溝幅Bに対し溝深さ(凸部高さ)hが深い基板
1を用いる場合を例示している。この場合原料ガスが凹
部12及びその近傍に十分至らず、また凹部12にはマ
スク3を施していることもあって、凸部11の上方部か
らしか結晶成長が起こらない。図1(b)において、20
はこの結晶成長開始時の結晶単位を示している。このよ
うな状況下、結晶成長が続くと凸部11の上方部を起点
とし横方向に成長した膜がつながって、やがて図1(c)
のように凹部に空洞部13を残したまま、基板1の凹凸
面を覆うことになる。この場合、横方向に成長した部
分、つまり凹部12上部には低転位領域が形成され、作
製した膜の高品質化が図れている。
FIG. 1 and FIG. 2 are cross-sectional views of a projection formed in a stripe shape. First, FIG. 1 illustrates a case where a substrate 1 having a groove depth (height of a convex portion) h larger than a groove width B as shown in FIG. In this case, the source gas does not sufficiently reach the concave portion 12 and its vicinity, and since the concave portion 12 is covered with the mask 3, crystal growth occurs only from above the convex portion 11. In FIG. 1B, 20
Indicates the crystal unit at the start of the crystal growth. Under such circumstances, when the crystal growth continues, the films grown in the lateral direction starting from the upper part of the convex portion 11 are connected, and the film shown in FIG.
As described above, the concave / convex surface of the substrate 1 is covered with the cavity 13 left in the concave. In this case, a low dislocation region is formed in the portion grown in the lateral direction, that is, in the upper part of the concave portion 12, thereby improving the quality of the formed film.

【0024】図2は、溝幅Bに対し溝深さ(凸部高さ)
hが非常に浅い場合、もしくは凸部11の幅Aに対し溝
幅Bが非常に広い基板1を用いる場合を例示している
(図2(a)参照)。この場合、原料ガスは凹部12のマ
スク3上及びその近傍にまで到達し得るため凹部12で
の成長が生じる可能性はある。しかし、凸部上部での成
長に比べ成長速度は非常に遅い。これはマスク3上に到
達した原料が再びガス中に脱離する割合が多いからであ
る。而して、凸部11の上方部から横方向の結晶成長が
生じ、図2(b)に示すように、凸部11の上方部と凹部
12表面に結晶単位20が生成される状態となる。この
ような状況下、結晶成長が続くと凸部11の上方部を起
点とし横方向に成長した膜がつながって、やがて図2
(c)のように基板1の凹凸面を覆うことになる。この場
合、凸部11を起点とし横方向成長した部分が図1の例
に比べて多いため、低転位領域の割合が多く、作製した
膜全体でみると図1の場合に比べて高品質化が図れてい
ることになる。
FIG. 2 shows groove depth (groove height) with respect to groove width B.
The case where h is very shallow, or the case where the substrate 1 whose groove width B is very large with respect to the width A of the convex portion 11 is used (see FIG. 2A). In this case, since the source gas can reach the mask 3 in the concave portion 12 and its vicinity, the growth in the concave portion 12 may occur. However, the growth rate is much slower than the growth at the upper part of the protrusion. This is because the rate at which the raw material reaching the mask 3 is desorbed again into the gas is large. As a result, crystal growth in the lateral direction occurs from the upper part of the convex part 11, and as shown in FIG. 2B, a crystal unit 20 is generated on the upper part of the convex part 11 and on the surface of the concave part 12. . Under such circumstances, when the crystal growth continues, the films grown in the lateral direction starting from the upper part of the convex portion 11 are connected, and the film shown in FIG.
As shown in (c), the uneven surface of the substrate 1 is covered. In this case, the portion grown in the lateral direction starting from the convex portion 11 is larger than in the example of FIG. 1, so that the ratio of the low dislocation region is large, and the quality of the formed film is higher than that of FIG. Will be achieved.

【0025】本発明にあっては、このような凸部11で
あれば特に制限はなく各種の形状を採用することができ
る。具体的には、上述したような溝幅Bに対し溝深さ
(凸部高さ)hが深い場合、溝幅Bに対し溝深さ(凸部
高さ)hが浅い場合、さらに溝幅Bに対し溝深さ(凸部
高さ)hが非常に浅い場合、もしくは凸部11の幅Aに
対し溝幅Bが非常に広い場合など種々の組み合わせを行
う事ができる。特に凸部11の幅Aに対し溝幅Bが広い
場合、凸部11上部を起点とし横方向成長した部分が多
くなり、低転位領域が広く形成される点で好ましい。
In the present invention, there is no particular limitation as long as such a convex portion 11 is used, and various shapes can be adopted. Specifically, when the groove depth (projection height) h is larger than the groove width B as described above, when the groove depth (projection height) h is smaller than the groove width B, the groove width is further increased. Various combinations can be performed, such as when the groove depth (height of the convex portion) h is very shallow with respect to B, or when the groove width B is very large with respect to the width A of the convex portion 11. In particular, it is preferable that the groove width B is wider than the width A of the convex portion 11 because a portion grown in the lateral direction starting from the upper portion of the convex portion 11 increases and a low dislocation region is formed widely.

【0026】このような凹凸面の形成の態様としては、
島状の点在型の凸部、ストライプ型の凸条からなる凸
部、格子状の凸部、これらを形成する線が曲線である凸
部などが例示できる。これら凸部の態様の中でも、スト
ライプ型の凸条を設ける態様のものは、その作製工程を
簡略化できると共に、規則的なパターンが作製容易であ
る点で好ましい。ストライプの長手方向は任意であって
よいが、基板上に成長させる材料をGaNとした場合、
GaN系材料の<11−20>方向や<1−100>方
向が好ましい。特に<1−100>方向にした場合、
{1−101}面などの斜めファセットが形成され難い
ため横方向成長(ラテラル成長)が速くなる。この結果
凹凸面を覆うのが速くなる点で特に好ましい。
As a mode of forming such an uneven surface,
Examples include island-shaped dotted projections, stripe-shaped projections, lattice-shaped projections, and projections in which the lines forming these are curved. Among these projections, the one in which the stripe-shaped projections are provided is preferable because the manufacturing process can be simplified and a regular pattern can be easily manufactured. The longitudinal direction of the stripe may be arbitrary, but when the material to be grown on the substrate is GaN,
The <11-20> direction and the <1-100> direction of the GaN-based material are preferable. In particular, in the case of <1-100> direction,
Since the oblique facet such as the {1-101} plane is hardly formed, the lateral growth (lateral growth) is accelerated. As a result, it is particularly preferable that the uneven surface is quickly covered.

【0027】凹部12上に形成するマスク3としては、
その層からは実質的に成長し得ないようにしていればよ
く、SiO、SiNx、TiO、ZrOなどが利
用できる。またこれら材料の積層構造とすることも可能
である。
As the mask 3 formed on the concave portion 12,
It is sufficient that the layer does not substantially grow from that layer, and SiO 2 , SiNx, TiO 2 , ZrO 2 and the like can be used. It is also possible to adopt a laminated structure of these materials.

【0028】図1に示す実施例のように、空洞部13を
残したまま基板1の凹凸部を埋め込み、続いてその上に
発光部を成長して発光素子を作製した場合、空洞部と半
導体界面の屈折率差が大きく取れる。この結果発光部下
方に向かった光がこの界面で反射される割合が増える。
例えばLEDを、サファイア基板面を下側にしてダイボ
ンドを行った場合は上方に取り出せる光量が増えるため
好ましい。
As in the embodiment shown in FIG. 1, when the light-emitting element is manufactured by filling the uneven portion of the substrate 1 while leaving the hollow portion 13 and then growing the light-emitting portion thereon, the hollow portion and the semiconductor A large difference in the refractive index at the interface can be obtained. As a result, the rate at which light directed downward from the light emitting portion is reflected at this interface increases.
For example, when the LED is die-bonded with the sapphire substrate surface facing downward, it is preferable because the amount of light that can be extracted upward increases.

【0029】また空洞部13を残したまま埋め込む事
は、基板1とその上に成長する半導体層との接触面積を
小さくできるという事であるため、半導体中に格子定数
差や熱膨張係数差に起因する歪を低減できる面で好まし
い。この歪の低減は、サファイア上にGaN系材料を厚
く成長した時に発生する反りを低減させる効果がある。
特に従来法ではSi基板上にGaN系材料を結晶成長す
る際に熱膨張係数差に起因した反りやクラックが発生し
良質の結晶成長を行えない問題があったが、本発明によ
る歪低減によりこの問題を解消できる。
Further, burying the cavity 13 while leaving it intact means that the contact area between the substrate 1 and the semiconductor layer grown thereon can be reduced, so that the difference between the lattice constant and the coefficient of thermal expansion in the semiconductor is reduced. This is preferable in that the resulting distortion can be reduced. This reduction in strain has the effect of reducing the warpage that occurs when a GaN-based material is grown thick on sapphire.
In particular, in the conventional method, when a GaN-based material is crystal-grown on a Si substrate, there is a problem that warpage and cracks are generated due to a difference in thermal expansion coefficient, so that high-quality crystal growth cannot be performed. Eliminate problems.

【0030】さらに基板1とその上に成長する半導体層
2との接触面積を小さくできる事を利用すると、半導体
層2を厚く成長していった場合、この小さい接触部に応
力が集中し、この部分から基板1と半導体層2の分離が
可能となる。これを応用する事でGaNなどの基板が作
製可能となる。
Further, taking advantage of the fact that the contact area between the substrate 1 and the semiconductor layer 2 grown thereon can be reduced, when the semiconductor layer 2 grows thick, stress concentrates on this small contact portion. The substrate 1 and the semiconductor layer 2 can be separated from the portion. By applying this, a substrate such as GaN can be manufactured.

【0031】以上、基板1の上に半導体層2を一層だけ
成長する場合について説明したが、転位欠陥をより少な
くするために、同様な工程を2回繰り返すようにしても
よい。即ち、図4に示すように、上記と同様な手法にて
基板1の凹凸面を覆うように第一の半導体層2aの結晶
成長を行った後に、該第一の半導体層2aの表面を凹凸
面とする加工を施し、その上に気相成長により第一半導
体層2aの凸部11aの上方部から専ら結晶成長するよ
う、マスク3aを設けて第二の半導体結晶2bを形成す
ることもできる。この場合、特に基板1の凸部11と上
記第一の半導体層2aに形成する凸部11aの位置と
を、垂直方向にずらす態様にすれば、第二の半導体層2
bには第一の半導体層2aの凸部11a上部にある多く
の転位が伝播しないことになる。つまり、かかる構成と
すれば、第二の半導体層2b全域を低転位領域とするこ
とができ、より高品質の半導体層が得られるものであ
る。
Although the case where only one semiconductor layer 2 is grown on the substrate 1 has been described above, the same process may be repeated twice to reduce dislocation defects. That is, as shown in FIG. 4, after the crystal growth of the first semiconductor layer 2a is performed to cover the uneven surface of the substrate 1 by the same method as described above, the surface of the first semiconductor layer 2a is A second semiconductor crystal 2b can be formed by providing a mask 3a so that the surface is processed and a crystal is exclusively grown on the surface of the first semiconductor layer 2a from above the convex portion 11a by vapor phase growth. . In this case, if the position of the protrusion 11 of the substrate 1 and the position of the protrusion 11a formed on the first semiconductor layer 2a are shifted in the vertical direction, the second semiconductor layer 2
Many dislocations above the protrusions 11a of the first semiconductor layer 2a do not propagate to b. That is, with such a configuration, the entire region of the second semiconductor layer 2b can be a low dislocation region, and a higher quality semiconductor layer can be obtained.

【0032】また、第二の半導体結晶2bの表面をさら
に凹凸面とし、その上に同様に気相成長法により形成さ
れる第3の半導体層を形成するようにしても良い。或い
は、さらに同様の工程を繰り返して、複数の半導体層を
多重的に形成するようにしても良い。このような構成と
すれば、上述したような上下間の凸部の位置調整を意図
的に行わずとも、層を重ねる毎に伝播する転位を漸減さ
せることができる。
Further, the surface of the second semiconductor crystal 2b may be made more uneven, and a third semiconductor layer similarly formed by vapor deposition may be formed thereon. Alternatively, a similar process may be repeated to form a plurality of semiconductor layers in a multiplex manner. With such a configuration, dislocations that propagate each time a layer is stacked can be gradually reduced without intentionally adjusting the position of the upper and lower convex portions as described above.

【0033】凸部の形成は、例えば通常のフォトリソグ
ラフイ技術を使って凸部形状に応じてパターン化し、R
IE技術等を使ってエッチング加工を行うことで作製で
きる。
The projections are formed by patterning according to the shape of the projections using, for example, ordinary photolithography technology.
It can be manufactured by performing an etching process using an IE technique or the like.

【0034】基板上に半導体層の結晶成長を行う方法は
HVPE、MOCVD、MBE法などがよい。厚膜を作
製する場合はHVPE法が好ましいが、薄膜を形成する
場合はMOCVD法が好ましい。
As a method for growing a crystal of a semiconductor layer on a substrate, HVPE, MOCVD, MBE or the like is preferable. When forming a thick film, the HVPE method is preferable, but when forming a thin film, the MOCVD method is preferable.

【0035】基板上に半導体層の結晶成長を行う時の成
長条件(ガス種、成長圧力、成長温度、など)は、本発
明の効果が出る範囲内であれば、目的に応じ使い分けれ
ばよい。
The growth conditions (gas type, growth pressure, growth temperature, etc.) for growing a semiconductor layer on a substrate may be properly selected depending on the purpose as long as the effects of the present invention can be obtained. .

【0036】[0036]

【実施例】[実施例1]c面サファイア基板上にフォトレ
ジストのパターニング(幅:2μm、周期:6μm、ス
トライプ方位:ストライプ延伸方向がサファイア基板の
<11−20>方向)を行い、RIE(Reactive Ion E
tching)装置で2μmの深さまで断面方形型にエッチン
グした。続いて基板全面にSiO膜を0.1μm堆積
し、その後リフトオフ工程によりフォトレジスト及びそ
の上に堆積されたSiO膜を除去した。このようにし
て基板凹部にマスク層を施した。その後、MOVPE装置に
基板を装着し、水素雰囲気下で1100℃まで昇温し、
サーマルエッチングを行った。その後温度を500℃ま
で下げ、3族原料としてトリメチルガリウム(以下TM
G)を、N原料としてアンモニアを流し、GaN低温バ
ッファー層を成長した。つづいて温度を1000℃に昇
温し原料としてTMG・アンモニアを、ドーパントとし
てシランを流しn型GaN層を基板上に成長した。その
時の成長時間は、通常の凹凸の施していない場合のGa
N成長における4μmに相当する時間とした。
[Example 1] Photoresist patterning (width: 2 µm, period: 6 µm, stripe orientation: stripe extending direction is <11-20> direction of sapphire substrate) on c-plane sapphire substrate, and RIE ( Reactive Ion E
Etching was performed in a rectangular cross section to a depth of 2 μm using a tching apparatus. Subsequently, a 0.1 μm SiO 2 film was deposited on the entire surface of the substrate, and then the photoresist and the SiO 2 film deposited thereon were removed by a lift-off process. Thus, the mask layer was applied to the concave portions of the substrate. Then, the substrate was mounted on the MOVPE device, and the temperature was raised to 1100 ° C. in a hydrogen atmosphere.
Thermal etching was performed. Thereafter, the temperature was lowered to 500 ° C., and trimethylgallium (hereinafter referred to as TM) was used as a Group 3 raw material.
G) was fed with ammonia as an N source to grow a GaN low temperature buffer layer. Subsequently, the temperature was raised to 1000 ° C., and TMG / ammonia was flowed as a raw material, and silane was flowed as a dopant to grow an n-type GaN layer on the substrate. The growth time at that time is the same as that of Ga
A time corresponding to 4 μm in N growth was set.

【0037】成長後の断面を観察すると基板凹部マスク
上に若干の成長の痕跡は見られるものの、図2(c)に示
すように凹部に空洞部13を残したまま凹凸部を覆い、平
坦になったGaN膜が得られた。
Observation of the cross section after growth reveals some traces of growth on the substrate concave mask, but as shown in FIG. 2C, the concave and convex portions are covered while leaving the hollow portions 13 in the concave portions, and are flattened. The resulting GaN film was obtained.

【0038】比較のために、通常のc面サファイア基板
上に同じ成長条件で成膜したGaN層と、同じパターン
のSiO2マスクを使ってELO成長したGaN膜を用意し
た。評価は、InGaN(InN混晶比=0.2、10
0nm厚)を続けて成長して現れるピット(転位に対応
している)をカウントして転位密度とした。評価結果を
表1に示す。
For comparison, a GaN layer formed on a normal c-plane sapphire substrate under the same growth conditions and a GaN film grown by ELO using an SiO 2 mask having the same pattern were prepared. The evaluation was performed using InGaN (InN mixed crystal ratio = 0.2, 10
The pits (corresponding to dislocations) appearing as they continue to grow (thickness of 0 nm) were counted and defined as dislocation densities. Table 1 shows the evaluation results.

【0039】[0039]

【表1】 [Table 1]

【0040】実施例のサンプルでは転位密度の低減が従
来ELOと同程度に図れている事が判る。またXRCの
FWHMは170secと一番小さく、総合的にみて高
品質の膜であるといえる。
It can be seen that in the sample of the embodiment, the dislocation density can be reduced to about the same level as in the conventional ELO. Further, the FWHM of XRC is 170 seconds, which is the smallest, and can be said to be a high quality film as a whole.

【0041】[実施例2]実施例1で得られた膜に連続
してn型AlGaNクラッド層、InGaN発光層、p
型AlGaNクラッド層、p型GaNコンタクト層を順
に形成し、発光波長370nmの紫外LEDウエハーを作
製した。その後、電極形成、素子分離を行い、LED素子
とした。ウェハ全体で採取されたLEDチップの出力の平
均値と逆電流特性を評価した。比較対象としては、従来
のELO技術を使って上記構造を作製した紫外LEDチップと
通常のサファイア基板を使って上記構造を作製した紫外
LEDチップである。これらの評価結果を表2に示す。
Example 2 An n-type AlGaN cladding layer, an InGaN light emitting layer, and a p-type layer were continuously formed on the film obtained in Example 1.
An AlGaN cladding layer and a p-type GaN contact layer were sequentially formed to produce an ultraviolet LED wafer having an emission wavelength of 370 nm. Thereafter, electrode formation and element isolation were performed to obtain an LED element. The average value of the output of the LED chips collected over the entire wafer and the reverse current characteristics were evaluated. For comparison, an ultraviolet LED chip with the above structure fabricated using conventional ELO technology and an ultraviolet LED with the above structure fabricated using a normal sapphire substrate
LED chip. Table 2 shows the evaluation results.

【0042】[0042]

【表2】 [Table 2]

【0043】表2に示すように本発明を用い作製したサ
ンプルでは従来例に比べ出力が高く、リーク電流の少な
い高品質のLEDが作製できる事がわかった。
As shown in Table 2, it was found that the sample manufactured using the present invention has a higher output and a higher quality LED with less leak current than the conventional example.

【0044】[実施例3]次にGaNを基板として用い
た例を示す。GaN基板上にフォトレジストのパターニ
ング(幅:2μm、周期:6μm、ストライプ方位:G
aN基板の<1−100>)を行い、RIE(Reactive Ion Et
ching)装置で2μmの深さまで断面方形型にエッチン
グした。続いて基板全面にSiO膜を0.1μm厚さ
に堆積し、その後リフトオフ工程によりフォトレジスト
及びその上に堆積されたSiO膜を除去した。このよ
うに加工したGaN基板をMOVPE装置に装着し、窒素、
水素、アンモニア混合雰囲気下で1000℃まで昇温し
た。その後、原料としてTMG・アンモニアを、ドーパ
ントとしてシランを流しn型GaN層を成長した。その
時の成長時間は通常の凹凸の施していない場合のGaN
成長における4μmに相当する時間とした。
Embodiment 3 Next, an example using GaN as a substrate will be described. Patterning of photoresist on GaN substrate (width: 2 μm, period: 6 μm, stripe orientation: G
aN substrate <1-100>) and RIE (Reactive Ion Et
ching) The device was etched in a square cross section to a depth of 2 μm. Subsequently, a SiO 2 film was deposited to a thickness of 0.1 μm on the entire surface of the substrate, and then the photoresist and the SiO 2 film deposited thereon were removed by a lift-off process. The GaN substrate thus processed is mounted on a MOVPE apparatus, and nitrogen,
The temperature was raised to 1000 ° C. in a mixed atmosphere of hydrogen and ammonia. Thereafter, TMG / ammonia was flowed as a raw material and silane was flowed as a dopant to grow an n-type GaN layer. The growth time at that time is the normal GaN
A time corresponding to 4 μm in growth was set.

【0045】成長後の断面を観察すると基板凹部マスク
上に若干の成長の痕跡、凸部側面への成長が見られるも
のの、図3に示すように空洞部を残したまま凹凸部を覆
い、平坦になったGaN膜が得られた。続いて得られた
膜のピットの評価を行った。基板としてもちいたGaN
のピット密度は2×105cm-3であったが、本実施例
の成長を行うと凸部上部で1×105cm-3、凹部上部
で5×103cm-3にピットが減少している事がわかっ
た。このように既に転位の少ない基板に対しても更なる
転位密度低減効果があることが確認できた。
Observation of the cross-section after growth reveals some traces of growth on the concave mask of the substrate, and growth on the side surfaces of the convex portion. However, as shown in FIG. Was obtained. Subsequently, the pits of the obtained film were evaluated. GaN used as substrate
The pit density was 2 × 10 5 cm −3 , but when the growth of this example was performed, the pits decreased to 1 × 10 5 cm −3 at the upper part of the convex part and to 5 × 10 3 cm −3 at the upper part of the concave part. I knew I was doing it. Thus, it was confirmed that even a substrate having a small number of dislocations has a further effect of reducing the dislocation density.

【0046】[実施例4]実施例1で作製したGaN結
晶を第一結晶とし、その上に第二結晶を成長させた。ま
ずGaN第一結晶にフォトレジストのパターニング
(幅:2μm、周期:6μm、ストライプ方位:GaN
基板の<1−100>)を行い、RIE装置で2μmの深さま
で断面方形型にエッチングした。この時のパターニング
は基板凸部の上に第一結晶の凹部がくるような配置とし
た。続いて基板全面にSiO膜を0.1μm厚さに堆
積し、その後リフトオフ工程によりフォトレジスト及び
その上に堆積されたSiO膜を除去した。このような
加工後、MOVPE装置に基板を装着し、窒素、水素、アン
モニア混合雰囲気下で1000℃まで昇温した。その
後、原料としてTMG・アンモニアを、ドーパントとし
てシランを流しn型GaN層を成長した。その時の成長
時間は通常の凹凸の施していない場合のGaN成長にお
ける4μmに相当する時間とした。
Example 4 The GaN crystal produced in Example 1 was used as a first crystal, on which a second crystal was grown. First, a photoresist is patterned on the first GaN crystal (width: 2 μm, period: 6 μm, stripe orientation: GaN
The substrate was subjected to <1-100>) and etched in a square cross section to a depth of 2 μm by RIE. At this time, the patterning was performed so that the concave portion of the first crystal came on the convex portion of the substrate. Subsequently, a SiO 2 film was deposited to a thickness of 0.1 μm on the entire surface of the substrate, and then the photoresist and the SiO 2 film deposited thereon were removed by a lift-off process. After such processing, the substrate was mounted on a MOVPE apparatus, and the temperature was raised to 1000 ° C. in a mixed atmosphere of nitrogen, hydrogen and ammonia. Thereafter, TMG-ammonia was flowed as a raw material and silane was flowed as a dopant to grow an n-type GaN layer. The growth time at that time was set to a time corresponding to 4 μm in the GaN growth in the case where the normal unevenness was not applied.

【0047】成長後の断面を観察すると基板凹部マスク
上に若干の成長の痕跡、凸部側面への成長が見られるも
のの、図4に示すように空洞部を残したまま凹凸部を覆
い、平坦になったGaN膜が得られた。続いて得られた
膜のピットの評価を行ったところ8×105cm-3にピ
ットが減少している事がわかった。このように本実施例
を繰り返す事により更なる転位密度低減効果があること
が確認できた。
Observation of the cross section after growth reveals some traces of growth on the concave mask of the substrate and growth on the side surfaces of the convex portion. However, as shown in FIG. Was obtained. Subsequently, when the pits of the obtained film were evaluated, it was found that the pits were reduced to 8 × 10 5 cm −3 . As described above, it was confirmed that the effect of reducing the dislocation density was further obtained by repeating this example.

【0048】[0048]

【発明の効果】以上説明した通りの本発明の半導体基材
及びその作製方法によれば、基板に対して凸部を設け、
凹部にその層からは実質的に成長し得ないマスクで覆う
ことで、結晶成長当初から実質的に低転位密度領域を形
成可能なラテラル成長を優先的に行わせることができ
る。従って通常のマスク層を形成するELO成長に起因
する問題点である軸の微小チルティングによるラテラル
成長部の合体部分の新たな欠陥の発生の問題やオートド
ーピングの問題を解消できる。また、基板に上記加工を
施すだけで、一回の成長でバッファ層成長から発光部等
の半導体結晶層の成長を連続して行えるので、製造プロ
セスの簡略化が図れるという利点がある。特に凹部での
成長を抑えることが出きるため、ラテラル成長の効率が
良くなる利点がある。さらに空洞部の利用による反射率
向上や、残留歪の抑制などの効果もあり特性向上、低コ
スト化の面から非常に価値のある発明である。
According to the semiconductor substrate and the method of manufacturing the same according to the present invention as described above, a projection is provided on a substrate,
By covering the recess with a mask that cannot substantially grow from the layer, lateral growth that can form a substantially low dislocation density region can be preferentially performed from the beginning of crystal growth. Therefore, it is possible to solve the problem of the generation of new defects in the united portion of the laterally grown portion due to the minute tilting of the axis, and the problem of autodoping, which are problems caused by the ELO growth for forming the normal mask layer. In addition, by simply performing the above-described processing on the substrate, the growth of the buffer layer and the growth of the semiconductor crystal layer such as the light emitting portion can be continuously performed in a single growth, so that there is an advantage that the manufacturing process can be simplified. In particular, since the growth in the concave portion can be suppressed, there is an advantage that the efficiency of lateral growth is improved. Further, the use of the hollow portion has an effect of improving the reflectance and suppressing residual strain, and is a very valuable invention in terms of improving characteristics and reducing costs.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係わる半導体基材の結晶成長状態を説
明するための断面図である。
FIG. 1 is a cross-sectional view for explaining a crystal growth state of a semiconductor substrate according to the present invention.

【図2】本発明に係わる半導体基材の結晶成長状態を説
明するための断面図である。
FIG. 2 is a cross-sectional view for explaining a crystal growth state of a semiconductor substrate according to the present invention.

【図3】本発明に係わる半導体基材の結晶成長状態を説
明するための断面図である。
FIG. 3 is a cross-sectional view for explaining a crystal growth state of a semiconductor substrate according to the present invention.

【図4】本発明に係わる半導体基材の結晶成長状態を説
明するための断面図である。
FIG. 4 is a cross-sectional view illustrating a crystal growth state of a semiconductor substrate according to the present invention.

【符号の説明】[Explanation of symbols]

1 基板 11 凸部 12 凹部 13 空洞部 2 半導体層 3 マスク DESCRIPTION OF SYMBOLS 1 Substrate 11 Convex part 12 Concavity 13 Cavity part 2 Semiconductor layer 3 Mask

フロントページの続き (72)発明者 湖東 雅弘 兵庫県伊丹市池尻4丁目3番地 三菱電線 工業株式会社伊丹製作所内 Fターム(参考) 4G077 AA03 BE11 DB01 ED04 ED05 EE07 5F045 AA04 AA05 AB14 AB17 AB18 AC01 AC08 AC12 AC15 AC19 AD14 AF02 AF04 AF09 AF12 CA11 DB02 DB04 Continued on the front page (72) Inventor Masahiro Koto 4-3 Ikejiri, Itami-shi, Hyogo Mitsubishi Electric Cable Industry Co., Ltd. Itami Works F-term (reference) 4G077 AA03 BE11 DB01 ED04 ED05 EE07 5F045 AA04 AA05 AB14 AB17 AB18 AC01 AC08 AC12 AC15 AC19 AD14 AF02 AF04 AF09 AF12 CA11 DB02 DB04

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 基板と該基板上に気相成長された半導体
結晶とからなる半導体基材であって、前記基板の結晶成
長面が凹凸面とされ、凹部はその層からは実質的に結晶
成長し得ないマスクで覆われ、前記半導体結晶は該凹凸
面における凸部の上方部から専ら結晶成長されたもので
あることを特徴とする半導体基材。
1. A semiconductor substrate comprising a substrate and a semiconductor crystal grown on the substrate by vapor phase growth, wherein the crystal growth surface of the substrate is an uneven surface, and the concave portion is substantially crystallized from the layer. A semiconductor substrate covered with a mask that cannot grow, wherein the semiconductor crystal is grown exclusively from a portion above the convex portion on the uneven surface.
【請求項2】 上記半導体結晶がInGaAlNである
ことを特徴とする請求項1記載の半導体基材。
2. The semiconductor substrate according to claim 1, wherein said semiconductor crystal is InGaAlN.
【請求項3】 上記基板の結晶成長面の凸部が、平行な
ストライプ形状からなる凸部であることを特徴とする請
求項1記載の半導体基材。
3. The semiconductor substrate according to claim 1, wherein the projection on the crystal growth surface of the substrate is a projection having a parallel stripe shape.
【請求項4】 上記半導体結晶がInGaAlNであっ
て、かつストライプの長手方向が該InGaAlN結晶
の(1−100)面と垂直であることを特徴とする請求
項3記載の半導体基材。
4. The semiconductor substrate according to claim 3, wherein the semiconductor crystal is InGaAlN, and a longitudinal direction of the stripe is perpendicular to a (1-100) plane of the InGaAlN crystal.
【請求項5】 基板と該基板上に気相成長された半導体
結晶とからなる半導体基材であって、前記基板の結晶成
長面が凹凸面とされ、凹部はその層からは実質的に結晶
成長し得ないマスクで覆われ、前記半導体結晶は該凹凸
面における凸部の上方部から専ら結晶成長された半導体
基材において、前記凹凸面が成長された半導体結晶で覆
われており、この半導体結晶層と前記凹凸面における凹
部との間には空洞部が形成されていることを特徴とする
請求項1記載の半導体基材。
5. A semiconductor substrate comprising a substrate and a semiconductor crystal vapor-grown on the substrate, wherein the crystal growth surface of the substrate is an uneven surface, and the concave portion is substantially crystallized from the layer. The semiconductor crystal is covered with a mask that cannot grow, and the semiconductor crystal is covered with the semiconductor crystal on which the uneven surface is grown, in a semiconductor substrate that is exclusively crystal-grown from above the convex portion on the uneven surface. The semiconductor substrate according to claim 1, wherein a cavity is formed between the crystal layer and the concave portion on the uneven surface.
【請求項6】 基板の結晶成長面を凹凸面とし、凹部を
その層からは実質的に結晶成長し得ないマスクで覆い、
気相成長法により前記凹凸面における凸部の上方部から
専ら結晶成長されることで形成された第一の半導体結晶
と、この第一の半導体結晶の表面を凹凸面とし、同様に
凹部をその層からは実質的に結晶成長し得ないマスクで
覆い、その凸部の上方部から専ら結晶成長されることで
形成された第二の半導体結晶とからなることを特徴とす
る半導体基材。
6. A crystal growth surface of a substrate is formed as an uneven surface, and a concave portion is covered with a mask which cannot substantially grow a crystal from the layer,
A first semiconductor crystal formed by exclusively growing a crystal from the upper portion of the convex portion in the concave-convex surface by a vapor phase growth method, and the surface of the first semiconductor crystal is a concave-convex surface, and the concave portion is similarly formed. A semiconductor substrate comprising a second semiconductor crystal formed by covering a layer with a mask that cannot substantially grow crystals, and performing crystal growth exclusively from above the convex portions.
【請求項7】 請求項6の半導体基材における第二の半
導体結晶の表面を凹凸面とし、凹部をその層からは実質
的に結晶成長し得ないマスクで覆い、その上に同様に気
相成長法により形成された第3の半導体層乃至は同様の
工程を繰り返すことで多重的に形成された複数の半導体
層を有することを特徴とする半導体基材。
7. The semiconductor substrate according to claim 6, wherein the surface of the second semiconductor crystal is an uneven surface, and the concave portion is covered with a mask that cannot substantially grow crystals from the layer. A semiconductor substrate having a third semiconductor layer formed by a growth method or a plurality of semiconductor layers formed in a multiplex manner by repeating similar steps.
【請求項8】 基板上に半導体結晶を気相成長させるに
あたり、予め基板表面に凹凸面加工を施し、該凹凸面に
おける凹部をその層からは実質的に結晶成長し得ないマ
スクで覆い、次いで該基板に対して原料ガスを供給し、
前記凹凸面における凸部の上方部から専ら結晶成長され
る半導体結晶にて前記基板の凹凸面を覆うことを特徴と
する半導体基材の作製方法。
8. In growing a semiconductor crystal in a vapor phase on a substrate, the surface of the substrate is subjected to an uneven surface processing in advance, and the concave portion in the uneven surface is covered with a mask that cannot substantially grow crystals from the layer. Supplying a source gas to the substrate;
A method of manufacturing a semiconductor base material, comprising: covering an uneven surface of the substrate with a semiconductor crystal exclusively grown from an upper portion of the convex portion on the uneven surface.
JP33642199A 1999-03-17 1999-11-26 Semiconductor substrate and manufacturing method thereof Expired - Fee Related JP3471687B2 (en)

Priority Applications (11)

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JP33642199A JP3471687B2 (en) 1999-11-26 1999-11-26 Semiconductor substrate and manufacturing method thereof
DE60030279T DE60030279T2 (en) 1999-03-17 2000-03-15 SEMICONDUCTOR BASIS, ITS MANUFACTURING METHOD AND SEMICONDUCTOR CRYSTAL MANUFACTURING METHOD
PCT/JP2000/001588 WO2000055893A1 (en) 1999-03-17 2000-03-15 Semiconductor base and its manufacturing method, and semiconductor crystal manufacturing method
EP00909660A EP1184897B8 (en) 1999-03-17 2000-03-15 Semiconductor base and its manufacturing method, and semiconductor crystal manufacturing method
KR1020017011785A KR100677683B1 (en) 1999-03-17 2000-03-15 Semiconductor base and its manufacturing method, and semiconductor crystal manufacturing method
DE60043122T DE60043122D1 (en) 1999-03-17 2000-03-15 Semiconductor base their production and Halbleiterkristallhersetllungsmethode
US09/936,683 US6940098B1 (en) 1999-03-17 2000-03-15 Semiconductor base and its manufacturing method, and semiconductor crystal manufacturing method
EP04022766A EP1501118B1 (en) 1999-03-17 2000-03-15 Semiconductor base and its manufacturing method, and semiconductor crystal manufacturing method
US10/842,777 US7115486B2 (en) 1999-03-17 2004-05-11 Semiconductor base and its manufacturing method, and semiconductor crystal manufacturing method
US11/529,905 US7504324B2 (en) 1999-03-17 2006-09-29 Semiconductor base and its manufacturing method, and semiconductor crystal manufacturing method
US11/541,201 US7589001B2 (en) 1999-03-17 2006-09-29 Semiconductor base and its manufacturing method, and semiconductor crystal manufacturing method

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004064080A (en) * 2002-07-30 2004-02-26 Lumileds Lighting Us Llc Group iii nitride light emitting device having p type active layer
JP2009302389A (en) * 2008-06-16 2009-12-24 Toyoda Gosei Co Ltd Group-iii nitride-based compound semiconductor light-emitting element, and method of manufacturing the same
JP2012031027A (en) * 2010-08-02 2012-02-16 Tokyo Univ Of Agriculture & Technology Method for producing single crystal aluminum nitride

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004064080A (en) * 2002-07-30 2004-02-26 Lumileds Lighting Us Llc Group iii nitride light emitting device having p type active layer
JP2009302389A (en) * 2008-06-16 2009-12-24 Toyoda Gosei Co Ltd Group-iii nitride-based compound semiconductor light-emitting element, and method of manufacturing the same
JP2012031027A (en) * 2010-08-02 2012-02-16 Tokyo Univ Of Agriculture & Technology Method for producing single crystal aluminum nitride

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