JP2004006931A - Semiconductor substrate and its manufacturing method - Google Patents

Semiconductor substrate and its manufacturing method Download PDF

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Publication number
JP2004006931A
JP2004006931A JP2003193119A JP2003193119A JP2004006931A JP 2004006931 A JP2004006931 A JP 2004006931A JP 2003193119 A JP2003193119 A JP 2003193119A JP 2003193119 A JP2003193119 A JP 2003193119A JP 2004006931 A JP2004006931 A JP 2004006931A
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substrate
crystal
semiconductor
growth
width
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JP2004006931A5 (en
Inventor
Hiroaki Okagawa
岡川 広明
Kazuyuki Tadatomo
只友 一行
Yoichiro Ouchi
大内 洋一郎
Masahiro Koto
湖東 雅弘
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Mitsubishi Cable Industries Ltd
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Mitsubishi Cable Industries Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method by which various problems caused by a mask layer used can be avoided, the manufacturing process of a semiconductor substrate can be simplified, and the conventional problem about the difficulty of the selective growth of AlGaN can be solved and, at the same time, the occurrence of warping and cracking can be suppressed when an Si substrate etc., is used. <P>SOLUTION: In the figure, 1 and 2 respectively represent a substrate and a semiconductor crystal grown by the vapor growth method. Protrusions 11 and recesses 12 are formed on the crystal growth surface of the substrate 1 so that crystal growth may be made only from the upside of the protrusions 11. The widths (a) of the projecting sections 11 are controlled to a submicron order of 0<a<1 μm and the ratio of the area occupied by the protrusions 11 to the whole surface of the substrate 1 is adjusted to ≤50 %. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明が属する技術分野】
本発明は、半導体基材及びその作製方法に関し、特に転位欠陥が生じ易い半導体材料を用いる場合に有用な構造及び方法に関するものである。
【0002】
【従来の技術】
GaN系材料を結晶成長する場合、GaN系材料は格子整合する基板がないためにサファイア、SiC、スピネル、最近ではSiなどの格子整合しない基板を用いている。しかしながら、格子整合しないことに起因し作製したGaNの膜中には1010個/cmもの転位が存在している。近年高輝度の発光ダイオード、半導体レーザーなどが実現されているが、特性向上を図るためには転位密度の低減が望まれている。
【0003】
【発明が解決しようとする課題】
この転位密度低減を図る方法としては、例えばGaN系半導体結晶等を、バッファ層及びGaN基板上に気相成長するにあたり、前記基板上に部分的なマスクを設けて選択成長する事でラテラル方向の結晶成長を行わせ、転位密度を低減した高品質な結晶を得る方法が提案されている(例えば特開平10−312971号公報)。
【0004】
しかしながら上記の方法によれば、マスク層上にラテラル方向成長された部分において、ラテラル成長方向にc軸が微小量ながら傾斜するといった問題が生じ、これにより結晶品質が低下するという新たな問題が有ることが判明した(MRS1998  Fall、Meeting予稿集G3・1)。これは、X線ロッキングカーブ測定(XRC)の入射方位依存性を測定(¢スキャン)することでも確認できる。即ち、ラテラル成長方向からの入射X線によるX線ロッキングカーブの半値全幅(FWHM)は、マスク層のストライプ方向からのX線によるFWHM値より大きくなっており、C軸の微小傾斜(チルティング)に方位依存性がある事を示している。この事は、マスク上のラテラル成長の合体部分に新たな欠陥を多数誘起する可能性を示唆している。
【0005】
また、マスク層材料として汎用されているものはSiOなのであるが、その上に結晶成長層が積重されるとSi成分がこの結晶成長層中に移行するという、いわゆるオートドーピング汚染の問題があることも判明した。
さらに、Alを含む半導体材料、例えばAlGaNをSiOマスク層付き基板上に成長させた場合、マスク層上にも結晶成長し、選択成長自体が効果的に行えないという問題もあった。
【0006】
このような問題を解消する試みとして、SiCのベース基板上にバッファ層及びGaN層を設けた基板に対して、SiC層にまで至るストライプ溝加工を施して凸部を形成し、この凸部の上方部に位置することになるGaN層から結晶成長させる方法が提案されている(MRS 1998  Fall  Meeting予稿集G3.38)。この方法によればSiOマスク層無しで選択成長させる事も出来、上述のSiOマスクを用いることに起因する各種の問題を解消することが可能となる。
【0007】
上記方法は、ベース基板としてサファイア基板を使用する事ができその方法も開示されている(例えば、特開平11−191659号公報)。しかしながら上記方法では、サファイアベース基板上にバッファ層材料ならびにGaN系材料を結晶成長させ、一旦成長炉から取り出し溝加工を施し、その後再び結晶成長を行うというステップが必要となることから、製造プロセスが複雑化するという新たな不都合が発生し、作業工程が多くなりコストがかかるなどの問題を有していた。
【0008】
またSi基板上にGaN系材料を結晶成長する試みもなされているが、GaN系結晶を成長すると熱膨張係数差に起因した反りやクラックが発生し良質の結晶成長を行えない問題があった。
【0009】
さらに、上述したラテラル方向成長技術を用いる場合、基板からの貫通転位を可及的に低減するには非マスク部を細く形成することが効果的なのであるが、前記の反りに起因してフォトリソグラフィが正確に行えない問題があり細いパターンを基板全面に形成する事が困難であった。
【0010】
従って本発明は上記問題に鑑み、マスク層を用いる事に起因する種々の問題を回避し、かつ製造工程の簡略化を図ることを目的としている。また従来困難であったAlGaNの選択成長ができない問題を解決する事を目的としている。さらにSi基板等を用いた場合の反りやクラックの発生を押さえることを目的としている。
【0011】
【課題を解決するための手段】
本発明の半導体基材は、基板と該基板上に気相成長された半導体結晶とからなる半導体基材であって、前記基板の結晶成長面が凹凸面とされ、前記半導体結晶は該凹凸面における凸部の上方部から専ら結晶成長された半導体基材において、前記凸部は、その幅aが0<a<1μmの範囲とされ、且つ、上記基板表面に対して該凸部の占有する面積の割合が50%以下とされていることを特徴とするものである。
【0012】
上記した如き半導体基材において、基板表面に対して凸部の占有する面積の割合が、2〜30%とすることは、転位欠陥を可及的に少なくする観点からは好ましいものである。
【0013】
本発明の他の半導体基材は、基板と該基板上に気相成長された半導体結晶とからなる半導体基材であって、前記基板の結晶成長面が凹凸面とされ、前記半導体結晶は該凹凸面における凸部の上方部から専ら結晶成長された半導体基材において、前記凸部は、その幅aが0<a<1μmの範囲とされ、且つ、上記基板表面に対して該凸部の占有する面積の割合が50〜70%とされていることを特徴とするものである。
【0014】
また本発明のさらに他の半導体基材は、基板と該基板上に気相成長された半導体結晶とからなる半導体基材であって、前記基板の結晶成長面が凹凸面とされ、前記半導体結晶は該凹凸面における凸部の上方部から専ら結晶成長された半導体基材において、前記凸部の幅aが0<a<1μmの範囲とされ、且つ、該凸部の幅aが前記凹部の幅bと同等以下とされている部分を有することを特徴とするものである。
【0015】
【作用】
本発明は、バッファ層等すら形成していない状態の基板に対して凹凸面を設けることで、結晶成長当初から実質的に低転位領域を形成可能なラテラル成長を起こす素地面を予め提供しておく点に特徴を有する。即ち、気相成長させた場合、成長初期には基板表面全体で結晶成長が起こり得るが、やがて凸部の上方部での成長が優位となり、この結果凹部に原材料が拡散しにくくなり、ひいては凸部の上方部から専ら成長された層にて上記の凹凸面が覆われるというものである。この凸部の成長ではC軸と垂直方向のいわゆるラテラル成長が起き、実質的に低転位領域の形成がマスク層レス(従来のようにマスク層を用いることなしに)で達成されることになる。しかもこの成長は、基板直上に位置する層(例えばバッファ層)の結晶成長から行い得るので、その後の成長工程を連続して行うことができるというメリットがある。
【0016】
加えて、請求項1記載の発明にあっては、前記凸部の幅aを0<a<1μmというサブミクロンオーダーの範囲とし、且つ、上記基板表面に対して該凸部の占有する面積を50%以下としたので、凸部の上方部から専ら成長された層にて上記の凹凸面が覆うまでに必要とする結晶厚みが薄くて済むことになる。その結果、結晶が保有する熱膨張応力が低減されて反りの発生を抑えることができる。
【0017】
また、請求項2記載の発明では、上記構成において基板表面に対して凸部の占有する面積の割合を、特に2〜30%とすることで、上記作用に加えて転位欠陥の承継も最小限に抑制することができる。つまり、転位線が延伸する可能性のある凸部面積割合を、ラテラル成長が達成し得る必要最小限の程度としたので、その上に成長される結晶に含まれてしまう転位欠陥を極小値に近づけることができるのである。
【0018】
請求項3記載の発明は、発明の観点を変えて、結晶厚みを極小にすることを専ら意図して、凸部の幅aを0<a<1μmの範囲とし、且つ、上記基板表面に対して該凸部の占有する面積割合を50〜70%としたものである。即ち、凸部の占有面積割合を大きくすることは、凸部の密集度を増加させることに帰着し、そのような凸部が存在する基板に対して上記のラテラル成長を生起せしめると、成長開始から短時間で凸部の上方部から専ら成長された層にて凹凸面が覆われ、結果としてより薄くて、而してより反り問題が改善された結晶層が得られるのである。
【0019】
請求項4に係る発明は、転位欠陥の極小化を目指した具体的アプローチの発明であって、例えば凸部を平行なストライプ状に設ける場合等において、凸部の幅aが0<a<1μmの範囲とされ、且つ、該凸部の幅aが前記凹部の幅bと同等以下とされている部分を有するよう凸部を形成するので、転位線の遮断効のある凹部が支配的なストライプ形状となり、転位欠陥の承継性が低く抑ええられて結果的に転位欠陥が抑制されることになる。
【0020】
【発明の実施の態様】
以下図面に基いて、本発明の実施態様につき詳細に説明する。
図1(a)乃至(c)は本発明に係る半導体基材の結晶成長状態を説明するための断面図である。図において、1は基板であり、2は該基板1上に気相成長された半導体結晶をそれぞれ示している。基板1の結晶成長面には凸部11及び凹部12が形成されており、前記凸部11の上方部から専ら結晶成長が行われるよう構成されている。
【0021】
本発明でいう基板とは、各種の半導体結晶層を成長させるためのベースとなる基板であって、格子整合のためのバッファ層等も未だ形成されていない状態のものを言う。このような基板としては、サファイア(C面、A面、R面)、SiC(6H、4H、3C)、GaN、Si、スピネル、ZnO,GaAs,NGOなどを用いることができるが、発明の目的に対応するならばこのほかの材料を用いてもよい。またこれら基板からoffしたものを用いてもよい。
【0022】
基板1上に成長される半導体結晶としては種々の半導体材料を用いることができ、AlXGa1−X−YInYN(0≦x≦1,0≦y≦1)ではx、yの組成比を変化させたGaN、Al0.5Ga0.05N、In0.5Ga0.05Nなどが例示できる。
【0023】
中でも、AlGaN等のAlを含有する半導体材料の場合、従来のマスク方式ではSiOマスク層上に成長するという問題があったが、本発明によるとマスクレス化によりかかる問題が解消されるため、従来できなかったAlGaNのラテラル成長が可能となり低転位で高品質な膜の成長が基板直上から可能となる。このため紫外線発光素子等で問題となるGaN層による光吸収がなくなり応用上特に好適である。
【0024】
基板1の結晶成長面に形成される凸部11は、その上方部から専ら結晶成長が行われるような形状とすると有効である。「上方部から専ら結晶成長が行われる」とは、凸部11の頂点ないし頂面及びその近傍での結晶成長が優勢に行い得る状態をいい、成長初期には凹部での成長が生じてもよいが最終的には凸部11の結晶成長が優勢となることを指す。つまり上方部を起点としたラテラル成長により低転位領域が形成されれば、従来のマスクを要するELOと同様の効果がある。これが本発明ではマスクレスで成長可能である事が特徴である。以下、この点についての説明を、図1に基づいて行う。
【0025】
図1は凸部11をストライプ状に形成したものの横断面図である。
本発明にあっては、この凸部11の幅aが、0<a<1μmとされる。このように、サブミクロンオーダーに凸部11の幅aを抑制するのは、前述の通り、基板の凹凸面を覆うに要する結晶の厚さを薄肉化するため、並びに、凸部の基板表面に占める面積割合と相俟って、転位欠陥を減少させることにある。この観点より、凸部11の幅aを1μm以上とした場合は、薄肉化の目的が十分達成できないことから好ましくない。従って、幅aは可及的に細い方が望ましいが、凹凸加工の作業性を考慮すると細すぎる幅は逆に好ましくなく、0.1<a<0.7μm程度の範囲で選定することが望ましい。なお、本発明でいう「凸部の幅」とは一般的には凸部頂面の幅を指すが、凸部の頂面幅と立ち上がり基底部の幅が相違する場合等においては、基底部の幅を指す場合も有る。また、溝深さ(凸部高さh)は本発明の効果が出る範囲内で適宜選べば良い。
【0026】
凸部11が基板表面に占める面積の割合は、目的に応じて設定することができる。先ず、半導体結晶2の厚さを薄くし、しかも低転位化を図るという本発明の一般的観点からは、凸部が占める面積割合は50%以下とされる。サファイア基板からの転位がまっすぐ伸びる成長モードの場合、凸部の占める面積割合が少ないほど転位の承継数が減るからである。
【0027】
従って凸部が占める面積割合は少ない方が好ましく、40%以下、更には30%以下とすることが望ましい。特に30%以下とした場合は、転位の承継を極小化するという目的を達成し得る。但し、極端に凸部が占める面積割合を少なくするとラテラル成長自体が発生し難くなる、乃至は成長に相当の時間を要してしまうことから、2%以上は凸部面積を確保しておくことが望ましい。ゆえに、転位の承継を極小化するという観点からは、凸部が占める面積割合は2〜30%、望ましくは4〜20%とすることが好ましい。
【0028】
一方、半導体結晶2の厚さを極小化するという観点からは、凸部が占める面積割合は50〜70%の範囲で選択される。このように凸部の密集度を上げることで、各凸部上方部から始まった結晶成長が互いに合体する時間を早めることができ、結果として半導体結晶2の厚さの極小化が目指せるからである。なお、面積割合が70%を超えるよう設定すると、転位の遮断効が大きく減少するため望ましくない。
【0029】
後述するが、凸部11の望ましい形態として、ストライプ状の凸部がある。このような凸部の場合は、凸部11の幅aと、凹部12の幅bとの関係において凸部の態様を定義できる。即ち、凸部11の幅aが、0<a<1μmであることを前提とした上で、該凸部の幅aを前記凹部の幅bと同等以下とすることによっても、転位欠陥の極小化を目指すことができる。この場合、幅aと幅bとの関係は、基板表面全面において厳格に満たされていることは必ずしも必要でなく、基板表面の主要部分が少なくともそのように構成されていれば良い。
【0030】
以下、ストライプ状の凸部の場合について、実施例を説明する。
図1(a)に示したものは、凸部の幅が0.5μm、基板表面に占める面積割合が50%程度で、凸部高さhも同程度とした場合を表している。この場合原料ガスは凹部12及びその近傍にまで到達し得るため凹部12での成長も生じる。また、凸部11の上方部からも結晶成長が生じ、図1(b)に示すように、凸部11の上方部と凹部12表面に、それぞれ結晶単位20、21が生成される状態となる。このような状況下、結晶成長が続くと凸部11の上方部を起点とし横方向に成長した膜がつながって、やがて図1(c)のように基板1の凹凸面を覆うことになる。この場合、凹部12上部には低転位領域が形成され、作製した膜の高品質化が図れている。なおこの時の凹部が覆われ平坦になるまでに要する厚みは0.5μmであった。
【0031】
本発明にあっては、このような凸部11であれば特に制限はなく各種の形状を採用することができる。
具体的には、上述したような溝幅Bに対し溝深さ(凸部高さ)hが深い場合、溝幅Bに対し溝深さ(凸部高さ)hが浅い場合、さらに溝幅Bに対し溝深さ(凸部高さ)hが非常に浅い場合、もしくは凸部11の幅Aに対し溝幅Bが非常に広い場合など種々の組み合わせを行う事ができる。特に溝幅Bに対し溝深さ(凸部高さ)hが深い場合、気相成長時に原料ガスが実質的に底部まで拡散できないため原料が効率良く凸部11上部の成長に寄与する点で好ましい。また凸部11の幅Aに対し溝幅Bが広い場合、横方向成長の領域が多くなり低転位領域が広く形成される点で好ましい。
【0032】
このような凹凸面の形成の態様としては、島状の点在型の凸部、ストライプ型の凸条からなる凸部、格子状の凸部、これらを形成する線が曲線である凸部などが例示できる。
これら凸部の態様の中でも、ストライプ型の凸条を設ける態様のものは、その作製工程を簡略化できると共に、規則的なパターンが作製容易である点で好ましい。ストライプの長手方向は任意であってよいが、基板上に成長させる材料をGaNとし、GaN系材料の<1−100>方向にした場合{1−101}面などの斜めファセットが形成され難いため横方向成長(ラテラル成長)が早くなる。この結果凹凸面を覆うのが速くなる点で特に好ましい。
【0033】
図1に示す実施例のように、空洞部13を残したまま基板1の凹凸面を埋め込み、続いてその上に発光部を成長して発光素子を作製した場合、空洞部と半導体界面の屈折率差が大きく取れる。この結果発光部下方に向かった光がこの界面で反射される割合が増える。例えばLEDを、サファイア基板面を下側にしてダイボンドを行った場合は、上方に取り出せる光量が増えるため好ましい。
【0034】
また空洞部13を残したまま埋め込む事は、基板1とその上に成長する半導体層との接触面積を小さくできるという事であるため、半導体中に格子定数差や熱膨張係数差に起因する歪を低減できる面で好ましい。この歪の低減は、サファイア上にGaN系材料を厚く成長した時に発生する反りを低減させる効果がある。特に従来法ではSi基板上にGaN系材料を結晶成長する際に熱膨張係数差に起因した反りやクラックが発生し良質の結晶成長を行えない問題があったが、本発明による歪低減によりこの問題を解消できる。
【0035】
さらに基板1とその上に成長する半導体層2との接触面積を小さくできる事を利用すると、半導体層2を厚く成長していった場合、この小さい接触部に応力が集中し、この部分から基板1と半導体層2の分離が可能となる。これを応用する事でGaNなどの基板が作製可能となる。
【0036】
以上、基板1の上に半導体層2を一層だけ成長する場合について説明したが、転位欠陥をより少なくするために、同様な工程を2回繰り返すようにしてもよい。即ち図2に示すように、上記と同様な手法にて基板1の凹凸面を覆うように第一の半導体層2aの結晶成長を行った後に、該第一の半導体層2aの表面を凹凸面とする加工を施し、その上に気相成長により第一半導体層2aの凸部の上方部から専ら結晶成長するようにして第二の半導体結晶2bを形成することもできる。この場合、特に基板1の凸部11と上記第一の半導体層2aに形成する凸部11aの位置とを、垂直方向にずらす態様にすれば、第二の半導体層2bには第一の半導体層2aの凸部11a上部にある多くの転位が伝播しないことになる。つまり、かかる構成とすれば、第二の半導体層2b全域を低転位領域とすることができ、より高品質の半導体層が得られるものである。
【0037】
また、第二の半導体結晶2bの表面をさらに凹凸面とし、その上に同様に気相成長法により形成される第3の半導体層を形成するようにしても良い。或いは、さらに同様の工程を繰り返して、複数の半導体層を多重的に形成するようにしても良い。このような構成とすれば、上述したような上下間の凸部の位置調整を意図的に行わずとも、層を重ねる毎に伝播する転位を漸減させることができる。
【0038】
凸部の形成は、例えば通常のフォトリソグラフイ技術を使って凸部形状に応じてパターン化し、RIE技術等を使ってエッチング加工を行うことで作製できる。
【0039】
基板上に半導体層の結晶成長を行う方法はHVPE、MOCVD、MBE法などがよい。厚膜を作製する場合はHVPE法が好ましいが、薄膜を形成する場合はMOCVD法が好ましい。
【0040】
基板上に半導体層の結晶成長を行う時の成長条件(ガス種、成長圧力、成長温度、など)は、本発明の効果が出る範囲内であれば、目的に応じ使い分ければよい。
【0041】
【実施例】
[実施例1]
c面サファイア基板上にフォトレジストのパターニング(幅:0.3μm、周期:4μm、ストライプ方位:ストライプ延伸方向がサファイア基板の<11−20>方向)を行い、RIE(Reactive Ion Etching)装置で3μmの深さまで断面方形型にエッチングした。フォトレジストを除去後、MOVPE装置に基板を装着した。その後、水素雰囲気下で1100℃まで昇温し、サーマルエッチングを行った。その後温度を500℃まで下げ、3族原料としてトリメチルガリウム(以下TMG)を、N原料としてアンモニアを流し、GaN低温バッファー層を成長した。つづいて温度を1000℃に昇温し原料としてTMG・アンモニアを、ドーパントとしてシランを流しn型GaN層を成長した。その時の成長時間は、通常の凹凸の施していない場合のGaN成長における4μmに相当する時間とした。
【0042】
成長後の断面を観察すると基板凹部に成長は生じているが、図1(c)に示すように凹部に空洞部13を残したまま凹凸部を覆い、平坦になったGaN膜が得られた。
この膜の上にInGaN(InN混晶比=0.2、100nm厚)を続けて成長して現れるピット(転位に対応している)をカウントして転位密度の評価を行ったところ2×10cm−3と転位密度が通常報告例に比べ低減していた。
【0043】
比較のために、通常のc面サファイア基板上に同じ成長条件でGaN層、更にInGaN層を成膜し評価を行なった。結果は2×10cm−3と通常報告例と同程度であり実施例−1に比べ非常に多い数であった。
【0044】
通常のELO法により実施例−1との比較を行なう事を試みた。まずサファイア基板上にバッファー層を介しGaN層を1.5μm形成した。その後SiO膜をリフトオフにより形成するためのレジストを塗布し、露光を試みた。ところがウエハーの中心部は0.5μmのストライプが形成されるものの、ウエハー周辺部ではパターンが形成されなかった。これはウエハーの反りに起因しマスクとウエハーの距離が面内で変動しているためであることがわかった。このため0.3μmのパターン形成は断念した。
【0045】
[実施例2]
実施例1で得られた膜に連続してn型AlGaNクラッド層、InGaN発光層、p型AlGaNクラッド層、p型GaNコンタクト層を順に形成し、発光波長370nmの紫外LEDウエハーを作製した。
その後、電極形成、素子分離を行い、LED素子とした。ウェハ全体で採取されたLEDチップの出力の平均値と逆電流特性を評価した。比較対象としては、通常のサファイア基板を使って上記構造を作製した紫外LEDチップである。これらの評価結果を表1に示す。
【0046】
【表1】

Figure 2004006931
【0047】
表2に示すように本発明を用い作製したサンプルでは従来例に比べ出力が高く、リーク電流の少ない高品質のLEDが作製できる事がわかった。
【0048】
[実施例3]
実施例1で作製したGaN結晶を第一結晶とし、その上に第二結晶を成長させた。まずGaN第一結晶にフォトレジストのパターニング(幅:2μm、周期:4μm、ストライプ方位:GaN基板の<1−100>)を行い、RIE装置で2μmの深さまで断面方形型にエッチングした。この時のパターニングは基板凸部の上に第一結晶の凹部がくるような配置とした。この時のアスペクト比は1であった。フォトレジストを除去後、MOVPE装置に基板を装着した。その後、窒素、水素、アンモニア混合雰囲気下で1000℃まで昇温した。その後、原料としてTMG・アンモニアを、ドーパントとしてシランを流しn型GaN層を成長した。その時の成長時間は、通常の凹凸の施していない場合のGaN成長における4μmに相当する時間とした。
【0049】
成長後の断面を観察すると基板凹部への成長、凸部側面への成長が見られるものの、図2に示すように空洞部を残したまま凹凸部を覆い、平坦になったGaN膜が得られた。続いて得られた膜のピットの評価を行ったところ2×10cm−3にピットが減少している事がわかった。このように本実施例を繰り返す事により更なる転位密度低減効果があることが確認できた。
【0050】
【発明の効果】
以上説明した通りの本発明の半導体基材及びその作製方法によれば、基板に対して凸部を設けておくことで、マスク層を使用することなく低転位領域を形成可能なラテラル成長を行わせることができる。従ってマスク層を形成することに起因する問題点である軸の微小チルティングによるラテラル成長部の合体部分の新たな欠陥の発生の問題やオートドーピングの問題、Al含有半導体材料が選択成長不可という問題を解消できる。また、基板に凹凸面を設けた後に、一回の成長でバッファ層成長から発光部等の半導体結晶層の成長を連続して行えるので、製造プロセスの簡略化が図れるという利点がある。また貫通転位のもととなる凸部の幅、面積を規定することで低転位密度領域を相対的に広くしたり、凹凸を覆い平坦化するのに用する厚みを薄くできる利点がある。
さらに空洞部の利用による反射率向上や、残留歪の現象などの効果もあり特性向上、低コスト化の面から非常に価値のある発明である。
【図面の簡単な説明】
【図1】本発明に係わる半導体基材の結晶成長状態を説明するための断面図である。
【図2】本発明に係わる半導体基材の結晶成長状態を説明するための断面図である。
【符号の説明】
1   基板
11  凸部
12  凹部
13 空洞部
2  半導体層[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor substrate and a method for manufacturing the same, and more particularly to a structure and a method useful when a semiconductor material in which dislocation defects easily occur is used.
[0002]
[Prior art]
When a GaN-based material is crystal-grown, a GaN-based material uses a substrate that does not have a lattice match, such as sapphire, SiC, spinel, or recently, Si because there is no substrate that has a lattice match. However, during the GaN film produced due to the fact that no lattice matching are present 10 10 / cm 2 things dislocation. In recent years, high-luminance light-emitting diodes, semiconductor lasers, and the like have been realized, but a reduction in dislocation density has been desired in order to improve characteristics.
[0003]
[Problems to be solved by the invention]
As a method of reducing the dislocation density, for example, when a GaN-based semiconductor crystal or the like is vapor-phase grown on a buffer layer and a GaN substrate, a partial mask is provided on the substrate and selectively grown by providing a selective mask. A method has been proposed in which crystal growth is performed to obtain a high-quality crystal with a reduced dislocation density (for example, Japanese Patent Application Laid-Open No. 10-312971).
[0004]
However, according to the above-mentioned method, there is a problem that the c-axis is tilted in the lateral growth direction with a small amount in the laterally grown portion on the mask layer, which causes a new problem that the crystal quality is reduced. (MRS1998 Fall, Meeting G3.1). This can also be confirmed by measuring the incident azimuth dependency of X-ray rocking curve measurement (XRC) (¢ scan). That is, the full width at half maximum (FWHM) of the X-ray rocking curve due to the incident X-rays from the lateral growth direction is larger than the FWHM value due to the X-rays from the stripe direction of the mask layer, and the C axis is slightly tilted (tilted). Indicates that there is orientation dependency. This suggests that a large number of new defects may be induced in the merged portion of the lateral growth on the mask.
[0005]
Although SiO 2 is commonly used as a mask layer material, there is a problem of so-called auto-doping contamination in which, when a crystal growth layer is stacked thereon, the Si component moves into the crystal growth layer. It turned out that there was.
Furthermore, when a semiconductor material containing Al, for example, AlGaN is grown on a substrate with a SiO 2 mask layer, there is also a problem that crystals grow on the mask layer, and the selective growth itself cannot be performed effectively.
[0006]
As an attempt to solve such a problem, a substrate in which a buffer layer and a GaN layer are provided on a base substrate of SiC is subjected to stripe groove processing up to the SiC layer to form a convex portion. There has been proposed a method of growing a crystal from a GaN layer that is to be positioned above (MRS 1998 Fall Meeting Preliminary G3.38). According to this method, selective growth can be performed without using a SiO 2 mask layer, and various problems caused by using the above-described SiO 2 mask can be solved.
[0007]
In the above method, a sapphire substrate can be used as a base substrate, and a method thereof is also disclosed (for example, JP-A-11-191659). However, the above-described method requires a step of growing a buffer layer material and a GaN-based material on a sapphire base substrate, crystallizing the buffer layer once, removing the groove from the growth furnace, and then performing crystal growth again. There has been a problem that a new inconvenience of complication occurs, the number of working steps increases, and the cost increases.
[0008]
Attempts have also been made to grow a GaN-based material on a Si substrate. However, when a GaN-based crystal is grown, there is a problem in that warpage and cracks occur due to a difference in thermal expansion coefficient, and high-quality crystal cannot be grown.
[0009]
Further, in the case of using the above-described lateral growth technique, it is effective to form the non-mask portion thin in order to reduce threading dislocations from the substrate as much as possible. However, it was difficult to form a fine pattern over the entire surface of the substrate.
[0010]
Therefore, in view of the above problems, it is an object of the present invention to avoid various problems caused by using a mask layer and to simplify a manufacturing process. Another object of the present invention is to solve the problem that selective growth of AlGaN cannot be performed, which has been difficult in the past. It is another object of the present invention to suppress the occurrence of warpage and cracks when using a Si substrate or the like.
[0011]
[Means for Solving the Problems]
The semiconductor substrate of the present invention is a semiconductor substrate comprising a substrate and a semiconductor crystal grown on the substrate by vapor phase, wherein the crystal growth surface of the substrate has an uneven surface, and the semiconductor crystal has the uneven surface. In the semiconductor base material which is exclusively crystal-grown from above the convex portion, the convex portion has a width a in a range of 0 <a <1 μm and occupies the convex portion with respect to the substrate surface. It is characterized in that the area ratio is 50% or less.
[0012]
In the semiconductor substrate as described above, it is preferable that the ratio of the area occupied by the projections to the substrate surface is 2 to 30% from the viewpoint of minimizing dislocation defects.
[0013]
Another semiconductor substrate of the present invention is a semiconductor substrate comprising a substrate and a semiconductor crystal vapor-grown on the substrate, wherein the crystal growth surface of the substrate is an uneven surface, and the semiconductor crystal is In the semiconductor base material which is exclusively crystal-grown from above the convex portion on the concave-convex surface, the convex portion has a width a in a range of 0 <a <1 μm, and the convex portion has a width a in the range of 0 <a <1 μm. The ratio of the occupied area is set to 50 to 70%.
[0014]
Still another semiconductor substrate of the present invention is a semiconductor substrate comprising a substrate and a semiconductor crystal vapor-grown on the substrate, wherein the crystal growth surface of the substrate has an uneven surface, In a semiconductor base material which is exclusively crystal-grown from above the convex portion on the concave-convex surface, the convex portion has a width a in a range of 0 <a <1 μm, and the convex portion has a width a of the concave portion. It has a portion that is equal to or less than the width b.
[0015]
[Action]
The present invention provides a substrate in which lateral growth capable of forming a substantially low dislocation region from the beginning of crystal growth is provided in advance by providing an uneven surface on a substrate in which even a buffer layer or the like is not formed. It is characterized by the fact that That is, in the case of vapor-phase growth, crystal growth can occur on the entire substrate surface in the initial stage of growth, but growth in the upper part of the convex part becomes dominant, and as a result, the raw material hardly diffuses into the concave part, and as a result, the convex part becomes convex. The uneven surface is covered with a layer exclusively grown from the upper part of the part. In the growth of the projections, so-called lateral growth in the direction perpendicular to the C axis occurs, and the formation of a low dislocation region can be substantially achieved without using a mask layer (without using a mask layer as in the related art). . In addition, since this growth can be performed from the crystal growth of a layer (for example, a buffer layer) located immediately above the substrate, there is an advantage that the subsequent growth process can be performed continuously.
[0016]
In addition, according to the first aspect of the present invention, the width a of the convex portion is set in a submicron order of 0 <a <1 μm, and the area occupied by the convex portion with respect to the substrate surface is reduced. Since it is 50% or less, the crystal thickness required until the above-mentioned uneven surface is covered with a layer exclusively grown from the upper part of the convex part can be reduced. As a result, the thermal expansion stress possessed by the crystal is reduced, and the occurrence of warpage can be suppressed.
[0017]
According to the second aspect of the present invention, the ratio of the area occupied by the projections to the substrate surface in the above configuration is particularly set to 2 to 30%, so that the inheritance of dislocation defects is minimized in addition to the above operation. Can be suppressed. In other words, the ratio of the area of the convex portions at which the dislocation lines may extend is set to the minimum necessary for achieving the lateral growth, so that the dislocation defects included in the crystal grown thereon have a minimum value. You can get closer.
[0018]
According to a third aspect of the present invention, the width a of the convex portion is set to be in a range of 0 <a <1 μm, and the purpose of the present invention is to change the viewpoint of the invention exclusively to minimize the crystal thickness. Thus, the area ratio occupied by the projections is set to 50 to 70%. That is, increasing the occupied area ratio of the protrusions results in increasing the density of the protrusions, and when the above-described lateral growth is caused on a substrate having such protrusions, the growth starts. The uneven surface is covered with a layer exclusively grown from above the convex portion in a short time, and as a result, a crystal layer which is thinner and thus has a further improved warpage problem can be obtained.
[0019]
The invention according to claim 4 is an invention of a specific approach aiming at minimizing dislocation defects. For example, when the convex portions are provided in a parallel stripe shape, the width a of the convex portions is 0 <a <1 μm. And the convex portion is formed so as to have a portion in which the width a of the convex portion is equal to or less than the width b of the concave portion, so that the concave portion having a dislocation line blocking effect is dominant. It becomes a shape, and the inheritability of dislocation defects is suppressed low, and consequently dislocation defects are suppressed.
[0020]
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
1A to 1C are cross-sectional views for explaining a crystal growth state of a semiconductor substrate according to the present invention. In the drawing, reference numeral 1 denotes a substrate, and 2 denotes a semiconductor crystal grown on the substrate 1 by vapor phase. A convex portion 11 and a concave portion 12 are formed on the crystal growth surface of the substrate 1, and the crystal growth is performed exclusively from above the convex portion 11.
[0021]
The substrate in the present invention refers to a substrate serving as a base for growing various semiconductor crystal layers, in which a buffer layer or the like for lattice matching has not been formed yet. As such a substrate, sapphire (C plane, A plane, R plane), SiC (6H, 4H, 3C), GaN, Si, spinel, ZnO, GaAs, NGO, etc. can be used. Other materials may be used as long as they correspond to the above. In addition, those off from these substrates may be used.
[0022]
Various semiconductor materials can be used as the semiconductor crystal grown on the substrate 1, and the composition ratio of x and y is changed in AlXGa 1 -X-YInYN (0 ≦ x ≦ 1, 0 ≦ y ≦ 1). GaN, Al 0.5 Ga 0.05 N, In 0.5 Ga 0.05 N and the like can be exemplified.
[0023]
Above all, in the case of a semiconductor material containing Al such as AlGaN, the conventional mask method has a problem of growing on a SiO 2 mask layer. However, according to the present invention, such a problem can be solved by masklessness. Lateral growth of AlGaN, which could not be done conventionally, becomes possible, and a high-quality film with low dislocations can be grown directly above the substrate. Therefore, light absorption by the GaN layer, which is a problem in an ultraviolet light emitting element or the like, is eliminated, which is particularly preferable in application.
[0024]
It is effective that the convex portion 11 formed on the crystal growth surface of the substrate 1 has a shape such that crystal growth is performed exclusively from above. “The crystal growth is performed exclusively from the upper part” refers to a state in which crystal growth can be predominantly performed at the apex or the top surface of the convex part 11 and in the vicinity thereof. Although good, it means that the crystal growth of the convex portion 11 becomes dominant eventually. That is, if a low dislocation region is formed by lateral growth starting from the upper part, the same effect as that of the conventional ELO requiring a mask can be obtained. This is a feature of the present invention in that it can be grown without a mask. Hereinafter, this point will be described with reference to FIG.
[0025]
FIG. 1 is a cross-sectional view of a projection 11 formed in a stripe shape.
In the present invention, the width a of the projection 11 is set to 0 <a <1 μm. As described above, the reason why the width a of the convex portion 11 is suppressed to the order of submicron is to reduce the thickness of the crystal required to cover the uneven surface of the substrate and to reduce the thickness of the substrate surface of the convex portion. It is to reduce dislocation defects in combination with the area ratio occupied. From this viewpoint, it is not preferable that the width a of the convex portion 11 is 1 μm or more, since the purpose of reducing the thickness cannot be sufficiently achieved. Therefore, it is desirable that the width a is as narrow as possible. However, considering the workability of unevenness processing, a width that is too narrow is not preferable, and it is desirable to select the width a in the range of about 0.1 <a <0.7 μm. . The “width of the convex portion” in the present invention generally refers to the width of the top surface of the convex portion. However, when the width of the top surface of the convex portion is different from the width of the rising base portion, the base portion width is different. Sometimes it refers to the width of. Further, the groove depth (convex height h) may be appropriately selected within a range in which the effect of the present invention is obtained.
[0026]
The ratio of the area occupied by the projections 11 on the substrate surface can be set according to the purpose. First, from the general viewpoint of the present invention that the thickness of the semiconductor crystal 2 is reduced and the dislocation is reduced, the area ratio occupied by the protrusion is set to 50% or less. This is because, in the growth mode in which dislocations from the sapphire substrate extend straight, the number of dislocations inherited decreases as the area ratio occupied by the projections decreases.
[0027]
Therefore, it is preferable that the area ratio occupied by the protrusions is small, and it is preferable that the area ratio be 40% or less, and more preferably 30% or less. In particular, when the content is 30% or less, the object of minimizing dislocation inheritance can be achieved. However, if the area ratio occupied by the projections is extremely reduced, lateral growth itself is unlikely to occur, or it takes a considerable time for the growth. Therefore, it is necessary to secure a projection area of 2% or more. Is desirable. Therefore, from the viewpoint of minimizing the succession of dislocations, the area ratio occupied by the protrusions is preferably 2 to 30%, and more preferably 4 to 20%.
[0028]
On the other hand, from the viewpoint of minimizing the thickness of the semiconductor crystal 2, the area ratio occupied by the convex portions is selected in the range of 50 to 70%. By increasing the density of the projections in this manner, the time during which the crystal growths starting from the upper portions of the respective projections unite with each other can be shortened, and as a result, the thickness of the semiconductor crystal 2 can be minimized. is there. If the area ratio exceeds 70%, the dislocation blocking effect is greatly reduced, which is not desirable.
[0029]
As will be described later, a desirable form of the convex portion 11 is a stripe-shaped convex portion. In the case of such a convex portion, the shape of the convex portion can be defined by the relationship between the width a of the convex portion 11 and the width b of the concave portion 12. That is, on the assumption that the width a of the convex portion 11 is 0 <a <1 μm, the width a of the convex portion is set to be equal to or less than the width b of the concave portion. Can be aimed at. In this case, the relationship between the width a and the width b does not necessarily have to be strictly satisfied over the entire surface of the substrate, and it is sufficient that at least a main portion of the substrate surface is configured as such.
[0030]
Hereinafter, an example will be described in the case of a stripe-shaped convex portion.
FIG. 1A shows a case where the width of the protrusion is 0.5 μm, the area ratio occupying the substrate surface is about 50%, and the height h of the protrusion is also substantially the same. In this case, the source gas can reach the concave portion 12 and the vicinity thereof, so that the growth in the concave portion 12 also occurs. Further, crystal growth also occurs from the upper part of the convex part 11, and as shown in FIG. 1B, crystal units 20 and 21 are generated on the upper part of the convex part 11 and on the surface of the concave part 12, respectively. . Under such circumstances, when the crystal growth continues, the films grown in the lateral direction starting from the upper part of the projection 11 are connected, and eventually cover the uneven surface of the substrate 1 as shown in FIG. In this case, a low dislocation region is formed in the upper part of the concave portion 12, thereby improving the quality of the formed film. At this time, the thickness required until the concave portion was covered and became flat was 0.5 μm.
[0031]
In the present invention, there is no particular limitation as long as such a convex portion 11 is used, and various shapes can be adopted.
Specifically, when the groove depth (projection height) h is larger than the groove width B as described above, when the groove depth (projection height) h is smaller than the groove width B, the groove width is further increased. Various combinations can be performed such as when the groove depth (height of the convex portion) h is very shallow with respect to B, or when the groove width B is very large with respect to the width A of the convex portion 11. In particular, when the groove depth (height of the convex portion) h is deeper than the groove width B, the raw material gas cannot substantially diffuse to the bottom during vapor phase growth, so that the raw material efficiently contributes to the growth of the upper portion of the convex portion 11. preferable. Further, it is preferable that the groove width B is wider than the width A of the convex portion 11 in that the lateral growth region is increased and the low dislocation region is formed wider.
[0032]
Examples of the mode of forming such a concavo-convex surface include island-shaped dotted projections, stripe-shaped projections, lattice-shaped projections, and projections in which the lines forming these are curved. Can be exemplified.
Among these convex portions, those having a stripe-shaped convex stripe are preferable in that the production process can be simplified and a regular pattern can be easily produced. The longitudinal direction of the stripe may be arbitrary, but if the material to be grown on the substrate is GaN and the <1-100> direction of the GaN-based material is used, it is difficult to form oblique facets such as {1-101} planes. Lateral growth (lateral growth) is faster. As a result, it is particularly preferable that the uneven surface is quickly covered.
[0033]
As in the embodiment shown in FIG. 1, when the concave and convex surface of the substrate 1 is buried while the cavity 13 is left, and then the light emitting portion is grown thereon to produce a light emitting element, the refraction of the interface between the cavity and the semiconductor is made. A large rate difference can be obtained. As a result, the rate at which light directed downward from the light emitting portion is reflected at this interface increases. For example, when the LED is die-bonded with the sapphire substrate surface facing down, it is preferable because the amount of light that can be taken out increases.
[0034]
Further, burying the cavity 13 while leaving it intact means that the contact area between the substrate 1 and the semiconductor layer grown thereon can be reduced. It is preferable in terms of reducing the amount. This reduction in strain has the effect of reducing the warpage that occurs when a GaN-based material is grown thick on sapphire. In particular, in the conventional method, when a GaN-based material is crystal-grown on a Si substrate, there is a problem that warpage and cracks are generated due to a difference in thermal expansion coefficient and high-quality crystal growth cannot be performed. Eliminate problems.
[0035]
Further, by utilizing the fact that the contact area between the substrate 1 and the semiconductor layer 2 grown thereon can be reduced, when the semiconductor layer 2 grows thick, stress concentrates on this small contact portion, and the substrate 1 and the semiconductor layer 2 can be separated. By applying this, a substrate such as GaN can be manufactured.
[0036]
As described above, the case where only one semiconductor layer 2 is grown on the substrate 1 has been described. However, in order to further reduce dislocation defects, a similar process may be repeated twice. That is, as shown in FIG. 2, after the crystal growth of the first semiconductor layer 2a is performed so as to cover the uneven surface of the substrate 1 by the same method as described above, the surface of the first semiconductor layer 2a is The second semiconductor crystal 2b can also be formed on the first semiconductor layer 2a by crystal growth exclusively from above the convex portion of the first semiconductor layer 2a by vapor phase growth. In this case, if the convex portion 11 of the substrate 1 and the position of the convex portion 11a formed on the first semiconductor layer 2a are shifted in the vertical direction, the first semiconductor Many dislocations above the protrusions 11a of the layer 2a will not propagate. That is, with such a configuration, the entire region of the second semiconductor layer 2b can be a low dislocation region, and a higher quality semiconductor layer can be obtained.
[0037]
Further, the surface of the second semiconductor crystal 2b may be made more uneven, and a third semiconductor layer similarly formed by a vapor phase growth method may be formed thereon. Alternatively, a similar process may be repeated to form a plurality of semiconductor layers in a multiplex manner. With such a configuration, dislocations that propagate each time the layers are stacked can be gradually reduced without intentionally adjusting the position of the upper and lower convex portions as described above.
[0038]
The projections can be formed, for example, by patterning the projections according to the shape of the projections using a normal photolithography technique, and performing etching using an RIE technique or the like.
[0039]
HVPE, MOCVD, MBE, or the like may be used as a method for growing a semiconductor layer on a substrate. When forming a thick film, the HVPE method is preferable, but when forming a thin film, the MOCVD method is preferable.
[0040]
The growth conditions (gas type, growth pressure, growth temperature, and the like) for growing a semiconductor layer on a substrate may be appropriately selected depending on the purpose as long as the effects of the present invention are obtained.
[0041]
【Example】
[Example 1]
A photoresist is patterned on the c-plane sapphire substrate (width: 0.3 μm, period: 4 μm, stripe orientation: stripe extending direction is <11-20> direction of the sapphire substrate), and 3 μm by RIE (Reactive Ion Etching) apparatus. Was etched in a square cross section to a depth of. After removing the photoresist, the substrate was mounted on a MOVPE apparatus. Thereafter, the temperature was increased to 1100 ° C. in a hydrogen atmosphere, and thermal etching was performed. Thereafter, the temperature was lowered to 500 ° C., and trimethylgallium (hereinafter, TMG) was used as a Group 3 raw material, and ammonia was flowed as an N raw material, to grow a GaN low-temperature buffer layer. Subsequently, the temperature was raised to 1000 ° C., and TMG / ammonia was flowed as a raw material and silane was flowed as a dopant to grow an n-type GaN layer. The growth time at that time was set to a time corresponding to 4 μm in the GaN growth in the case where the normal unevenness was not applied.
[0042]
Observation of the cross section after the growth shows that the growth has occurred in the concave portions of the substrate, but as shown in FIG. 1C, the concave and convex portions were covered while leaving the hollow portions 13 in the concave portions, and a flat GaN film was obtained. .
On this film, pits (corresponding to dislocations) appearing when InGaN (InN mixed crystal ratio = 0.2, 100 nm thickness) was continuously grown were counted to evaluate the dislocation density. The dislocation density was 6 cm −3 , which was lower than that of the normal reported example.
[0043]
For comparison, a GaN layer and an InGaN layer were formed on a normal c-plane sapphire substrate under the same growth conditions and evaluated. The result was 2 × 10 9 cm −3, which was almost the same as that of the normal report example, and was much larger than that of Example-1.
[0044]
An attempt was made to compare with Example-1 by the ordinary ELO method. First, a GaN layer having a thickness of 1.5 μm was formed on a sapphire substrate via a buffer layer. Thereafter, a resist for forming an SiO 2 film by lift-off was applied, and exposure was attempted. However, although a 0.5 μm stripe was formed at the center of the wafer, no pattern was formed at the periphery of the wafer. It has been found that this is because the distance between the mask and the wafer fluctuates in the plane due to the warpage of the wafer. Therefore, pattern formation of 0.3 μm was abandoned.
[0045]
[Example 2]
An n-type AlGaN cladding layer, an InGaN light-emitting layer, a p-type AlGaN cladding layer, and a p-type GaN contact layer were sequentially formed on the film obtained in Example 1 to produce an ultraviolet LED wafer having an emission wavelength of 370 nm.
Thereafter, electrode formation and element separation were performed to obtain an LED element. The average value of the output of the LED chips collected over the entire wafer and the reverse current characteristics were evaluated. As an object to be compared, there is an ultraviolet LED chip having the above structure manufactured using a normal sapphire substrate. Table 1 shows the evaluation results.
[0046]
[Table 1]
Figure 2004006931
[0047]
As shown in Table 2, it was found that a sample manufactured using the present invention has a higher output and a higher quality LED with less leakage current than the conventional example.
[0048]
[Example 3]
The GaN crystal produced in Example 1 was used as a first crystal, and a second crystal was grown thereon. First, the GaN first crystal was patterned with a photoresist (width: 2 μm, period: 4 μm, stripe orientation: <1-100> of the GaN substrate), and etched by a RIE apparatus into a square cross section to a depth of 2 μm. At this time, the patterning was performed so that the concave portion of the first crystal came on the convex portion of the substrate. The aspect ratio at this time was 1. After removing the photoresist, the substrate was mounted on a MOVPE apparatus. Thereafter, the temperature was raised to 1000 ° C. in a mixed atmosphere of nitrogen, hydrogen and ammonia. Thereafter, TMG / ammonia was flowed as a raw material and silane was flowed as a dopant to grow an n-type GaN layer. The growth time at that time was set to a time corresponding to 4 μm in the GaN growth in the case where the normal unevenness was not applied.
[0049]
Observation of the cross-section after growth reveals growth on the concave portions of the substrate and growth on the side surfaces of the convex portions. However, as shown in FIG. 2, a flat GaN film is obtained that covers the concave and convex portions while leaving the hollow portions. Was. Subsequently, when the pits of the obtained film were evaluated, it was found that the pits were reduced to 2 × 10 5 cm −3 . Thus, it was confirmed that the effect of reducing the dislocation density was further obtained by repeating this example.
[0050]
【The invention's effect】
According to the semiconductor substrate of the present invention and the method for manufacturing the same as described above, by providing the substrate with a convex portion, lateral growth capable of forming a low dislocation region without using a mask layer is performed. Can be made. Therefore, the problems caused by the formation of the mask layer, such as the problem of generation of new defects in the united portion of the lateral growth portion due to the micro tilting of the axis, the problem of autodoping, and the problem that the Al-containing semiconductor material cannot be selectively grown Can be eliminated. In addition, since the growth of the buffer layer and the growth of the semiconductor crystal layer such as the light-emitting portion can be continuously performed in one growth after providing the uneven surface on the substrate, there is an advantage that the manufacturing process can be simplified. In addition, by defining the width and the area of the convex portion that is the source of threading dislocation, there is an advantage that the low dislocation density region can be relatively widened, and the thickness used for covering the unevenness and flattening can be reduced.
Furthermore, the use of the cavity has the effect of improving the reflectance and the phenomenon of residual strain, and is a very valuable invention in terms of improving characteristics and reducing costs.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view for explaining a crystal growth state of a semiconductor substrate according to the present invention.
FIG. 2 is a cross-sectional view for explaining a crystal growth state of a semiconductor substrate according to the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Substrate 11 Convex part 12 Concavity 13 Cavity part 2 Semiconductor layer

Claims (4)

基板と該基板上に気相成長された半導体結晶とからなる半導体基材であって、前記基板の結晶成長面が凹凸面とされ、前記半導体結晶は該凹凸面における凸部の上方部から専ら結晶成長された半導体基材において、前記凸部は、その幅aが0<a<1μmの範囲とされ、且つ、上記基板表面に対して該凸部の占有する面積の割合が50%以下とされていることを特徴とする半導体基材。A semiconductor substrate comprising a substrate and a semiconductor crystal vapor-grown on the substrate, wherein a crystal growth surface of the substrate is an uneven surface, and the semiconductor crystal is exclusively formed from an upper portion of a convex portion in the uneven surface. In the semiconductor substrate on which the crystal has been grown, the protrusion has a width a in a range of 0 <a <1 μm and a ratio of an area occupied by the protrusion to the substrate surface is 50% or less. A semiconductor substrate characterized in that: 基板表面に対して凸部の占有する面積の割合が、2〜30%とされていることを特徴とする請求項1記載の半導体基材。2. The semiconductor substrate according to claim 1, wherein a ratio of an area occupied by the projection to the substrate surface is 2 to 30%. 基板と該基板上に気相成長された半導体結晶とからなる半導体基材であって、前記基板の結晶成長面が凹凸面とされ、前記半導体結晶は該凹凸面における凸部の上方部から専ら結晶成長された半導体基材において、前記凸部は、その幅aが0<a<1μmの範囲とされ、且つ、上記基板表面に対して該凸部の占有する面積の割合が50〜70%とされていることを特徴とする半導体基材。A semiconductor substrate comprising a substrate and a semiconductor crystal vapor-grown on the substrate, wherein a crystal growth surface of the substrate is an uneven surface, and the semiconductor crystal is exclusively formed from an upper portion of a convex portion in the uneven surface. In the semiconductor substrate on which the crystal has been grown, the protrusion has a width a in a range of 0 <a <1 μm, and a ratio of an area occupied by the protrusion to the substrate surface is 50 to 70%. A semiconductor substrate characterized in that: 基板と該基板上に気相成長された半導体結晶とからなる半導体基材であって、前記基板の結晶成長面が凹凸面とされ、前記半導体結晶は該凹凸面における凸部の上方部から専ら結晶成長された半導体基材において、前記凸部の幅aが0<a<1μmの範囲とされ、且つ、該凸部の幅aが前記凹部の幅bと同等以下とされている部分を有することを特徴とする半導体基材。A semiconductor substrate comprising a substrate and a semiconductor crystal vapor-grown on the substrate, wherein a crystal growth surface of the substrate is an uneven surface, and the semiconductor crystal is exclusively formed from an upper portion of a convex portion in the uneven surface. In the semiconductor substrate on which the crystal is grown, there is a portion in which the width a of the protrusion is in the range of 0 <a <1 μm, and the width a of the protrusion is equal to or less than the width b of the recess. A semiconductor substrate, characterized in that:
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006339534A (en) * 2005-06-03 2006-12-14 Sony Corp Light emitting diode, manufacturing method therefor, light emitting diode back light, light emitting diode lighting device, light emitting diode display and electronic apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006339534A (en) * 2005-06-03 2006-12-14 Sony Corp Light emitting diode, manufacturing method therefor, light emitting diode back light, light emitting diode lighting device, light emitting diode display and electronic apparatus

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