JP2009023853A - Group iii-v nitride semiconductor substrate, method for manufacturing the same, and group iii-v nitride semiconductor device - Google Patents

Group iii-v nitride semiconductor substrate, method for manufacturing the same, and group iii-v nitride semiconductor device Download PDF

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JP2009023853A
JP2009023853A JP2007186012A JP2007186012A JP2009023853A JP 2009023853 A JP2009023853 A JP 2009023853A JP 2007186012 A JP2007186012 A JP 2007186012A JP 2007186012 A JP2007186012 A JP 2007186012A JP 2009023853 A JP2009023853 A JP 2009023853A
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nitride semiconductor
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Takeshi Meguro
健 目黒
Kazutoshi Watanabe
和俊 渡辺
Takamasa Suzuki
貴征 鈴木
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Hitachi Cable Ltd
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Hitachi Cable Ltd
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<P>PROBLEM TO BE SOLVED: To provide a group III-V nitride semiconductor substrate and a method for manufacturing the substrate in which fluctuation in plane orientation of the substrate surface can be decreased by reducing warpage of the substrate in an as-grown state, and to provide a group III-V nitride semiconductor device using the above substrate and having excellent uniformity in the substrate plane. <P>SOLUTION: A light emitting element is fabricated by using a GaN self-standing substrate 10 and by forming an epitaxial layer comprising a GaN semiconductor crystal on the substrate, the substrate having a dislocation density of not more than 3×10<SP>6</SP>cm<SP>-2</SP>on the back face of the substrate and showing decrease in the dislocation density by a rate of not more than 3×10<SP>6</SP>cm<SP>-2</SP>/mm in the thickness direction from the back face to the top face of the substrate. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、III−V族窒化物系半導体基板及びその製造方法、並びにIII−V族窒化物系半導体デバイスに関し、特に、アズグロウン(as grown)状態での基板の反りを小さくすることにより、基板表面の面方位のばらつきを低減させることができるIII−V族窒化物系半導体基板及びその製造方法、並びに当該基板を使用して基板面内均一性に優れた、短波長LD(レーザーダイオード)、LED(発光ダイオード)及び高耐圧HEMT(高電子移動度トランジスタ)等のIII−V族窒化物系半導体デバイスに関するものである。   The present invention relates to a group III-V nitride semiconductor substrate, a method for manufacturing the same, and a group III-V nitride semiconductor device, and more particularly, by reducing the warpage of the substrate in an as grown state. III-V nitride semiconductor substrate capable of reducing variations in surface plane orientation and method for manufacturing the same, and short-wavelength LD (laser diode) excellent in in-plane uniformity using the substrate, The present invention relates to a group III-V nitride semiconductor device such as an LED (light emitting diode) and a high breakdown voltage HEMT (high electron mobility transistor).

窒化物半導体材料は、禁制帯幅が充分大きくバンド間遷移も直接遷移型であるため、短波長発光素子、特に青色発光ダイオード(LED)の製造に用いられている。また、最近では、更に短波長の紫外LEDや、これらLEDと蛍光体を組み合わせた白色LEDが実用化され始めている。   Nitride semiconductor materials have a sufficiently large forbidden band and a direct transition type between bands, and are therefore used in the manufacture of short wavelength light emitting devices, particularly blue light emitting diodes (LEDs). In addition, recently, ultraviolet LEDs with shorter wavelengths and white LEDs in which these LEDs and phosphors are combined have begun to be put into practical use.

半導体のデバイスを作製する場合、その下地基板にはエピタキシャル成長する結晶と格子定数や線膨張係数の同じ基板を使用する、いわゆるホモエピタキシャル成長を行うのが一般的である。例えば、GaAsやAlGaAsのエピタキシャル成長を行うための基板には、GaAs単結晶基板が用いられている。   When a semiconductor device is manufactured, so-called homoepitaxial growth is generally performed using a substrate having the same lattice constant and linear expansion coefficient as that of a crystal to be epitaxially grown as an underlying substrate. For example, a GaAs single crystal substrate is used as a substrate for epitaxial growth of GaAs or AlGaAs.

しかし、III−V族窒化物系半導体結晶に限っては、これまでに実用に足るサイズ、特性のIII−V族窒化物系半導体基板を製造することができなかった。このため、これまでに実用化されている窒化物系発光ダイオードは、そのほとんどが格子定数の近いサファイア基板上に、有機金属気相成長(MOVPE)法を用いてIII−V族窒化物系半導体結晶をヘテロエピタキシャル成長させることにより製造されている。従って、ヘテロ成長であることに起因した様々な問題が発生していた。   However, it has not been possible to produce a group III-V nitride semiconductor substrate having a size and characteristics sufficient for practical use so far only for a group III-V nitride semiconductor crystal. For this reason, most nitride-based light-emitting diodes that have been put to practical use so far are formed on a sapphire substrate having a lattice constant close to that of a group III-V nitride-based semiconductor using a metal organic vapor phase epitaxy (MOVPE) method. Manufactured by heteroepitaxial growth of crystals. Therefore, various problems due to hetero-growth have occurred.

例えば、サファイア基板とGaNの線膨張係数の違いに起因して、エピタキシャル成長後の基板が大きく反ってしまうという問題が生じていた。これは、エピタキシャル成長後のフォトリソグラフィ工程やチップ加工工程において、基板の割れを生じさせるなど、歩留り低下の原因となる。   For example, due to the difference in coefficient of linear expansion between the sapphire substrate and GaN, there has been a problem that the substrate after epitaxial growth is greatly warped. This causes a decrease in yield, such as cracking of the substrate in the photolithography process and chip processing process after epitaxial growth.

また、サファイア基板とGaNでは、格子定数が異なるため、窒化物結晶を単結晶成長させるために、一旦本来の結晶成長温度よりも低い温度でバッファ層を堆積させる必要があり、これが結晶成長の工程時間を延ばす要因になっている。更に、サファイア基板上の成長では、サファイアとGaNの格子定数差に起因して、GaNエピ層中に10から10個/cm−2もの多量の転位が発生してしまう。この転位は、発光素子の出力や信頼性を阻害する要因となる。従来の青色系のLEDでは、これまで転位が問題とされることは少なかったが、今後、より高出力化が求められるようになり、また、紫外LEDの実現に向けて短波長化が促進されると、デバイス特性に及ぼす転位の影響が大きくなってくることが予想されており、何らかの対策が必要となっている。 Also, since the lattice constants of sapphire substrate and GaN are different, in order to grow a single crystal of nitride crystal, it is necessary to deposit a buffer layer at a temperature lower than the original crystal growth temperature, which is the process of crystal growth It is a factor that extends time. Further, in the growth on the sapphire substrate, as many as 10 8 to 10 9 dislocations / cm −2 are generated in the GaN epilayer due to the difference in lattice constant between sapphire and GaN. This dislocation is a factor that hinders the output and reliability of the light emitting element. In conventional blue LEDs, dislocation has not been a problem so far, but higher output will be required in the future, and shortening of the wavelength will be promoted toward the realization of ultraviolet LEDs. Then, it is expected that the effect of dislocations on device characteristics will increase, and some countermeasures are required.

これらの問題を解決するため、近年、GaNの単結晶自立基板が開発されてきた。GaN自立基板の製造方法としては、例えば、下地基板に開口部を有するマスクを形成し、開口部からラテラル成長させることにより転位の少ないGaN層を得る技術、いわゆるELO(Epitaxial Lateral Overgrowth)技術を用いてサファイア基板上にGaN層を形成した後、サファイア基板をエッチング等により除去し、GaN自立基板を得ることが提案されている(例えば、特許文献1参照)。   In order to solve these problems, GaN single crystal free-standing substrates have been developed in recent years. As a method for manufacturing a GaN free-standing substrate, for example, a so-called ELO (Epitaxial Lateral Overgrowth) technique is used, in which a mask having an opening is formed on a base substrate and a GaN layer with few dislocations is obtained by lateral growth from the opening. It has been proposed to form a GaN layer on a sapphire substrate and then remove the sapphire substrate by etching or the like to obtain a GaN free-standing substrate (see, for example, Patent Document 1).

また、ELO法をさらに発展させた方法として、FIELO(Facet-Initiated Epitaxial Lateral Overgrowth)法が開発されている(例えば、非特許文献1参照)。FIELO法は、酸化シリコンマスクを用いて選択成長を行う点でELO法と共通するが、選択成長の際にマスク開口部にファセットを形成する点で相違している。ファセットを形成することにより、転位の伝搬方向を変え、エピタキシャル成長層の上面に至る貫通転位を低減する。FIELO法を用いて、例えばサファイア等の下地基板上に厚膜のGaN層を成長させ、その後下地基板を除去すれば、結晶欠陥の比較的少ない良質のGaN自立基板を得ることができる。   Further, as a further development of the ELO method, a FIELO (Facet-Initiated Epitaxial Lateral Overgrowth) method has been developed (for example, see Non-Patent Document 1). The FIELO method is common to the ELO method in that selective growth is performed using a silicon oxide mask, but differs in that facets are formed in the mask opening during selective growth. By forming facets, the propagation direction of dislocations is changed, and threading dislocations reaching the upper surface of the epitaxial growth layer are reduced. If a thick GaN layer is grown on a base substrate such as sapphire using the FIELO method, and then the base substrate is removed, a high-quality GaN free-standing substrate with relatively few crystal defects can be obtained.

上記以外にも、低転位のGaN自立基板を得る方法として、DEEP(Dislocation Elimination by the Epi-growth with Inverted-Pyramidal Pits)法が開発されている(例えば、非特許文献2、特許文献2参照)。DEEP法は、GaAs基板上にパターニングした窒化珪素等のマスクを用いてGaNを成長させることにより、結晶表面に意図的にファセット面で囲まれたピットを複数形成し、前記ピットの底部に転位を集積させることにより、その他の領域を低転位化するものである。   In addition to the above, DEEP (Dislocation Elimination by the Epi-growth with Inverted-Pyramidal Pits) method has been developed as a method for obtaining a low-dislocation GaN free-standing substrate (see, for example, Non-Patent Document 2 and Patent Document 2). . In the DEEP method, by growing GaN using a mask made of silicon nitride or the like patterned on a GaAs substrate, a plurality of pits intentionally surrounded by facet surfaces are formed on the crystal surface, and dislocations are formed at the bottom of the pits. By accumulating, other regions are lowered in dislocation.

これらELO法やDEEP法等の方法を用いて異種基板上にHVPE法でGaN膜を成長し、その後、下地基板からGaN層を剥離して得られたGaN基板は、特に低転位結晶の必要なレーザーダイオード(LD)の開発に主に用いられているが、最近では、LED用の基板としても使われるようになってきている。
特開平11−251253号公報 特開2003−165799号公報 Akira Usui et. al.,「Thick GaN Epitaxial Growth with Low Dislocation Density by Hydride Vapor Phase Epitaxy」, Jpn. J. Appl. Phys. vol. 36(1997) pp. L899-L902 Kensaku Motoki et. al., 「Preparation of Large Freestanding GaN Substrates by Hydride Vapor Phase Epitaxy Using GaAs as a Starting Substrate」, Jpn. J. Appl. Phys. Vol. 40(2001)pp. L140-L143
A GaN substrate obtained by growing a GaN film by a HVPE method on a heterogeneous substrate using such an ELO method or DEEP method, and then peeling the GaN layer from the underlying substrate requires a particularly low dislocation crystal. Although it is mainly used for the development of laser diodes (LD), it has recently been used as a substrate for LEDs.
JP-A-11-251253 JP 2003-165799 A Akira Usui et.al., "Thick GaN Epitaxial Growth with Low Dislocation Density by Hydride Vapor Phase Epitaxy", Jpn. J. Appl. Phys. Vol. 36 (1997) pp. L899-L902 Kensaku Motoki et.al., "Preparation of Large Freestanding GaN Substrates by Hydride Vapor Phase Epitaxy Using GaAs as a Starting Substrate", Jpn. J. Appl. Phys. Vol. 40 (2001) pp. L140-L143

しかしながら、上記の方法で得られたアズグロウンのGaN自立基板においても、表面平坦性が悪い、基板の反りが大きい等の理由のため、そのままでは窒化物系半導体用基板として用いることが出来ない。このため、通常、GaN自立基板の表面と裏面を研磨加工して鏡面に仕上げてから、デバイス作製に使用するのが一般的である。   However, the as-grown GaN free-standing substrate obtained by the above method cannot be used as it is as a nitride-based semiconductor substrate because of its poor surface flatness and large substrate warpage. For this reason, it is general that the front and back surfaces of a GaN free-standing substrate are polished to a mirror finish before use in device fabrication.

しかし、アズグロウンの状態で反りが大きいと、鏡面研磨後に表面の面方位に大きな面内分布を生じてしまう。このような基板を用いてLEDやLDを製作すると、面方位の分布が直接的に発光波長の分布に影響を与えてしまうため、歩留りを大きく損ねてしまうという問題があった。   However, if the warp is large in the as-grown state, a large in-plane distribution is generated in the surface orientation after mirror polishing. When an LED or LD is manufactured using such a substrate, the surface orientation distribution directly affects the emission wavelength distribution, resulting in a significant loss of yield.

従って、本発明の目的は、上記の課題を解決すること、具体的には、アズグロウンの状態での基板の反りを小さくすることにより、基板表面の面方位のばらつきを低減させることができるIII−V族窒化物系半導体基板及びその製造方法、並びに当該基板を使用して基板面内均一性に優れたIII−V族窒化物系半導体デバイスを提供することにある。   Therefore, an object of the present invention is to solve the above-described problems, specifically, to reduce the variation in the plane orientation of the substrate surface by reducing the warpage of the substrate in the as-grown state. It is an object of the present invention to provide a group V nitride semiconductor substrate, a method of manufacturing the same, and a group III-V nitride semiconductor device excellent in in-plane uniformity using the substrate.

上記目的を達成すべく本発明のIII−V族窒化物系半導体基板は、III−V族窒化物系半導体結晶からなる自立した半導体基板であって、基板裏面の転位密度が3×10cm−2以下であり、かつ厚さ方向において基板裏面から表面に至るまで転位密度が3×10cm−2/mm以下の割合で減少していることを特徴とする。 In order to achieve the above object, the group III-V nitride semiconductor substrate of the present invention is a self-supporting semiconductor substrate made of a group III-V nitride semiconductor crystal, and the rear surface has a dislocation density of 3 × 10 6 cm. −2 or less, and the dislocation density is reduced at a rate of 3 × 10 6 cm −2 / mm or less from the substrate back surface to the surface in the thickness direction.

前記基板厚さは100μm以上10mm以下であることが好ましい。また、前記III−V族窒化物系半導体結晶の組成をInGaAl1−x−yN(0≦x≦1、0≦y≦1、0≦x+y≦1)で表すことができる。 The substrate thickness is preferably 100 μm or more and 10 mm or less. Further, the composition of the group III-V nitride-based semiconductor crystal can be expressed by In x Ga y Al 1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). .

また、上記目的を達成すべく本発明のIII−V族窒化物系半導体基板の製造方法は、異種基板上に、III−V族窒化物系半導体結晶を厚さ方向において転位密度が3×10cm−2/mm以下の割合で減少するように堆積する工程と、前記III−V族窒化物系半導体層と前記異種基板とを分離する工程と、前記III−V族窒化物系半導体層の前記異種基板を分離した側の面に対して、転位密度が3×10cm−2以下となるように転位密度を低減する工程と、を含むことを特徴とする。 In order to achieve the above object, the method for producing a group III-V nitride semiconductor substrate of the present invention has a dislocation density of 3 × 10 3 in the thickness direction on a group III-V nitride semiconductor crystal on a different substrate. A step of depositing so as to decrease at a rate of 6 cm −2 / mm or less; a step of separating the group III-V nitride-based semiconductor layer from the dissimilar substrate; and the group III-V nitride-based semiconductor layer And a step of reducing the dislocation density so that the dislocation density is 3 × 10 6 cm −2 or less with respect to the surface on the side where the different substrate is separated.

前記III−V族窒化物系半導体結晶を堆積する工程は、HVPE法により行うことが好ましい。また、前記III−V族窒化物系半導体結晶の組成をInGaAl1−x−yN(0≦x≦1、0≦y≦1、0≦x+y≦1)で表すことができる。 The step of depositing the III-V nitride semiconductor crystal is preferably performed by HVPE. Further, the composition of the group III-V nitride-based semiconductor crystal can be expressed by In x Ga y Al 1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). .

更に、前記転位密度を低減する工程は、前記III−V族窒化物系半導体層を、前記異種基板を分離した側の面から所定の厚さだけ研磨するものとすることができる。   Further, in the step of reducing the dislocation density, the group III-V nitride semiconductor layer may be polished by a predetermined thickness from the surface on the side where the dissimilar substrate is separated.

前記III−V族窒化物系半導体基板上に、III−V族窒化物系半導体結晶からなるエピタキシャル層を形成してIII−V族窒化物系半導体デバイスとすることができる。III−V族窒化物系半導体デバイスとしては、LD(レーザーダイオード)、LED(発光ダイオード)、及びHEMT(高電子移動度トランジスタ)等を挙げることができる。   An epitaxial layer made of a group III-V nitride semiconductor crystal can be formed on the group III-V nitride semiconductor substrate to form a group III-V nitride semiconductor device. Examples of the III-V nitride semiconductor device include LD (laser diode), LED (light emitting diode), and HEMT (high electron mobility transistor).

本発明のIII−V族窒化物系半導体基板によれば、アズグロウンの状態での基板の反りを小さくして、基板表面の面方位のばらつきを低減させることができる。   According to the group III-V nitride semiconductor substrate of the present invention, it is possible to reduce the warpage of the substrate in the as-grown state and to reduce the variation in the plane orientation of the substrate surface.

また、本発明のIII−V族窒化物系半導体基板の製造方法によれば、上記の基板表面の面方位のばらつきを低減したIII−V族窒化物系半導体基板を確実に得ることができる。   Further, according to the method for producing a group III-V nitride semiconductor substrate of the present invention, a group III-V nitride semiconductor substrate with reduced variations in the plane orientation of the substrate surface can be obtained with certainty.

更に、本発明のIII−V族窒化物系半導体デバイスによれば、基板表面の面方位のばらつきを低減させた基板を用いているので、基板面内均一性に優れた特性を有し、歩留りが向上する。   Furthermore, according to the III-V nitride semiconductor device of the present invention, since a substrate with reduced variation in the plane orientation of the substrate surface is used, it has excellent in-plane uniformity and yield. Will improve.

本実施形態に係るIII−V族窒化物系半導体基板は、異種基板上にGaN系半導体単結晶を成長した後、これを剥離することにより得られる自立したGaN単結晶基板であって、基板裏面の転位密度及び、厚さ方向における基板裏面から表面に至るまでの転位密度の割合を特定の範囲としている。以下、これらの点を中心に詳しく説明する。   The group III-V nitride semiconductor substrate according to the present embodiment is a self-supporting GaN single crystal substrate obtained by growing a GaN-based semiconductor single crystal on a heterogeneous substrate and then peeling the GaN-based semiconductor single crystal. The dislocation density and the ratio of the dislocation density from the substrate back surface to the front surface in the thickness direction are within a specific range. Hereinafter, these points will be mainly described in detail.

(自立基板)
まず、自立基板(自立した基板)とは、自らの形状を保持できるだけでなく、ハンドリングに不都合が生じない程度の強度を有する基板をいう。このような強度を有するためには、自立基板の厚さを好ましくは100μm以上、更に好ましくは200μm以上とする。
(Independent substrate)
First, a self-supporting substrate (self-supporting substrate) refers to a substrate that not only can hold its own shape but also has a strength that does not cause inconvenience in handling. In order to have such strength, the thickness of the free-standing substrate is preferably 100 μm or more, more preferably 200 μm or more.

(基板裏面)
基板裏面は平坦に研磨加工することが好ましい。これは、転位密度の高い領域を取り除いて後述する低転位密度の範囲に収めると共に、基板にエピ成長を行う際に、基板とサセプタとの密着性を良くするためである。基板の裏面全面が、サセプタと均等に接触していないと、サセプタからの熱伝導が不均一になって、エピ成長中の基板温度が面内で不均一になってしまう。基板温度の面内ばらつきは、結晶成長速度や組成、不純物濃度のばらつきとなって現れるため、特性の面内均一性の高いエピを成長することができなくなってしまう。エピの成長装置には、基板の裏面をサセプタと密着させない、フェイスダウン方式も存在するが、この場合も、基板の裏面に均熱板と呼ぶ平板を置くことが一般的であり、基板の裏面と均熱板との距離にばらつきがあれば、前述の温度ばらつきが生じ、特性の均一性に支障を来たす結果になる。
(Back side of substrate)
The back surface of the substrate is preferably polished flat. This is because the region having a high dislocation density is removed so as to fall within the range of the low dislocation density described later, and the adhesion between the substrate and the susceptor is improved when the substrate is epitaxially grown. If the entire back surface of the substrate is not evenly in contact with the susceptor, the heat conduction from the susceptor becomes non-uniform, and the substrate temperature during epi growth becomes non-uniform in the plane. In-plane variations in the substrate temperature appear as variations in crystal growth rate, composition, and impurity concentration, and it becomes impossible to grow epi with high in-plane uniformity of characteristics. Epi growth equipment also has a face-down method in which the back surface of the substrate is not in close contact with the susceptor, but in this case as well, it is common to place a flat plate called a soaking plate on the back surface of the substrate. If there is a variation in the distance between the soaking plate and the soaking plate, the aforementioned temperature variation occurs, resulting in a problem in the uniformity of characteristics.

また、GaN基板の裏面(N面)は、表面(Ga面)に較べて研磨が容易であり、裏面の平坦化研磨は、表面ほど工数の増加、歩留りの低下をもたらさない。裏面は、エピ成長時のサセプタとの密着性が問題なく得られる程度に平坦であれば良く、必ずしも鏡面になっている必要はない。即ち、ラップ面や研削面、あるいはこれに歪除去のための処理(エッチング等)を施した面であっても構わない。   Further, the back surface (N surface) of the GaN substrate is easier to polish than the front surface (Ga surface), and the flattening polishing of the back surface does not increase the man-hour and decrease the yield as much as the front surface. The back surface need only be flat to such an extent that adhesion to the susceptor during epi growth can be obtained without any problem, and does not necessarily have to be a mirror surface. That is, it may be a lapping surface, a ground surface, or a surface subjected to a treatment for removing strain (etching or the like).

(基板表面)
GaN基板の基板表面においては、基板裏面のように、低転位密度の範囲に収めたり、基板とサセプタとの密着性を良くしたりする目的で研磨する必要はないが、アズグロウンの状態(結晶成長したままの状態であり、研削や研磨などの加工工程を加えていない状態)では、完全に平坦な面が得られない。デバイスの作成プロセスに微細加工が必要なことから、基板表面においても、裏面と同様に研磨加工を行うことが好ましい。
(Substrate surface)
The substrate surface of the GaN substrate does not need to be polished for the purpose of keeping it within a low dislocation density range or improving the adhesion between the substrate and the susceptor unlike the back surface of the substrate, but the as-grown state (crystal growth) In a state in which no processing step such as grinding or polishing is applied), a completely flat surface cannot be obtained. Since microfabrication is required for the device fabrication process, it is preferable to perform polishing on the substrate surface as well as on the back surface.

(基板の導電型、キャリア濃度)
基板の導電型は、目的とするデバイスに合わせて適宜制御すべきであり、一律に決めることはできないが、例えば、Si、S、O等をドープしたn型や、MgやZn等をドープしたp型とすることができる。また、基板のキャリア濃度の絶対値も、目的とするデバイスに合わせて適宜制御すべきであるから、一律に決めることはできない。しかし、LED用の基板にあっては、裏面電極のコンタクトが容易に取れる程度の導電性基板であることが望ましく、このためには、基板のキャリア濃度は5×1017cm−3以上であることが望ましい。但し、LED用の基板のキャリア濃度としては、あまり高すぎても、基板の結晶性を下げ、また透明性を損なう原因にもなるため、5×1017cm−3以上、1×1019cm−3以下に制御することがより望ましい。
(Substrate conductivity type, carrier concentration)
The conductivity type of the substrate should be appropriately controlled according to the target device and cannot be determined uniformly. For example, n-type doped with Si, S, O, etc., or doped with Mg, Zn, etc. It can be p-type. Further, since the absolute value of the carrier concentration of the substrate should be appropriately controlled according to the target device, it cannot be determined uniformly. However, it is desirable that the LED substrate is a conductive substrate that can easily contact the back electrode, and for this purpose, the carrier concentration of the substrate is 5 × 10 17 cm −3 or more. It is desirable. However, if the carrier concentration of the substrate for the LED is too high, the crystallinity of the substrate is lowered and the transparency is impaired, so that it is 5 × 10 17 cm −3 or more and 1 × 10 19 cm. It is more desirable to control to -3 or less.

(基板の転位密度)
異種基板上に、ELO法やFIELO法などによりGaNを成長させると、成長初期(おおよそ30μm程度)で大幅に転位が減少し、その後は、一般的な傾向として欠陥がゆっくりと減少していくが、最終的に基板の裏面と表面とで転位密度に大きな差があると格子間隔に差が生じるため、その差により基板が反ってしまう。このため、(1)この成長初期の転位が多い領域を研磨により除去して、裏面の転位密度を裏面の鏡面研磨後の状態で3×10cm−2以下にする、(2)上記の欠陥がゆっくりと減少していく領域の成長条件を制御して、基板の厚さ方向の単位長さ当たり転位密度差を3×10cm−2/mm以下にする、ことによりアズグロウンでの反りを減少させて、面方位のばらつきを抑え、後述する実施例の結果からも明らかなように、大幅に歩留りを向上させることが可能になる。
(Dislocation density of substrate)
When GaN is grown on a heterogeneous substrate by the ELO method, the FIELO method, or the like, dislocations are greatly reduced at the initial stage of growth (about 30 μm), and thereafter, defects generally slowly decrease. Finally, if there is a large difference in dislocation density between the back surface and the front surface of the substrate, a difference occurs in the lattice spacing, which causes the substrate to warp. For this reason, (1) the region where there are many dislocations in the initial stage of growth is removed by polishing, and the dislocation density on the back surface is 3 × 10 6 cm −2 or less in the state after mirror polishing of the back surface. (2) By controlling the growth conditions of the region where defects are slowly reduced, the difference in dislocation density per unit length in the thickness direction of the substrate is 3 × 10 6 cm −2 / mm or less, thereby warping in as-grown. As shown in the results of Examples to be described later, it is possible to significantly improve the yield.

上記の(1)と(2)の条件を満たせば、例えば、基板表面近傍において厚さ250μmで転位密度が1×10cm−2変化する場合(即ち、1mmあたり4×10cm−2位変化する場合)のような急激な転位密度の低下が除かれ、アズグロウンでの反りは大きくならず、よって面方位のばらつきもあまり変化しなくなる。さらに、現状では基板表面全面で10cm−2台の低転位密度を達成したGaN基板は存在しないが、基板裏面の転位密度が3×10cm−2であり、仮に基板表面の転位密度が理想的に0としても、これは最大3×10倍転位密度が異なる場合であり、厚さが1mm以上であれば(1)、(2)の条件を満たすため、十分に小さい面方位ばらつきが得られることになる。 If the above conditions (1) and (2) are satisfied, for example, when the dislocation density changes by 1 × 10 6 cm −2 at a thickness of 250 μm near the substrate surface (that is, 4 × 10 6 cm −2 per 1 mm). A sudden drop in the dislocation density as in the case of a change in position is eliminated, and the warpage in as-grown does not increase, so that the variation in plane orientation does not change much. Furthermore, at present, there is no GaN substrate that has achieved a low dislocation density of 10 4 cm −2 on the entire surface of the substrate, but the dislocation density on the back surface of the substrate is 3 × 10 6 cm −2. Is ideally 0, this is a case where the maximum dislocation density is 3 × 10 6 times different. If the thickness is 1 mm or more, the conditions (1) and (2) are satisfied. Variation will be obtained.

(基板の材料)
本実施形態の基板の材料としては、GaNのみならず、一般式:InGaAl1−x−yN(ただし、0≦x≦1、0≦y≦1、及び0≦x+y≦1)で表すIII−V族窒化物系半導体を用いることができる。III−V族窒化物系半導体結晶には、GaNを始めとしてAlNやInN、また、これらの混晶が実用に供されている。基板という観点で見たとき、ある程度の大口径でかつ厚みの厚い結晶を容易に得ることができ、また、ホモエピタキシャル成長も容易なのがGaNであるが、これ以外には、AlNやAlGaNの基板が使い勝手の点で有利である。また、これらの基板表面は(0001)のIII族面であることが望ましい。GaN系の結晶は極性が強く、III族面の方がV族面(窒素面)より化学的及び熱的に安定で、デバイスの作製が容易であるからである。
(Substrate material)
As a material for the substrate of the present embodiment, not only GaN but also the general formula: In x Ga y Al 1-xy N (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, and 0 ≦ x + y ≦ 1) III-V group nitride semiconductors represented by As the group III-V nitride semiconductor crystal, GaN, AlN, InN, and mixed crystals thereof are practically used. From the viewpoint of a substrate, GaN can easily obtain a crystal having a large diameter and a large thickness, and homoepitaxial growth is easy, but other than this, substrates of AlN or AlGaN are also available. It is advantageous in terms of usability. Further, these substrate surfaces are preferably (0001) group III surfaces. This is because the GaN-based crystal has a strong polarity, the group III surface is more chemically and thermally stable than the group V surface (nitrogen surface), and the device can be easily manufactured.

(基板の製造方法)
本実施形態の基板は、異種基板上にGaN系半導体単結晶を成長した後、これを剥離することにより得られる。
GaN系半導体単結晶は、HVPE法(ハイドライド気相成長)により成長することが望ましい。これは、HVPE法は結晶成長速度が速く、厚膜成長を必要とする基板の作製に適するからである。また、GaN系半導体単結晶を成長した後、これを剥離する方法には、ボイド形成剥離法(VAS法)を用いることができる。VAS法は、大口径の基板を再現良く剥離することが可能で、かつ、低転位で特性の均一なGaN系自立基板を得ることができるという点で優れている。異種基板上にGaN系半導体単結晶を成長した後、これを剥離する手法を用いるのは、現状、直径φ2インチ以上でかつハンドリングに耐える十分な厚さを有するGaN系自立基板の成長方法は、VAS法や、FIELO法にレーザーリフトオフ法を組み合わせたような手法に限られているためである。
(Substrate manufacturing method)
The substrate of this embodiment is obtained by growing a GaN-based semiconductor single crystal on a different substrate and then peeling it.
The GaN-based semiconductor single crystal is desirably grown by HVPE (hydride vapor phase epitaxy). This is because the HVPE method has a high crystal growth rate and is suitable for manufacturing a substrate that requires thick film growth. Further, as a method of peeling a GaN-based semiconductor single crystal after it has been grown, a void formation peeling method (VAS method) can be used. The VAS method is excellent in that a large-diameter substrate can be peeled off with good reproducibility, and a GaN-based free-standing substrate having low dislocations and uniform characteristics can be obtained. The method of growing a GaN-based semiconductor single crystal on a heterogeneous substrate and then peeling it off is currently used to grow a GaN-based free-standing substrate having a diameter of φ2 inches or more and a sufficient thickness to withstand handling. This is because the method is limited to a method in which the laser lift-off method is combined with the VAS method or the FIELO method.

(GaN系デバイス)
本実施形態のGaN自立基板は、その上にMOVPE法でIII−V族窒化物系半導体結晶をエピタキシャル成長させ、短波長のLD、LED及び高耐圧HEMTを製造する用途に適している。本実施形態のGaN自立基板では面方位のばらつきが低減されているので、その基板を用いて、短波長のLDやLEDを製造することにより、発光波長の面内分布が均一なLDやLEDを得ることができる。また、HEMTなどの高周波素子では、基板表面の面方位のばらつきにより、エピ・基板界面に蓄積される導電性を与える不純物の取り込みに差が生じる可能性があるが、本実施形態のGaN自立基板を用いることにより、その面方位のばらつきを抑えてバッファリークの安定化が可能であり、不純物低減の諸策と相まって、低リーク且つそのばらつきが小さい高性能なHEMTエピの提供が可能になる。
(GaN device)
The GaN free-standing substrate of this embodiment is suitable for applications in which a III-V nitride semiconductor crystal is epitaxially grown on the GaN substrate by MOVPE to produce a short wavelength LD, LED, and high voltage HEMT. In the GaN free-standing substrate of this embodiment, variation in the plane orientation is reduced. By using the substrate to manufacture a short wavelength LD or LED, an LD or LED having a uniform in-plane distribution of emission wavelengths can be obtained. Obtainable. Further, in a high-frequency device such as HEMT, there is a possibility that a difference occurs in the incorporation of impurities that give conductivity accumulated at the epi-substrate interface due to variations in the plane orientation of the substrate surface. By using this, it is possible to stabilize the buffer leak by suppressing variations in the plane orientation, and in combination with various measures for reducing impurities, it is possible to provide a high-performance HEMT epi with low leakage and small variations.

(GaN自立基板の製造)
図1に示す製造工程により、GaN自立基板を製造した。
まず、直径2インチ径のC面サファイア基板1上に、MOVPE法で、20nmの低温成長GaNバッファ層を介してSiドープGaN層3を0.5μm成長させた(a)。成長条件は、圧力を常圧とし、バッファ層成長時の基板温度を600℃、エピ層成長時の基板温度を1100℃とした。原料は、III族原料としてTMGを、V族原料としてNHを、ドーパントとしてモノシランを用いた。キャリアガスは、水素と窒素の混合ガスである。結晶の成長速度は4μm/hとした。エピ層のキャリア濃度は、2×1018cm−3とした。
(Manufacture of GaN free-standing substrates)
A GaN free-standing substrate was manufactured by the manufacturing process shown in FIG.
First, on the C-plane sapphire substrate 1 having a diameter of 2 inches, the Si-doped GaN layer 3 was grown by 0.5 μm through a 20 nm low-temperature growth GaN buffer layer by the MOVPE method (a). The growth conditions were normal pressure, substrate temperature during buffer layer growth of 600 ° C., and substrate temperature during epi layer growth of 1100 ° C. The raw materials used were TMG as a group III raw material, NH 3 as a group V raw material, and monosilane as a dopant. The carrier gas is a mixed gas of hydrogen and nitrogen. The crystal growth rate was 4 μm / h. The carrier concentration of the epi layer was 2 × 10 18 cm −3 .

次に、このSiドープGaN層3上に、金属Ti薄膜5を20nmの厚さに蒸着した(b)。こうして得られた基板を電気炉に入れ、20%のNHを含有するH気流中において1050℃で20分間熱処理した。その結果、GaN層3の一部がエッチングされて高密度の空隙層(ボイド層)6が発生し、またTi層は窒化されて表面にサブミクロンの微細な穴が高密度に形成されたTiN層7に変化した(c)。 Next, a metal Ti thin film 5 was deposited on the Si-doped GaN layer 3 to a thickness of 20 nm (b). The substrate thus obtained was placed in an electric furnace and heat-treated at 1050 ° C. for 20 minutes in a H 2 stream containing 20% NH 3 . As a result, a part of the GaN layer 3 is etched to generate a high-density void layer (void layer) 6, and the Ti layer is nitrided to form submicron fine holes on the surface with high density TiN Changed to layer 7 (c).

この基板をHVPE炉に入れ、キャリアガス中に8×10−3atmのGaCl及び4.8×10−2atmのNHからなる原料ガスを含有する供給ガス用いて、GaN層8を600μmの厚さに成長させた(d)。ここで、キャリアガスは、Hを5%含有するNガスを用いた。GaN層の成長条件は、常圧及び1080℃の基板温度とした。またGaN結晶の成長工程において、ドーピング原料ガスとしてSiHClを基板領域に供給することによりSiをドープした。成長が終了した後、HVPE装置を冷却する過程で、GaN層8はボイド層6を境に下地基板から自然に剥離し、GaNの自立基板が得られた。 This substrate was put into an HVPE furnace, and a GaN layer 8 was formed in a thickness of 600 μm using a supply gas containing a source gas composed of 8 × 10 −3 atm GaCl and 4.8 × 10 −2 atm NH 3 in a carrier gas. Grow to thickness (d). Here, N 2 gas containing 5% of H 2 was used as the carrier gas. The growth conditions for the GaN layer were normal pressure and a substrate temperature of 1080 ° C. In the GaN crystal growth process, Si was doped by supplying SiH 2 Cl 2 as a doping source gas to the substrate region. After the growth was completed, in the process of cooling the HVPE apparatus, the GaN layer 8 naturally separated from the base substrate with the void layer 6 as a boundary, and a GaN free-standing substrate was obtained.

得られたGaN自立基板9は、裏面側に凸向きに反りを生じており、表面は、裏面の反りの形状を反映した凹面形状になっていた(e)。次に、GaN自立基板9を窒化物系半導体素子用基板として用いることができるようにするため、両面を研磨した。研磨は裏面側から行った。裏面(N面)の研磨は、研削により行ったが、ラップ(GC♯800などを使用)により行ってもよい。一例として、GaN自立基板9を、約150μmから300μmの厚さ、研磨した。その後、NaOH水溶液または塩酸と過酸化水素水の混合液を用いて裏面をエッチングした。例えば、当該混合液は、塩酸:過酸化水素水:水=1:1:2の比率で混合した混合液を用いた。エッチング後裏面粗さは数μm〜数百nmになった。裏面エッチング後GaN自立基板の表面(Ga面)を鏡面化するためラップ後ポリッシュした。更に、表面についても同様の工程で研磨を行い、GaN自立基板10が得られた(f)。   The obtained GaN free-standing substrate 9 was warped in a convex direction on the back surface side, and the front surface was a concave shape reflecting the shape of the warp on the back surface (e). Next, both surfaces were polished so that the GaN free-standing substrate 9 can be used as a substrate for a nitride-based semiconductor element. Polishing was performed from the back side. The back surface (N surface) is polished by grinding, but may be performed by lapping (using GC # 800 or the like). As an example, the GaN free-standing substrate 9 was polished to a thickness of about 150 μm to 300 μm. Thereafter, the back surface was etched using a NaOH aqueous solution or a mixed solution of hydrochloric acid and hydrogen peroxide. For example, the mixed solution used was a mixed solution mixed at a ratio of hydrochloric acid: hydrogen peroxide solution: water = 1: 1: 2. After etching, the back surface roughness was several μm to several hundred nm. After the back surface etching, polishing was performed after lapping in order to mirror the surface (Ga surface) of the GaN free-standing substrate. Further, the surface was polished in the same process, and the GaN free-standing substrate 10 was obtained (f).

この基板(No.1)の裏面及び表面の転位密度はそれぞれ8.1×10、4.3×10cm−2であり、裏面と表面の転位密度比は1.9であった。また、単位厚さあたりの転位密度差は7.6×10cm−2/mmであった。得られた結果を表1に示す。 The dislocation density of the back surface and the front surface of this substrate (No. 1) was 8.1 × 10 6 and 4.3 × 10 6 cm −2 , respectively, and the dislocation density ratio between the back surface and the front surface was 1.9. Moreover, the dislocation density difference per unit thickness was 7.6 × 10 6 cm −2 / mm. The obtained results are shown in Table 1.

上記と同様に、図1に示す製造工程により、GaN自立基板を製造した(No.2)。   In the same manner as described above, a GaN free-standing substrate was manufactured by the manufacturing process shown in FIG.

上記と同様に、図1に示す製造工程により、GaN自立基板を製造した(No.3)。   In the same manner as described above, a GaN free-standing substrate was manufactured by the manufacturing process shown in FIG.

(GaN系発光素子の製造)
得られたNo.1〜3のGaN自立基板10上に、減圧MOVPE法を用いてGaN系発光素子を製造した。
(Manufacture of GaN-based light emitting devices)
No. obtained A GaN-based light emitting device was manufactured on the GaN free-standing substrate 1 to 3 using a reduced pressure MOVPE method.

図2に、製造したGaN系発光素子の構造を示す。この発光素子は、GaN自立基板10上に、3層のInGaN井戸層21と4層のGaN障壁層とからなる多重量子井戸構造20、Mgをドープしたp型AlGaNクラッド層23、及びMgをドープしたp型GaNコンタクト層24を順次積層し、GaN自立基板10の裏面にn型電極25、p型GaNコンタクト層24の表面にp型電極26を形成したものである。   FIG. 2 shows the structure of the manufactured GaN-based light emitting device. This light emitting device has a multi-quantum well structure 20 composed of three InGaN well layers 21 and four GaN barrier layers, a p-type AlGaN cladding layer 23 doped with Mg, and Mg doped on a GaN free-standing substrate 10. The p-type GaN contact layer 24 is sequentially laminated, and an n-type electrode 25 is formed on the back surface of the GaN free-standing substrate 10, and a p-type electrode 26 is formed on the surface of the p-type GaN contact layer 24.

このGaN系発光素子は、周知の有機金属気相成長(MOCVD)法により、有機金属原料として、トリメチルガリウム(TMG),トリメチルアルミニウム(TMA),トリメチルインジウム(TMI),ビスシクロペンタジエニルマグネシウム(CpMg)を、ガス原料として、アンモニア(NH),シラン(SiH)を、キャリアガスとして、水素及び窒素を用い、以下のようにして製造した。 This GaN-based light emitting device is formed by using a known metal organic chemical vapor deposition (MOCVD) method as an organic metal raw material, such as trimethyl gallium (TMG), trimethyl aluminum (TMA), trimethyl indium (TMI), biscyclopentadienyl magnesium ( Cp 2 Mg) was manufactured as follows using ammonia (NH 3 ) and silane (SiH 4 ) as gas raw materials and hydrogen and nitrogen as carrier gases.

まず、No.1のGaN自立基板10上に、厚さ3nmのIn0.15Ga0.85N井戸層21が3層と、厚さ10nmのGaN障壁層22が4層とから成る多重量子井戸構造(MQW)20を有するInGaN系活性層を形成した。この際、それぞれの井戸層及び障壁層形成後に成長中断をおいた。なお、成長中断は、TMG、TMI等のIII族原料の供給を一時的に停止することにより実施した。次に、多重量子井戸構造20の上部に、p型Al0.1Ga0.9Nクラッド層23,p型GaNコンタクト層24を順に形成した。最後に、GaN自立基板10の裏面(N面)側にn型電極25を、p型GaNコンタクト層24上にp型電極26を形成した。 First, no. A multi-quantum well structure (MQW) comprising three In 0.15 Ga 0.85 N well layers 21 having a thickness of 3 nm and four GaN barrier layers 22 having a thickness of 10 nm on one GaN free-standing substrate 10. An InGaN-based active layer having 20) was formed. At this time, the growth was interrupted after the respective well layers and barrier layers were formed. The growth interruption was performed by temporarily stopping the supply of Group III materials such as TMG and TMI. Next, a p-type Al 0.1 Ga 0.9 N clad layer 23 and a p-type GaN contact layer 24 were formed in this order on the multiple quantum well structure 20. Finally, an n-type electrode 25 was formed on the back surface (N surface) side of the GaN free-standing substrate 10, and a p-type electrode 26 was formed on the p-type GaN contact layer 24.

次に、No.2、3のGaN自立基板上にも同様にしてGaN系発光素子を製造し、良品率を比較した。なお、GaN基板の厚さは500μmに合わせている。結果を表2に示す。   Next, no. Similarly, GaN-based light emitting devices were manufactured on a few GaN free-standing substrates, and the yield rates were compared. The thickness of the GaN substrate is set to 500 μm. The results are shown in Table 2.

良品率の絶対値は、エピ構造、成長方法及び規格などにより変わるが、同じ条件で比較した結果、表2に示したとおり、裏面の転位密度が3×10cm−2以下で、かつ単位厚さあたりの転位密度差が3×10cm−2/mm以下とすることにより、大幅な歩留改善を成し遂げることができることが分かった。 The absolute value of the yield rate varies depending on the epi structure, the growth method, and the standard. As a result of comparison under the same conditions, as shown in Table 2, the rear surface dislocation density is 3 × 10 6 cm −2 or less, and the unit It has been found that when the dislocation density difference per thickness is 3 × 10 6 cm −2 / mm or less, significant yield improvement can be achieved.

[他の実施形態]
以上、本発明を実施例に基づいて詳細に説明したが、これらは例示であり、それらの各プロセスの組合せ等にいろいろな変形例が可能なこと、またそうした変形例も本発明の範囲にあることは当業者に理解されるところである。たとえば、実施例においてはGaN結晶成長をHVPE法で行ったが、GaN結晶成長の一部にMOVPE法を組合せても良い。
[Other Embodiments]
As described above, the present invention has been described in detail based on the embodiments. However, these are exemplifications, and various modifications can be made to combinations of these processes, and such modifications are also within the scope of the present invention. This will be understood by those skilled in the art. For example, in the examples, the GaN crystal growth is performed by the HVPE method, but the MOVPE method may be combined with a part of the GaN crystal growth.

上記実施例では、LED構造における効果を検証したが、MQWを備えるLD構造でも、同様の効果が推定される。   In the above embodiment, the effect in the LED structure was verified, but the same effect is also estimated in the LD structure including MQW.

また、結晶成長の初期又は途中の段階で、結晶成長界面に複数の凹凸を出しながら成長を行わせるために、SiO等のマスクを用いる周知のELO技術を組合せて用いても良い。 In addition, in order to cause the growth to occur while projecting a plurality of irregularities at the crystal growth interface at an initial stage or in the middle of the crystal growth, a known ELO technique using a mask such as SiO 2 may be used in combination.

また、実施例では下地基板にサファイア基板を用いたが、GaAsやSi、ZrB、ZnO等のように、従来GaN系エピタキシャル層用基板として報告例のある基板は、すべて適用が可能である。 In the embodiments, a sapphire substrate is used as the base substrate, but any substrate that has been reported as a conventional GaN-based epitaxial layer substrate, such as GaAs, Si, ZrB 2 , or ZnO, can be applied.

更に、実施例ではSiドープのGaNの自立基板の製造方法を例示したが、アンドープや他のドーパント、例えばMgやFe、S、O、Zn、Ni、Cr、Se等をドープしたGaN自立基板に適用することもできる。   Further, in the examples, a method for producing a Si-doped GaN free-standing substrate was illustrated, but the GaN free-standing substrate doped with undoped or other dopants such as Mg, Fe, S, O, Zn, Ni, Cr, Se, etc. It can also be applied.

また、実施例ではGaNの自立基板の製造方法を例示したが、AlN、AlGaN、InGaN、AlInGaNの基板に適用することも可能である。   Moreover, although the manufacturing method of the GaN self-supporting substrate was illustrated in the embodiment, it can be applied to AlN, AlGaN, InGaN, and AlInGaN substrates.

実施例1に係るGaN自立基板の製造方法を示す模式図である。6 is a schematic diagram showing a method for manufacturing a GaN free-standing substrate according to Example 1. FIG. 実施例2に係るGaN系発光素子を示す断面図である。6 is a cross-sectional view showing a GaN-based light emitting device according to Example 2. FIG.

符号の説明Explanation of symbols

1 サファイア基板
3 SiドープGaN層
5 Ti薄膜
6 ボイド層
7 TiN層
8 GaN層
9 GaN自立基板
10 GaN自立基板
20 多重量子井戸構造
21 InGaN井戸層
22 GaN障壁層
23 p型AlGaNクラッド層
24 p型GaNコンタクト層
25 n型電極
26 p型電極
1 sapphire substrate 3 Si-doped GaN layer 5 Ti thin film 6 void layer 7 TiN layer 8 GaN layer 9 GaN free-standing substrate 10 GaN free-standing substrate 20 multiple quantum well structure 21 InGaN well layer 22 GaN barrier layer 23 p-type AlGaN cladding layer 24 p-type GaN contact layer 25 n-type electrode 26 p-type electrode

Claims (8)

III−V族窒化物系半導体結晶からなる自立した半導体基板であって、基板裏面の転位密度が3×10cm−2以下であり、かつ厚さ方向において基板裏面から表面に至るまで転位密度が3×10cm−2/mm以下の割合で減少していることを特徴とするIII−V族窒化物系半導体基板。 A self-supporting semiconductor substrate made of a III-V nitride-based semiconductor crystal, the dislocation density on the back surface of the substrate being 3 × 10 6 cm −2 or less, and the dislocation density from the back surface to the front surface in the thickness direction Is reduced at a rate of 3 × 10 6 cm −2 / mm or less, a group III-V nitride-based semiconductor substrate. 前記基板厚さが100μm以上10mm以下であることを特徴とする請求項1に記載のIII−V族窒化物系半導体基板。   2. The group III-V nitride semiconductor substrate according to claim 1, wherein the substrate thickness is 100 μm or more and 10 mm or less. 前記III−V族窒化物系半導体結晶の組成がInGaAl1−x−yN(0≦x≦1、0≦y≦1、0≦x+y≦1)で表されることを特徴とする請求項1に記載のIII−V族窒化物系半導体基板。 The composition of the III-V nitride semiconductor crystal is represented by In x Ga y Al 1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). The group III-V nitride semiconductor substrate according to claim 1. 異種基板上に、III−V族窒化物系半導体結晶を厚さ方向において転位密度が3×10cm−2/mm以下の割合で減少するように堆積する工程と、
前記III−V族窒化物系半導体層と前記異種基板とを分離する工程と、
前記III−V族窒化物系半導体層の前記異種基板を分離した側の面に対して、転位密度が3×10cm−2以下となるように転位密度を低減する工程と、
を含むことを特徴とするIII−V族窒化物系半導体基板の製造方法。
Depositing a group III-V nitride-based semiconductor crystal on a heterogeneous substrate so that the dislocation density decreases at a rate of 3 × 10 6 cm −2 / mm or less in the thickness direction;
Separating the III-V nitride-based semiconductor layer and the heterogeneous substrate;
Reducing the dislocation density such that the dislocation density is 3 × 10 6 cm −2 or less with respect to the surface of the group III-V nitride-based semiconductor layer on which the heterogeneous substrate is separated;
A method for producing a group III-V nitride semiconductor substrate, comprising:
前記III−V族窒化物系半導体結晶を堆積する工程は、HVPE法により行われることを特徴とする請求項4に記載のIII−V族窒化物系半導体基板の製造方法。   The method of manufacturing a group III-V nitride semiconductor substrate according to claim 4, wherein the step of depositing the group III-V nitride semiconductor crystal is performed by an HVPE method. 前記III−V族窒化物系半導体結晶の組成がInGaAl1−x−yN(0≦x≦1、0≦y≦1、0≦x+y≦1)で表されることを特徴とする請求項4に記載のIII−V族窒化物系半導体基板の製造方法。 The composition of the III-V nitride semiconductor crystal is represented by In x Ga y Al 1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). A method for producing a group III-V nitride semiconductor substrate according to claim 4. 前記転位密度を低減する工程は、前記III−V族窒化物系半導体層を、前記異種基板を分離した側の面から所定の厚さだけ研磨するものであることを特徴とする請求項4に記載のIII−V族窒化物系半導体基板の製造方法。   5. The step of reducing the dislocation density comprises polishing the group III-V nitride semiconductor layer by a predetermined thickness from the surface on the side where the different substrate is separated. The manufacturing method of the group III-V nitride type semiconductor substrate of description. 請求項1乃至3のいずれか1項に記載のIII−V族窒化物系半導体基板上に、III−V族窒化物系半導体結晶からなるエピタキシャル層が形成されてなるIII−V族窒化物系半導体デバイス。   A group III-V nitride system in which an epitaxial layer made of a group III-V nitride semiconductor crystal is formed on the group III-V nitride semiconductor substrate according to any one of claims 1 to 3. Semiconductor device.
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JP2016150865A (en) * 2015-02-17 2016-08-22 古河機械金属株式会社 Group iii nitride semiconductor substrate, and production method of group iii nitride semiconductor substrate
JP2016150864A (en) * 2015-02-17 2016-08-22 古河機械金属株式会社 Group iii nitride semiconductor substrate, and production method of group iii nitride semiconductor substrate

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Cited By (4)

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JP2014192475A (en) * 2013-03-28 2014-10-06 Japan Oclaro Inc Nitride optical semiconductor element and optical semiconductor device
JP2015133354A (en) * 2014-01-09 2015-07-23 日立金属株式会社 nitride semiconductor epitaxial wafer and nitride semiconductor device
JP2016150865A (en) * 2015-02-17 2016-08-22 古河機械金属株式会社 Group iii nitride semiconductor substrate, and production method of group iii nitride semiconductor substrate
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