JP2016150865A - Group iii nitride semiconductor substrate, and production method of group iii nitride semiconductor substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a new technology for producing a group III nitride semiconductor substrate.SOLUTION: There is provided a group III nitride semiconductor substrate 1 having a tabular first layer 2 including a plurality of crystal pieces 10 of a group III nitride semiconductor arranged with each clearance 30 therebetween, and a binder 20 interposed between each clearance 30, for holding the plurality of crystal pieces 10, and the clearance 30 has a width widened gradually from a first principal surface 3 toward a second principal surface 4 of the first layer 2.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a group III nitride semiconductor substrate and a method for manufacturing a group III nitride semiconductor substrate.

  Patent Document 1 discloses a group III in which a plurality of crystal substrates cut out from a group III nitride bulk crystal are arranged adjacent to each other in the lateral direction, and a group III nitride crystal is grown on the substrate. A method for producing a nitride crystal is disclosed. Further, Patent Document 1 discloses that if there is a gap between crystal substrates, the crystallinity of crystals growing on the crystal substrates is lowered, so that the crystal substrates are arranged adjacent to each other.

Japanese Patent No. 5332168

  In the case of the technique described in Patent Document 1, the plurality of crystal substrates constituting the substrate are separated from each other. When a plurality of crystal substrates are separated from each other, it is necessary to hold each of the plurality of crystal pieces and move them when moving the substrate composed of the plurality of crystal substrates. Further, when a substrate composed of a plurality of crystal substrates is set at a predetermined position, each of the plurality of crystal pieces needs to be set at a predetermined position with a predetermined positional relationship. Thus, workability is poor when a plurality of crystal substrates are separated from each other.

  An object of the present invention is to provide a new technique for manufacturing a group III nitride semiconductor substrate.

According to the present invention,
A plurality of group III nitride semiconductor crystal pieces arranged with a gap between each other; and
A binder interposed in the gap and holding a plurality of the crystal pieces;
A plate-like first layer comprising:
The group III nitride semiconductor substrate in which the gap is widened from the first main surface to the second main surface of the first layer is provided.

Moreover, according to the present invention,
A preparation step of preparing a plurality of crystal pieces, each of which is a plate-like crystal piece made of a group III nitride semiconductor, and at least a part of the side surface is different from an angle formed by 90 ° with the main surface;
An arrangement step of arranging a plurality of the crystal pieces with a gap between each other on the mounting table;
Forming a binder that is interposed in the gap and holds the plurality of crystal pieces; and
Have
In the arranging step, there is provided a manufacturing method of a group III nitride semiconductor substrate in which the side surfaces are opposed to each other and the crystal pieces are arranged so that the width of the gap increases from the contact side contacting the mounting table to the exposed side. Is done.

  According to the present invention, a new technique for manufacturing a group III nitride semiconductor substrate is realized.

It is an example of the cross-sectional schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the plane schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the plane schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the plane schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the plane schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the cross-sectional schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the cross-sectional schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the cross-sectional schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the plane schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the plane schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the cross-sectional schematic diagram of the crystal piece of this embodiment. It is an example of the cross-sectional schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the cross-sectional schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the cross-sectional schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the plane schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the plane schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the cross-sectional schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is a flowchart which shows an example of the manufacturing method of the group III nitride semiconductor substrate of this embodiment. It is a schematic diagram for demonstrating an example of the process which cuts out a crystal piece from a group III nitride semiconductor substrate. It is a schematic diagram for demonstrating an example of the process which cuts out a crystal piece from a group III nitride semiconductor substrate. It is a schematic diagram for demonstrating an example of the process which processes the crystal | crystallization piece cut out from the group III nitride semiconductor substrate. It is a schematic diagram for demonstrating an example of the process which processes the crystal | crystallization piece cut out from the group III nitride semiconductor substrate. It is a schematic diagram for demonstrating an example of the process which cuts out a crystal piece from a group III nitride semiconductor substrate. It is a schematic diagram for demonstrating an example of the process which cuts out a crystal piece from a group III nitride semiconductor substrate. It is an example of the side surface schematic diagram of the some crystal piece arrange | positioned at the arrangement | positioning process. It is an example of the plane schematic diagram of the some crystal piece arrange | positioned at the arrangement | positioning process. It is an example of the plane schematic diagram of the some crystal piece arrange | positioned at the arrangement | positioning process. It is an example of the plane schematic diagram of the some crystal piece arrange | positioned at the arrangement | positioning process. It is an example of the side surface schematic diagram of the some crystal piece arrange | positioned at the arrangement | positioning process. It is an example of the plane schematic diagram of the some crystal piece arrange | positioned at the arrangement | positioning process. It is an example of the plane schematic diagram of the some crystal piece arrange | positioned at the arrangement | positioning process. It is an example of the side surface schematic diagram of the some crystal piece arrange | positioned at the arrangement | positioning process. It is an example of the side surface schematic diagram which shows the state after a formation process. It is an example of the side surface schematic diagram which shows the state after a formation process. It is a figure for demonstrating the effect of the group III nitride semiconductor substrate of this embodiment. It is a schematic diagram for demonstrating an example of the manufacturing method of the group III nitride semiconductor substrate of this embodiment. It is a schematic diagram for demonstrating an example of the manufacturing method of the group III nitride semiconductor substrate of this embodiment. It is a schematic diagram for demonstrating an example of the manufacturing method of the group III nitride semiconductor substrate of this embodiment. It is a flowchart which shows an example of the manufacturing method of the group III nitride semiconductor substrate of this embodiment.

  Hereinafter, embodiments of a group III nitride semiconductor substrate and a method for manufacturing a group III nitride semiconductor substrate of the present invention will be described with reference to the drawings. The drawings are only schematic diagrams for explaining the configuration of the invention, and the size, shape, number, and ratio of different member sizes are not limited to those shown in the drawings.

<< First Embodiment >>
FIG. 1 shows an example of a schematic cross-sectional view of a group III nitride semiconductor substrate 1 of the present embodiment. 2 and 3 show an example of a schematic plan view of the group III nitride semiconductor substrate 1 of FIG. 1 observed from the first main surface 3 side (from the top to the bottom in the drawing). 4 and 5 show an example of a schematic plan view of the group III nitride semiconductor substrate 1 of FIG. 1 observed from the second main surface 4 side (from the bottom to the top in the figure). 2 corresponds to FIG. 4, and FIG. 3 corresponds to FIG.

  As shown in FIGS. 1 to 5, the group III nitride semiconductor substrate 1 of the present embodiment includes a first layer 2 including a plurality of crystal pieces 10 and a binder 20. The plurality of crystal pieces 10 are arranged with a gap 30 between them. The binder 20 is interposed in the gap 30 and holds the plurality of crystal pieces 10. The gap 30 increases in width from the first main surface 3 (upper surface in FIG. 1) of the first layer 2 toward the second main surface 4 (lower surface in FIG. 1). . In addition, the number of the crystal pieces 10 to show in figure is an example, and is not limited to this.

The crystal piece 10 is composed of a single crystal of a group III nitride semiconductor. The plurality of crystal pieces 10 attached to each other through the binder 20 are formed of the same type of group III nitride semiconductor (Al _x Ga _1-xy In _y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) and x and y of the crystal pieces 10 are preferably the same). The crystal piece 10 can be cut from a group III nitride semiconductor substrate, a fragment of the substrate, or the like.

  The binder 20 is made of a polycrystalline group III nitride semiconductor. The binder 20 may be the same type of group III nitride semiconductor as the crystal piece 10 or may be a different type.

  The crystal piece 10 is a plate-like body having two main surfaces (a first main surface 11 and a second main surface 12) and a side surface 13. The first main surface 11 and the second main surface 12 are in a front-back relationship. The first main surface 11 and the second main surface 12 may be parallel to each other. The shape of the first main surface 11 is, for example, a rectangle as shown in FIGS. 2 and 3, and the size is, for example, 2 mm or more and 100 mm or less and 2 mm or more and 100 mm or less. Moreover, the shape of the 2nd main surface 12 is a rectangle as shown, for example in FIG.4 and FIG.5, The magnitude | size is 2 mm or more and 100 mm or less, for example, 2 mm or more and 100 mm or less in width. The first main surface 11 and the second main surface 12 may have other shapes.

  At least a part of the side surface 13 included in the crystal piece 10 is obliquely processed as shown in FIG. Specifically, the side surface 13 goes to the center of the main surface (a surface parallel to the first main surface 11 and the second main surface 12) as it goes from the first main surface 11 to the second main surface 12. It is processed diagonally. In other words, the second main surface 12 and the side surface 13 are obliquely processed so that the angle formed by the first main surface 11 and the side surface 13 is greater than 90 °, and the angle formed by the first main surface 11 and the side surface 13 is smaller than 90 °. The The portion of the side surface 13 that is not obliquely processed may be perpendicular to the first main surface 11 and the second main surface 12.

  When the shape of the first main surface 11 and the second main surface 12 is a quadrangle, the crystal piece 10 has four side surfaces 13. In this case, one of the four side surfaces 13 may be processed obliquely, or two, three, or all four may be processed obliquely.

  The thickness of the crystal piece 10 (the distance between the first main surface 11 and the second main surface 12) is, for example, 50 μm or more and 20 mm or less.

  It is preferable that the shape and size of the plurality of crystal pieces 10, particularly the shape and size of the first main surface 11, are aligned. “Shape and size are uniform” is a concept including a state in which the shape and size are completely matched and a state in which there is a shift due to a processing error.

  The first main surface 11 is a surface having a predetermined plane orientation. For example, the first main surface 11 may be a + c plane, an m plane, or an a plane. In addition, the first main surface 11 is a {hk− (h + k) l} surface (h, k, and l are integers), or a surface obtained by inclining the {hk− (h + k) l} surface by a predetermined angle. It may be a surface different from the + c surface, the m surface, and the a surface.

  For example, the first main surface 11 is a + c surface, a surface obtained by inclining a + c surface by a predetermined angle (eg, ± 10 ° or less), a m surface, a surface obtained by inclining a m surface by a predetermined angle (eg, ± 10 ° or less), a Surface, a surface inclined by a predetermined angle (eg, ± 10 ° or less), {11-22} surface, surface {11-22} surface inclined by a predetermined angle (eg: ± 10 ° or less), {11− 24} plane, {11-24} plane tilted by a predetermined angle (eg, ± 10 ° or less), {10-12} plane, {10-12} plane tilted by a predetermined angle (eg, ± 10 ° or less) {10-11} plane, {10-11} plane tilted by a predetermined angle (eg, ± 10 ° or less), {20-21} plane, {20-21} plane by a predetermined angle (eg: Any of the inclined surface, {20-23} surface, and {20-23} surface inclined by a predetermined angle (eg, ± 10 ° or less) may be used. .

  The plane orientations of the first principal surfaces 11 of the plurality of crystal pieces 10 are preferably aligned. “The plane orientation is aligned” means that the plane orientations of the first principal surfaces 11 of the plurality of crystal pieces 10 coincide with each other and / or the desired reference plane orientation and the plurality of crystal pieces 10. This is a concept including a state in which the difference from the plane orientation of each first main surface 11 is ± 0.5 ° or less.

  As shown in FIGS. 1 to 3, the first main surface 11 is exposed. The first main surface 11 becomes a growth surface (a surface on which a group III nitride semiconductor crystal is grown) of the group III nitride semiconductor substrate 1 of the present embodiment.

  The plurality of crystal pieces 10 are preferably aligned in the direction in which the first main surface 11 faces. “The direction in which the first main surface 11 faces is aligned” means that the normal directions of the first main surfaces 11 of the plurality of crystal pieces 10 coincide with each other and / or a desired reference direction. And a concept including a state in which the difference between the normal direction of the first main surface 11 of each of the plurality of crystal pieces 10 is ± 0.5 ° or less.

  The plurality of crystal pieces 10 preferably have an orientation accuracy of ± 0.5 ° or less in a direction parallel to the first main surface 11. That is, the crystal pieces 10 have an azimuth accuracy in a direction parallel to the paper surface in FIGS. 2 to 5, in other words, an azimuth accuracy adjusted by rotating around a rotation axis perpendicular to the paper surface is ± 0.5 °. It is preferable that: “Direction accuracy is ± 0.5 ° or less” means that a difference from a desired reference direction is ± 0.5 ° or less.

  As shown in FIG. 1, the plurality of crystal pieces 10 are arranged so that the side surfaces 13 face each other. At least one of the opposing side surfaces 13 is the side surface 13 subjected to the oblique processing described above. In this case, as shown in FIG. 1, the gap 30 between the crystal pieces 10 has a configuration in which the width increases from the first main surface 3 to the second main surface 4 of the first layer 2. .

  In the example shown in FIG. 1, adjacent crystal pieces 10 are in contact with each other on the first main surface 3 of the first layer 2. For this reason, as shown in FIGS. 2 and 3, the gap 30 between the adjacent crystal pieces 10 is not opened on the first main surface 3 side of the first layer 2. On the other hand, in the second main surface 4 of the first layer 2, the adjacent crystal pieces 10 are not in contact with each other. For this reason, as shown in FIGS. 4 and 5, the gap 30 between the adjacent crystal pieces 10 opens on the second main surface 4 side of the first layer 2. As a result, the binder 20 is exposed in the opening. The width G2 of the opening on the second main surface 4 side is, for example, 50 μm or more and 10 mm or less.

  In the example shown in FIGS. 1 to 5, the binder 20 exists not only in the gap 30 but also along the outer periphery of the plurality of crystal pieces 10 and includes the plurality of crystal pieces 10. Further, the binder 20 is not present on the first main surface 11 and the second main surface 12.

  The plurality of crystal pieces 10 are preferably arranged according to a predetermined regularity. For example, as shown in FIGS. 2 and 3, the plurality of crystal pieces 10 may be arranged so that the longitudinal directions of the rectangular first main surface 11 are parallel to each other. Further, the plurality of crystal pieces 10 may be arranged so as to be linearly arranged in one or a plurality of rows.

  Note that a gap 30 may exist in at least a part of the outer periphery of each crystal piece 10, and the crystal piece 10 may be bonded to another crystal piece 10 with the binder 20 interposed in the gap 30. For example, the gap 30 may exist all along the outer periphery of the crystal piece 10, and all the crystal pieces 10 existing along the outer periphery of the crystal piece 10 may be bonded via the binder 20. Alternatively, the gap 30 exists only in a part along the outer periphery of the crystal piece 10, and the crystal piece 10 and only the crystal piece 10 facing the crystal piece 10 with the gap 30 in between are interposed via the binder 20. It may be joined.

  Here, a modification of the group III nitride semiconductor substrate 1 is shown. In addition, it can also be set as the modification which combined the some modification shown here.

<First Modification>
As shown in FIG. 6, the binder 20 may extend to the second main surface 12 of the crystal piece 10. The binder 20 may cover a part or all of the second main surface 12. The second layer 5 may be formed by the binder 20 on the second main surface 4 of the first layer 2. The thickness (the thickness of the second layer 5) M of the binder 20 on the second main surface 12 is, for example, greater than 0 μm and not greater than 20 mm, and preferably greater than 0 μm and not greater than 1 mm. In the example shown in FIG. 1, the value of M is 0.

<Second Modification>
As shown in FIG. 7, the plurality of crystal pieces 10 may be arranged so that the side surfaces 13 that are obliquely processed face each other.

<Third Modification>
As shown in FIG. 8, the binder 20 may not exist along the outer periphery of the plurality of crystal pieces 10. 9 and 10 are schematic plan views of the group III nitride semiconductor substrate 1 of FIG. 8 observed from the first main surface 3 side (from the top to the bottom in the figure).

<Fourth Modification>
As shown in FIG. 11, at least a part of the side surface 13 of the crystal piece 10 includes a first portion 13-1 that is perpendicular to the first main surface 11 and a second portion 13 that is processed obliquely. -2 and may be processed so that these two portions appear in this order from the first main surface 11 toward the second main surface 12. FIG. 12 shows an example of a schematic cross-sectional view of a group III nitride semiconductor substrate 1 having such a crystal piece 10.

<Fifth Modification>
As shown in FIG. 13, the gap 30 may not be completely filled with the binder 20, and a part of the gap 30 may remain as the remaining gap 31. In this case, the height of the binder 20 interposed in the gap 30 (the height from the opening surface of the gap 30 in the second main surface 4) is one third or more of the depth of the gap 30, preferably 2 minutes. 1 or more, more preferably 2/3 or more.

<Sixth Modification>
As shown in FIG. 14, adjacent crystal pieces 10 do not have to be in contact with each other on the first main surface 3 of the first layer 2. That is, the gap 30 between the adjacent crystal pieces 10 may be open on both the second main surface 4 and the first main surface 3 of the first layer 2. The width G1 of the opening in the first main surface 3 of the first layer 2 is smaller than the width G2 of the opening in the second main surface 4 of the first layer 2. The width G1 of the opening in the first main surface 3 of the first layer 2 is, for example, 0 μm or more and 10 mm or less.

  In the case of the example shown in FIG. 14, the binder 20 fills the gap 30, and the first main surface 11 of the crystal piece 10 and the binder 20 are flush with each other on the first main surface 3 of the first layer 2. ing.

  FIGS. 15 and 16 are schematic plan views of the group III nitride semiconductor substrate 1 of FIG. 14 observed from the first main surface 3 side (from the top to the bottom in the drawing).

<Seventh Modification>
As shown in FIG. 17, when adopting the sixth modification, the gap 30 may not be completely filled with the binder 20. In this case, the height of the binder 20 interposed in the gap 30 (the height from the opening surface of the gap 30 in the second main surface 4) is one third or more of the depth of the gap 30, preferably 2 minutes. 1 or more, more preferably 2/3 or more.

  In the case of the example, on the first main surface 3, the crystal piece 10 and the binder 20 are exposed, the crystal piece 10 is a convex portion, and the binder 20 is a concave portion. The upper limit of the step D between the adjacent crystal piece 10 and the binder 20 can be set to a predetermined value according to the substrate thickness (thickness of the group III nitride semiconductor substrate 1). For example, the step D can be 1 μm or more and (substrate thickness−100) μm or less. That is, when the substrate thickness is 400 μm, the step D is 1 μm to 300 μm, when the substrate thickness is 600 μm, the step D is 1 μm to 500 μm, and when the substrate thickness is 800 μm, the step D is 1 μm to 700 μm. be able to. If it does in this way, the thickness of the binder 20 can be 100 micrometers or more. As a result, the holding power of the plurality of crystal pieces 10 by the binder 20 can be sufficiently increased.

  Next, an example of the manufacturing method of the group III nitride semiconductor substrate 1 of this embodiment is demonstrated using the flowchart of FIG. As shown in the drawing, the method for manufacturing the group III nitride semiconductor substrate 1 of the present embodiment includes a preparation step S10, an arrangement step S20, and a formation step S30.

  In the preparation step S10, a plurality of crystal pieces 10 which are plate-like crystal pieces 10 made of a group III nitride semiconductor and in which at least a part of the side surface 13 forms an angle different from 90 ° with the main surface. Prepare. The “part where the angle with the main surface is different from 90 °” corresponds to the side surface 13 that has been obliquely processed. In the step, a portion of the side surface 13 formed with the first main surface 11 is smaller than 90 ° and the angle formed with the second main surface 12 is larger than 90 ° (the obliquely processed side surface 13). A crystal piece 10 having the above is prepared. Hereinafter, an example of the process will be described.

  For example, a plurality of crystal pieces 10 are prepared by cutting out crystal pieces 10 having a predetermined shape from a group III nitride semiconductor substrate or a fragment of the substrate.

  The means for cutting out is not particularly limited, and the crystal piece 10 may be cut out using a band saw, an inner peripheral blade, an outer peripheral blade or the like, or may be cut out by cleaving at a cleavage plane. In addition, the shape and size of the crystal piece 10 may be adjusted by subjecting the cut crystal piece 10 to a process such as polishing.

  An example of the process of cutting the crystal piece 10 from the group III nitride semiconductor substrate will be described with reference to FIGS. 19 and 20. FIG. 19 is a schematic side view of the group III nitride semiconductor substrate 40, and FIG. 20 is a schematic plan view of the group III nitride semiconductor substrate 40. The group III nitride semiconductor substrate 40 may be a substrate obtained by + c-plane growth as shown, or may be other.

  For example, as shown in FIGS. 19 and 20, a plurality of group III nitride semiconductor substrates 40 are separated from each other by a first cut surface 41 parallel to the m-axis direction and a second cut surface 42 perpendicular to the m-axis direction. The crystal piece 10 may be cut out. By adjusting the distance between each of the first cut surface 41 and the second cut surface 42, the first cut surface 41 or the second cut surface 42 is changed to the first main surface of the crystal piece 10. 11 can be used. The second cut surface 42 is an m-plane. By adjusting the inclination of the first cut surface 41 with respect to the + c-axis direction, the surface orientation of the first main surface 11 can be the a-plane or a desired semipolar plane.

  In this case, the + c plane and the −c plane become the side surface 13. One of the first cut surface 41 and the second cut surface 42 is the side surface 13.

  Next, a process for obliquely processing the side surface 13 will be described. FIG. 21 is a side view of the crystal piece 10 cut out as shown in FIG. 19 observed in the m-axis direction. For example, as shown in FIG. 21, the left side surface 13 in the drawing may be left as it is, and the right side surface 13 in the drawing may be processed as indicated by the dotted line (1) or (2). The inclination of (2) can be adjusted as appropriate.

  In the case of machining with the dotted line (1), the side surface 13 on the left side in the drawing becomes the side surface 13 that is obliquely machined. The right side surface 13 in the drawing is a side surface 13 perpendicular to the first main surface 11. On the other hand, when the processing is performed by the dotted line (2), both the left side surface 13 and the right side surface 13 in the figure become the side surfaces 13 that are obliquely processed.

  FIG. 22 is a side view of the crystal piece 10 of FIG. 21 observed in the left-right direction in the drawing. The two side surfaces 13 may maintain a state perpendicular to the first main surface 11 as illustrated. Or you may perform at least one of the diagonal process in the dotted line of (1), and the diagonal process in the dotted line of (2). By the processing, at least one of the left side surface 13 and the right side surface 13 in the drawing can be made into the obliquely processed side surface 13. Note that the slopes of (1) and (2) can be adjusted as appropriate.

  Another example of the process of cutting the crystal piece 10 from the group III nitride semiconductor substrate will be described with reference to FIGS. FIG. 23 is a schematic side view of the group III nitride semiconductor substrate 40, and FIG. 24 is a schematic plan view of the group III nitride semiconductor substrate 40. The group III nitride semiconductor substrate 40 may be a substrate obtained by + c-plane growth as shown, or may be other.

  For example, as shown in FIGS. 23 and 24, a plurality of groups from the group III nitride semiconductor substrate 40 are formed by a first cut surface 41 parallel to the m-axis direction and a second cut surface 42 perpendicular to the m-axis direction. The crystal piece 10 may be cut out. By adjusting the distance between each of the first cut surface 41 and the second cut surface 42, the exposed surface 43 of the group III nitride semiconductor substrate 40 is used as the first main surface 11 of the crystal piece 10. Can do. In the example shown in FIGS. 23 and 24, the first main surface 11 is a + c plane. The m-plane and the a-plane become the side surface 13.

  In the case of this example, any of the side surfaces 13 has a shape as shown in FIG. By performing the processing as indicated by the dotted line (1) or (2) on at least one side surface 13, the side surface 13 subjected to the oblique processing as described above can be obtained.

  Returning to FIG. 18, in the arranging step S <b> 20, the plurality of crystal pieces 10 are arranged on the mounting table with the gap 30 between them. Specifically, the first main surface 11 is brought into contact with the mounting surface of the mounting table, the second main surface 12 is exposed, and the side surface 13 faces the side surface 13 of the other crystal piece 10. Arrange them side by side on the mounting table. At least one of the opposing side surfaces 13 is a side surface 13 that is obliquely processed. As a result, the width of the gap 30 between the adjacent crystal pieces 10 increases from the contact side in contact with the mounting table toward the exposed side.

  For example, as shown in FIG. 25, a plurality of crystal pieces 10 are arranged side by side on the mounting table 50. The mounting table 50 has a mounting surface 51 on which a plurality of crystal pieces 10 are mounted. The plurality of crystal pieces 10 are arranged on the mounting surface 51 according to, for example, predetermined regularity. Adjacent crystal pieces 10 are in contact with each other on the first main surface 11.

  FIGS. 26 to 28 are schematic plan views when a plurality of crystal pieces 10 are arranged so that adjacent crystal pieces 10 are in contact with each other on the first main surface 11 (FIG. 25 is observed from the top to the bottom in the figure). An example) is shown. In these drawings, a plan view and a side view of the crystal piece 10 are further displayed. FIG. 26 is an example in which crystal pieces 10 in which three side surfaces 13 are obliquely processed are arranged. FIG. 27 shows an example in which crystal pieces 10 in which four side surfaces 13 are obliquely processed are arranged. FIG. 28 is an example in which crystal pieces 10 in which two side surfaces 13 are obliquely processed are arranged.

  FIG. 29 shows another example in which a plurality of crystal pieces 10 are arranged side by side on the mounting table 50. In the example, the adjacent crystal pieces 10 are not in contact with each other on the first main surface 11.

  FIG. 30 shows an example of a schematic plan view of FIG. 29 observed from the top to the bottom in the drawing. On the mounting table 50, there is an adjusting member 53 for aligning the direction in the direction parallel to the first main surface 11 of the crystal piece 10. The adjustment member 53 has an orientation adjustment surface on which the predetermined side surface 13 of the crystal piece 10 is in surface contact or side contact. As shown in FIG. 30, all the crystal pieces 10 are arranged in a “state in which the predetermined side surface 13 is in surface contact or side contact with the orientation adjustment surface of the adjustment member 53”. When arranged in this state, the crystal piece 10 is processed so that the direction parallel to the first main surface 11 is in a desired state.

  According to the arrangement method using the adjusting member 53, it is possible to easily roll the direction in the direction parallel to the first main surface 11 of each of the plurality of crystal pieces 10 into a desired state. As shown in FIG. 30, the crystal pieces 10 adjacent to each other in the direction parallel to the adjustment member 53 do not have to be in contact with each other on the first main surface 11.

  A modification of the arrangement method using the adjustment member 53 will be described with reference to FIG. As shown in FIG. 31, at least a part of the crystal pieces 10 adjacent to each other in the direction parallel to the adjustment member 53 may be in contact with each other on the first main surface 11. However, in the case of the arrangement method using the adjustment member 53, “the predetermined side surface 13 is in surface contact with the orientation adjustment surface of the adjustment member 53 rather than“ contact between the crystal pieces 10 adjacent to each other in the direction parallel to the adjustment member 53 ”. Or, “side contact” is given priority. In the case where the crystal pieces 10 adjacent to each other in the direction parallel to the adjustment member 53 can be brought into contact with each other while ensuring that “the predetermined side surface 13 is in surface contact or side contact with the orientation adjustment surface of the adjustment member 53”, The crystal pieces 10 may be brought into contact with each other. However, for example, in the state where the processing accuracy of the opposite side surface 13 is poor and “the predetermined side surface 13 is in surface contact or side contact with the orientation adjustment surface of the adjustment member 53”, it is adjacent in the direction parallel to the adjustment member 53. When the crystal pieces 10 to be brought into contact with each other cannot be brought into contact with each other, a gap 31 is formed between them as shown in FIG.

  The adjustment member 53 may be removable from the mounting table 50. And if the crystal piece 10 is arrange | positioned in a desired state and it fixes to the position, the adjustment member 53 may be removed from the mounting base 50 before formation process S30. In this case, after the adjustment member 53 is removed, the space where the adjustment member 53 exists becomes the gap 30. The width of the adjustment member 53 is, for example, 50 μm or more and 10 mm or less.

  The adjustment member 53 may be positioned on the mounting table 50 during the formation step S30. In this case, as shown in FIG. 32, the height of the adjustment member 53 is configured to be smaller than the thickness of the crystal piece 10. 32 is an example of a side view of FIGS. 30 and 31 viewed from the left to the right in the drawing. In this case, as illustrated in FIG. 32, a gap 30 having a width of, for example, 50 μm or more and 10 mm or less is formed between the crystal pieces 10 and above the adjustment member 53.

  The means for holding the crystal pieces 10 on the mounting table 50 is not particularly limited. For example, even if a plurality of crystal pieces 10 are bonded and held using an adhesive that does not cause impurity contamination and does not adversely affect the formation of the binder 20. Good. The mounting table 50 may be made of, for example, ceramic.

  Returning to FIG. 18, in the forming step S30, the binder 20 made of a polycrystalline group III nitride semiconductor is formed on the plurality of crystal pieces 10 so as to be interposed in the gaps 30 (see FIGS. 33 and 34). . As shown in FIGS. 33 and 34, the binder 20 is formed on the second main surface 12 while being interposed in the gap 30. As a method for forming the binder 20, a vapor phase epitaxial growth method (for example, HVPE method, MOVPE method), a sodium flux liquid phase growth method, an ammonothermal growth method, a sputtering method, a molecular beam epitaxial growth method, a sintering method, and the like can be considered. .

  The formation conditions can be the same as general conditions. In the present embodiment, the width G2 of the opening of the gap 30 between the crystal pieces 10 is 50 μm or more. For this reason, for example, when a group III nitride semiconductor crystal is formed under the general growth conditions of the HVPE method, the source gas enters the gap 30 and, for example, the binder 20 interposed in the gap 30 is formed.

  After the formation step S30, the group III nitride semiconductor substrate 1 may be removed from the mounting table 50, and then surface processing may be performed by polishing such as CMP and / or etching with a chemical solution. Similarly, the side surface of the group III nitride semiconductor substrate 1 may be processed.

  As described above, the group III nitride semiconductor substrate 1 of the above-described example is obtained. In addition, when embedding of the binder 20 in the gap 30 is insufficient, a state as shown in FIG. 13 is obtained.

  The group III nitride semiconductor substrate 1 of the present embodiment is a free-standing substrate on which electronic devices and optical devices are formed, and a base for obtaining a free-standing substrate by forming a group III nitride semiconductor layer thereon It can be used as a substrate.

  Next, the effect of this embodiment is demonstrated.

  The group III nitride semiconductor substrate 1 of this embodiment is composed of a plurality of crystal pieces 10 as shown in FIGS. There are gaps 30 between the plurality of crystal pieces 10. And the binder 20 exists in the said clearance gap 30 and the crystal piece 10 is hold | maintained. Thus, although the group III nitride semiconductor substrate 1 of this embodiment is comprised by the several crystal piece 10, they are hold | maintained by the binder 20 which exists among each other. That is, the plurality of crystal pieces 10 are in one lump.

  When the plurality of crystal pieces 10 are separated from each other, it is necessary to hold each of the plurality of crystal pieces 10 and move them when moving the substrate made of the plurality of crystal pieces 10. Further, when a substrate made of a plurality of crystal pieces 10 is set at a predetermined position, each of the plurality of crystal pieces 10 needs to be set at a predetermined position with a predetermined positional relationship. Thus, when the several crystal piece 10 is isolate | separated from each other, workability | operativity is bad. In the group III nitride semiconductor substrate 1 of the present embodiment, as described above, the plurality of crystal pieces 10 are bundled together by the binder 20. For this reason, workability at the time of moving the group III nitride semiconductor substrate 1 or setting it to a predetermined position is good.

  Further, if the plurality of crystal pieces 10 remain separated from each other, there is a risk of cracking during the manufacturing process of the substrate made of the plurality of crystal pieces 10 and the handling of the substrate in a subsequent process. In addition, even when the plurality of separated crystal pieces 10 are processed and removed, there is a risk of cracking due to stress concentration on the separated portions. The group III nitride semiconductor substrate 1 of this embodiment can reduce such inconvenience.

  Further, in the group III nitride semiconductor substrate 1 of the present embodiment, as shown in FIGS. 1 to 17, at least one of the side surfaces 13 that face each other between adjacent crystal pieces 10 is a side surface 13 that is obliquely processed. it can. That is, the width of the gap 30 between the crystal pieces 10 can be configured to expand from one main surface (first main surface 3) toward the other main surface (second main surface 4). . In this case, compared to the case where the side surface 13 is perpendicular to the first main surface 11, the area of the inner side surface in the gap 30 between the crystal pieces 10 is increased. As a result, the contact area between the side surface 13 of the crystal piece 10 and the binder 20 is increased, and the bonding force between the crystal piece 10 and the binder 20 is increased.

  Further, in the group III nitride semiconductor substrate 1 of the present embodiment, as shown in FIGS. 1 to 17, the width of the gap 30 between the crystal pieces 10 is from the first main surface 3 of the first layer 2 to the first main surface 3. It can be set as the structure which spreads toward the 2nd main surface 4. FIG. In the group III nitride semiconductor substrate 1 of the present embodiment, the first main surface 3 of the first layer 2 is a growth surface. From the viewpoint of improving the crystallinity of the group III nitride semiconductor formed on the first main surface 3, the exposed area of the binder 20 on the first main surface 3 is preferably small. That is, the opening of the gap 30 in the first main surface 3 is preferably small. On the other hand, from the viewpoint of forming the binder 20 interposed in the gap 30 by allowing the raw material of the binder 20 to enter between the gaps 30, the opening of the gap 30 in the second main surface 4 is preferably large.

  When the width of the gap 30 is substantially the same from the first main surface 3 to the second main surface 4 of the first layer 2, it is difficult to satisfy both of these requirements. In the case of the present embodiment, as described above, the width of the gap 30 between the crystal pieces 10 can be configured to expand from the first main surface 3 to the second main surface 4 of the first layer 2. . For this reason, the two conflicting requirements can be satisfied. That is, the opening of the gap 30 on the first main surface 3 can be reduced, and the exposed area of the binder 20 on the first main surface 3 can be reduced. Moreover, the opening of the gap 30 in the second main surface 4 can be enlarged, and the raw material of the binder 20 can be efficiently infiltrated into the gap 30 to form the binder 20 interposed in the gap 30.

  Note that the group III nitride semiconductor substrate 1 of the present embodiment includes a plurality of crystal pieces 10 so that the side surfaces 13 that are obliquely processed face each other as described with reference to FIG. 7 as the second modification. Can be arranged. In this way, the above-described effect becomes remarkable.

  Further, in the group III nitride semiconductor substrate 1 of the present embodiment, the size of the crystal piece 10 can be controlled to a predetermined size. For example, the main surface (the first main surface 11 and the second main surface 12) of the crystal piece 10 can be a rectangle having a length of 2 mm to 100 mm and a width of 2 mm to 100 mm. When the upper limit of the size of the main surface is set in this way, inconvenience that the crystal piece 10 becomes too large can be suppressed. As a result, the crystal piece 10 is difficult to peel off. Further, when the lower limit of the size of the main surface is set in this way, the size of the main surface can be made large enough to form a device.

  Further, the thickness of the group III nitride semiconductor substrate 10 can be set to 50 μm or more and 20 mm or less. When the lower limit of the thickness is set in this way, the contact area between the binder 20 existing in the gap 30 between the crystal pieces 10 and the side surface 13 of the crystal piece 10 can be sufficiently increased. As a result, the crystal piece 10 can be held with sufficient strength by the binder 20. Further, when the upper limit of the thickness is set in this way, it is possible to avoid the disadvantage that the thickness of the group III nitride semiconductor substrate 1 becomes unnecessarily thick. As a result, the weight and thickness of the group III nitride semiconductor substrate 1 can be reduced, and the workability when carrying the group III nitride semiconductor substrate 1 can be improved, and the space can be saved during storage. The

  In addition, the group III nitride semiconductor substrate 1 of this embodiment uses the 1st main surface 3 as a growth surface. In the case of the configuration shown in FIGS. 1 to 13, the inconvenience that the binder 20 is exposed on the first main surface 3 can be suppressed. As a result, a single crystal of a group III nitride semiconductor with good crystallinity can be grown on the growth surface. The present inventors have confirmed that the crystallinity is slightly inferior to the upper part of the interface between the crystal pieces 10 as compared with other parts.

  On the other hand, in the configuration shown in FIGS. 14 to 17, the binder 20 is exposed on the first main surface 3 (growth surface). When the present inventors have grown a single crystal of a group III nitride semiconductor on such a growth surface, many dislocations are generated above the binder 20, but above the first main surface 11. It was confirmed that the crystallinity was good. That is, according to the group III nitride semiconductor substrate 1 of the present embodiment, an appropriate area on the group III nitride semiconductor substrate 1 (an area above the first main surface 11 having good crystallinity) is selected. Thus, a predetermined device can be formed.

  Moreover, the group III nitride semiconductor substrate 1 of this embodiment can make the shape and magnitude | size of the several crystal piece 10 especially the shape and magnitude | size of the 1st main surface 11 uniform. As described above, when a device is formed on any of the group III nitride semiconductor substrate 1 shown in FIGS. 1 to 13 and the group III nitride semiconductor substrate 1 shown in FIGS. It is preferable to form the device while avoiding the interface and the binder 20. When the shape and size of the first main surface 11 are uniform and the plurality of crystal pieces 10 are regularly arranged as in the present embodiment, the group III nitride semiconductor substrate 1 is based on the regularity. It is possible to easily specify the position at which the first main surface 11 is exposed on the growth surface. As a result, workability during device creation is improved.

  Further, in the group III nitride semiconductor substrate 1 of the present embodiment, the width G2 of the gap 30 between the crystal pieces 10 on the second main surface 4 can be set to 50 μm or more. When the lower limit of the gap 30 is set in this way, the gas used as the raw material of the binder 20 can sufficiently enter the gap 30 during the process of forming the binder 20. As a result, the binder 20 can be formed in the gap 30.

  In addition, as shown in FIGS. 1 to 5, the group III nitride semiconductor substrate 1 of the present embodiment exists such that the binder 20 encloses the plurality of crystal pieces 10 along the outer periphery of the plurality of crystal pieces 10. It can also be configured. According to the said structure, the contact area of the crystal piece 10 and the binder 20 becomes large. As a result, the holding force of the crystal piece 10 by the binder 20 is increased, which is preferable.

  In the group III nitride semiconductor substrate 1 of the present embodiment, as described with reference to FIGS. 8 to 10 as the third modification, the binder 20 does not exist along the outer periphery of the plurality of crystal pieces 10. A configuration that exists only in the gap 30 between the crystal pieces 10 can also be adopted. According to the said structure, the weight reduction and size reduction (surface area size reduction) of the group III nitride semiconductor substrate 1 are implement | achieved. In addition, device yield can be improved, and orientation flat orientation measurement using the side surface of the group III nitride semiconductor substrate 1 can be performed.

  Further, the group III nitride semiconductor substrate 1 of the present embodiment has a configuration in which the binder 20 extends from the gap 30 toward the second main surface 12 as described with reference to FIG. 6 as the first modification. can do. The plurality of crystal pieces 10 can be held by the binder 20 in contact with and closely contacting the crystal pieces 10 on the side surface 13 and the second main surface 12. According to the said structure, the contact area of the crystal piece 10 and the binder 20 becomes large. As a result, the holding force of the crystal piece 10 by the binder 20 is increased, which is preferable.

  In this case, the thickness M of the binder 20 from the second main surface 12 (the thickness of the second layer 5) can be set to 1 mm or more and 20 mm or less. If it does in this way, the intensity | strength of the binder 20 as a backing layer will become enough. As a result, the strength against bending of the group III nitride semiconductor substrate 1 as a whole is increased, and the inconvenience that the group III nitride semiconductor substrate 1 is bent or cracked, the inconvenience of the crystal piece 10 being peeled off from the binder 20, and the like can be suppressed.

  In the group III nitride semiconductor substrate 1 of the present embodiment, the binder 20 does not extend to the first main surface 11 and the second main surface 12 as shown in FIGS. It can be set as the structure which exists only in this. According to this configuration, the group III nitride semiconductor substrate 1 can be reduced in weight and thickness. Further, when manufacturing a device that requires a back electrode, contact between the crystal piece 10 on the back surface side and the electrode is required. In the case of this configuration, it is not necessary to drop the binder 20, or even if the substrate thickness is reduced. The degree of freedom increases.

  Further, in the group III nitride semiconductor substrate 1 of the present embodiment, the height of the binder 20 interposed in the gap 30 (the height from the opening surface of the gap 30 in the second main surface 4) is the depth of the gap 30. Is a state in which the exposed surface of the binder 20 and the first main surface 11 of the crystal piece 10 are flush with each other. It can be. Thus, since the binder 20 can be sufficiently interposed in the gap 30, the contact area between the crystal piece 10 and the binder 20 can be increased. As a result, the adhesive force between the crystal piece 10 and the binder 20 can be further increased.

  Further, as described with reference to FIG. 13 as the fifth modification, the gap 30 may not be completely filled with the binder 20, and a part of the gap 30 may remain as the remaining gap 31.

  Even in such a case, the crystal piece 10 can be held by the binder 20 because at least a part of the side surface 13 is in contact with the binder 20.

  In addition, since a part of the gap 30 may be left as the remaining gap 31, it is not necessary to devise intrusion of the gas that is the raw material of the binder 20 at the back of the gap 30. As a result, the degree of freedom in designing the process for forming the binder 20 is widened as compared to the case where the binder 20 is completely interposed to the back of the gap 30.

  Further, the exposure of the binder 20 on the first main surface 3 is reduced, and the effect of increasing the distance from the first main surface to the binder 20 is obtained. For this reason, when forming the group III nitride semiconductor single crystal on the first main surface 3 of the group III nitride semiconductor substrate 1, the disadvantage that the crystallinity of the single crystal deteriorates due to the binder 20 can be reduced. .

  In addition, as described with reference to FIGS. 11 and 12 as the fourth modification, at least a part of the side surface 13 of the crystal piece 10 is a first portion that is perpendicular to the first main surface 11. 13-1 and a second portion 13-2 that is obliquely processed, and is processed so that these two portions appear in this order from the first main surface 11 to the second main surface 12. May be. In the case of this example, the exposure of the binder 20 on the first main surface 3 of the group III nitride semiconductor substrate 1 is reduced, and further, the distance from the first main surface to the binder 20 is increased. For this reason, when forming the group III nitride semiconductor single crystal on the first main surface 3 of the group III nitride semiconductor substrate 1, the disadvantage that the crystallinity of the single crystal deteriorates due to the binder 20 can be reduced. .

  Further, in the manufacturing method of the group III nitride semiconductor substrate 1 of the present embodiment, as in the example described with reference to FIGS. 30 to 32, all the crystal pieces 10 are “adjusted with the side surface 13 having a predetermined plane orientation. It can arrange | position so that it may be in the state which contacts the member 53 or a surface contact. Thereby, the direction of the direction parallel to the 1st main surface 11 of each of the some crystal piece 10 will be in a desired state. The group III nitride semiconductor substrate 1 of the present embodiment manufactured by such a manufacturing method has a surface in which a plurality of crystal pieces 10 are not in contact with other crystal pieces 10 (surface contact or side contact with the adjustment member 53). The side surface 13) is provided.

  By the way, as a method of arranging a plurality of crystal pieces 10 side by side, a method of arranging adjacent crystal pieces 10 in contact with each other is conceivable. In the case of placing with priority on reducing the gap between the crystal pieces 10, the placement method is preferable. However, in the case of this method, the orientation of a certain crystal piece 10 in the direction parallel to the first main surface 11 depends on the state of the other crystal piece 10 (the orientation of the other crystal piece 10, the direction of the side surface of the other crystal piece 10). Accuracy). For this reason, it is necessary to sufficiently increase the processing accuracy on the side surface 13 of the crystal piece 10. The above effect will be described with reference to FIG.

  An arrow A shown in FIG. 35 is a predetermined axial direction of the crystal piece 10 (example: m-axis direction). The desired arrangement state is a state in which a predetermined axial direction (eg, m-axis direction) of the crystal piece 10 is parallel to the first direction.

  In the left crystal piece 10 shown in FIG. 35, the predetermined axial direction indicated by the arrow A is parallel to the first direction. However, in the crystal piece 10 on the right side, the predetermined axial direction indicated by the arrow A is not parallel to the first direction. This is due to the fact that the processing accuracy of the right side surface of the left crystal piece 10 is inferior and is cut slightly diagonally, and that the side surface of the right crystal piece 10 is placed in contact with the side surface.

  As described above, when arranging a plurality of crystal pieces 10 in a state where the side surfaces are in contact with each other, when the orientation of the crystal pieces 10 is deviated at a certain location, Due to the presence of processing accuracy such as perpendicularity, the state of other crystal pieces 10 is affected. Furthermore, as the number of the crystal pieces 10 increases, the number of contact portions increases, and the influence of the state of the crystal pieces 10 is accumulated, so that the possibility that the misalignment increases is increased. As a result, there are many crystal pieces 10 whose orientation in the direction parallel to the first main surface 11 is deviated from a desired state.

  In the case of the present embodiment, all the crystal pieces 10 can be arranged in a “state in which the side surface 13 of a predetermined surface orientation is in surface contact or side contact with the orientation adjustment surface of the adjustment member 53”. For this reason, the above inconveniences can be avoided. As a result, the orientation accuracy in the direction parallel to the first main surface 11 of the plurality of crystal pieces 10 can be easily realized to be ± 0.5 ° or less. According to the group III nitride semiconductor substrate 1 having such orientation accuracy, the crystallinity of the group III nitride semiconductor grown on the group III nitride semiconductor substrate 1 is improved.

  In the present embodiment, the binder 20 can be composed of a polycrystalline group III nitride semiconductor. In this case, the binder 20 having a desired thickness can be formed in a shorter time compared to the case where the binder 20 is formed of a single crystal group III nitride semiconductor.

  In the case of this embodiment, the crystal piece 10 can be cut out from a single crystal group III nitride semiconductor fragment or the like. Such debris has been conventionally discarded. According to the present embodiment, it is possible to use debris that has been conventionally discarded, which is advantageous in terms of cost.

  Further, the group III nitride semiconductor substrate 1 of the present embodiment is formed on the first main surface 3 (growth surface) of the group III nitride semiconductor substrate 1 as described with reference to FIG. 17 as the seventh modification. The crystal piece 10 may be a convex portion and the binder 20 may be a concave portion. In this case, the binder 20 is exposed on the first main surface 3 (growth surface) of the group III nitride semiconductor substrate 1, but the adverse effect of the binder 20 can be reduced. That is, when a single crystal group III nitride semiconductor is epitaxially grown on the growth surface, it is possible to reduce the occurrence of inconvenience such as abnormal growth at the interface between the crystal piece 10 and the binder 20. For example, even if a polycrystal is formed in the recess during the growth process, the polycrystal is prevented from protruding upward from the projection. As a result, the influence on the lithography process at the time of device fabrication is reduced. Further, the crystals grown from each of the two convex portions adjacent to each other across the concave portion are joined to each other in a state of covering the crystal grown from the concave portion between each other. As a result, the crystal grown from the convex portion is covered with the crystal grown from the concave portion. For this reason, the disadvantage that the crystal grown from the recess appears on the growth surface can be reduced. That is, it is possible to reduce the inconvenience that a crystal grown from a polycrystalline group III nitride semiconductor (binder 20) appears on the growth surface.

  In the case of the seventh modification, in the group III nitride semiconductor substrate 1 of this embodiment, the step D between the adjacent crystal piece 10 and the binder 20 is 1 μm or more (substrate thickness (μm) −100 (μm)). It can be set to μm or less. By setting the step D to be 1 μm or more, it is possible to suppress the above-described polycrystal on the concave portion from protruding from the convex portion, or to obtain a state where the crystal grown from the convex portion covers the crystal grown from the concave portion. It becomes easy. Moreover, the thickness of the binder 20 can be 100 micrometers or more by making the level | step difference D into (board | substrate thickness -100) micrometers or less. As a result, it is possible to obtain effects such as preventing substrate breakage during handling and suppressing crystal fragments from being divided when reducing the substrate thickness during device fabrication.

<< Second Embodiment >>
FIG. 39 is a flowchart showing a process flow of the method for manufacturing the group III nitride semiconductor substrate 1 of the present embodiment. As shown in the drawing, it has a preparation step S10, an arrangement step S20, a formation step S30, and an exposure step S40.

  The preparation step S10 is the same as the preparation step S10 described in the first embodiment.

  For example, as shown in FIGS. 23 and 24, from the group III nitride semiconductor substrate 40 grown in the + c plane, a first cut surface 41 parallel to the m-axis direction and parallel to the + c-axis direction, and in the m-axis direction The plurality of crystal pieces 10 may be cut out from the group III nitride semiconductor substrate 40 by the vertical second cut surface 42. By appropriately adjusting the distance between the first cut surface 41 and the second cut surface 42, the exposed surface 43 of the group III nitride semiconductor substrate 40 can be used as the first main surface 11 of the crystal piece 10. .

  In the arranging step S20, as shown in FIG. 36, the plurality of crystal pieces 10 are arranged side by side on the holding member 60 in the horizontal direction (in the drawing, the left-right direction and the direction perpendicular to the paper surface). At this time, the plurality of crystal pieces 10 are arranged so that a predetermined axial direction of each of the plurality of crystal pieces 10 is perpendicular to the lateral direction.

  The predetermined axial direction is determined according to a desired plane orientation as a growth plane of the group III nitride semiconductor substrate 1. When the growth surface of group III nitride semiconductor substrate 1 is the + c plane, the predetermined axis direction is the + c axis direction. When the growth surface of group III nitride semiconductor substrate 1 is the m-plane, the predetermined axial direction is the m-axis direction. When the growth surface of group III nitride semiconductor substrate 1 is the a-plane, the predetermined axial direction is the a-axis direction. When the growth surface of group III nitride semiconductor substrate 1 is a predetermined semipolar surface, the predetermined axial direction is an axial direction perpendicular to the predetermined semipolar surface.

  For example, the crystal pieces 10 can be arranged as shown in FIG. The vertical direction in FIG. 36 is the thickness direction of group III nitride semiconductor substrate 1. The plurality of crystal pieces 10 are arranged so that the above-described predetermined axial direction is parallel to the thickness direction of the crystal piece layer. For example, as shown in FIG. 36, such an arrangement may be realized by using a holding member 50 that allows a plurality of crystal pieces 10 to be arranged at a predetermined angle. The holding member 50 shown in the figure has wavy unevenness on the mounting surface on which the crystal piece 10 is mounted. And the crystal piece 10 is arrange | positioned so that it may fit in this recessed part. By appropriately adjusting the angle, depth, and the like of the side surface of the recess, the plurality of crystal pieces 10 can be arranged side by side at a predetermined angle. In FIG. 36, adjacent crystal pieces 10 are not in contact, but adjacent crystal pieces 10 may be in contact.

  In the forming step S <b> 30, the binder 20 is formed on the plurality of crystal pieces 10 so as to be interposed in the gaps between the crystal pieces 10. The configuration of the forming step S30 is the same as that in the first embodiment. When the binder 20 is formed on the plurality of crystal pieces 10 in the state shown in FIG. 36, for example, the state shown in FIG. 37 is obtained.

  In the exposure step S <b> 40, the exposed surface side (surface opposite to the surface on which the binder 20 is formed) of the crystal piece layer is polished to expose a desired surface from the plurality of crystal pieces 10. The desired surface is a surface to be used as a growth surface of the group III nitride semiconductor substrate 1. As described above, the plurality of crystal pieces 10 are arranged side by side in the lateral direction (in FIG. 37, the left-right direction and the direction perpendicular to the paper surface), and the predetermined axial direction determined according to the desired plane is , And perpendicular to the lateral direction (the direction in which the plurality of crystal pieces 10 extend). For this reason, when a plurality of crystal pieces 10 are polished with a polishing surface parallel to the lateral direction, a desired surface is exposed.

  For example, after the state shown in FIG. 37 is obtained, the stacked body including the plurality of crystal pieces 10 and the binder 20 is removed from the holding member 60. Then, polishing (CMP or the like) is performed from the surface where the crystal piece 10 is exposed (the exposed surface on the lower side of FIG. 37) on the polishing surface perpendicular to the thickness direction of the stacked body. Thereby, a desired surface can be exposed on the surface where the crystal piece 10 is exposed (the lower exposed surface in FIG. 37). As a result, a group III nitride semiconductor substrate 1 as shown in FIG. 38 is obtained. FIG. 36 is a schematic cross-sectional view of group III nitride semiconductor substrate 1.

  Note that the opposite exposed surface (upper surface in FIG. 37) and side surfaces of the laminate may be further polished.

  According to the present embodiment described above, the same operational effects as those of the first embodiment can be realized. That is, the group III nitride semiconductor substrate 1 that achieves the same effects as those of the first embodiment can be realized by a manufacturing method different from that of the first embodiment. As a result, variations in the manufacturing method increase.

Hereinafter, examples of the reference form will be added.
1. A plurality of group III nitride semiconductor crystal pieces arranged with a gap between each other; and
A binder interposed in the gap and holding a plurality of the crystal pieces;
A plate-like first layer comprising:
The group III nitride semiconductor substrate, wherein the gap is widened from the first main surface to the second main surface of the first layer.
2. In the group III nitride semiconductor substrate according to 1,
The adjacent crystal pieces are in contact with each other on the first main surface and are not in contact with each other on the second main surface.
3. In the group III nitride semiconductor substrate according to 1,
The group III nitride semiconductor substrate in which the plurality of crystal pieces do not contact other crystal pieces.
4). In the group III nitride semiconductor substrate according to 3,
The plurality of crystal pieces are group III nitride semiconductor substrates having an orientation accuracy of ± 0.5 ° or less in a direction parallel to the first main surface.
5. In the group III nitride semiconductor substrate according to 3 or 4,
A group III nitride semiconductor substrate in which the crystal piece and the binder are exposed on the first main surface, the crystal piece is a convex portion, and the binder is a concave portion.
6). In the group III nitride semiconductor substrate according to 5,
A group III nitride semiconductor substrate in which a step between the adjacent crystal piece and the binder is 1 μm or more (thickness of group III nitride semiconductor substrate (μm) −100 (μm)) μm or less.
7). In the group III nitride semiconductor substrate according to any one of 1 to 6,
The group III nitride semiconductor substrate, wherein the binder extends from the gap to the second main surface.
8). In the group III nitride semiconductor substrate according to any one of 1 to 7,
A group III nitride semiconductor substrate in which the first main surface serves as a growth surface for growing a group III nitride semiconductor crystal.
9. In the group III nitride semiconductor substrate according to any one of 1 to 8,
The binder is a group III nitride semiconductor substrate composed of a polycrystalline group III nitride semiconductor.
10. A preparation step of preparing a plurality of crystal pieces, each of which is a plate-like crystal piece made of a group III nitride semiconductor, and at least a part of the side surface is different from an angle formed by 90 ° with the main surface;
An arrangement step of arranging a plurality of the crystal pieces with a gap between each other on the mounting table;
Forming a binder that is interposed in the gap and holds the plurality of crystal pieces; and
Have
The method of manufacturing a group III nitride semiconductor substrate, wherein in the arranging step, the side surfaces are opposed to each other, and the crystal pieces are arranged so that the width of the gap increases from the contact side contacting the mounting table to the exposed side.

DESCRIPTION OF SYMBOLS 1 III group nitride semiconductor substrate 2 1st layer 3 1st main surface 4 2nd main surface 5 2nd layer 10 Crystal piece 11 1st main surface 12 2nd main surface 13 Side surface 13-1 1st 1 part 13-2 second part 20 binder 30 gap 31 gap 40 group III nitride semiconductor substrate 41 first cut surface 42 second cut surface 43 exposed surface 50 holding member 51 mounting surface 52 hole 53 adjusting member 60 Holding member

Claims (10)

A plurality of group III nitride semiconductor crystal pieces arranged with a gap between each other; and
A binder interposed in the gap and holding a plurality of the crystal pieces;
A plate-like first layer comprising:
The group III nitride semiconductor substrate, wherein the gap is widened from the first main surface to the second main surface of the first layer. In the group III nitride semiconductor substrate according to claim 1,
The adjacent crystal pieces are in contact with each other on the first main surface and are not in contact with each other on the second main surface. In the group III nitride semiconductor substrate according to claim 1,
The group III nitride semiconductor substrate in which the plurality of crystal pieces do not contact other crystal pieces. In the group III nitride semiconductor substrate according to claim 3,
The plurality of crystal pieces are group III nitride semiconductor substrates having an orientation accuracy of ± 0.5 ° or less in a direction parallel to the first main surface. In the group III nitride semiconductor substrate according to claim 3 or 4,
A group III nitride semiconductor substrate in which the crystal piece and the binder are exposed on the first main surface, the crystal piece is a convex portion, and the binder is a concave portion. In the group III nitride semiconductor substrate according to claim 5,
A group III nitride semiconductor substrate in which a step between the adjacent crystal piece and the binder is 1 μm or more (thickness of group III nitride semiconductor substrate (μm) −100 (μm)) μm or less. In the group III nitride semiconductor substrate according to any one of claims 1 to 6,
The group III nitride semiconductor substrate, wherein the binder extends from the gap to the second main surface. In the group III nitride semiconductor substrate according to any one of claims 1 to 7,
A group III nitride semiconductor substrate in which the first main surface serves as a growth surface for growing a group III nitride semiconductor crystal. In the group III nitride semiconductor substrate according to any one of claims 1 to 8,
The binder is a group III nitride semiconductor substrate composed of a polycrystalline group III nitride semiconductor. A preparation step of preparing a plurality of crystal pieces, each of which is a plate-like crystal piece made of a group III nitride semiconductor, and at least a part of the side surface is different from an angle formed by 90 ° with the main surface;
An arrangement step of arranging a plurality of the crystal pieces with a gap between each other on the mounting table;
Forming a binder that is interposed in the gap and holds the plurality of crystal pieces; and
Have
The method of manufacturing a group III nitride semiconductor substrate, wherein in the arranging step, the side surfaces are opposed to each other, and the crystal pieces are arranged so that the width of the gap increases from the contact side contacting the mounting table to the exposed side.

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