JP4915128B2 - Nitride semiconductor wafer and method for manufacturing the same - Google Patents

Description

  The present invention relates to a nitride semiconductor wafer for forming a nitride semiconductor element made of a III-V nitride semiconductor, and more particularly to a nitride semiconductor wafer excellent in crystal quality and mass productivity and a method for manufacturing the same.

  Group III-V nitride semiconductors are used in various electronic devices such as green to ultraviolet and white light emitting diodes, green to ultraviolet laser diodes, photodiodes, and HEMTs.

Conventional electronic devices using nitride semiconductors are generally fabricated on different types of wafers, such as sapphire or silicon carbide, different from the nitride semiconductor layer to be deposited. In the most commonly used metal organic chemical vapor deposition method (hereinafter referred to as “MOCVD method”), GaN is vapor grown from ammonia and a metal organic compound, but a bulk single crystal layer cannot be formed. In addition, the number of dislocations per unit area is reduced by using the buffer layer. However, this method can only reduce the number of dislocations to about 10 ⁸ / cm ² .

Therefore, recently, a lateral growth method has been used to reduce the defect density of the nitride semiconductor layer (for example, Patent Document 1). In this method, a GaN layer is grown on a sapphire wafer, and linear or reticulated SiO ₂ is further deposited thereon. By performing GaN lateral growth on the substrate thus prepared, the dislocation density of GaN is suppressed to about 10 ⁷ / cm ² or less.

  In electronic devices using nitride semiconductors, basic characteristics including element lifetime are greatly affected by dislocations and stresses present in the semiconductor layer. However, as long as heteroepitaxial growth using a heterogeneous wafer such as sapphire is performed, there is a limit to the reduction of dislocations and stress. Therefore, an attempt has been made to fabricate a nitride semiconductor wafer capable of homoepitaxial growth instead of a heterogeneous wafer such as sapphire.

  For example, after a GaN layer having a low dislocation density is formed by a lateral growth method, the GaN layer is further grown to a thick film by a halide vapor phase growth method (hereinafter referred to as “HVPE method”), and then the sapphire wafer is removed. A wafer made of GaN single crystal can be obtained (Patent Document 2).

  Various studies have also been made on directly growing GaN single crystals. For example, in the HNP method (Non-Patent Document 1), crystals are grown in dissolved gallium, that is, in a liquid phase, and a GaN crystal of about 10 mm is generated. In order to dissolve sufficient nitrogen in gallium, it is necessary to set the temperature to 1500 ° C. and the nitrogen pressure to 15 kbar. On the other hand, the use of supercritical ammonia has also been proposed as a method for growing a GaN single crystal at a relatively low temperature and low pressure (Non-patent Documents 2, 3, etc.).

  Further, Patent Document 3 proposes that a GaN single crystal ingot is sliced on a plane parallel to the growth direction to form a wafer. Specifically, first, a GaN ingot having a thickness of several centimeters is produced by c-axis growth of GaN on a GaAs substrate using a lateral growth method. A GaN seed crystal having a C plane, an M plane, and an A plane is formed from the GaN ingot. Then, from a GaN single crystal grown on each GaN seed crystal by c-axis, m-axis, or a-axis, a plane parallel to the growth direction (A-plane or M-plane for c-axis growth, m-axis growth for m-axis growth) A GaN single crystal wafer is manufactured by slicing into A plane or C plane, or M plane or C plane in the case of a-axis growth. This method is intended to obtain a GaN single crystal wafer having a low dislocation density by utilizing dislocations running parallel to the growth direction.

JP 11-43398 A Japanese Patent Laid-Open No. 10-312971 JP 2002-29897 A JP-T-2004-533391 “Prospects for high-pressure crystal growth of III-V nitrides” S, Porowski et al., Inst.Phys.Conf.Series, 137, 369 (1998) “Ammono method of BN, AlN, and GaN synthesis and crystal growth” R. Dwilinski et al., Proc. EGW-3, Warsaw, June 22-24, 1998, MRS Internet Journal of Nitride Semiconductor Research “Crystal Growth of gallium nitride in supercritical ammonia” J. W. Kolis et al., J. Cryst. Growth 222, 431-434 (2001)

  However, in the conventional nitride semiconductor wafer manufacturing method, it has been difficult to achieve both a sufficiently low dislocation density and a wide wafer area.

For example, if a nitride semiconductor wafer is manufactured by the lateral growth method and the exfoliation of a heterogeneous substrate as in Patent Document 2, a nitride semiconductor wafer having a large area can be obtained as in the case of a conventional heterogeneous wafer. However, dislocations on the SiO ₂ mask are reduced in the course of the lateral growth method, but dislocations generated at the interface with the different wafer remain in the openings of the SiO ₂ masks. Therefore, a region having a high dislocation density locally remains in the wafer.

  In addition, the HNP method of Non-Patent Document 1 and the growth method using supercritical ammonia of Non-Patent Document 2 or 3 can obtain a GaN single crystal having a low dislocation density, but it has an inch-size like a conventional heterogeneous wafer. It is difficult to manufacture a wafer with high productivity.

  Furthermore, according to the method of Patent Document 3, it is theoretically possible to manufacture a nitride semiconductor wafer having a low dislocation density over the entire surface and an inch size. However, in order to manufacture an inch-size wafer by the method of Patent Document 3, it is necessary to grow a GaN single crystal to a thickness of at least several centimeters. However, with the current vapor phase growth technique, various problems occur when attempting to grow a GaN single crystal to a thickness of several centimeters or more. For example, when attempting to grow a GaN single crystal by a general HVPE method, if vapor phase growth is continued for a long time, adhesion of Ga metal occurs in the vapor phase growth apparatus, and the flow rate balance of the source gas is disturbed. It becomes easy. In addition, since the GaN seed crystal is originally heteroepitaxially grown from a different wafer, strain generated at the interface with the different wafer remains in the crystal. In addition, the influence of the stress due to the strain increases as the thickness of the GaN single crystal increases. Therefore, when a GaN single crystal is grown to a thickness of several centimeters or more, a morphology abnormality or a crystal defect is likely to occur.

  Accordingly, an object of the present invention is to provide a nitride semiconductor wafer capable of achieving both a low dislocation density and a wide wafer area, and a method for manufacturing the same.

The method of manufacturing a nitride semiconductor wafer according to the present invention is as follows:
(A) a step of obtaining a primary wafer comprising a hexagonal nitride semiconductor and two opposing principal surfaces each comprising a C-plane;
(B) cutting the primary wafer along the M-plane to obtain a plurality of nitride semiconductor bars;
(C) arranging the plurality of nitride semiconductor bars such that the C surfaces of adjacent nitride semiconductor bars face each other and the M surface of each nitride semiconductor bar is an upper surface;
(D) forming a nitride semiconductor layer having a continuous M-plane as a main surface by regrowth of a nitride semiconductor on the upper surface of the arranged nitride semiconductor bars;
It has.

  In the present invention, the term “x-axis growth” (x is c, m, a, etc.) means that the principal plane of the crystal to be grown is the X plane (X is C, M, A, etc.). This refers to crystal growth, and the growth method may be growth through a buffer layer or so-called lateral growth. A “wafer” refers to a plate-like substrate for forming a semiconductor element. The “wafer” is not limited to a circle, and can take various shapes such as a rectangle. The “main surface” of the wafer refers to two surfaces (upper surface or lower surface) having the widest area of the wafer having a plate shape.

  The nitride semiconductor wafer manufactured according to the present invention has a low dislocation density and a sufficiently large area for manufacturing a nitride semiconductor element. In other words, in the present invention, since nitride semiconductor bars are cut out from the primary wafer, and are rearranged after the nitride semiconductor bars are arranged, the primary wafer may be grown with a film thickness sufficient to maintain good crystallinity. In addition, since dislocations extend in parallel with the M plane in the nitride semiconductor bar serving as the foundation of the regrown layer, there are few threading dislocations proceeding toward the upper surface (M plane) of the nitride semiconductor bar. Furthermore, even when the nitride semiconductor bar 6 is regrowth after arranging the nitride semiconductor bars, the individual nitride semiconductor bars are separated from each other, so that an increase in stress is suppressed even if the area of the wafer is increased. Is done. Therefore, if the number of nitride semiconductor bars arranged is increased, the area of the nitride semiconductor wafer can be easily increased without lowering the crystallinity.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Embodiment 1. FIG.
FIG. 1 shows a hexagonal nitride semiconductor represented by the general formula Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). It is a schematic diagram which shows the primary wafer 2 formed by axial growth. The primary wafer 2 can be produced, for example, by growing a nitride semiconductor on a different type of wafer different from a nitride semiconductor such as sapphire, SiC, silicon, GaAs, etc., and then removing the different type of wafer. The primary wafer 2 desirably has a thickness of 200 μm or more and 5 mm or less, preferably 1 mm or less so that the nitride semiconductor can be grown with a good crystal.

Further, as shown in FIG. 1, the primary wafer 2 has two main surfaces composed of a C plane, one main surface being a C ⁺ plane and the other main surface being a C ^- plane. In this specification, an N-terminated C-plane (= (000-1) plane) is referred to as a “C ^- plane”, and a Ga-terminated (or terminated with other metal element) C-plane (= (0001 plane)) referred to as "C ⁺ plane". for example, when a nitride semiconductor is GaN, the growth surface when grown c-axis on the heterogeneous wafer such as a sapphire C plane becomes Ga termination, removal surface after removal of the sapphire substrate Is known to be N-terminated.

  In the present embodiment, the primary wafer 2 shown in FIG. 1 is sliced into strips along a certain M plane, and the nitride semiconductor bar 4 is cut out. In the hexagonal nitride semiconductor crystal, the (1-100) plane, (10-10) plane, (01-10) plane, (-1100) plane, (-1010) plane, There are six planes called (0-110) plane, and these are collectively referred to as M plane (= {1-100} plane). Six M-planes can be arranged to form six sides of a regular hexagon (adjacent M-planes form an angle of 120 degrees). The M plane for cutting out the nitride semiconductor bar 4 from the primary wafer 2 is any one M plane, which may be any of the above six M planes.

FIG. 2 is a perspective view schematically showing the cut-out nitride semiconductor bar 4. The plurality of nitride semiconductor bars 4 cut out in a strip shape along the M-plane have a substantially quadrangular prism shape and have two sets of side surfaces facing each other. One set of side faces consists of M planes, and the other set of side faces consists of C planes (C ⁺ plane and C ⁻ plane). In general, dislocations in a nitride semiconductor grown by c-axis proceed in the crystal growth direction, that is, in the c-axis direction. For this reason, dislocations extend in a plane parallel to the M plane inside the cut-out nitride semiconductor bar 4. The “side surfaces” of the nitride semiconductor bar 4 refer to the four surfaces having the widest area of the bar having a substantially quadrangular prism shape. The nitride semiconductor bar 4 can be used as a support for growing a nitride semiconductor wafer. Examples of this growth method include a vapor phase growth method and a growth method in which a nitride dissolved in a nitrogen-containing solvent in a supercritical state is crystallized.

  As shown in FIG. 3, the nitride semiconductor bars 4 are arranged in parallel to each other so that one M-plane is an upper surface. In the present embodiment, the nitride semiconductor bars 4 are arranged so as to be in close contact with each other on the C planes.

  If a nitride semiconductor layer is regrown on the upper surface of the arranged nitride semiconductor bars 4, as shown in FIG. 4, the nitride semiconductor having the M plane as the main surface on the arrangement of the nitride semiconductor bars 4 is provided. A layer 6 (hereinafter sometimes referred to as “regrowth layer 6”) is obtained. In this way, a nitride semiconductor wafer 8 having the M surface as the main surface is obtained. The nitride semiconductor wafer 8 may be used as it is, or only the upper layer portion having good crystallinity may be cut out by an appropriate means such as a wire saw.

  The nitride semiconductor wafer 8 has a low dislocation density and a sufficiently large area for manufacturing a nitride semiconductor element. That is, the nitride semiconductor bar 4 is originally cut from the primary wafer 2, and the primary wafer 2 is grown with a film thickness sufficient to maintain good crystallinity. Therefore, the crystallinity of the nitride semiconductor bar 4 is good, and the crystallinity of the nitride semiconductor layer 6 regrown thereon is also good. In addition, since the dislocations 40 extend in parallel with the M plane in the nitride semiconductor bar 4 serving as the foundation of the regrown layer 6, most of the threading dislocations proceed toward the upper surface (M plane) of the nitride semiconductor bar 4. not exist. Therefore, the nitride semiconductor layer 6 regrowth on the upper surface of the nitride semiconductor bar 4 has an extremely low dislocation density as compared with the nitride semiconductor bar 4. In addition, if the number of nitride semiconductor bars 4 arranged is increased, the area of the nitride semiconductor wafer 8 can be easily increased without lowering the crystallinity.

  The nitride semiconductor wafer 8 formed in this way is also advantageous in terms of strain stress. That is, generally, a nitride semiconductor layer grown on a different type of wafer contains stress due to a lattice mismatch difference or a thermal expansion coefficient difference with the different type wafer. Since this stress does not completely disappear after the removal of the dissimilar wafer, a certain stress is also inherent in the primary wafer 2. The stress inherent in the primary wafer becomes more prominent as the area of the primary wafer 2 increases. In the present embodiment, the primary wafer 2 is divided into appropriate widths to form the nitride semiconductor bars 2, so that the stress inherent in each nitride semiconductor bar 2 is reduced. Moreover, when the nitride semiconductor bar 2 is arranged and the nitride semiconductor layer 6 is regrown, the increase in stress is suppressed by the separation of the individual nitride semiconductor bars 2 from each other.

  Furthermore, nitride semiconductor wafer 8 of the present embodiment is advantageous in comparison with a conventional wafer having a C-plane as a main surface in that the main surface is an M-plane. That is, as described above, the C plane has two polarities depending on the configuration of the crystal end face, and the polarities can cause distortion in the nitride semiconductor device. For example, when an InGaN layer is used as an active layer in a c-axis oriented nitride semiconductor, there is a problem that the light emission efficiency decreases as the emission wavelength increases from the ultraviolet region. This is presumably because electron-hole pairs are spatially separated by spontaneous polarization or a piezoelectric field generated in the active layer. Therefore, if a nitride semiconductor wafer having a nonpolar growth surface is produced, the occurrence of a polarization electric field in the growth axis direction of the active layer is suppressed, and the probability of luminescent recombination is improved. The M-plane of the nitride semiconductor does not have a polarity like the C-plane. Therefore, by using the nitride semiconductor wafer 8 having the M-plane as the main surface as in the present embodiment, it is possible to form an excellent nitride semiconductor element with high light emission efficiency.

  The nitride semiconductor wafer 8 of the present embodiment requires many steps for the initial production, but can be easily duplicated once produced. That is, as shown in FIG. 5, if a nitride semiconductor is grown using the nitride semiconductor wafer 8 manufactured by the above method as a substrate, a nitride semiconductor layer having the same crystallinity can be easily grown. . Then, new nitride semiconductor wafers 8 'and 8' 'can be obtained by slicing the grown wafer parallel to the main surface. For example, if a nitride semiconductor is grown on the nitride semiconductor wafer 8 to a thickness of about 2 mm and sliced with a wire saw to a thickness of 400 μm, 4 to 5 nitride semiconductor wafers 8 can be replicated at once. Therefore, a nitride semiconductor wafer having a low dislocation and a large area can be manufactured at a low cost and with a high throughput.

Hereinafter, each manufacturing step of nitride semiconductor wafer 8 in the present embodiment will be described in detail.
1. Production of Primary Wafer 2 The primary wafer 2 may be produced by any method as long as it is a wafer made of c-axis grown hexagonal nitride semiconductor. The hexagonal nitride semiconductor constituting the primary wafer 2 is not particularly limited, but Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). More preferably, it is desirable to use Al _x Ga _1-x N (0 ≦ x ≦ 1), and most preferably gallium nitride.

  Further, if the thickness of the primary wafer 2 is too thin, the number of connecting surfaces between the bars increases when the cut-out nitride semiconductor bars 4 are arranged, which is not preferable. If the primary wafer 2 is too thin, the process of polishing the M surface of the nitride semiconductor bar 4 becomes difficult. Therefore, it is desirable that the film thickness of the primary wafer 2 is 200 μm or more, preferably 500 μm or more. On the other hand, if the film thickness of the primary wafer 2 is too large, the crystallinity of the primary wafer 2 tends to be lowered, and the stress in the primary wafer 2 tends to increase. Therefore, the film thickness of the primary wafer 2 is desirably 3 mm or less, preferably 1 mm or less.

  The width of the main surface of the primary wafer 2 is not particularly limited as long as the nitride semiconductor bar 4 having an appropriate size can be cut out. That is, since the width of the nitride semiconductor wafer 8 to be finally produced can be adjusted by the number of nitride semiconductor bars 4 to be arranged, the width of the nitride semiconductor wafer 8 is the width of the main surface of the primary wafer 2. Not directly constrained. Therefore, the main surface of the primary wafer 2 may be narrower than the main surface of the nitride semiconductor wafer 8 to be finally produced. Further, the primary wafer 2 may have any shape such as a circle and a rectangle, and may be an elongated rectangle. In particular, when the primary wafer 2 is an elongated rectangle, a longer nitride semiconductor bar 4 can be obtained by cutting the nitride semiconductor bar 4 along the M plane along the longitudinal direction thereof.

  If the maximum diameter of the main surface of the primary wafer 2 is too small, the length of the nitride semiconductor bar 4 that can be cut out becomes short, and when trying to obtain the nitride semiconductor wafer 8 with a large area, the nitride semiconductor bar The number of arrangements of 4 increases. Therefore, the main surface of the primary wafer 2 preferably has a maximum diameter of at least 10 mm or more, more preferably 1 inch or more. Further, if the minimum diameter of the main surface of the primary wafer 2 is too small, the side surface made of the C-plane of the square pillar nitride semiconductor bar 4 becomes narrow and the mechanical strength of the nitride semiconductor bar 4 decreases, which is not preferable. Therefore, it is desirable that the main surface of the primary wafer 2 has a minimum diameter of at least 10 mm or more, more preferably 1 inch or more.

Further, the primary wafer 2 may have an off-angle formed on the C surface which is the main surface. Since the C-plane has an off angle, there is an advantage that the crystallinity of the primary wafer 2 is improved. However, if the off angle is too large, a problem of step bunching occurs. Therefore, the off angle is preferably 1 ° or less, preferably 0.2 ° or less, and more preferably 0.05 ° or less. Here, the off angle of the surface can be considered in three directions. For example, as shown in FIG. 20, in the case of the M plane, there are three off angles: a twist angle α around the m axis, a tilt angle β with respect to the c axis, and a tilt angle γ with respect to the a axis. Similarly, in the case of the C plane, there are three off angles: a twist angle α around the c axis, a tilt angle β with respect to the a axis, and a tilt angle γ with respect to the m axis. Moreover, when forming an off angle in the primary wafer 2, it is preferable that the off angles formed in the upper and lower main surfaces are the same. For example, when the primary wafer 2 is grown on a different wafer, when the off angle is formed on the C ⁺ surface as a growth surface by forming the off angle on the different wafer, the C ⁻ that is the removal surface of the different wafer. It is preferable to form the same off angle on the surface. Of C Primary wafer 2 ^- Formation of off-angle to the face, while measuring the orientation of the crystal axis of the primary wafer 2 in the X-ray, C single wafer 2 on controllable stage tilt angle ^- polishing the surface Can be done. Here, the same off angle means that the azimuth forming the off angle and the magnitude of the angle are the same.

  In this case, the primary wafer 2 has the same off-angle formed on two C planes facing each other, and dislocations in the primary wafer 2 travel in a direction substantially perpendicular to the C plane. With such a primary wafer 2, when the nitride semiconductor bars 4 are cut out and arranged, the alignment between the C surfaces of the cut-out nitride semiconductor bars 4 becomes good. Further, since dislocations in the nitride semiconductor bar 4 proceed in a direction parallel to the M plane, the crystallinity of the nitride semiconductor layer 6 to be regrown on the nitride semiconductor bar 4 is improved. Even when the nitride semiconductor bars 4 are arranged apart from each other, the crystallinity of the nitride semiconductor layer 6 to be regrown is good because the C-planes of the nitride semiconductor bars 4 are aligned. Become.

  Furthermore, the surface roughness on the C-plane which is the main surface of the primary wafer 2 is preferably 5000 mm or less, more preferably 3000 mm or less. In this specification, “surface roughness” refers to Ra measured by a non-contact roughness measuring machine. The surface roughness Ra can be measured by applying a laser to the control object and reading the deviation of the reflected light. MP2000 (manufactured by Chapman) is used as the measuring device. For example, the surface roughness Ra is measured with a measurement range of 5 mm and a cut-off of 80 μm. By reducing the surface roughness of the C surface, the C surfaces of the nitride semiconductor bars 4 can be more closely contacted with each other. Therefore, by controlling the surface roughness of the C surface of the primary wafer 2 to be small, it is possible to suppress the occurrence of abnormal growth on the connection surfaces of the nitride semiconductor bars 4 when the nitride semiconductor layer 6 is regrown. . Even when the nitride semiconductor bars 4 are arranged apart from each other, the crystallinity of the nitride semiconductor layer 6 to be regrown is improved due to the small surface roughness of the C surface of the nitride semiconductor bar 4.

  The primary wafer 2 can be produced by various methods. For example, the primary wafer 2 can be fabricated by removing a heterogeneous wafer after c-axis growth of a nitride semiconductor on the heterogeneous wafer such as sapphire, SiC, or silicon. According to this method, the primary wafer 2 having a large area can be easily produced. More specifically, if the primary wafer 2 is produced by the following method, the primary wafer 2 having a low dislocation density and a necessary thickness and area can be obtained.

1) Nitride Semiconductor Growth on Different Type Wafer First, a nitride semiconductor is laterally grown on a different type wafer to form a nitride semiconductor layer having a low dislocation density, and further grown to a predetermined film thickness by HVPE or the like. Here, the “lateral growth method” refers to all growth methods including a growth process in a direction parallel to the main surface of the substrate to be grown. For example, when a semiconductor is heteroepitaxially grown on a different type of wafer, an appropriate selective growth technique is used to cause lateral growth substantially parallel to the main surface of the wafer. By growing a crystal in a direction substantially parallel to the main surface of the wafer, dislocations can also grow in the lateral direction, and the dislocation density on the growth surface can be reduced. In the present embodiment, any of various conventionally known lateral growth methods may be used. For example, as a method of laterally growing a nitride semiconductor layer, as shown in FIG. 6A, a nitride semiconductor layer 48 is formed on a heterogeneous wafer 46, and a mask 50 such as SiO ₂ is periodically formed. There is. Since the nitride semiconductor layer 52 selectively grown from the window portion of the mask 50 grows laterally on the mask 50, the density of dislocations 40 generated at the interface with the different wafer 46 can be reduced. Further, as shown in FIG. 6B, there is a method in which the nitride semiconductor layer 48 grown on the heterogeneous wafer 46 is etched to locally expose the surface of the heterogeneous wafer 46. Since the nitride semiconductor 52 grows laterally starting from the nitride semiconductor 48 as a growth starting point, the density of dislocations 40 generated at the interface with the different kind of wafer can be reduced.

Further, in the method shown in FIG. 6A, before the nitride semiconductors 52 grown in the lateral direction on the mask 50 made of SiO ₂ or the like are bonded to each other, the growth is temporarily stopped, and after the mask 50 made of SiO ₂ or the like is removed, the nitride is removed. There is also a method of joining the semiconductors 52 together. Further, a method is known in which a facet surface is formed in the process of growing a nitride semiconductor in the lateral direction, and dislocations are terminated in a loop shape.

  After this lateral growth, a nitride semiconductor layer 54 is further grown by HVPE or the like. Thus, the nitride semiconductor layer is formed to have a film thickness that can stand alone. For example, the nitride semiconductor layer is grown until the thickness becomes 200 to 250 μm. Immediately after lateral growth on a heterogeneous wafer, there is a region where dislocations are periodically concentrated, but after that, dislocations are dispersed in-plane in the process of growing a nitride semiconductor into a thick film, and The in-plane distribution becomes uniform.

2) Removal of foreign wafer Then, the foreign wafer is peeled off by a method such as irradiating a laser from the back surface of the foreign wafer or polishing the foreign wafer from the back surface. By removing the different wafer before the following nitride semiconductor thick film growth, warpage and crack generation based on the difference in thermal expansion coefficient and lattice constant from the different wafer can be suppressed.

3) Thick film growth of nitride semiconductor layer Thereafter, a nitride semiconductor is grown to a thick film by an appropriate method such as HVPE. For example, the nitride semiconductor is grown until the film thickness becomes 1 to 2 mm. In this way, the primary wafer 2 having a necessary film thickness can be obtained. In this process, dislocations distributed by lateral growth are further dispersed. Further, dislocation advances in the c-axis direction during the thick film growth process by the HVPE method or the like. For this reason, when the nitride semiconductor bar 4 is cut out, dislocations extend in a direction parallel to the M plane.

  Further, instead of the above method, the primary wafer 2 may be formed by a growth method in which a nitride obtained by dissolving a primary wafer 2 in a nitrogen-containing solvent in a supercritical state is crystallized. Specifically, (a) a gallium-containing feedstock, an alkali metal-containing composition, a seed for crystal growth, and a nitrogen-containing solvent are charged into the container, (b) the nitrogen-containing solvent is brought into a supercritical state, and (c) A second temperature that is higher than the first temperature while at least partially dissolving the gallium-containing feedstock at a temperature of 1 and a first pressure, and (d) the nitrogen-containing solvent is in a supercritical state. And a method of growing a gallium-containing nitride crystal that crystallizes the gallium-containing nitride at a pressure lower than the first pressure.

2. Production of Nitride Semiconductor Bar 4 The nitride semiconductor bar 4 is obtained by slicing the primary wafer 2 into strips along the M plane. The cutting of the nitride semiconductor bar 4 from the primary wafer 2 can be performed, for example, as follows.

a) Determination of M-plane / M-plane of primary wafer 2 First, the M-plane of the primary wafer 2 is determined using a cut surface inspection apparatus. The cut surface inspection apparatus measures the tilt of the crystal surface using X-rays. As shown in FIG. 7, in the hexagonal nitride semiconductor, the C-plane, M-plane, and A-plane are orthogonal to each other. The c-axis, m-axis, and a-axis are also orthogonal to each other. Therefore, for example, if the inclination in the c-axis direction and the inclination in the a-axis direction are measured, the inclination of a certain surface from the M plane can be found. If the inclination from the M plane is known, the M plane can be obtained by grinding or the like.

b) Slicing of the primary wafer 2 Next, as shown in FIG. 8A, the primary wafer 2 is sliced into strips along the M plane with reference to the M plane extracted in the step (a). For example, a wire saw 10 can be used for slicing. If the slice interval (= corresponding to the width of the nitride semiconductor bar 4) when slicing with the wire saw 10 is too narrow, the mechanical strength of the nitride semiconductor bar 4 is insufficient, which is not preferable. On the other hand, when the slice interval is too wide, the number of nitride semiconductor bars 2 that can be taken from the primary wafer 2 is reduced. Therefore, the slice interval when slicing with the wire saw 10 is desirably 0.5 μm to 3 mm, more preferably 1 μm to 2 mm.

c) Polishing of M surface Next, the M surface sliced by the wire saw 10 is polished. When polishing the M surface, it is preferable to adjust the angle of the polishing surface while confirming the correct orientation of the M surface using a cut surface inspection apparatus. For example, as shown in FIG. 8B, if the sliced nitride semiconductor bar 4 is fixed on the stage 12 capable of adjusting the biaxial angle, the inclination of the polished surface with respect to the c-axis and the a-axis is measured using X-rays. However, the angle of the polishing surface can be adjusted. As the polishing, it is preferable to coarsely polish the M surface with coarse abrasive grains such as diamond abrasive grains and then finely polish using colloidal silica of 50 to 100 nm. Since the M plane has a relatively good cleaving property, an ideal M plane can be obtained after fine polishing if the orientation of the polishing surface is controlled with a certain degree of accuracy.

  The nitride semiconductor bar 4 thus formed has a substantially quadrangular prism shape having two sets of side surfaces facing each other. One set of side surfaces is formed of a C plane, and the other set of surfaces is formed of an M plane. . The dislocations in the nitride semiconductor bar 4 mainly extend in a direction substantially parallel to the M plane. Such a nitride semiconductor bar 4 can be configured as a substrate for growing a nitride semiconductor on the M-plane by arranging the M-plane as an upper surface and the C-planes facing each other. Moreover, since the dislocations in the nitride semiconductor bar 4 extend parallel to the M-plane, the nitride semiconductor layer regrown on such a substrate has a very low dislocation density. Furthermore, the size of the substrate can be freely controlled by simply changing the number of nitride semiconductor bars 4 arranged. Therefore, the nitride semiconductor bar 4 has excellent characteristics as a substrate for growing a nitride semiconductor.

  Moreover, it is preferable that the nitride semiconductor bar 4 has an A surface on the upper surface and the lower surface. At this time, the upper and lower surfaces of the nitride semiconductor bar 4 are orthogonal to the four side surfaces. Since the upper surface and the lower surface of the nitride semiconductor bar 4 are A surfaces, the crystallinity of the regrowth layer is improved when the regrowth substrate is formed by arranging the nitride semiconductor bars 4 in a two-dimensional matrix. That is, since the connection surfaces between the nitride semiconductor bars 4 are the A plane and the C plane, and the main surface for regrowth is the M plane, the crystal growth state at the connection portion between the nitride semiconductor bars 4 becomes good. The crystallinity of the regrown layer 6 is improved. This is presumably because the growth rate increases in the order of a-axis> c-axis> m-axis when the nitride semiconductor is regrown by the MOCVD method or the like.

  Moreover, it is preferable that the surface roughness of the two side surfaces composed of the C surface of the nitride semiconductor bar 4 is 1000 mm or less. As a result, the connection surfaces of the side surfaces of the nitride semiconductor bars 4 can be in close contact with each other, so that the crystallinity of the nitride semiconductor layer 6 to be regrown on the array of the nitride semiconductor bars 4 is improved. Further, even when the nitride semiconductor bars 4 are arranged apart from each other, the crystallinity of the regrown layer grown from the side surface of the nitride semiconductor bar 4 is improved.

  In addition, it is preferable that the same off angle is formed on both of the two side surfaces formed of the C-plane of the nitride semiconductor bar 4. However, if the off angle is too large, a problem of step bunching occurs. Therefore, it is desirable that the off angle is 1 ° or less, preferably 0.2 ° or less, more preferably 0.05 ° or less. If the nitride semiconductor bars 4 have the same off-angle, the alignment between the C faces becomes good when they are arranged. Even when the nitride semiconductor bars 4 are arranged apart from each other, the crystallinity of the nitride semiconductor layer 6 to be regrown is good because the C-planes of the nitride semiconductor bars 4 are aligned. Become. The formation of the off-angle improves the reproducibility during regrowth on the bar array.

  Furthermore, it is desirable that at least one of the two side surfaces composed of the M surface of the nitride semiconductor bar 4 has a surface roughness of 100 mm or less, more preferably 20 mm or less. If the surface roughness of at least one M-plane is 100 mm or less, the morphologies of the regrowth layer 6 are improved by making that surface a regrowth surface.

3. Arrangement of Nitride Semiconductor Bars 4 As shown in FIG. 3, the nitride semiconductor bars 4 are arranged in parallel with each other so that one M-plane is an upper surface. In the present embodiment, the nitride semiconductor bars 4 are arranged so as to be in close contact with each other on the C planes. At this time, there are three combinations of the C planes: C ⁺ plane and C ⁻ plane, C ⁺ plane and C ⁺ plane, and C ⁻ plane and C ⁻ plane. In this embodiment, any combination can be used, but (1) C ⁺ plane and C ⁺ plane, (2) C ⁺ plane and C ⁻ plane, (3) C ⁻ plane and C ⁻ plane in this order. Next, the state of the nitride semiconductor to be regrown is improved. However, when three or more nitride semiconductor bars 4 are arranged, it is not possible to make all the connection surfaces a combination of the C ⁺ surface and the C ⁺ surface. Therefore, in order to make the state in all the connection surfaces constant, it is preferable to arrange the adjacent nitride semiconductor bars so that the C ⁺ surface and the C ⁻ surface face each other.

  In addition, the nitride semiconductor bars 4 may be arranged not only one-dimensionally in the c-axis direction but also two-dimensionally arranged in the c-axis direction and the a-axis direction as shown in FIG. In this case, the C surfaces of the nitride semiconductor bars 4 are opposed to each other, and the A surfaces are opposed to each other. Since the A surface of the nitride semiconductor has no polarity, unlike the combination of the C surfaces, the combination of the A surfaces becomes one. By arranging the nitride semiconductor bars 4 two-dimensionally, a regrowth substrate having a larger area can be formed.

4). Regrowth of Nitride Semiconductor Layer 6 As shown in FIG. 4, the nitride semiconductor layer 6 is regrown on the array of nitride semiconductor bars 4 to obtain a nitride semiconductor wafer 8. The nitride semiconductor layer 6 to be regrown may have the same composition as the nitride semiconductor bar 4 or a different composition. However, from the viewpoint of crystallinity of the finally obtained nitride semiconductor wafer 8, it is preferable that the nitride semiconductor layer 6 to be regrown has the same composition as the nitride semiconductor bar 4. Further, an appropriate impurity may be added to the nitride semiconductor layer 6 in order to make the nitride semiconductor wafer 8 conductive.

  The regrowth of the nitride semiconductor layer 6 can be performed by appropriate vapor phase growth such as HVPE or MOCVD. Further, a nitride semiconductor layer 6 is grown in multiple layers by combining a vapor phase growth method and a nitride growth method (hereinafter referred to as an ammono method) for crystallizing nitride dissolved in a nitrogen-containing solvent in a supercritical state. Also good. The regrowth of the nitride semiconductor layer 6 may be performed a plurality of times while changing the growth conditions. For example, first, a nitride semiconductor layer may be grown to a thickness of about 50 to 200 μm on the array of nitride semiconductor bars 4 by low pressure MOCVD, and then grown to a thickness of 200 μm or more by HVPE. In particular, when the growth is performed by MOCVD under reduced pressure, the nitride semiconductor layer grows preferentially in the lateral direction, so that the crystallinity of the connection portion between the nitride semiconductor bars 4 can be improved. The pressure of the reduced pressure MOCVD is, for example, preferably 500 Torr or less, more preferably 400 Torr or less. In addition, there are MOCVD method / ammono method / HVPE method, ammono method / MOCVD method, and MOCVD method / HVPE method.

  The film thickness of the nitride semiconductor layer 6 to be regrown is desirably 5 mm or less, more preferably 3 mm or less. This is because if the nitride semiconductor layer 6 to be regrown is too thick, the supply balance of the raw material in the vapor phase growth apparatus is broken and the crystallinity is likely to be lowered. Further, since the nitride semiconductor bar 4 may inherently have stress generated when grown from a different wafer, if the nitride semiconductor layer 6 to be regrown is too thick, the influence of the stress becomes significant. . On the other hand, if the nitride semiconductor layer 6 to be regrown is too thin, the influence of the connection portion between the nitride semiconductor bars 4 is likely to remain on the surface of the regrown layer 6. Therefore, the thickness of the nitride semiconductor layer 6 to be regrown is desirably 30 μm or more, more preferably 100 μm or more.

  After the nitridation semiconductor layer 6 is regrown, it may be used as the nitride semiconductor wafer 8 as it is, or only a portion having good crystallinity is cut out with a wire saw or the like from the regrowth nitride semiconductor layer 6 and nitrided. The semiconductor wafer 8 may be used.

5. Replication of Nitride Semiconductor Wafer 8 As shown in FIG. 5, a nitride semiconductor is grown on nitride semiconductor wafer 8 by an appropriate method, and then sliced in parallel with the main surface of the wafer with a wire saw or the like. Nitride semiconductor wafers 8 ′, 8 ″ and the like thus obtained can be obtained. The duplicated nitride semiconductor wafers 8 ′ and 8 ″ have the same area as the original nitride semiconductor wafer 8 and have low dislocations like the original nitride semiconductor wafer 8.

  The nitride semiconductor for replicating the nitride semiconductor wafer 8 may have the same composition as the nitride semiconductor wafer 8 or a different composition. However, from the viewpoint of crystallinity of the nitride semiconductor wafer 8 ′ to be replicated, it is preferable that the nitride semiconductor to be grown has the same composition as the original nitride semiconductor wafer 8. Further, in order to give conductivity to the duplicated nitride semiconductor wafer 8 'or the like, the nitride semiconductor may be grown while adding an appropriate impurity.

  The growth of the nitride semiconductor on the nitride semiconductor wafer 8 can be performed by an appropriate method such as a vapor phase growth method such as HVPE method or MOCVD method, an ammono method or the like. Among these, it is preferable to grow a nitride semiconductor by an HVPE method capable of thick film growth.

  If a nitride semiconductor is grown thickly on the nitride semiconductor wafer 8, a large number of replica wafers can be obtained by a single crystal growth. On the other hand, if the film is grown too thick, the crystallinity of the replicated nitride semiconductor wafer 8 'or the like tends to decrease. Therefore, the thickness of the nitride semiconductor grown on the nitride semiconductor wafer 8 is preferably 0.5 to 5 cm. The film thickness of the nitride semiconductor wafer 8 'or the like cut out by slicing is preferably 0.5 to 1 mm. This is because if the thickness is too thin, the mechanical strength of the duplicated nitride semiconductor wafer 8 ′, etc. will be insufficient, while if it is too thick, the number of nitride semiconductor wafers 8 ′, etc. obtained in a single growth will decrease. is there.

Embodiment 2. FIG.
FIG. 9 is an end view showing the arrangement of the nitride semiconductor bars 4 according to the second embodiment. In the present embodiment, an off-angle is formed on the M plane which is the regrowth plane of the nitride semiconductor bar 4. Other points are the same as in the first embodiment.

  According to the present embodiment, when the nitride semiconductor layer 6 is regrown on the array of the nitride semiconductor bars 4, the crystallinity of the regrown layer 6 can be improved. That is, the M-plane with an off-angle has a minute step, and the minute step serves as a growth nucleus and enables uniform regrowth. In addition, if the M-plane of each nitride semiconductor bar 4 has an off-angle, a relatively large stepped portion 14 is formed at the connection portion 7 between the nitride semiconductor bars 4. Since the step portion 14 becomes a growth nucleus when the nitride semiconductor layer 6 is regrown, the crystallinity of the regrown layer 6 in the connection portion 7 can be improved. That is, in the connection portion 7 between the nitride semiconductor bars 4, a fine gap is easily generated between the nitride semiconductor bars 4, and abnormal crystal growth may occur in the gap due to insufficient supply of raw materials. By forming the stepped portion 14 in the connection portion 7 between the nitride semiconductor bars 4, regrowth proceeds preferentially in the connection portion 7, so that abnormal crystal growth in the connection portion 7 can be suppressed.

  Here, the off angle applied to the M-plane is desirably 5 ° or less, more preferably 0.2 ° or less. That is, if the off angle is too small, the step and the step 14 are not effectively formed, and the crystallinity improving effect due to the off angle is reduced. On the other hand, if the off angle is too large, a problem of step bunching occurs. Further, the orientation for forming the off-angle is preferably a direction perpendicular to the joint surface between the nitride semiconductor bars 4 (β or γ in FIG. 20), and the off-angle is 1 ° or less, preferably 0.2 °. The following is preferable. This is because a continuous M-plane becomes difficult if the off angle is too large.

  In order to make the M-plane of the nitride semiconductor bar 4 have an off-angle, the polishing surface may be controlled so that a desired off-angle is formed in the M-plane polishing step as shown in FIG. 8B. That is, in the polishing process of the M surface of the nitride semiconductor bar 4, the inclination of the polished surface with respect to the a axis and the c axis is measured by X-rays, and the surface having a predetermined off angle on the M surface is polished. 12 may be adjusted.

  One of a pair of side surfaces formed of the M-plane of the nitride semiconductor bar 4 may have an off angle, or both of them may have an off angle. However, in order to effectively form the stepped portion 14 when the nitride semiconductor bars 4 are arranged, it is preferable that only one M plane has an off-angle. For the same reason, when both M planes have off-angles, it is preferable that the M-plane as a growth plane has a larger off-angle. Furthermore, the orientation in which the off-angle is applied may be changed while the off-angle having the same size is applied to both M-planes. This also makes it possible to form an effective step 14 at the connection between the nitride semiconductor bars 4.

Embodiment 3 FIG.
FIG. 10 is a perspective view schematically showing the arrangement of the nitride semiconductor bars 4 according to the third embodiment. In the present embodiment, an unevenness that can be fitted to the side surface made of the C surface of the nitride semiconductor bar 4 is formed. The other points are the same as in the first embodiment.

  As shown in FIG. 10, a ridge 16 parallel to the longitudinal direction of the nitride semiconductor bar 4 is formed on one C surface of the nitride semiconductor bar 4, and the ridge 16 and the other C surface are formed on the other C surface. A recessed groove 18 that can be fitted is formed. When the nitride semiconductor bars 4 are arranged, the protrusions 16 and the grooves 18 are fitted between the adjacent C surfaces. Thereby, the regrowth of the nitride semiconductor layer 6 on the M-plane of the array of nitride semiconductor bars 4 becomes good. That is, when the nitride semiconductor layer 6 is regrown on the array of the nitride semiconductor bars 4, the nitride semiconductor bar 4 may cause a slight shift due to an air current or the like in the growth apparatus. This minute shift leads to a shift in crystal orientation at the connection portion between the nitride semiconductor bars. If there is a deviation in the crystal orientation, it leads to abnormal growth such as growth of different planes, and the quality of the nitride semiconductor wafer 8 is lowered. If the nitride semiconductor bars 4 are connected to each other by the ridges 16 and the concave grooves 18 as in the present embodiment, the crystal orientation of the nitride semiconductor bars 4 is prevented from shifting, and the crystallinity is good. The nitride semiconductor wafer 8 can be obtained stably.

  For example, grinding as shown in FIG. 11 is suitable for forming the protrusions 16 on the C-plane of the nitride semiconductor bar 4. That is, the nitride semiconductor bar 4 is placed on a table 20 that can move in two axes, x and y, and is ground by a diamond grindstone 22 that can move in the z-axis direction. In order to form the fine ridge 16 with high dimensional accuracy, it is preferable to use a projection grinder. As shown in FIG. 11, the projection grinding machine applies light to the workpiece (= nitride semiconductor bar 4) from below and performs grinding while watching the shadow 26 reflected on the upper screen 24. If a projection grinding machine is used, the fine protrusion 16 can be formed with high dimensional accuracy.

  On the other hand, it is preferable to use, for example, wire electric discharge machining as shown in FIG. 12 for forming the groove 18 on the C-plane of the nitride semiconductor bar 4. As shown in FIG. 12, the wire electric discharge machining is an apparatus that applies electric current to the wire 32 and performs machining by electric discharge between the wire 32 and the workpiece (= nitride semiconductor bar 4). The nitride semiconductor bar 4 as a work is sandwiched between chucks 30 fixed to the table 28 and placed in a pure water bath or an oil bath 34. And it discharges between the wire 32 and the nitride semiconductor bar 4, and processes it, melt | dissolving a nitride semiconductor with the heat | fever (6000-7000 degreeC) by discharge. The wire 32 is preferably made of brass having good conductivity or tungsten resistant to heat. Moreover, it is preferable to cool the wire 32 by sending the wire 32 continuously during processing. The diameter of the wire 32 is preferably 0.2 to 0.05 mm. By this wire electric discharge machining, the fine groove 18 can be formed with high accuracy.

  In addition, the shape of the protrusion 16 and the recessed groove 18 is not limited to this, What kind of shape may be sufficient as long as it can be mutually fitted. For example, instead of the ridge 16 and the groove 18, a dot-like convex portion and a concave portion fitted to it may be provided. A plurality of irregularities may be formed on one nitride semiconductor bar 4.

Embodiment 4 FIG.
FIG. 13 is an end view showing the arrangement of nitride semiconductor bars 4 according to the fourth embodiment. In the present embodiment, before the nitride semiconductor is regrown, a ridge where the C plane of the nitride semiconductor bar 4 intersects with the M plane serving as the regrown plane is chamfered. The other points are the same as in the third embodiment. “Chamfering the ridge” means that a part of the corner of the ridge where the two surfaces intersect is partially removed along the ridge line, and a new surface that obliquely intersects with any of the two surfaces is formed on the ridge. It refers to forming.

  By chamfering the ridge where the C-plane of the nitride semiconductor bar 4 and the M-plane serving as the regrowth plane intersect, two inclined surfaces 36 and 37 that obliquely intersect both the C-plane and the M-plane. Can be formed. The inclined surfaces 36 and 37 are preferably parallel to the a-axis of the nitride semiconductor bar 4. A portion sandwiched between the inclined surface 36 and the inclined surface 37 forms a V-shaped groove 38 in the connecting portion between the nitride semiconductor bars 4. Since the V-shaped groove 38 serves as a growth nucleus when the nitride semiconductor bar 6 is regrown on the nitride semiconductor bar 4, it promotes the regrowth of the nitride semiconductor 6 at the connection portion between the nitride semiconductor bars 4. I can expect that. Further, as shown in FIG. 14, the growth of the nitride semiconductor layer 6 in the V-shaped groove 38 is facet growth, so that the dislocation 40 generated at the interface between the nitride semiconductor bar 4 and the nitride semiconductor layer 6 forms a loop. Disappears and the dislocation density can be reduced. In particular, the connection portion 7 between the nitride semiconductor bars 4 is a region in which new dislocations are likely to occur in the nitride semiconductor layer 6 to be regrown. The dislocation density can be preferably reduced.

  The inclined surfaces 36 and 37 forming the V-shaped groove 38 are preferably R surfaces such as a (10-12) surface. Thereby, facet growth in the V-shaped groove 38 is promoted, and the dislocation density of the regrowth layer 6 can be further reduced. Moreover, it is preferable that the width | variety in the direction perpendicular | vertical to the a-axis of the inclined surfaces 36 and 37 is 100-500 micrometers. If the inclined surfaces 36 and 37 are too narrow, the V-shaped groove 38 becomes shallow and facet growth is difficult to obtain. On the other hand, if the inclined surfaces 36 and 37 are too wide, the V-shaped groove 38 becomes too deep and the V-groove tends to remain on the surface of the regrowth layer 6.

  Further, only one of the inclined surfaces 36 and 37 forming the V-shaped groove 38 may be formed. That is, it is possible to chamfer only the ridge portion where one C-plane of the nitride semiconductor bar 4 and the M-plane serving as the regrowth plane intersect. However, as shown in FIGS. 13 and 14, if both inclined surfaces 36 and 37 are formed with the same size and the same angle, the V-shaped groove 38 becomes symmetrical, and the surface of the nitride semiconductor layer 6 to be regrown Tends to be flat.

Embodiment 5. FIG.
FIG. 15 is a perspective view schematically showing the arrangement of nitride semiconductor bars 4 according to the fifth embodiment. FIG. 16 is a cross-sectional view schematically showing a process of regrowing a nitride semiconductor layer on the array of nitride semiconductor bars 4 shown in FIG. In the present embodiment, a stripe-shaped protective film 42 is formed on the upper surface (= M surface) of the nitride semiconductor bar 4 so as to cover the connection portion 7 between the nitride semiconductor bars 4. Other points are the same as in the first embodiment.

  According to the present embodiment, since the protective film 42 is formed so as to cover the connection portion 7 between the nitride semiconductor bars 4, the dislocation density in the regrowth layer 6 is further reduced. That is, in the connection portion between the nitride semiconductor bars 4 in the first embodiment, a slight misalignment of crystal orientation and a fine gap are likely to be formed, so that the crystallinity of the regrowth layer 6 may be locally deteriorated. is there. If the connection portion between the nitride semiconductor bars 4 is covered with the protective film 42, the crystallinity of the regrowth layer 6 is not affected even if there is a slight gap or crystal orientation misalignment in the connection portion between the nitride semiconductor bars 4. In addition, if the protective film 42 is made of a different material from which the nitride semiconductor layer 6 is difficult to grow directly, the nitride semiconductor layer 6 grown from the window between the protective films 42 also extends laterally on the protective film 42. Since the crystal grows in the direction, dislocations caused by lattice mismatch with the protective film 42 are not generated, and dislocations appearing on the surface of the nitride semiconductor layer 6 are reduced. In addition, since dislocations of the nitride semiconductor bar 4 extend substantially parallel to the M-plane, the dislocation density in the window portion between the protective films 42 is sufficiently low, unlike normal lateral growth. Therefore, the nitride semiconductor wafer 8 having a low dislocation and a large area can be obtained.

  The protective film 42 used in the present embodiment can be made of, for example, silicon oxide, silicon nitride, refractory metal, or the like. Here, the refractory metal refers to a metal having a melting point of 1200 ° C. or higher such as W, Ti, or Cu.

Embodiment 6 FIG.
FIG. 17 is a perspective view schematically showing the arrangement of nitride semiconductor bars 4 in the sixth embodiment. In the present embodiment, the nitride semiconductor bars 4 are not closely attached to each other but are arranged at a predetermined interval. Other points are the same as in the first embodiment.

  The arrangement of the nitride semiconductor bars 4 can be as follows, for example. Similar to the first embodiment, the nitride semiconductor bars 4 are arranged in the c-axis direction with a certain interval so that the M-plane becomes the upper surface and the C-planes of the adjacent nitride semiconductor bars 4 face each other. At this time, it is preferable that the C-planes of adjacent nitride semiconductor bars 4 are arranged in parallel to each other. The nitride semiconductor bars 4 are preferably arranged on a substrate 44 such as sapphire where nitride semiconductors are difficult to grow directly.

  In general, the growth rate in the c-axis direction of a nitride semiconductor is faster than the growth rate in the m-axis direction. Therefore, when the nitride semiconductor layer 6 is regrown on the nitride semiconductor bars 4 arranged as shown in FIG. 17, as shown in FIG. 18, the top and side surfaces (or top surfaces) of the adjacent nitride semiconductor bars 4 are obtained. Nitride semiconductors grown from (1) extend in the lateral direction and are joined to each other. Then, a continuous regrowth layer 6 can be obtained on the entire surface.

  This method is similar to the lateral growth shown in FIG. 6B but differs greatly in the following respects. First, unlike the conventional lateral growth, the upper surface of the nitride semiconductor bar 4 serving as a seed crystal is an M plane, and the side surface is a C plane. As described above, the growth rate in the c-axis direction of the nitride semiconductor is larger than the growth rate in the m-axis direction. For this reason, the regrowth layer 6 tends to be flat as compared with the lateral growth shown in FIG. 6B. Moreover, the dislocations 40 extend parallel to the main surface of the wafer inside the nitride semiconductor bar 4 to be a seed crystal. Therefore, almost no threading dislocations extending in the vertical direction from the upper surface of the nitride semiconductor bar 4 are generated, and the nitride semiconductor wafer 8 having low dislocations on the entire surface can be obtained.

Embodiment 7 FIG.
FIG. 19 is a perspective view schematically showing the arrangement of nitride semiconductor bars 4 according to the seventh embodiment. In the present embodiment, the nitride semiconductor bars 4 arranged in the sixth embodiment are further arranged in the a-axis direction, and the nitride semiconductor bars 4 are arranged in a two-dimensional matrix. Thereby, nitride semiconductor wafer 8 having a larger area can be obtained.

  In the present embodiment, it is preferable that the upper surface and the lower surface of the substantially square columnar nitride semiconductor bar 4 be the A plane. As a result, the A surfaces of the nitride semiconductor bars 4 arranged in the a-axis direction face each other. In general, the growth rate of a nitride semiconductor increases in the order of a-axis direction> c-axis direction> m-axis direction. Accordingly, when the nitride semiconductor layer 6 is regrown on the nitride semiconductor bars 4 arranged as shown in FIG. 19, the nitride semiconductor grown from the upper surface and the side surface (or the upper surface) of the adjacent nitride semiconductor bar 4. Extend in the a-axis direction and the c-axis direction and are joined to each other. Then, a continuous regrowth layer 6 can be obtained on the entire surface.

  Also in the present embodiment, as in the sixth embodiment, dislocations 40 extend parallel to the main surface of the wafer inside the nitride semiconductor bar 4 serving as a seed crystal. Therefore, the threading dislocation extending in the vertical direction from the upper surface of the nitride semiconductor bar 4 hardly occurs, and the nitride semiconductor wafer 8 having a low dislocation over the entire surface can be obtained.

Embodiment 8 FIG.
In this embodiment, the process of joining the nitride semiconductor bars is performed twice or more. First, a first nitride semiconductor bar is formed from a wafer grown in the c-axis direction. The method described in other embodiments may be used as the method for forming the first nitride semiconductor bar. The first nitride semiconductor bar is bonded to each other with the M-plane of the first nitride semiconductor bar as the upper surface, and the first nitride semiconductor is grown on the first nitride semiconductor bar, whereby the wafer having the M-plane as the main surface Form. Next, parts other than the first nitride semiconductor are removed from the wafer. Next, a second nitride semiconductor bar is formed from the first nitride semiconductor. A wafer having the C-plane as the main surface by bonding the second nitride semiconductor bars to each other with the C-plane of the second nitride semiconductor bar as the upper surface and growing the second nitride semiconductor thereon. Form. Next, by removing other than the second nitride semiconductor from the wafer, a nitride semiconductor wafer having a low-dislocation C-plane as the main surface is obtained on the entire surface.

Embodiment 9 FIG.
In the embodiment described above, the nitride semiconductor bars are bonded to each other with the R surface of the nitride semiconductor bar as the upper surface in the step of forming the nitride semiconductor bars from the nitride semiconductor wafer. A first nitride semiconductor is grown thereon to form a wafer having the R surface as the main surface. Next, by removing other than the first nitride semiconductor from the wafer, a nitride semiconductor wafer having a low-dislocation R-plane as the main surface is obtained on the entire surface.

Embodiment 10 FIG.
In the above-described embodiment, in the step of forming a nitride semiconductor bar from a nitride semiconductor wafer, the nitride semiconductor bars are bonded to each other with one of the A, M, and R surfaces of the nitride semiconductor bar as the upper surface. Let A first nitride semiconductor is grown thereon. Next, parts other than the first nitride semiconductor are removed from the wafer. A second nitride semiconductor bar is formed from the first nitride semiconductor. The nitride semiconductor bars are bonded to each other with the C-plane, A-plane, M-plane, or R-plane of the second nitride semiconductor bar as the upper surface. A second nitride semiconductor is grown thereon. Next, a nitride semiconductor wafer having low dislocations on the entire surface is obtained by removing other than the second nitride semiconductor from the wafer.

In the conventional nitride semiconductor wafer, even if the off-angle of the wafer central part is matched by lattice bowing, the outer peripheral part has a different value. The difference between the values increases remarkably in proportion to the wafer diameter.
The off-angle distribution of the nitride semiconductor wafer of the present invention is determined by the processing error of each nitride semiconductor bar and the lattice bowing of the nitride semiconductor bar alone to be joined. Since the size of the nitride semiconductor bar is much smaller than the nitride semiconductor wafer to be finally used, the influence of lattice bowing is also reduced.
Specifically, in the nitride semiconductor wafer of the present invention, the off-angle error between both ends of the wafer is reduced even when the wafer size is increased. For example, if the size of the nitride semiconductor wafer is 2 inches, the off-angle error is 0.286 ° in the conventional wafer, whereas the wafer of the present invention is 0.257 °. Further, when it is 3 inches, the off-angle error is 0.430 ° in the conventional wafer, whereas in the wafer of this embodiment, the above error is maintained in a small range of 0.257 °. That is, the nitride semiconductor wafer of the present invention is particularly preferable for manufacturing a large area wafer because the off-angle error does not depend on the wafer size.

(1) Production of primary wafer 2 In the MOCVD reactor, a sapphire substrate having a predetermined off-angle with a 2-inch φ C-plane as the main surface is disposed. The off-angle of the main surface is such that the tilt angle with respect to the a-axis is 0.15 to 0.3 ° and the tilt angle with respect to the m-axis is 0 to 0.1 °. Next, the temperature of the substrate is set to 500 ° C. Next, a buffer layer made of GaN is grown to a thickness of 200 Å using trimethyl gallium (TMG) and ammonia (NH ₃ ) on the substrate having the off angle. After growing the buffer layer, the temperature is set to 1050 ° C., and an underlying layer made of GaN is grown to a thickness of 4 μm.

After growing the underlayer, the wafer is taken out of the reaction vessel, a striped photomask is formed on the surface of the underlayer, and a SiO 2 having a stripe width of 10 to 300 μm and a stripe interval (window) of 5 to 300 μm is formed by a CVD apparatus. _A protective film made of ₂ is formed.
After forming the protective film, a GaN layer is grown using trimethylgallium (TMG) and ammonia (NH ₃ ) in the MOCVD reactor.
Next, the wafer is transferred to an HVPE (hydride vapor phase epitaxy) apparatus, Ga metal, HCl gas, and ammonia are used as raw materials, H ₂ is used as a carrier gas, and a nitride semiconductor made of GaN is a film having a thickness of 100 μm or more. Grow with thickness. Thus, when a GaN thick film of 100 μm or more is grown by the HVPE method, crystal defects can be reduced. From the above process, GaN was grown with a film thickness of 200 to 250 μm.

  Next, a KrF laser having a wavelength of 249 nm was irradiated from the back surface of the sapphire substrate, and the sapphire substrate was peeled off to obtain a GaN substrate having a C-plane of about 30 mm and a thickness of about 200 to 250 μm as the main surface.

  Then, the two main surfaces (= C surface) of the obtained thick GaN substrate were polished using diamond abrasive grains, so that the surface roughness Ra was about 20 to 30 mm. Thus, a primary wafer 2 made of GaN having a thickness of about 1.9 mm was obtained.

(2) Production of Nitride Semiconductor Bar 4 Next, the primary wafer 2 made of GaN was applied to a cut surface inspection apparatus, and the M surface was determined. The primary wafer 2 was ground from the side surface to expose the M surface. The particle diameter of the diamond abrasive used for grinding was about 40 to 120 μm.

  Then, using the exposed M-plane as a reference, the primary wafer 2 was sliced into strips with a width of 2 mm using a wire saw, and a nitride semiconductor bar 4 was obtained. Each nitride semiconductor bar 4 was again subjected to a cut surface inspection device, and the sliced M surface was roughly polished with diamond abrasive grains having a particle diameter of 4 to 8 μm, and further polished with diamond abrasive grains having a particle diameter of 0.1 to 2 μm. Then, fine polishing was performed using colloidal silica having a particle size of about 80 nm. The M surface after fine polishing had a surface roughness Ra of 5 to 10 mm.

(3) Arrangement of Nitride Semiconductor Bars 4 The four nitride semiconductor bars 4 were arranged so that the M-plane was the upper surface and the C ⁺ plane and C ^- plane of the adjacent nitride semiconductor bar 4 were in contact with each other.

(4) Re-growth of nitride semiconductor layer 6 Next, an array of nitride semiconductor bars 4 was placed in the HVPE growth apparatus so that the finely polished M-plane became the growth plane. In the HVPE growth apparatus, Ga metal was installed in a boat. Then, the temperature was raised to 980 ° C., the NH ₃ was 1.00 L / min supply of _{H 2} as a carrier gas, and 100 cc / min supply of HCl and _{H 2} as a carrier gas, the film thickness is grown a GaN of approximately 300μm I let you. Then the temperature was brought to 900 ° C., the NH ₃ and 0.75 l / min supply of _{H 2} as the carrier gas, HCl and _{H 2} as a carrier gas was 100 cc / min supply, further thickness growth of GaN 200~300μm I let you.

A portion of the grown GaN layer was sliced with a wire saw to produce a nitride semiconductor wafer 8 having a diameter of 25 mm, a film thickness of 1000 μm, and a main surface of which is an M plane. The nitride semiconductor wafer 8 had an XRD FWHM of 100 S or less. The EPD by CL measurement was 2.6 × 10 ⁴ pieces / cm ² or less.

  In Example 1, after the sapphire substrate was peeled off, a GaN substrate having a C-plane of about 30 mm and a thickness of about 200 to 2000 μm as the main surface was obtained. A GaN layer was grown on the GaN substrate by HVPE using Ga metal, HCl gas as a source gas, and ammonia as a carrier gas until the total film thickness became 3 mm. The other conditions are the same.

FIG. 1 is a perspective view schematically showing a primary wafer in the first embodiment. FIG. 2 is a perspective view schematically showing the nitride semiconductor bar in the first embodiment. FIG. 3 is a perspective view schematically showing the arrangement of the nitride semiconductor bars in the first embodiment. FIG. 4 is a perspective view schematically showing the nitride semiconductor wafer in the first embodiment. FIG. 5 is a perspective view schematically showing a method for replicating a nitride semiconductor wafer in the first embodiment. FIG. 6A is a cross-sectional view showing an example of a primary wafer manufacturing method in the first embodiment. FIG. 6B is a cross-sectional view showing another example of the method for manufacturing a primary wafer in the first exemplary embodiment. FIG. 7 is a schematic diagram showing the relationship between crystal planes and crystal axes in a hexagonal nitride semiconductor. FIG. 8A is a schematic diagram showing a process of slicing a primary wafer in the first embodiment. FIG. 8B is a schematic diagram showing a process of polishing the M surface of the nitride semiconductor bar in the first embodiment. FIG. 9 is an end view schematically showing the arrangement of the nitride semiconductor bars in the second embodiment. FIG. 10 is a perspective view schematically showing the arrangement of nitride semiconductor bars in the third embodiment. FIG. 11 is a schematic diagram showing a step of forming protrusions on the nitride semiconductor bar in the third embodiment. FIG. 12 is a schematic diagram showing a step of forming a groove in the nitride semiconductor bar in the third embodiment. FIG. 13 is an end view schematically showing the arrangement of nitride semiconductor bars in the fourth embodiment. FIG. 14 is a partially enlarged view schematically showing a process of regrowing a nitride semiconductor layer in the fourth embodiment. FIG. 15 is a perspective view schematically showing an array of nitride semiconductor bars in the fifth embodiment. FIG. 16 is a cross-sectional view schematically showing a step of regrowing a nitride semiconductor layer in the fifth embodiment. FIG. 17 is a perspective view schematically showing the arrangement of nitride semiconductor bars in the sixth embodiment. FIG. 18 is a cross-sectional view schematically showing a process of regrowing a nitride semiconductor layer in the sixth embodiment. FIG. 19 is a perspective view schematically showing the arrangement of the nitride semiconductor bars in the seventh embodiment. FIG. 20 is a schematic diagram showing an off angle applied to the M-plane of the nitride semiconductor.

Explanation of symbols

2 Primary wafer,
4 Nitride semiconductor bar,
6 regrowth layer,
8 Nitride semiconductor wafer,
8 ′, 8 ″ replicated nitride semiconductor wafer,
12 2-axis adjustment base,
14 Step 16 ridge (convex)
18 groove (concave)
40 dislocations

Claims (14)

(A) a step of obtaining a primary wafer comprising a hexagonal nitride semiconductor and two opposing principal surfaces each comprising a C-plane;
(B) separating the primary wafer along the M-plane to obtain a plurality of nitride semiconductor bars;
(C) a plurality of nitride semiconductor bars, C surface of the adjacent nitride semiconductor bars are opposed, M faces of the nitride semiconductor bars are arranged in close contact so that the top surface, further them Joining, and
(D) forming a nitride semiconductor layer having a continuous M-plane as a main surface by regrowth of the nitride semiconductor on the upper surface of the bonded nitride semiconductor bar; and a nitride semiconductor wafer comprising: Manufacturing method.   A nitride semiconductor wafer having a M-plane as a main surface is replicated by re-growing a nitride semiconductor on the nitride semiconductor wafer manufactured by the method according to claim 1 and separating from the nitride semiconductor wafer. A method for manufacturing a nitride semiconductor wafer, comprising:   The method for producing a nitride semiconductor wafer according to claim 1, wherein the primary wafer is obtained by c-axis growth of a nitride semiconductor in a supercritical ammonia fluid.   4. The method for manufacturing a nitride semiconductor wafer according to claim 1, wherein in the step (a), an off-angle is formed on the two opposing main surfaces. 5.   5. The method for manufacturing a nitride semiconductor wafer according to claim 1, wherein an off-angle is formed in the M-plane which is an upper surface in the step (c).   6. The ridge portion where one C-plane of the nitride semiconductor bar intersects with an M-plane serving as a regrowth surface is chamfered before the step (d). The manufacturing method of the nitride semiconductor wafer of description.   7. The method for manufacturing a nitride semiconductor wafer according to claim 6, further comprising chamfering a side where the other C-plane intersects with the M-plane serving as a regrowth plane.   8. The step (c), wherein the plurality of nitride semiconductor bars are arranged in a matrix so that their C faces face each other and their A faces face each other. The manufacturing method of the nitride semiconductor wafer in any one.   9. The nitride semiconductor wafer according to claim 1, wherein in the step (c), the plurality of nitride semiconductor bars are arranged so that their C + plane and C− plane face each other. Manufacturing method.   In the step (d), after forming a protective film covering the bonding interface between the nitride semiconductor bars on the upper surface of the arranged nitride semiconductor bars, the nitride semiconductor is regrown. The method for manufacturing a nitride semiconductor wafer according to claim 1. A substantially rectangular pillar-shaped nitride semiconductor bar made of a nitride semiconductor and having two sets of opposite side surfaces,
One set of the side faces consists of a C plane, and the other set of the side faces consists of an M plane, and dislocations in the nitride semiconductor bar mainly extend in a direction substantially parallel to the M plane.
A nitride semiconductor bar, wherein an off angle is formed on at least one of the two side surfaces of the M-plane.   12. The nitride semiconductor bar according to claim 11, wherein an upper surface and a lower surface perpendicular to the side surface of the nitride semiconductor bar are both A-planes.   The nitride semiconductor bar according to claim 11 or 12, wherein the two side surfaces composed of the C-plane have a surface roughness of 5000 mm or less.   The nitride semiconductor bar according to any one of claims 11 to 13, wherein at least one of the ridges where the side surface formed of the C plane and the side surface formed of the M plane intersect is chamfered.

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