JP2008153285A - Nitride semiconductor apparatus and nitride semiconductor manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nitride semiconductor apparatus having a nitride-gallium semiconductor layer having a growing main plane other than a c-face and having a flat plane and less crystal defect, and to provide a nitride semiconductor manufacturing method for forming such a nitride-gallium semiconductor layer. <P>SOLUTION: A GaN substrate 1 has a main plane other than the c-plane (e.g., m-plane). A GaN semiconductor layer 2 is formed on the GaN substrate 1 by an organic metal chemical vapor phase growth method. An N-type contact layer 21 is obtained by growing a second N-type GaN layer 212 under the condition of the V/III ratio being high, on a first N-type GaN layer 211 grown under the condition with the V/III ratio of the nitrogen material (molar ratio) to a gallium material being low. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to nitride semiconductor devices such as nitride semiconductor light emitting elements (light emitting diodes, laser diodes, etc.), nitride semiconductor electronic devices (transistors, diodes, etc.) such as power device high frequency devices, and such nitride semiconductor The present invention relates to a method for manufacturing a nitride semiconductor that can be applied to manufacture of a device.

A semiconductor using nitrogen as a group V element in a group III-V semiconductor is called a “group III nitride semiconductor”, and typical examples thereof are aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN). is there. In general, it can be expressed as Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1), which is expressed as “gallium nitride semiconductor” or “GaN semiconductor”. I will say.

  A nitride semiconductor manufacturing method is known in which a group III nitride semiconductor is grown on a gallium nitride (GaN) substrate having a c-plane as a main surface by metal organic chemical vapor deposition (MOCVD). By applying this method, a GaN semiconductor multilayer structure having an N-type layer and a P-type layer can be formed, and a light-emitting device using this multilayer structure can be manufactured. Such a light emitting device can be used as a light source of a backlight for a liquid crystal panel, for example.

  The main surface of the GaN semiconductor regrowth on the GaN substrate having the c-plane as the main surface is the c-plane. The light extracted from the c-plane is in a randomly polarized (non-polarized) state. Therefore, when incident on the liquid crystal panel, other than the specific polarized light corresponding to the incident side polarizing plate is shielded and does not contribute to the luminance toward the emission side. Therefore, there is a problem that it is difficult to realize a display with high luminance (efficiency is 50% at the maximum).

  In order to solve this problem, a GaN semiconductor having a main surface other than the c-plane, that is, a non-polar (non-polar) surface such as a-plane or m-plane, or a semi-polar (semi-polar) surface is grown. Fabrication is under consideration. When a light-emitting device having a P-type layer and an N-type layer is manufactured using a GaN semiconductor layer having a nonpolar surface or a semipolar surface as a main surface, light having a strong polarization state can be emitted. Therefore, the loss in the incident side polarizing plate can be reduced by matching the polarization direction of such a light emitting device with the direction of the passing polarized light of the incident side polarizing plate of the liquid crystal panel. As a result, a display with high luminance can be realized.

However, the conditions for forming a GaN semiconductor regrowth layer with few dislocations (crystal defects) and a good surface state on a nonpolar or semipolar surface are extremely severe.
More specifically, when a GaN semiconductor is regrown on a GaN substrate having a c-plane as a main surface, the V / III ratio, which is the ratio (molar ratio) of the nitrogen source to the gallium source, is about 3000. The MOCVD method is applied. When a GaN semiconductor with the m-plane as the growth principal surface is grown under the same conditions, an N-polar plane such as a (000-1) plane is formed in the lateral direction or oblique direction, and the growth rate is slow. It becomes. Therefore, a flat film cannot be obtained.

  On the other hand, when a GaN semiconductor layer is grown by MOCVD on a GaN substrate having an m-plane as a main surface, it has been proposed to suppress the occurrence of dislocations and stacking faults by setting the V / III ratio to less than 1000. ing. However, when the V / III ratio is low, many N depletions occur and the microcrystalline property deteriorates. In other words, there is a problem in that the luminous efficiency decreases due to an increase in non-radiative recombination.

Thus, even when a light emitting device is manufactured using a GaN semiconductor layer having many crystal defects and a poor surface state, the external quantum efficiency is low, and satisfactory light emission characteristics cannot be obtained.
T. Takeuchi et al., Jap. J. Appl. Phys. 39, 413-416, 2000 A. Chakraborty, BA Haskell, HS Keller, JS Speck, SP DenBaars, S. Nakamura and UK Mishra: Jap. J. Appl. Phys. 44 (2005) L173

  SUMMARY OF THE INVENTION An object of the present invention is to provide a nitride semiconductor device having a gallium nitride semiconductor layer having a growth principal surface other than the c-plane and being flat and having few crystal defects, and manufacturing a nitride semiconductor for forming such a gallium nitride semiconductor layer Is to provide a method.

  In order to achieve the above object, the invention according to claim 1 is characterized in that a V / III ratio, which is a ratio (molar ratio) of a nitrogen source to a group III element source (more specifically, for example, a gallium source), is a predetermined value. A first group III nitride semiconductor layer having a growth main surface other than the c-plane, and a second V / III ratio higher than the first V / III ratio, provided on the first group III nitride semiconductor layer. A nitride semiconductor device including a second group III nitride semiconductor layer having a III ratio and having the same main growth surface as the first group III nitride semiconductor layer.

According to this configuration, the first group III nitride semiconductor layer is a layer grown under conditions with a low V / III ratio. Such a group III nitride semiconductor layer is a flat film because the growth rate of the N-polar plane is high at the time of formation. On the other hand, the Group III nitride semiconductor layer is a layer grown under conditions with a high V / III ratio. Such a group III nitride semiconductor layer has a low defect density and good crystallinity.
Thus, according to the configuration of the present invention, it is possible to realize a nitride semiconductor device having a group III nitride semiconductor layer with good flatness and crystallinity. For example, when such a nitride semiconductor device is applied to a light-emitting device, non-radiative recombination can be suppressed and light emission efficiency can be improved.

According to a second aspect of the present invention, the nitride semiconductor device further includes a substrate and an AlN layer (for example, 10 nm or less) formed on the substrate, and the first group III is formed on the AlN layer. A nitride semiconductor layer may be formed.
According to a third aspect of the present invention, the first and second group III nitride semiconductor layers are gallium nitride semiconductor layers having a growth main surface as an m-plane, and the substrate has an m-plane as a main surface. It may be a silicon carbide substrate.

Furthermore, as described in claim 4, the first and second group III nitride semiconductor layers are gallium nitride semiconductor layers having a growth main surface as an m-plane, and the substrate has an m-plane as a main surface. It may be a gallium nitride substrate.
The main growth surface of the first and second group III nitride semiconductor layers may be a nonpolar (nonpolar) surface or a semipolar (semipolar) surface.

Moreover, as described in claim 6, the first V / III ratio is preferably a value within a range of 100 to 1000.
Furthermore, as described in claim 7, the second V / III ratio is preferably a value within a range of 1000 to 10000.
In addition, as described in claim 8, it is preferable that the thickness of the first group III nitride semiconductor layer is 2 μm or more.

Furthermore, as described in claim 9, the first and second group III nitride semiconductor layers may be group III nitride semiconductor layers doped with silicon.
Further, as described in claim 10, a plurality of group III nitride semiconductor layers whose conductivity type is controlled by doping impurities may be formed on the second group III nitride semiconductor layer. Thereby, a semiconductor device such as a diode or a transistor can be configured.

  The invention according to claim 11 is a method for growing a group III nitride semiconductor having a main growth surface other than the c-plane (more specifically, growing by a metal organic chemical vapor deposition method). Growing a first group III nitride semiconductor layer having a growth principal surface other than the c-plane under a growth condition in which a V / III ratio, which is a ratio of a nitrogen material to a material, is a predetermined first V / III ratio; A Group III nitride semiconductor layer having the same growth principal surface as the Group III nitride semiconductor layer is grown on the Group III nitride semiconductor layer under a growth condition of a second V / III ratio higher than the 1 V / III ratio. A method of manufacturing a nitride semiconductor.

  According to this method, the first group III nitride semiconductor layer is grown under conditions with a low V / III ratio, so that the growth rate of the N-polar plane is high and a flat film is obtained. Therefore, the second group III nitride semiconductor layer formed on the first group III nitride semiconductor layer is also a flat film. And since the 2nd group III nitride semiconductor layer is grown on conditions with a high V / III ratio, it has a low defect density and has favorable crystallinity. Thus, the first and second group III nitride semiconductor layers form a semiconductor layer having good flatness and crystallinity as a whole.

13. The method of claim 12, further comprising growing an AlN layer (eg, 10 nm or less) on a substrate, and growing the first group III nitride semiconductor layer on the AlN layer. You may do it.
In addition, as described in claim 13, the first and second group III nitride semiconductor layers are gallium nitride semiconductor layers having a growth main surface as an m-plane, and the substrate has an m-plane as a main surface. It may be a silicon carbide substrate.

Furthermore, as described in claim 14, the first and second group III nitride semiconductor layers are gallium nitride semiconductor layers having a growth main surface as an m-plane, and the substrate has an m-plane as a main surface. It may be a gallium nitride substrate.
Furthermore, the growth main surface of the first and second group III nitride semiconductor layers may be a nonpolar surface or a semipolar surface.

Preferably, the first V / III ratio is a value within a range of 100 to 1000.
Moreover, as described in claim 17, the second V / III ratio is preferably a value within a range of 1000 to 10,000.
Furthermore, it is preferable that the first group III nitride semiconductor layer is grown to a thickness of 2 μm or more.

The step of growing the first and second group III nitride semiconductor layers may be a step of growing a group III nitride semiconductor while doping silicon.
Furthermore, the method may further include a step of growing a plurality of group III nitride semiconductor layers on the second group III nitride semiconductor layer while doping impurities to control the conductivity type.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic sectional view for explaining the structure of a light emitting diode according to an embodiment of the present invention. This light emitting diode is configured by regrowing a GaN semiconductor layer 2 as a group III nitride semiconductor layer on a GaN (gallium nitride) substrate 1. Although it is better not to have a buffer layer such as an AlN layer between the GaN substrate 1 and the GaN semiconductor layer 2, an AlN layer 8 having a thickness of 10 nm or less is formed as necessary in order to improve flatness. It may be interposed.

  The GaN semiconductor layer 2 includes an N-type contact layer 21, a quantum well (QW) layer 22, a GaN final barrier layer 25, a P-type electron blocking layer 23, and a P-type in order from the GaN substrate 1 side. It has a laminated structure in which contact layers 24 are laminated. An anode electrode 3 as a transparent electrode is formed on the surface of the P-type contact layer 24, and a connection portion 4 for wiring connection is joined to a part of the anode electrode 3. The cathode electrode 5 is joined to the N-type contact layer 21. Thus, a light emitting diode structure is formed.

  The GaN substrate 1 is bonded to a support substrate (wiring substrate) 10. Wirings 11 and 12 are formed on the surface of the support substrate 10. The connection portion 4 and the wiring 11 are connected by a bonding wire 13, and the cathode electrode 5 and the wiring 12 are connected by a bonding wire 14. Further, although not shown in the drawings, the light emitting diode element is configured by sealing the light emitting diode structure and the bonding wires 13 and 14 with a transparent resin such as an epoxy resin.

The N-type contact layer 21 is composed of an N-type GaN layer to which silicon is added as an N-type dopant. The layer thickness is preferably 3 μm or more. The doping concentration of silicon is, for example, 10 ¹⁸ cm ⁻³ .
More specifically, the N-type contact layer 21 is grown on the first N-type GaN layer 211 grown on the GaN substrate 1 (or on the AlN layer 8), and on the first N-type GaN layer 211. And a second N-type GaN layer 212. The first N-type GaN layer 211 is a layer grown under a condition where the V / III ratio, which is the ratio of the molar fraction of the nitrogen source (ammonia) to the molar fraction of the gallium source (trimethylgallium), is relatively low. The second N-type GaN layer 212 is a layer grown under conditions where the V / III ratio is relatively high. More specifically, the first N-type GaN layer 211 is grown with a V / III ratio in the range of 100 to 1000 (more preferably, 200 to 400, for example, 300). Is preferably 2 μm or more. On the other hand, the second N-type GaN layer 212 is grown with a V / III ratio in the range of 1000 to 10000 (more preferably 2000 to 4000, for example, 3000). For example, the film thickness is 1 μm or more. It is preferable to do.

The quantum well layer 22 is formed by alternately laminating a silicon-doped InGaN layer (for example, 3 nm thickness) and a GaN layer (for example, 9 nm thickness) for a predetermined period (for example, 5 periods). A GaN final barrier layer 25 (for example, 40 nm thick) is laminated between the quantum well layer 22 and the P-type electron blocking layer 23.
The P-type electron blocking layer 23 is composed of an AlGaN layer to which magnesium as a P-type dopant is added. The layer thickness is, for example, 28 nm. The doping concentration of magnesium is, for example, 3 × 10 ¹⁹ cm ⁻³ .

The P-type contact layer 24 is composed of a GaN layer to which magnesium as a P-type dopant is added at a high concentration. The layer thickness is, for example, 70 nm. The doping concentration of magnesium is, for example, 10 ²⁰ cm ⁻³ .
The anode electrode 3 is composed of a transparent thin metal layer (for example, 200 mm or less) composed of Ni and Au.

The cathode electrode is a film composed of Ti and an Al layer.
The GaN substrate 1 is a substrate made of GaN having a main surface other than the c-plane. More specifically, the main surface is a nonpolar surface or a semipolar surface. More specifically, the main surface of the GaN substrate 1 is a surface having an off angle within ± 1 ° from the plane orientation of the nonpolar plane, or an off angle within ± 1 ° from the plane orientation of the semipolar plane. It is a surface having The GaN substrate 1 is preferably a single crystal substrate.

  FIG. 2 is an illustrative view showing a unit cell having a crystal structure of a group III nitride semiconductor. The crystal structure of the group III nitride semiconductor can be approximated by a hexagonal system, and the surface (the top surface of the hexagonal column) whose normal is the c axis along the axial direction of the hexagonal column is the c plane (0001). . In the group III nitride semiconductor, the polarization direction is along the c-axis. For this reason, the c-plane is called a polar plane because it exhibits different properties on the + c-axis side and the −c-axis side. On the other hand, the side surfaces of the hexagonal columns are m-planes (10-10), respectively, and the plane passing through a pair of ridge lines that are not adjacent to each other is the a-plane (11-20). Since these are crystal planes perpendicular to the c-plane and orthogonal to the polarization direction, they are nonpolar planes, that is, nonpolar planes. Furthermore, since the crystal plane inclined with respect to the c-plane (not parallel nor perpendicular) intersects the polarization direction obliquely, it has a slightly polar plane, that is, a semipolar plane (Semipolar plane). Plane). Specific examples of the semipolar plane include planes such as the (10-1-1) plane, the (10-1-3) plane, and the (11-22) plane.

Non-Patent Document 1 shows the relationship between the declination of the crystal plane relative to the c-plane and the polarization in the normal direction of the crystal plane. From this non-patent document 1, the (11-24) plane, the (10-12) plane, etc. are also low-polarization crystal planes, and may be adopted to extract light in a large polarization state. It can be said that.
For example, a GaN single crystal substrate having an m-plane as a main surface can be produced by cutting out from a GaN single crystal having a c-plane as a main surface. The m-plane of the cut substrate is polished by, for example, a chemical mechanical polishing process, and an orientation error with respect to both the (0001) direction and the (11-20) direction is within ± 1 ° (preferably ± 0.3). (Within °). In this way, a GaN single crystal substrate having the m-plane as the main surface and free from crystal defects such as dislocations and stacking faults can be obtained. There is only an atomic level step on the surface of such a GaN single crystal substrate.

On the GaN single crystal substrate thus obtained, a light emitting diode (LED) structure is grown by MOCVD.
FIG. 3 is an illustrative view for explaining a configuration of a processing apparatus for growing each layer constituting the GaN semiconductor layer 2. A susceptor 32 incorporating a heater 31 is disposed in the processing chamber 30. The susceptor 32 is coupled to a rotation shaft 33, and the rotation shaft 33 is rotated by a rotation drive mechanism 34 disposed outside the processing chamber 30. Thus, by holding the wafer 35 to be processed on the susceptor 32, the wafer 35 can be heated to a predetermined temperature in the processing chamber 30 and can be rotated. The wafer 35 is, for example, a GaN single crystal wafer constituting the GaN substrate 1 described above.

An exhaust pipe 36 is connected to the processing chamber 30. The exhaust pipe 36 is connected to exhaust equipment such as a rotary pump. Thereby, the pressure in the processing chamber 30 is set to 1/10 atm to normal pressure, and the atmosphere in the processing chamber 30 is always exhausted.
On the other hand, a raw material gas supply path 40 for supplying a raw material gas toward the surface of the wafer 35 held by the susceptor 32 is introduced into the processing chamber 30. The source gas supply path 40 includes an ammonia source pipe 41 for supplying ammonia as a nitrogen source gas, a gallium source pipe 42 for supplying trimethylgallium (TMG) as a gallium source gas, and trimethylaluminum as an aluminum source gas. An aluminum raw material pipe 43 for supplying (TMAl), an indium raw material pipe 44 for supplying trimethylindium (TMIn) as an indium raw material gas, and ethylcyclopentadienylmagnesium (EtCp ₂ Mg) as a magnesium raw material gas are supplied. A magnesium raw material pipe 45 and a silicon raw material pipe 46 for supplying silane (SiH ₄ ) as a silicon raw material gas are connected. Valves 51 to 56 are interposed in these raw material pipes 41 to 46, respectively. Each source gas is supplied together with a carrier gas composed of hydrogen, nitrogen, or both.

  For example, a GaN single crystal wafer having an m-plane as a main surface is held on the susceptor 32 as a wafer 35. In this state, the valves 52 to 56 are closed, the ammonia material valve 51 is opened, and the carrier gas and ammonia gas (nitrogen material gas) are supplied into the processing chamber 30. Further, the heater 31 is energized, and the wafer temperature is raised to 1000 ° C. to 1100 ° C. (for example, 1050 ° C.). As a result, the GaN semiconductor can be grown without causing surface roughness.

  After waiting until the wafer temperature reaches 1000 ° C. to 1100 ° C., the gallium material valve 52 and the silicon material valve 56 are opened. Thereby, trimethylgallium and silane are supplied from the source gas supply path 40 together with the carrier gas. As a result, an N-type contact layer 21 made of a GaN layer doped with silicon grows on the surface of the wafer 35.

  In the growth process of the N-type contact layer 21, each of the nitrogen source gas and the gallium source gas is set so that the V / III ratio becomes a value within the range of 100 to 1000 (for example, 300) in the first period. The flow rate is set. Thereby, the first N-type GaN layer 211 is formed. In the subsequent period, the flow rates of the nitrogen source gas and the gallium source gas are set so that the V / III ratio becomes a value within the range of 1000 to 10,000 (for example, 3000). That is, during the growth process of the N-type contact layer 21, the flow rate of the nitrogen source gas and / or the gallium source gas is changed halfway. Thereby, the second N-type GaN layer 212 is continuously formed on the first N-type GaN layer 211.

When the AlN layer 8 is formed on the wafer 35, the ammonia source valve 51 and the aluminum source gas valve 52 are opened before the N-type contact layer 21 is formed. Thereby, the AlN layer 8 can be formed on the surface of the wafer 35.
After the N-type contact layer 21 is formed, next, the silicon source valve 56 is closed, and the quantum well layer 22 is grown. The quantum well layer 22 is grown by opening an ammonia source valve 51, a gallium source valve 52, and an indium source valve 54 to supply ammonia, trimethylgallium and trimethylindium to the wafer 35, and growing an InGaN layer. The step of growing the additive-free GaN layer can be performed alternately by closing the material valve 54 and opening the ammonia material valve 51 and the gallium material valve 52 to supply ammonia and trimethylgallium to the wafer 35. . For example, a GaN layer is formed first, and an InGaN layer is formed thereon. After this is repeated five times, finally, the GaN final barrier layer 25 is formed on the InGaN layer. When the quantum well layer 22 and the GaN final barrier layer 25 are formed, the temperature of the wafer 35 is preferably set to 700 ° C. to 800 ° C. (for example, 730 ° C.), for example.

  Next, a P-type electron blocking layer 23 is formed. That is, the ammonia material valve 51, the gallium material valve 52, the aluminum material valve 53, and the magnesium material valve 55 are opened, and the other valves 54 and 56 are closed. As a result, ammonia, trimethylgallium, trimethylaluminum, and ethylcyclopentadienylmagnesium are supplied toward the wafer 35, and a P-type electron blocking layer 23 made of an AlGaN layer doped with magnesium is formed. When forming the P-type electron blocking layer 23, the temperature of the wafer 35 is preferably set to 1000 ° C. to 1100 ° C. (for example, 1000 ° C.).

  Next, a P-type contact layer 24 is formed. That is, the ammonia material valve 51, the gallium material valve 52, and the magnesium material valve 55 are opened, and the other valves 53, 54, and 56 are closed. As a result, ammonia, trimethylgallium and ethylcyclopentadienylmagnesium are supplied toward the wafer 35, and the P-type contact layer 24 made of a GaN layer doped with magnesium is formed. When the P-type contact layer 24 is formed, the temperature of the wafer 35 is preferably set to 1000 ° C. to 1100 ° C. (for example, 1000 ° C.).

  Thus, when the GaN semiconductor layer 2 is grown on the wafer 35, the wafer 35 is transferred to an etching apparatus, and a recess for exposing the N-type contact layer 21 by plasma etching, for example, as shown in FIG. 7 is formed. The recess 7 may be formed so as to surround the quantum well layer 22, the P-type electron blocking layer 23 and the P-type contact layer 24 in an island shape, whereby the quantum well layer 22, the P-type electron blocking layer 23 and the P-type contact layer 24 are formed. The mold contact layer 24 may be shaped into a mesa shape.

Furthermore, the anode electrode 3, the connection part 4, and the cathode electrode 5 are formed by the metal vapor deposition apparatus by resistance heating or an electron beam. Thereby, the light emitting diode structure shown in FIG. 1 can be obtained.
After such a wafer process, the individual elements are cut out by cleaving the wafer 35, and the individual elements are connected to the lead electrodes by die bonding and wire bonding, and then sealed in a transparent resin such as an epoxy resin. . Thus, a light emitting diode element is manufactured.

  As described above, in this embodiment, the N-type contact layer 21 is the second N-type GaN grown on the first N-type GaN layer 211 grown on the low V / III ratio under the high V / III ratio. The layer 212 has a stacked structure. Since the first N-type GaN layer 211 is grown under conditions with a low V / III ratio, the growth rate of the N-polar surface is increased, and as a result, the first N-type GaN layer 211 is formed into a flat film. Therefore, the second N-type GaN layer 212 continuously grown on the first N-type GaN layer 211 is also a flat film. Since the second N-type GaN layer 212 is grown under conditions with a high V / III ratio, the defect density is low. Thereby, non-radiative recombination can be suppressed and luminous efficiency can be improved.

When the layers 22 to 24 stacked on the N-type contact layer 21 are grown, for example, the mole content of the gallium raw material (trimethylgallium) supplied to the wafer 35 in the processing chamber 30 in the growth of any layer. The V / III ratio, which is the ratio of the molar fraction of the nitrogen raw material (ammonia) to the rate, is maintained at a high value of 3000 or more.
As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form. For example, in the above-described embodiment, the example in which the present invention is applied to the formation of a light emitting diode structure has been described. However, the present invention is not limited to other light emitting devices such as a laser diode, but also other electrons such as a transistor and a diode. It can also be applied to device fabrication.

In the above-described embodiment, the example in which the GaN semiconductor layer 2 is regrown on the GaN substrate 1 has been described. For example, on the silicon carbide substrate having the m-plane as the main surface, the growth main surface is defined as the m-plane. The grown GaN semiconductor layer may be grown.
In the above-described embodiment, the example in which the anode electrode 3 as the transparent electrode is formed of the Ni / Au film has been described. However, a transparent electrode made of a metal oxide film such as ZnO or ITO is applied to the anode electrode 3. May be.

  In addition, various design changes can be made within the scope of matters described in the claims.

1 is a schematic cross-sectional view for explaining a structure of a light emitting diode according to an embodiment of the present invention. FIG. 4 is an illustrative view showing a unit cell of a crystal structure of a group III nitride semiconductor. It is an illustration figure for demonstrating the structure of the processing apparatus for growing each layer which comprises a GaN semiconductor layer.

Explanation of symbols

1 GaN substrate 2 GaN semiconductor layer 3 Anode electrode (transparent electrode)
4 connection portion 5 cathode electrode 7 recess 8 AlN layer 10 support substrate 11, 12 wiring 13, 14 bonding wire 21 N-type contact layer 211 1st N-type GaN layer 212 2nd N-type GaN layer 22 quantum well layer 23 P-type electron blocking layer 24 P-type contact layer 25 Final barrier layer 30 Processing chamber 31 Heater 32 Susceptor 33 Rotating shaft 34 Rotation drive mechanism 35 Wafer 36 Exhaust piping 40 Raw material gas supply passage 41 Ammonia raw material piping 42 Gallium raw material piping 43 Aluminum raw material piping 44 Indium raw material piping 45 Magnesium material piping 46 Silicon material piping 51 Ammonia material valve 52 Gallium material valve 53 Aluminum material valve 54 Indium material valve 55 Magnesium material valve 56 Silicon material valve

Claims (20)

A first group III nitride semiconductor layer having a V / III ratio, which is a ratio of a nitrogen source to a group III element source, of a predetermined first V / III ratio and having a main growth surface other than the c-plane;
A second group III nitride provided on the first group III nitride semiconductor layer, having a second V / III ratio higher than the first V / III ratio and having the same main growth surface as the first group III nitride semiconductor layer A nitride semiconductor device including a semiconductor layer. A substrate,
An AlN layer formed on the substrate;
The nitride semiconductor device according to claim 1, wherein the first group III nitride semiconductor layer is formed on the AlN layer. The first and second group III nitride semiconductor layers are gallium nitride semiconductor layers having an m-plane growth main surface;
The nitride semiconductor device according to claim 2, wherein the substrate is a silicon carbide substrate having an m-plane as a main surface. The first and second group III nitride semiconductor layers are gallium nitride semiconductor layers having an m-plane growth main surface;
The nitride semiconductor device according to claim 2, wherein the substrate is a gallium nitride substrate having an m-plane as a main surface.   5. The nitride semiconductor device according to claim 1, wherein a main growth surface of the first and second group III nitride semiconductor layers is a nonpolar plane or a semipolar plane.   The nitride semiconductor device according to any one of claims 1 to 5, wherein the first V / III ratio is a value within a range of 100 to 1000.   The nitride semiconductor device according to any one of claims 1 to 6, wherein the second V / III ratio is a value within a range of 1000 to 10,000.   The nitride semiconductor device according to claim 1, wherein a thickness of the first group III nitride semiconductor layer is 2 μm or more.   The nitride semiconductor device according to any one of claims 1 to 8, wherein the first and second group III nitride semiconductor layers are group III nitride semiconductor layers doped with silicon.   The nitride according to any one of claims 1 to 9, wherein a plurality of group III nitride semiconductor layers whose conductivity type is controlled by doping impurities are formed on the second group III nitride semiconductor layer. Semiconductor device. A method of growing a group III nitride semiconductor having a growth principal surface other than c-plane,
A step of growing a first group III nitride semiconductor layer having a growth principal surface other than the c-plane under a growth condition in which a V / III ratio, which is a ratio of a nitrogen source to a group III element source, is a predetermined first V / III ratio; ,
A second group III nitride semiconductor layer having the same growth principal surface as the first group III nitride semiconductor layer is grown on the first group III nitride semiconductor layer under the second V / III ratio growth condition higher than the first V / III ratio. And a method of growing the nitride semiconductor. Further comprising growing an AlN layer on the substrate;
The nitride semiconductor manufacturing method according to claim 11, wherein the first group III nitride semiconductor layer is grown on the AlN layer. The first and second group III nitride semiconductor layers are gallium nitride semiconductor layers having an m-plane growth main surface;
The nitride semiconductor manufacturing method according to claim 12, wherein the substrate is a silicon carbide substrate having an m-plane as a main surface. The first and second group III nitride semiconductor layers are gallium nitride semiconductor layers having an m-plane growth main surface;
The nitride semiconductor manufacturing method according to claim 12, wherein the substrate is a gallium nitride substrate having an m-plane as a main surface.   The nitride semiconductor manufacturing method according to any one of claims 11 to 14, wherein a growth main surface of the first and second group III nitride semiconductor layers is a nonpolar surface or a semipolar surface.   The nitride semiconductor manufacturing method according to any one of claims 11 to 15, wherein the first V / III ratio is a value within a range of 100 to 1000.   The nitride semiconductor manufacturing method according to any one of claims 11 to 16, wherein the second V / III ratio is a value within a range of 1000 to 10,000.   The nitride semiconductor manufacturing method according to claim 11, wherein the first group III nitride semiconductor layer is grown to a thickness of 2 μm or more.   The nitride semiconductor according to any one of claims 11 to 18, wherein the step of growing the first and second group III nitride semiconductor layers is a step of growing a group III nitride semiconductor while doping silicon. Production method.   20. The method according to claim 11, further comprising growing a plurality of group III nitride semiconductor layers on the second group III nitride semiconductor layer while doping impurities to control a conductivity type. Nitride semiconductor manufacturing method.

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