JP2008153286A - Nitride semiconductor laminate structure, nitride semiconductor apparatus and manufacturing method for the nitride semiconductor laminate structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nitride semiconductor laminate structure having a group III nitride semiconductor layer, having a growing main plane other than a c-face and less crystal defect, and to provide a manufacturing method therefor and a nitride semiconductor apparatus, equipped with such a nitride-gallium semiconductor laminate structure. <P>SOLUTION: A GaN substrate 1 has a main face other than a c-plane (e.g., m-plane). A GaN semiconductor layer 2 is formed on the GaN substrate 1 by an organic metal chemical vapor phase growth method. A plurality of protrusions 60 forming stripes parallel to the c-face is arranged on the main plane of the GaN semiconductor substrate 1. Masks 65, each of which has a growth regulating surface 66 parallel to the c-face, are formed along negative-c axis side faces 62 of the protrusions 60. An N-type contact layer 21 is formed by a lateral selection growth anisotropic in a positive-c axis direction so as to cover the masks 65 from a region between the masks 65. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to nitride semiconductor devices such as nitride semiconductor light emitting elements (light emitting diodes, laser diodes, etc.), nitride semiconductor electronic devices (transistors, diodes, etc.) such as power device high frequency devices, and such nitride semiconductors. The present invention relates to a nitride semiconductor multilayer structure that can be applied to manufacture of a device, and a method for manufacturing a nitride semiconductor multilayer structure.

A semiconductor using nitrogen as a group V element in a group III-V semiconductor is called a “group III nitride semiconductor”, and typical examples thereof are aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN). is there. In general, it can be expressed as Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1), which is expressed as “gallium nitride semiconductor” or “GaN semiconductor”. I will say.

  A nitride semiconductor manufacturing method is known in which a group III nitride semiconductor is grown on a gallium nitride (GaN) substrate having a c-plane as a main surface by metal organic chemical vapor deposition (MOCVD). By applying this method, a GaN semiconductor multilayer structure having an N-type layer and a P-type layer can be formed, and a light-emitting device using this multilayer structure can be manufactured. Such a light emitting device can be used as a light source of a backlight for a liquid crystal panel, for example.

  The main surface of the GaN semiconductor regrowth on the GaN substrate having the c-plane as the main surface is the c-plane. The light extracted from the c-plane is in a randomly polarized (non-polarized) state. Therefore, when incident on the liquid crystal panel, other than the specific polarized light corresponding to the incident side polarizing plate is shielded and does not contribute to the luminance toward the emission side. Therefore, there is a problem that it is difficult to realize a display with high luminance (efficiency is 50% at the maximum).

  In order to solve this problem, a GaN semiconductor having a main surface other than the c-plane, that is, a non-polar (non-polar) surface such as a-plane or m-plane, or a semi-polar (semi-polar) surface is grown. Fabrication is under consideration. When a light-emitting device having a P-type layer and an N-type layer is manufactured using a GaN semiconductor layer having a nonpolar surface or a semipolar surface as a main surface, light having a strong polarization state can be emitted. Therefore, the loss in the incident side polarizing plate can be reduced by matching the polarization direction of such a light emitting device with the direction of the passing polarized light of the incident side polarizing plate of the liquid crystal panel. As a result, a display with high luminance can be realized.

However, a GaN semiconductor is formed on a nonpolar surface such as m-plane (10-10) or a-plane (11-20) or a semipolar surface such as (10-11) (10-13) or (11-22). When grown, an N-polar plane (−c plane) such as a (000-1) plane is formed in the lateral direction or oblique direction, and many stacking faults enter the GaN semiconductor growth layer.
Thus, even if a light emitting device is manufactured using a GaN semiconductor layer having many crystal defects, the external quantum efficiency is low and satisfactory light emission characteristics cannot be obtained.
T. Takeuchi et al., Jap. J. Appl. Phys. 39, 413-416, 2000 A. Chakraborty, BA Haskell, HS Keller, JS Speck, SP DenBaars, S. Nakamura and UK Mishra: Jap. J. Appl. Phys. 44 (2005) L173

  An object of the present invention is to provide a nitride semiconductor multilayer structure having a group III nitride semiconductor layer having a growth principal plane other than the c-plane and having few crystal defects, a method for manufacturing the same, and such a gallium nitride semiconductor multilayer structure. Another object of the present invention is to provide a nitride semiconductor device.

  In order to achieve the above object, the invention according to claim 1 is a semiconductor layer having a principal surface other than the c-plane, and is formed on the semiconductor layer in a stripe shape parallel to the c-plane and grown parallel to the c-plane. A + c axis so as to cover the mask from a mask made of a material other than a III-V semiconductor and a mask having a regulation surface (a growth regulation surface that regulates growth in the −c axis direction) And a group III nitride semiconductor layer having a main surface other than the c-plane, formed by anisotropic lateral selective growth in the direction.

  According to this configuration, since the striped mask has a growth regulation surface parallel to the c-plane, when the group III nitride semiconductor layer is selectively grown in the lateral direction in the region between the masks, the −c axis Crystal growth in the direction can be suppressed. Thereby, formation of the N polar face (-c face) can be suppressed, and only the Ga polar face (+ c face) can be selectively grown. Therefore, the group III nitride semiconductor layer is excellent in that there are few crystal defects. It becomes a thing. Therefore, by using such a semiconductor multilayer structure, a nitride semiconductor device having excellent characteristics can be realized. For example, when a light emitting device is manufactured, the external quantum efficiency can be increased, and excellent light emission characteristics can be realized.

According to a second aspect of the present invention, a convex part of a stripe pattern is formed on the main surface of the semiconductor layer, and preferably along the −c-axis side side surface of the convex part of the semiconductor layer (preferably from the convex part). The nitride semiconductor multilayer structure according to claim 1, wherein the mask is disposed.
The convex part of the stripe pattern forms a stripe shape parallel to the c-plane corresponding to the mask of the stripe pattern. The side surface of the convex portion on the −c axis side is covered with a mask. On the surface of the mask, the surface that covers the −c-axis side surface of the convex portion serves as a growth regulating surface that regulates crystal growth from the convex portion in the −c-axis direction. With such a configuration, the group III nitride semiconductor layer grown in the region between the masks becomes a semiconductor layer obtained by growing anisotropically from the + c-axis side surface of the convex portion in the + c-axis direction, Good crystallinity.

  The mask is preferably formed higher than the convex portion and protrudes from the −c-axis side side surface of the convex portion. In this case, the surface on the + c-axis side in the protruding portion is also a growth regulating surface. That is, with such a configuration, the group III nitride semiconductor layer grown in the region between the masks is anisotropically grown in the + c-axis direction from the + c-axis side surface of the convex portion, and the convex portion The layer obtained by anisotropic growth in the + c-axis direction while the growth in the −c-axis direction is regulated by the growth regulation surface of the mask. Therefore, such a group III nitride semiconductor layer has good crystallinity.

According to a third aspect of the present invention, the convex portion may be formed by processing the main surface of the semiconductor layer into an uneven shape.
According to a fourth aspect of the present invention, the convex portion may be formed by adding a convex portion made of a group III nitride semiconductor to the flat main surface of the semiconductor layer.
Furthermore, as described in claim 5, the mask may include a belt-shaped portion having an L-shaped cross section or an inverted T-shaped cross section formed on a flat main surface of the semiconductor layer.

  In this case, the group III nitride semiconductor layer is formed by crystal growth using the surface of the semiconductor layer exposed from between the L-shaped section or the T-shaped strip portion as a seed. In this case, the exposed portion of the semiconductor layer between the strips is located closer to the −c axis direction than the intermediate position between the strips, and is located near the growth regulating surface (the surface on the + c axis side) of the mask. It is preferable. As a result, crystal growth in the −c-axis direction can be effectively suppressed by the growth regulating surface of the mask, so that the group III nitride semiconductor layer has excellent crystallinity.

The semiconductor layer may include a substrate having a main surface other than the c-plane. A mask may be formed on the surface of the substrate, and the group III nitride semiconductor layer may be grown from the surface of the substrate.
In addition, as described in claim 7, the semiconductor layer may include a group III nitride semiconductor layer formed on the substrate and having a growth main surface other than the c-plane. In this case, a mask may be formed on the surface of the group III nitride semiconductor layer, and the group III nitride semiconductor layer may be grown from the surface of the group III nitride semiconductor layer.

Examples of the substrate include a sapphire substrate (for example, a surface having an r-plane as a main surface), a silicon carbide substrate (for example, a surface having an m-plane as a main surface), a gallium nitride substrate (for example, an a-plane or an m-plane as a main surface). Can be used).
Examples of the group III nitride semiconductor layer combined with these include those having a growth principal surface of the a-plane or m-plane. More specifically, an a-plane GaN layer is formed on an r-plane sapphire substrate, an m-plane GaN layer is formed on an m-plane silicon carbide substrate, or an a-plane GaN layer is formed on an a-plane gallium nitride substrate. Or an m-plane GaN layer may be formed on an m-plane gallium nitride substrate.

And as described in Claim 8, the main surface of the said group III nitride semiconductor layer may be a nonpolar surface or a semipolar surface. The plane orientation of the main surface of the group III nitride semiconductor layer follows the plane orientation of the main surface of the semiconductor layer.
According to a ninth aspect of the present invention, the mask preferably contains silicon oxide, silicon nitride, or silicon oxynitride.

The invention according to claim 10 is formed on the nitride semiconductor multilayer structure according to any one of claims 1 to 9 and the group III nitride semiconductor layer, and the conductivity type is controlled by doping impurities. A nitride semiconductor device including a plurality of group III nitride semiconductor layers. Thereby, a semiconductor device such as a diode or a transistor can be configured.
The invention according to claim 11 is a group III-V having a growth regulating surface (growth regulating surface for regulating growth in the −c axis direction) parallel to the c surface on the semiconductor layer having a principal surface other than the c surface A mask forming step of forming a mask made of a material other than a semiconductor in a stripe shape parallel to the c-plane and an anisotropic lateral selective growth in the + c-axis direction from the region between the stripe-shaped mask by III And a step of forming a group III nitride semiconductor layer having a principal surface other than the c-plane while growing the group nitride semiconductor, covering the mask, and the like.

According to this method, the group III nitride semiconductor layer can be grown by anisotropic lateral selective growth in the + c-axis direction while suppressing crystal growth in the −c-axis direction by the growth regulation surface of the mask. . As a result, the growth of the N-polar plane (-c plane) can be suppressed, so that an excellent crystalline group III nitride semiconductor layer can be formed.
The step of forming the group III nitride semiconductor layer according to claim 12 includes a hydride vapor phase epitaxy (HVPE) method, a metal organic chemical vapor deposition (MOCVD). It is preferably performed by a Vapor Deposition (MBE) method or a molecular beam epitaxy (MBE) method.

  In addition, the manufacturing method of the nitride semiconductor multilayer structure can be modified in the same manner as in the invention of the nitride semiconductor multilayer structure.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic sectional view for explaining the structure of a light emitting diode according to an embodiment of the present invention. This light emitting diode is configured by regrowing a GaN semiconductor layer 2 as a group III nitride semiconductor layer on a GaN (gallium nitride) substrate 1.
The GaN semiconductor layer 2 includes an N-type contact layer 21, a quantum well (QW) layer 22, a GaN final barrier layer 25, a P-type electron blocking layer 23, and a P-type in order from the GaN substrate 1 side. It has a laminated structure in which contact layers 24 are laminated. An anode electrode 3 as a transparent electrode is formed on the surface of the P-type contact layer 24, and a connection portion 4 for wiring connection is joined to a part of the anode electrode 3. The cathode electrode 5 is joined to the N-type contact layer 21. Thus, a light emitting diode structure is formed.

  The GaN substrate 1 is bonded to a support substrate (wiring substrate) 10. Wirings 11 and 12 are formed on the surface of the support substrate 10. The connection portion 4 and the wiring 11 are connected by a bonding wire 13, and the cathode electrode 5 and the wiring 12 are connected by a bonding wire 14. Further, although not shown in the drawings, the light emitting diode element is configured by sealing the light emitting diode structure and the bonding wires 13 and 14 with a transparent resin such as an epoxy resin.

The N-type contact layer 21 is composed of an N-type GaN layer to which silicon is added as an N-type dopant. The layer thickness is preferably 3 μm or more. The doping concentration of silicon is, for example, 10 ¹⁸ cm ⁻³ . More specifically, the N-type contact layer 21 is made of an N-type GaN semiconductor that is crystal-grown on the GaN substrate 1 (or on the AlN layer 8).
The quantum well layer 22 is formed by alternately laminating a silicon-doped InGaN layer (for example, 3 nm thickness) and a GaN layer (for example, 9 nm thickness) for a predetermined period (for example, 5 periods). A GaN final barrier layer 25 (for example, 40 nm thick) is laminated between the quantum well layer 22 and the P-type electron blocking layer 23.

The P-type electron blocking layer 23 is composed of an AlGaN layer to which magnesium as a P-type dopant is added. The layer thickness is, for example, 28 nm. The doping concentration of magnesium is, for example, 3 × 10 ¹⁹ cm ⁻³ .
The P-type contact layer 24 is composed of a GaN layer to which magnesium as a P-type dopant is added at a high concentration. The layer thickness is, for example, 70 nm. The doping concentration of magnesium is, for example, 10 ²⁰ cm ⁻³ .

The anode electrode 3 is composed of a transparent thin metal layer (for example, 200 mm or less) composed of Ni and Au.
The cathode electrode is a film composed of Ti and an Al layer.
The GaN substrate 1 is a substrate made of GaN having a main surface other than the c-plane. More specifically, the main surface is a nonpolar surface or a semipolar surface. The main surface of the GaN substrate 1 is subjected to uneven processing, and a plurality of ridges 60 formed in parallel at predetermined intervals are formed in stripes parallel to the c-plane. Each ridge 60 has a rectangular cross section, one side surface is a + c-axis side surface 61 facing the + c-axis direction of the GaN substrate 1, and the other side surface is facing the −c-axis direction of the GaN substrate 1. -The c-axis side surface 62. A top surface 63 parallel to the main surface of the GaN substrate 1 is formed between the side surfaces 61 and 62.

  The −c-axis side surface 62 of each ridge 60 is covered with a strip-shaped mask 65. Therefore, the mask 65 is formed in a stripe shape parallel to the c-plane on the main surface of the GaN substrate 1. In this example, the mask 65 is formed in a rectangular cross section and covers the entire area of the −c-axis side surface 62 of the ridge 60. The mask 65 is formed higher than the ridge 60 and protrudes above the −c-axis side surface 62. In the surface of the mask 65, the surface facing the + c axis direction forms the growth regulating surface 66. That is, the growth regulating surface 66 has a portion that covers the −c-axis side surface 62 of the ridge 60 and a portion that protrudes above the ridge 60.

  The N-type contact layer 21 is obtained by epitaxial growth from the surface of the GaN substrate 1 exposed in the region between the stripe-shaped masks 65, and crystal growth in the −c axis direction is performed by the action of the growth regulating surface 66. And is formed by anisotropic selective lateral growth in the + c-axis direction. For this reason, formation of an N-polar plane (-c plane) is suppressed, and thus excellent crystallinity is obtained.

  FIG. 2 is an illustrative view showing a unit cell having a crystal structure of a group III nitride semiconductor. The crystal structure of the group III nitride semiconductor can be approximated by a hexagonal system, and the surface (the top surface of the hexagonal column) whose normal is the c axis along the axial direction of the hexagonal column is the c plane (0001). . In the group III nitride semiconductor, the polarization direction is along the c-axis. For this reason, the c-plane is called a polar plane because it exhibits different properties on the + c-axis side and the −c-axis side. On the other hand, the side surfaces of the hexagonal columns are m-planes (10-10), respectively, and the plane passing through a pair of ridge lines that are not adjacent to each other is the a-plane (11-20). Since these are crystal planes perpendicular to the c-plane and orthogonal to the polarization direction, they are nonpolar planes, that is, nonpolar planes. Furthermore, since the crystal plane inclined with respect to the c-plane (not parallel nor perpendicular) intersects the polarization direction obliquely, it has a slightly polar plane, that is, a semipolar plane (Semipolar plane). Plane). Specific examples of the semipolar plane include planes such as the (10-1-1) plane, the (10-1-3) plane, and the (11-22) plane.

Non-Patent Document 1 shows the relationship between the declination of the crystal plane relative to the c-plane and the polarization in the normal direction of the crystal plane. From this non-patent document 1, the (11-24) plane, the (10-12) plane, etc. are also low-polarization crystal planes, and may be adopted to extract light in a large polarization state. It can be said that.
For example, a GaN single crystal substrate having an m-plane as a main surface can be produced by cutting from a GaN single crystal having a c-plane as a main surface. The m-plane of the cut substrate is polished by, for example, a chemical mechanical polishing process, and an orientation error with respect to both the (0001) direction and the (11-20) direction is within ± 1 ° (preferably ± 0.3). (Within °). In this way, a GaN single crystal substrate having the m-plane as the main surface and free from crystal defects such as dislocations and stacking faults can be obtained. There is only an atomic level step on the surface of such a GaN single crystal substrate.

A light emitting diode (LED) structure can be grown on the GaN single crystal substrate thus obtained by MOCVD.
FIG. 3 is a cross-sectional view showing a method of forming the N-type contact layer 21 in the order of steps.
First, the main surface of the GaN substrate 1 whose main surface is the m-plane (10-10) (or a-plane (11-20)) is subjected to uneven processing by etching treatment, and a plurality of ridges 60 are striped. (Fig. 3 (a)). Then, a striped pattern mask 65 is formed so as to cover the −c-axis side surface 62 of each ridge 60 (FIG. 3B). The mask 65 can be made of, for example, silicon oxide, silicon nitride, or silicon oxynitride. After a film of such a material is formed on the entire surface of the GaN substrate 1, a resist pattern corresponding to the pattern of the mask 65 is formed on the substrate 1 by photolithography, and etching is performed using this resist pattern as an etching mask. Thus, a stripe-shaped mask 65 can be formed.

Thereafter, an N-type contact layer covering the area above the mask 65 from the region between the masks 65 by growing a GaN semiconductor on the GaN substrate 1 under the condition that the c-plane is easy to grow while doping silicon by MOCVD. 21 can be formed.
The GaN semiconductor 20 is crystal-grown using the top surface 63 and the + c-axis side surface 61 of the ridge 60 and the surface of the GaN substrate 1 between the ridge 60 and the mask 65 as seeds (FIG. 3C). At this time, crystal growth is performed under the condition that the c-plane is easy to grow, so that the lateral selective growth from the + c-axis side surface 61 proceeds. On the other hand, the −c-axis side surface 62 of the ridge 60 is covered by the growth regulating surface 66 of the mask 65, and further, the growth regulating surface 65 extends to a position higher than the ridge 60. Crystal growth in the axial direction is suppressed. As a result, anisotropic lateral selective growth in the + c-axis direction proceeds. When the region between the masks 65 is filled by this lateral selective growth, the GaN semiconductor 20 grows so as to cover the region above the mask 65. Thus, the N-type contact layer 21 is obtained (FIG. 3D). 3 (c) and 3 (d), the surface shape of the crystal in the middle of growth is shown stepwise in order to represent the state of crystal growth of the GaN semiconductor 20.

  Since the N-type contact layer 21 is obtained by crystal growth in a state where formation of the N pole face (-c face) is suppressed, the crystal defect density is low and the crystallinity is good. The plane orientation of the main surface of the N-type contact layer 21 follows the plane orientation of the main surface of the GaN substrate 1. That is, if the main surface of the GaN substrate 1 is m-plane, the main surface of the N-type contact layer 21 is also m-plane. If the main surface of the GaN substrate 1 is a-plane, the main surface of the N-type contact layer 21 is also a-plane. is there.

Each of the layers 22 to 25 further epitaxially grown on the N-type contact layer 21 also has the same main surface as the N-type contact layer 21.
FIG. 4 is an illustrative view for explaining the configuration of a processing apparatus for growing each layer constituting the GaN semiconductor layer 2. A susceptor 32 incorporating a heater 31 is disposed in the processing chamber 30. The susceptor 32 is coupled to a rotation shaft 33, and the rotation shaft 33 is rotated by a rotation drive mechanism 34 disposed outside the processing chamber 30. Thus, by holding the wafer 35 to be processed on the susceptor 32, the wafer 35 can be heated to a predetermined temperature in the processing chamber 30 and can be rotated. The wafer 35 is, for example, a GaN single crystal wafer constituting the GaN substrate 1 described above. On the main surface of the wafer 35, a stripe pattern ridge 60 and a stripe pattern mask 65 are formed.

An exhaust pipe 36 is connected to the processing chamber 30. The exhaust pipe 36 is connected to exhaust equipment such as a rotary pump. Thereby, the pressure in the processing chamber 30 is set to 1/10 atm to normal pressure, and the atmosphere in the processing chamber 30 is always exhausted.
On the other hand, a raw material gas supply path 40 for supplying a raw material gas toward the surface of the wafer 35 held by the susceptor 32 is introduced into the processing chamber 30. The source gas supply path 40 includes an ammonia source pipe 41 for supplying ammonia as a nitrogen source gas, a gallium source pipe 42 for supplying trimethylgallium (TMG) as a gallium source gas, and trimethylaluminum as an aluminum source gas. An aluminum raw material pipe 43 for supplying (TMAl), an indium raw material pipe 44 for supplying trimethylindium (TMIn) as an indium raw material gas, and ethylcyclopentadienylmagnesium (EtCp ₂ Mg) as a magnesium raw material gas are supplied. A magnesium raw material pipe 45 and a silicon raw material pipe 46 for supplying silane (SiH ₄ ) as a silicon raw material gas are connected. Valves 51 to 56 are interposed in these raw material pipes 41 to 46, respectively. Each source gas is supplied together with a carrier gas composed of hydrogen, nitrogen, or both.

  For example, a GaN single crystal wafer having an m-plane as a main surface is held on the susceptor 32 as a wafer 35. In this state, the valves 52 to 56 are closed, the ammonia material valve 51 is opened, and the carrier gas and ammonia gas (nitrogen material gas) are supplied into the processing chamber 30. Further, the heater 31 is energized, and the wafer temperature is raised to 1000 ° C. to 1100 ° C. (for example, 1050 ° C.). As a result, the GaN semiconductor can be grown without causing surface roughness.

  After waiting until the wafer temperature reaches 1000 ° C. to 1100 ° C., the gallium material valve 52 and the silicon material valve 56 are opened. Thereby, trimethylgallium and silane are supplied from the source gas supply path 40 together with the carrier gas. As a result, an N-type contact layer 21 made of a GaN layer doped with silicon grows on the surface of the wafer 35.

  In the growth process of the N-type contact layer 21, V / III is a ratio of the molar fraction of the nitrogen source (ammonia) to the molar fraction of the gallium source (trimethylgallium) supplied to the wafer 35 in the processing chamber 30. The flow rates of the nitrogen source gas and the gallium source gas are set so that the ratio is a value within the range of 1000 to 10,000 (for example, 3000). As a result, the growth of the c-plane is promoted, and the lateral selective growth of the GaN semiconductor can be performed on the GaN substrate 1.

  After the N-type contact layer 21 is formed, next, the silicon source valve 56 is closed, and the quantum well layer 22 is grown. The quantum well layer 22 is grown by opening an ammonia source valve 51, a gallium source valve 52, and an indium source valve 54 to supply ammonia, trimethylgallium and trimethylindium to the wafer 35, and growing an InGaN layer. The step of growing the additive-free GaN layer can be performed alternately by closing the material valve 54 and opening the ammonia material valve 51 and the gallium material valve 52 to supply ammonia and trimethylgallium to the wafer 35. . For example, a GaN layer is formed first, and an InGaN layer is formed thereon. After this is repeated five times, finally, the GaN final barrier layer 25 is formed on the InGaN layer. When the quantum well layer 22 and the GaN final barrier layer 25 are formed, the temperature of the wafer 35 is preferably set to 700 ° C. to 800 ° C. (for example, 730 ° C.), for example.

  Next, a P-type electron blocking layer 23 is formed. That is, the ammonia material valve 51, the gallium material valve 52, the aluminum material valve 53, and the magnesium material valve 55 are opened, and the other valves 54 and 56 are closed. As a result, ammonia, trimethylgallium, trimethylaluminum, and ethylcyclopentadienylmagnesium are supplied toward the wafer 35, and a P-type electron blocking layer 23 made of an AlGaN layer doped with magnesium is formed. When forming the P-type electron blocking layer 23, the temperature of the wafer 35 is preferably set to 1000 ° C. to 1100 ° C. (for example, 1000 ° C.).

  Next, a P-type contact layer 24 is formed. That is, the ammonia material valve 51, the gallium material valve 52, and the magnesium material valve 55 are opened, and the other valves 53, 54, and 56 are closed. As a result, ammonia, trimethylgallium and ethylcyclopentadienylmagnesium are supplied toward the wafer 35, and the P-type contact layer 24 made of a GaN layer doped with magnesium is formed. When the P-type contact layer 24 is formed, the temperature of the wafer 35 is preferably set to 1000 ° C. to 1100 ° C. (for example, 1000 ° C.).

  Thus, when the GaN semiconductor layer 2 is grown on the wafer 35, the wafer 35 is transferred to an etching apparatus, and a recess for exposing the N-type contact layer 21 by plasma etching, for example, as shown in FIG. 7 is formed. The recess 7 may be formed so as to surround the quantum well layer 22, the P-type electron blocking layer 23 and the P-type contact layer 24 in an island shape, whereby the quantum well layer 22, the P-type electron blocking layer 23 and the P-type contact layer 24 are formed. The mold contact layer 24 may be shaped into a mesa shape.

Furthermore, the anode electrode 3, the connection part 4, and the cathode electrode 5 are formed by the metal vapor deposition apparatus by resistance heating or an electron beam. Thereby, the light emitting diode structure shown in FIG. 1 can be obtained.
After such a wafer process, the individual elements are cut out by cleaving the wafer 35, and the individual elements are connected to the lead electrodes by die bonding and wire bonding, and then sealed in a transparent resin such as an epoxy resin. . Thus, a light emitting diode element is manufactured.

  As described above, in this embodiment, the N-type contact layer 21 is formed by anisotropic lateral selective growth in the + c-axis direction while suppressing crystal growth in the −c-axis direction. Therefore, the N-type contact layer 21 has fewer crystal defects, and accordingly, the defect density of each of the layers 22 to 24 formed on the N-type contact layer 21 is also suppressed. Thereby, non-radiative recombination can be suppressed and luminous efficiency can be improved.

  FIG. 5 is a cross-sectional view for explaining a second step of forming the N-type contact layer 21. In this example, a GaN semiconductor layer 69 having an m-plane as a main surface is epitaxially grown on a GaN substrate 1 having an m-plane as a main surface (in this example, a flat surface). The surface of the GaN semiconductor layer 69 is processed to be uneven by an etching process, whereby a plurality of ridges 70 are formed in a stripe shape. The plurality of ridges 70 are formed in parallel at a predetermined interval, and the direction of formation is parallel to the c-plane. Each ridge 70 has a rectangular cross section, and has a + c-axis side surface 71, a −c-axis side surface 72, and a top surface 73 between these side surfaces 71 and 72.

  A strip-shaped mask 75 having a rectangular cross section is formed along the −c-axis side surface 72 of each protrusion 70. Therefore, a plurality of strip-like masks 75 are formed in stripes on the main surface of the GaN semiconductor layer 69. The extending direction of each strip-shaped mask 75 is parallel to the c-plane. The mask 75 is formed at a height that projects upward from the ridge 70. The + c-axis side surface of the mask 75 is a growth regulating surface 76. The growth regulating surface 76 covers the −c-axis side surface 72 of the ridge 70, regulates crystal growth from the side surface 72, and regulates crystal growth in the −c-axis direction also above the ridge 70. To do. The mask 75 is formed by a photolithography process.

  After the formation of the mask 75, the N-type contact layer 21 is formed by MOCVD. This forming method is the same as described above. In this case, the crystal of the GaN semiconductor constituting the N-type contact layer 21 is mainly formed by anisotropic lateral selective growth from the + c-axis side surface 71 of the ridge 70 in the + c-axis direction. Become. FIG. 5 shows the surface shape of the crystal during the growth step by step in order to represent the state of crystal growth of the GaN semiconductor.

  In the region up to the top surface 73 of the ridge 70, the growth regulating surface 76 of the mask 75 covers the −c axis side surface 72 of the ridge 70, so that crystal growth on the −c axis side is regulated. Even in the region above the ridge 70, crystal growth in the −c axis direction is suppressed by the action of the growth regulating surface 76 of the mask 75. Thus, the N-type contact layer 21 can be formed by crystal growth of the GaN semiconductor while suppressing the formation of the N-polar plane (−c plane). Therefore, the N-type contact layer 21 has good crystallinity with a low defect density.

  FIG. 6 is a cross-sectional view for explaining a third formation step of the N-type contact layer 21. In this example, a plurality of ridges 80 are formed by adding a GaN semiconductor on the GaN substrate 1 having a flat main surface (m-plane). The plurality of ridges 80 can be obtained by epitaxially growing a GaN semiconductor layer on the GaN semiconductor substrate 1 and etching the GaN semiconductor layer into a stripe pattern until the GaN semiconductor substrate 1 is exposed.

The extending direction of the ridges 80 is parallel to the c-plane. The ridge 80 is formed in a rectangular cross section, and has a + c-axis side surface 81, a −c-axis side surface 82, and a top surface 83 therebetween.
A strip-shaped mask 85 having a rectangular cross section is formed along the −c-axis side surface 82 of each protrusion 80. Therefore, a plurality of strip-like masks 85 are formed in stripes on the main surface of the GaN substrate 1. The extending direction of each strip-shaped mask 85 is parallel to the c-plane. The mask 85 is formed at a height that projects upward from the ridge 80. The + c-axis side surface of the mask 85 is a growth regulating surface 86. The growth regulating surface 86 covers the −c-axis side surface 82 of the ridge 80, regulates crystal growth from the side surface 82, and regulates crystal growth in the −c-axis direction also above the ridge 80. To do. The mask 85 is formed by a photolithography process.

  After the formation of the mask 85, the N-type contact layer 21 is formed by MOCVD. This forming method is the same as described above. In this case, the GaN semiconductor crystal constituting the N-type contact layer 21 is mainly formed by anisotropic lateral selective growth in the + c-axis direction from the + c-axis side surface 81 of the ridge 80. FIG. 6 shows the surface shape of the crystal during the growth step by step in order to express the state of crystal growth of the GaN semiconductor.

  In the region up to the top surface 83 of the ridge 80, the growth regulating surface 86 of the mask 85 covers the −c axis side surface 82 of the ridge 80, so that crystal growth on the −c axis side is regulated. Even in the region above the ridge 80, crystal growth in the −c axis direction is suppressed by the action of the growth regulating surface 86 of the mask 85. Thus, since the GaN semiconductor can be crystal-grown while suppressing the formation of the N-polar plane (-c plane), the N-type contact layer 21 has good crystallinity with a low defect density.

  FIG. 7 is a cross-sectional view for explaining a fourth step of forming the N-type contact layer 21. In this example, the main surface (m-plane) of the GaN substrate 1 is flat, and a plurality of strip-shaped masks 90 having an L-shaped cross section are formed in stripes on the flat main surface. The extending direction of the mask 90 is parallel to the c-plane. Each mask 90 has a bottom 91 parallel to the main surface of the GaN substrate 1 and a growth regulating wall 92 rising from the + c-axis side edge of the bottom 91. The growth regulating surface 93 is a side surface on the + c axis side of the growth regulating wall 92. In the band-like region between the −c-axis side edge of the bottom portion 91 and the growth regulating surface 93, the GaN substrate 1 is exposed. The exposed portion 95 serves as a seed for growing the GaN semiconductor crystal (N-type contact layer 21).

The mask 85 is formed by a photolithography process. More specifically, first, the bottom 91 is formed by photolithography, and the growth regulating wall 92 may be formed by photolithography on the + c-axis side edge of the bottom 91.
After the formation of the mask 85, the N-type contact layer 21 is formed by MOCVD. In this case, the GaN semiconductor crystal constituting the N-type contact layer 21 is first grown to a state protruding from the bottom 91 of the mask 90 by selective growth in the vertical direction from the exposed portion 95. Thereafter, anisotropic growth in the + c-axis direction is performed by lateral direction selective growth. The crystal growth toward the −c axis is suppressed by the action of the growth regulating surface 93 of the mask 90. By continuing the crystal growth after the GaN semiconductor crystal reaches the upper end of the mask 90, the N-type contact layer 21 reaching the region covering the mask 90 is formed. Thus, since the GaN semiconductor can be crystal-grown while suppressing the formation of the N-polar plane (-c plane), the N-type contact layer 21 has good crystallinity with a low defect density.

  FIG. 8 is a cross-sectional view for explaining a fifth step of forming the N-type contact layer 21. In FIG. 8, parts corresponding to the parts shown in FIG. 7 are given the same reference numerals as those in FIG. In this example, the main surface (m-plane) of the GaN substrate 1 is flat, and a GaN semiconductor layer 89 is epitaxially grown on the flat main surface. The main surface (m-plane) of the GaN semiconductor layer 89 is a flat surface, and a plurality of strip-shaped masks 90 having an L-shaped cross section are formed on the main surface in stripes. The extending direction of the mask 90 is parallel to the c-plane. Each mask 90 has a bottom 91 parallel to the main surface of the GaN semiconductor layer 89 and a growth regulating wall 92 rising from the + c-axis side edge of the bottom 91. The growth regulating surface 93 is a side surface on the + c axis side of the growth regulating wall 92. The GaN semiconductor layer 89 is exposed in the band-like region between the −c-axis side edge of the bottom portion 91 and the growth regulating surface 93. The exposed portion 96 serves as a seed for growing the GaN semiconductor crystal (N-type contact layer 21).

  After the formation of the mask 85, the N-type contact layer 21 is formed by MOCVD. In this case, the GaN semiconductor crystal constituting the N-type contact layer 21 is first grown to a state protruding from the bottom portion 91 of the mask 90 by selective growth in the vertical direction from the exposed portion 96. Thereafter, anisotropic growth in the + c-axis direction is performed by lateral direction selective growth. The crystal growth toward the −c axis is suppressed by the action of the growth regulating surface 93 of the mask 90. By continuing the crystal growth after the GaN semiconductor crystal reaches the upper end of the mask 90, the N-type contact layer 21 reaching the region covering the mask 90 is formed. Thus, since the GaN semiconductor can be crystal-grown while suppressing the formation of the N-polar plane (-c plane), the N-type contact layer 21 has good crystallinity with a low defect density.

  FIG. 9 is a cross-sectional view for explaining a sixth step of forming the N-type contact layer 21. In FIG. 9, parts that are the same as the parts shown in FIG. 8 are given the same reference numerals. In this example, in this example, a plurality of strip-like masks 100 having a reverse T-shaped cross section are formed in stripes on the flat main surface (m-plane) of the GaN semiconductor layer 89. The extending direction of the mask 100 is parallel to the c-plane. Each mask 100 has a bottom 101 parallel to the main surface of the GaN semiconductor layer 89 and a growth regulating wall 102 rising from a position near the + c-axis side edge of the bottom 101. A growth regulating surface 103 is a side surface on the + c axis side of the growth regulating wall 102. Between adjacent masks 100, a GaN semiconductor layer 89 is formed in a band-like region between the −c-axis side edge of the bottom 101 in one mask 100 and the + c-axis side edge of the bottom 101 in the other mask 100. Exposed. The exposed portion 96 serves as a seed for growing the GaN semiconductor crystal (N-type contact layer 21).

The mask 100 is formed by a photolithography process. More specifically, first, the bottom 101 is formed by photolithography, and the growth regulating wall 102 may be formed by photolithography near the + c-axis side edge of the bottom 101.
After the formation of the mask 100, the N-type contact layer 21 is formed by MOCVD. In this case, the GaN semiconductor crystal constituting the N-type contact layer 21 is first grown to a state protruding from the bottom 101 of the mask 100 by selective growth in the vertical direction from the exposed portion 96. Thereafter, anisotropic growth in the + c-axis direction is performed by lateral direction selective growth. Crystal growth toward the −c axis is suppressed by the action of the growth regulating surface 103 of the mask 100. By continuing the crystal growth after the GaN semiconductor crystal reaches the upper end of the mask 100, the N-type contact layer 21 reaching the region covering the mask 100 is formed. Thus, since the GaN semiconductor can be crystal-grown while suppressing the formation of the N-polar plane (-c plane), the N-type contact layer 21 has good crystallinity with a low defect density.

  As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form. For example, in the above-described embodiment, the example in which the present invention is applied to the formation of a light emitting diode structure has been described. However, the present invention is not limited to other light emitting devices such as a laser diode, but also other electrons such as a transistor and a diode. It can also be applied to device fabrication.

In the above-described embodiment, the example using the GaN substrate 1 mainly having the m-plane as the main surface has been described. However, a GaN substrate having the a-plane as the main surface may be used. Moreover, you may use the GaN board | substrate which uses a semipolar surface as a main surface, such as (10-11) plane, (10-13) plane, (11-22).
In the above-described example, the example in which the GaN semiconductor layer and the GaN semiconductor layer 2 are regrown on the GaN substrate 1 has been described. For example, the growth main surface is formed on the silicon carbide substrate having the m plane as the main surface. A GaN semiconductor having an m-plane may be grown, or a GaN semiconductor having an a-plane as a main surface may be grown on a sapphire substrate having an r-plane as a main surface.

Furthermore, in the above-described embodiment, the example in which the GaN semiconductor is epitaxially grown on the GaN substrate 1 by the MOCVD method has been described, but other epitaxial growth methods such as the HVPE method and the MBE method may be applied.
Further, in the examples of FIGS. 3, 5, and 6 described above, the example in which the masks 65, 75, and 85 are formed higher than the ridges 60, 70, and 80 has been described. Masks 65, 75, and 85 may be formed at the same height. Even in this case, crystal growth in the −c-axis direction from the −c-axis side side surfaces 62, 72, and 82 of the ridges 60, 70, and 80 can be regulated.

  In addition, various design changes can be made within the scope of matters described in the claims.

1 is a schematic cross-sectional view for explaining a structure of a light emitting diode according to an embodiment of the present invention. FIG. 4 is an illustrative view showing a unit cell of a crystal structure of a group III nitride semiconductor. It is sectional drawing which shows the formation method of an N type contact layer in order of a process. It is an illustration figure for demonstrating the structure of the processing apparatus for growing each layer which comprises a GaN semiconductor layer. It is sectional drawing for demonstrating the 2nd formation process of a N-type contact layer. It is sectional drawing for demonstrating the 3rd formation process of a N-type contact layer. It is sectional drawing for demonstrating the 4th formation process of a N-type contact layer. It is sectional drawing for demonstrating the 5th formation process of a N-type contact layer. It is sectional drawing for demonstrating the 6th formation process of a N-type contact layer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 GaN substrate 2 GaN semiconductor layer 3 Anode electrode 4 Connection part 5 Cathode electrode 7 Recessed part 10 Support substrate 11,12 Wiring 13,14 Bonding wire 20 GaN semiconductor 21 N-type contact layer 22 Quantum well layer 23 P-type electron blocking layer 24 P Type contact layer 25 Final barrier layer 30 Processing chamber 31 Heater 32 Susceptor 33 Rotating shaft 34 Rotation drive mechanism 35 Wafer 36 Exhaust piping 40 Raw material gas supply passage 41 Ammonia raw material piping 42 Gallium raw material piping 43 Aluminum raw material piping 44 Indium raw material piping 45 Magnesium raw material Piping 46 Silicon raw material piping 51 Ammonia raw material valve 52 Gallium raw material valve 53 Aluminum raw material valve 54 Indium raw material valve 55 Magnesium raw material valve 56 Silicon raw material valve 60 Projection 6 + C-axis side surface 62 -c-axis side surface 63 top surface 65 mask 65 growth regulation surface 66 growth regulation surface 69 GaN semiconductor layer 70 ridge 71 + c-axis side surface 72 -c-axis side surface 73 top surface 75 mask 76 growth regulation surface 80 ridge 81 + c-axis side surface 82 −c-axis side surface 83 top surface 85 mask 86 growth regulating surface 89 GaN semiconductor layer 90 mask 91 bottom portion 92 growth regulating wall 93 growth regulating surface 95 exposed portion 96 exposed portion 100 mask 101 bottom portion 102 Growth regulation wall 103 Growth regulation surface

Claims (12)

a semiconductor layer having a principal surface other than the c-plane;
A mask formed on the semiconductor layer in a stripe shape parallel to the c-plane, having a growth regulating surface parallel to the c-plane, and made of a material other than a III-V semiconductor;
A group III nitride semiconductor layer formed by anisotropic lateral selective growth in the + c-axis direction so as to cover the mask from the region between the masks and having a main surface other than the c-plane. Semiconductor semiconductor laminated structure.   The nitride semiconductor according to claim 1, wherein a convex portion of a stripe pattern is formed on a main surface of the semiconductor layer, and the mask is arranged along a −c-axis side side surface of the convex portion of the semiconductor layer. Laminated structure.   The nitride semiconductor multilayer structure according to claim 2, wherein the convex portion is formed by processing the main surface of the semiconductor layer into an uneven shape.   The nitride semiconductor multilayer structure according to claim 2, wherein the convex portion is formed by adding a convex portion made of a group III nitride semiconductor to a flat main surface of the semiconductor layer.   2. The nitride semiconductor multilayer structure according to claim 1, wherein the mask includes a belt-shaped portion having an L-shaped cross section or an inverted T-shaped cross section formed on a flat main surface of the semiconductor layer.   The nitride semiconductor multilayer structure according to claim 1, wherein the semiconductor layer includes a substrate having a main surface other than a c-plane.   The nitride semiconductor multilayer structure according to claim 6, wherein the semiconductor layer includes a group III nitride semiconductor layer formed on the substrate and having a main growth surface other than the c-plane.   The nitride semiconductor multilayer structure according to any one of claims 1 to 7, wherein a main surface of the group III nitride semiconductor layer is a nonpolar surface or a semipolar surface.   The nitride semiconductor multilayer structure according to claim 1, wherein the mask includes silicon oxide, silicon nitride, or silicon oxynitride. The nitride semiconductor multilayer structure according to any one of claims 1 to 9,
A nitride semiconductor device comprising: a plurality of group III nitride semiconductor layers formed on the group III nitride semiconductor layer and doped with impurities to control conductivity type. a mask forming step of forming, on a semiconductor layer having a principal surface other than the c-plane, a mask made of a material other than a group III-V semiconductor having a growth regulating surface parallel to the c-plane in a stripe shape parallel to the c-plane; ,
A group III nitride semiconductor is grown from the region between the stripe-shaped masks by anisotropic lateral selective growth in the + c-axis direction, covers the mask, and has a main surface other than the c-plane Forming a nitride semiconductor layer, and a method of manufacturing a nitride semiconductor multilayer structure.   The method for producing a nitride semiconductor multilayer structure according to claim 11, wherein the step of forming the group III nitride semiconductor layer is performed by a hydride vapor deposition method, a metal organic chemical vapor deposition method, or a molecular beam epitaxy method.

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