JP6934802B2 - Method for manufacturing group III nitride semiconductor substrate and group III nitride semiconductor substrate - Google Patents

Description

The present invention relates to a group III nitride semiconductor substrate and a method for manufacturing a group III nitride semiconductor substrate.

Related techniques are disclosed in Patent Document 1 and Patent Document 2. As disclosed in Patent Document 1 and Patent Document 2, when a device (eg, optical device, electronic device, etc.) is formed on the c-plane of a group III nitride semiconductor crystal, the internal quantum is caused by the piezo electric field. Efficiency is reduced. Therefore, attempts have been made to form the device on a so-called semi-polar surface (a surface different from the polar surface and the non-polar surface).

Further, related techniques are disclosed in Patent Document 3 and Patent Document 4. As disclosed in Patent Documents 3 and 4, a semipolar crystal piece having a semipolar plane as a main surface is cut out from a bulk group III nitride semiconductor crystal and the crystal pieces are joined to form a semipolarity. Attempts have been made to produce group III nitride semiconductor crystals with a surface as the main surface.

Further, the related technique is disclosed in Patent Document 5. As disclosed in Patent Document 5, a GaN-based semiconductor optical device having a (20-21) plane and a (20-2-1) plane, which are semipolar planes inclined in the m-axis direction from the c plane, as main planes. Attempts have been made to manufacture.

Japanese Unexamined Patent Publication No. 2012-160755 Japanese Unexamined Patent Publication No. 2016-12717 Japanese Unexamined Patent Publication No. 2010-13298 Japanese Unexamined Patent Publication No. 2013-82628 Japanese Unexamined Patent Publication No. 2012-15555

An object of the present invention is to provide a technique for improving the internal quantum efficiency of a device formed on a group III nitride semiconductor substrate.

According to the present invention
A sapphire substrate whose main surface is inclined at any angle of greater than 0 ° and less than 10.5 ° in the direction in which the {10-10} plane is parallel to the a plane.
At least one of the surfaces located on the main surface of the sapphire substrate and having an off angle within 10 ° from the {-1-12-4} surface and the {-1-12-4} surface, and the other. A polycrystalline buffer layer including faces and
A group III nitride semiconductor layer located above the buffer layer and having a main surface having an off-angle within 10 ° from the {-1-12-4} plane or the {-1-12-4} plane. ,
A group III nitride semiconductor substrate having the above is provided.

Further, according to the present invention.
On the main surface of the sapphire substrate, the surface orientation of the main surface is a surface that is inclined at any angle from 0 ° to less than 10.5 ° in the direction parallel to the a plane. , A polycrystalline buffer layer containing at least one of the {-1-12-4} plane and the {-1-12-4} plane having an off-angle within 10 ° and the other plane. The buffer layer forming step to be formed and
A group III nitride semiconductor layer whose main surface is a surface having an off angle within 10 ° from the {-1-12-4} surface or the {-1-12-4} surface is formed on the buffer layer. Growth process and
A method for producing a group III nitride semiconductor substrate having the above is provided.

According to the present invention, the internal quantum efficiency of the device formed on the group III nitride semiconductor substrate can be improved.

It is a figure which shows the characteristic of the group III nitride semiconductor substrate of this embodiment. This is an example showing a difference from the group III nitride semiconductor substrate of the present embodiment. It is a flowchart which shows an example of the process flow of the manufacturing method of the group III nitride semiconductor substrate of this embodiment. It is a side schematic diagram which shows an example of the group III nitride semiconductor substrate of this embodiment. It is a side schematic diagram which shows an example of the group III nitride semiconductor substrate of this embodiment. It is a figure which shows the characteristic of the group III nitride semiconductor substrate of this embodiment. It is a figure which shows the characteristic of the group III nitride semiconductor substrate of this embodiment. It is a figure which shows the difference from the group III nitride semiconductor substrate of this embodiment. It is a figure which shows the characteristic of the group III nitride semiconductor substrate of this embodiment. It is a side schematic diagram which shows an example of the manufacturing process of the group III nitride semiconductor substrate of this embodiment. It is a side schematic diagram which shows an example of the group III nitride semiconductor substrate of this embodiment. It is a figure for demonstrating the feature of the group III nitride semiconductor substrate of this embodiment. It is a figure for demonstrating the feature of the group III nitride semiconductor substrate of this embodiment. It is a figure for demonstrating the feature of the group III nitride semiconductor substrate of this embodiment.

Hereinafter, embodiments of the group III nitride semiconductor substrate of the present invention and the method for manufacturing the group III nitride semiconductor substrate will be described with reference to the drawings. It should be noted that the figure is merely a schematic view for explaining the configuration of the invention, and the size, shape, number, ratio of different member sizes, etc. of each member are not limited to those shown.

First, the outline of the present embodiment will be described. According to the method for manufacturing a group III nitride semiconductor substrate of the present embodiment including a plurality of characteristic steps, a group III nitride semiconductor is grown on a sapphire substrate with the semipolar surface on the N-polar side as a growth surface. Can be done. As a result, the exposed surface (main surface) is a semi-polar surface on the N-polar side, specifically, a surface having an off angle within 10 ° from the {-1-12-4} surface or the {-1-12-4} surface. A group III nitride semiconductor substrate (template substrate) in which the group III nitride semiconductor layer is located on the sapphire substrate can be obtained. Further, by peeling the sapphire substrate from the template substrate or from the laminate in which the group III nitride semiconductor is grown as a thick film on the template substrate, the semipolar surface on the N-polar side, specifically {- Group III nitride semiconductor substrate (self-supporting substrate) composed of a group III nitride semiconductor layer having a surface having an off angle within 10 ° from the 1-12-4} surface or the {-1-12-4} surface as the main surface. Is obtained.

In the present embodiment, "a semi-polar surface which is represented by the Miller index (hkml) and where l exceeds 0" may be referred to as "a semi-polar surface on the Ga polar side". Further, a "semi-polar surface which is represented by the Miller index (hkml) and whose l is less than 0" may be referred to as a "semi-polar surface on the N-polar side".

By forming the device on such a group III nitride semiconductor substrate (template substrate, self-supporting substrate), improvement of internal quantum efficiency is realized. Hereinafter, a detailed description will be given.

First, a method for manufacturing a group III nitride semiconductor substrate (template substrate) will be described. FIG. 3 is a flowchart showing an example of a processing flow of a method for manufacturing a group III nitride semiconductor substrate (template substrate). As shown in the figure, the method for manufacturing a group III nitride semiconductor substrate (template substrate) includes a substrate preparation step S10, a heat treatment step S20, a pre-flow step S30, a buffer layer forming step S40, and a growth step S50. ..

In the substrate preparation step S10, a sapphire substrate is prepared. The diameter of the sapphire substrate is, for example, 1 inch or more. The thickness of the sapphire substrate is, for example, 250 μm or more.

The plane orientation of the main surface of the sapphire substrate is one of a plurality of elements that control the plane orientation of the growth surface of the group III nitride semiconductor layer epitaxially grown on the sapphire substrate. The relationship between the element and the plane orientation of the growth surface of the group III nitride semiconductor layer is shown in the following examples. In the substrate preparation step S10, a sapphire substrate whose main surface has a desired plane orientation is prepared.

The main surface of the sapphire substrate is, for example, a {10-10} surface or a surface in which the {10-10} surface is inclined by a predetermined angle in a predetermined direction.

A surface in which the {10-10} plane is tilted in a predetermined direction by a predetermined angle is, for example, a plane in which the {10-10} plane is tilted in any direction from 0 ° to 0.5 ° or less. It may be a surface.

Further, the surface in which the {10-10} plane is inclined by a predetermined angle in a predetermined direction is any one of those larger than 0 ° and less than 10.5 ° in the direction in which the {10-10} plane is parallel to the a plane. It may be an angled surface. Alternatively, the surface in which the {10-10} plane is tilted by a predetermined angle in a predetermined direction is any one of those greater than 0 ° and 10.5 ° or less in the direction in which the {10-10} plane is parallel to the a plane. It may be an angled surface. For example, a surface in which the {10-10} plane is tilted by a predetermined angle in a predetermined direction is 0.5 ° or more and 1.5 ° or less, 1.5 ° in a direction in which the {10-10} plane is parallel to the a plane. A surface inclined at any of the following angles: 2.5 ° or more, 4.5 ° or more and 5.5 ° or less, 6.5 ° or more and 7.5 ° or less, and 9.5 ° or more and 10.5 ° or less. It may be.

The heat treatment step S20 is performed after the substrate preparation step S10. In the heat treatment step S20, the sapphire substrate is heat-treated under the following conditions.

Temperature: 800 ° C. or higher 1200 ° C. or less pressure: 30 torr or more 760torr following heat treatment time: 5 minutes or more 20 minutes or less carrier gas: _{H 2,} or, _{H 2} and _N 2 _{(H 2} ratio 0% to 100%)
Carrier gas supply amount: 3 slm or more and 50 slm or less (However, the supply amount varies depending on the size of the growth device, and is not limited to this.)

The heat treatment on the sapphire substrate may be performed while performing the nitriding treatment or may be performed without performing the nitriding treatment. When the heat treatment is performed while performing the nitriding treatment, NH _{3 of} 0.5 slm or more and 20 slm or less is supplied onto the sapphire substrate during the heat treatment (however, the supply amount varies depending on the size of the growth apparatus and is not limited to this). Further, when the heat treatment is performed without performing the nitriding treatment, NH ₃ is not supplied during the heat treatment.

The presence or absence of nitriding treatment during the heat treatment may be one of a plurality of factors that control the plane orientation of the growth surface of the group III nitride semiconductor layer epitaxially grown on the main surface of the sapphire substrate. The relationship between the element and the plane orientation of the growth surface of the group III nitride semiconductor layer is shown in the following examples.

The pre-flow step S30 is performed after the heat treatment step S20. In the pre-flow step S30, the metal-containing gas is supplied onto the main surface of the sapphire substrate under the following conditions. The pre-flow step S30 may be performed in, for example, a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus.

Temperature: 500 ° C or more and 1000 ° C or less Pressure: 30 torr or more and 200 torr or less Trimethylaluminum supply amount, supply time: 20 cm or more and 500 ccm or less, 1 second or more and 60 seconds or less Carrier gas: H ₂ or H ₂ and N ₂ (H ₂ ratio) 0-100%)
Carrier gas supply amount: 3 slm or more and 50 slm or less (However, the gas supply amount is not limited to this because it varies depending on the size and configuration of the growth apparatus).

The above conditions are for supplying trimethylaluminum and triethylaluminum, which are organic metal raw materials, as the metal-containing gas. In this step, a metal-containing gas containing another metal is supplied instead of trimethylaluminum triethylaluminum, and another metal film such as a titanium film, a vanadium film or a copper film is used instead of the aluminum film on the main surface of the sapphire substrate. It may be formed on top. In addition, other metal carbide films such as aluminum carbide, titanium carbide, vanadium carbide and copper carbide, which are reaction films with hydrocarbon compounds such as methane, ethylene and ethane produced from organic metal raw materials, are placed on the main surface of the sapphire substrate. It may be formed.

By the pre-flow step S30, a metal film and a metal carbide film are formed on the main surface of the sapphire substrate. The presence of the metal film is a condition for reversing the polarity of the crystals grown on it. That is, the implementation of the pre-flow step S30 is among a plurality of elements for setting the plane orientation of the growth surface of the group III nitride semiconductor layer epitaxially grown on the main surface of the sapphire substrate as the semi-polar surface on the N-polar side. It is one of.

The buffer layer forming step S40 is performed after the pre-flow step S30. In the buffer layer forming step S40, the buffer layer is formed on the main surface of the sapphire substrate. The thickness of the buffer layer is, for example, 20 nm or more and 300 nm or less.

The buffer layer is, for example, an AlN layer. For example, an AlN crystal may be epitaxially grown under the following conditions to form a buffer layer.

Growth method: MOCVD method Growth temperature: 800 ° C or more and 950 ° C or less Pressure: 30 torr or more and 200 torr or less Trimethylaluminum supply amount: 20 cm cm or more and 500 cm or less NH ₃ supply amount: 0.5 slm or more and 10 slm or less Carrier gas: H ₂ or H ₂ And N ₂ (H ₂ ratio 0-100%)
Carrier gas supply amount: 3 slm or more and 50 slm or less (However, the gas supply amount is not limited to this because it varies depending on the size and configuration of the growth apparatus).

The growth condition of the buffer layer forming step S40 may be one of a plurality of elements that control the plane orientation of the growth surface of the group III nitride semiconductor layer epitaxially grown on the main surface of the sapphire substrate. The relationship between the element and the plane orientation of the growth surface of the group III nitride semiconductor layer is shown in the following examples.

Further, the growth conditions in the buffer layer forming step S40 (relatively low predetermined growth temperature, specifically 800 to 950 ° C., and relatively low pressure) are for growing AlN while maintaining the N polar side. It becomes a condition. That is, the growth condition in the buffer layer forming step S40 is a plurality of elements for setting the plane orientation of the growth surface of the group III nitride semiconductor layer epitaxially grown on the main surface of the sapphire substrate to the semi-polar surface on the N-polar side. It is one of them.

Further, the state of the main surface (growth surface) of the buffer layer is one element for controlling the plane orientation of the growth surface of the group III nitride semiconductor layer epitaxially grown on the buffer layer.

Specifically, the surface orientation of the main surface of the sapphire substrate is set to be a surface inclined at any angle of greater than 0 ° and less than 10.5 ° in the direction in which the {10-10} plane is parallel to the a plane. When the heat treatment step S20 and the pre-flow step S30 are performed under the above conditions and then the buffer layer forming step S40 is performed under the above conditions to form the AlN layer (buffer layer), the main surface of the AlN layer becomes {-1-12. The state includes at least one of the -4} surface and the surface having an off angle within 10 ° from the {-1-12-4} surface, and the other surface (see FIG. 10). That is, the AlN layer is polycrystalline. Other planes include at least one of the {10-10} plane, the {11-21} plane, the {11-22} plane, and the {10-13} plane. As shown in the following examples, when the growth step S50 described below is carried out after the buffer layer forming step S40 to form the group III nitride semiconductor layer on the AlN layer (buffer layer) as described above, The main surface of the group III nitride semiconductor layer can be a surface having an off angle within 10 ° from the {-1-12-4} surface or the {-1-12-4} surface (see FIG. 11). .. That is, the group III nitride semiconductor layer is a single crystal.

Returning to FIG. 3, the growth step S50 is performed after the buffer layer forming step S40. In the growth step S50, a group III nitride semiconductor crystal (eg, GaN crystal) is epitaxially grown on the buffer layer under the following growth conditions, and the growth plane becomes a predetermined plane orientation (semipolar plane on the N polar side). It forms a group III nitride semiconductor layer. The thickness of the group III nitride semiconductor layer 30 is, for example, 1 μm or more and 20 μm or less.

Growth method: MOCVD method Growth temperature: 800 ° C or higher and 1025 ° C or lower
Pressure: 30 torr or more and 200 torr or less TMGa supply amount: 25 sccm or more and 1000 sccm or less NH3 supply amount: 1 slm or more and 20 slm or less Carrier gas: H ₂ or H ₂ and N ₂ (H ₂ ratio 0 to 100%)
Carrier gas supply amount: 3 slm or more and 50 slm or less (However, the gas supply amount is not limited to this because it varies depending on the size and configuration of the growth apparatus).
Growth rate: 10 μm / h or more

The growth conditions (relatively low growth temperature, relatively low pressure, relatively fast growth rate) in the growth step S50 are conditions for growing GaN while maintaining the N-polar side. That is, the growth condition in the growth step S50 is among a plurality of elements for setting the plane orientation of the growth surface of the group III nitride semiconductor layer epitaxially grown on the main surface of the sapphire substrate to the semi-polar surface on the N-polar side. It is one of.

By manufacturing under the above conditions, the sapphire substrate 21, the buffer layer 22, and the group III nitride semiconductor layer 23 are laminated in this order as shown in FIG. 4, and the growth surface of the group III nitride semiconductor layer 23 is formed. It is possible to manufacture a group III nitride semiconductor substrate 20 in which the plane orientation of 24 is a semipolar plane on the N-polar side. Further, by adjusting the manufacturing conditions within the range of the above conditions, the plane orientation of the growth plane 24 can be changed from the desired semipolar plane (example: -1-12-4} plane or {-1-12-4} plane to 10 A surface having an off angle within °).

Next, a method for manufacturing a group III nitride semiconductor substrate (self-supporting substrate) will be described.

For example, after producing a laminate (template substrate) as shown in FIG. 4 by the flow shown in FIG. 3, the sapphire substrate 21 and the buffer layer 22 are removed from the laminate (peeling step), as shown in FIG. A group III nitride semiconductor substrate 10 (self-supporting substrate) composed of the group III nitride semiconductor layer 23 can be manufactured. The means for removing the sapphire substrate 21 and the buffer layer 22 is not particularly limited. For example, the stress caused by the difference in the coefficient of linear expansion between the sapphire substrate 21 and the group III nitride semiconductor layer 23 may be used to separate them. Then, the buffer layer 22 may be removed by polishing, etching, or the like.

As another removal example, a release layer may be formed between the sapphire substrate 21 and the buffer layer 22. For example, a carbon layer in which carbides (aluminum carbide, titanium carbide, zirconium carbide, hafnium carbide, vanadium carbide or tantalum carbide) are dispersed, and carbides (aluminum carbide, titanium carbide, zirconium carbide, hafnium carbide, vanadium carbide or tantalum carbide). After forming the laminate of the layers on the sapphire substrate 21, the layer subjected to the carbide treatment may be formed as a release layer.

After forming the buffer layer 22 and the group III nitride semiconductor layer 23 on such a release layer, the laminate is heated at a temperature higher than the heating temperature at which the group III nitride semiconductor layer 23 is formed. It can be separated into a portion on the sapphire substrate 21 side and a portion on the group III nitride semiconductor layer 23 side with the portion of the release layer as a boundary. By removing the buffer layer 22 and the like from the portion on the side of the group III nitride semiconductor layer 23 by polishing, etching, or the like, the group III nitride semiconductor substrate 10 composed of the group III nitride semiconductor layer 23 as shown in FIG. 5 ( A self-supporting substrate) can be obtained.

As an example of another manufacturing method of the self-supporting substrate, after producing a laminate (template substrate) as shown in FIG. 4 by the flow shown in FIG. 3, it is placed on the template substrate (on the group III nitride semiconductor layer 23). In), for example, the HVPE layer may be formed by growing a group III nitride semiconductor as a thick film by the HVPE (Hydride Vapor Phase Epitaxy) method. As a result, an HVPE layer of a group III nitride semiconductor having an exposed surface as a semi-polar surface on the N-polar side is obtained on the template substrate (on the group III nitride semiconductor layer 23). The growth conditions for epitaxially growing a group III nitride semiconductor by the HVPE method are not particularly limited. Can be made to. Then, the group III nitride semiconductor substrate 10 (self-supporting substrate) may be obtained by slicing or the like from the HVPE layer.

Next, the configurations and features of the group III nitride semiconductor substrate 20 (template substrate) and the group III nitride semiconductor substrate 10 (self-supporting substrate) obtained by the above manufacturing method will be described.

As shown in FIG. 4, the group III nitride semiconductor substrate 20 (template substrate) includes a sapphire substrate 21, a buffer layer 22 formed on the sapphire substrate 21, and a group III formed on the buffer layer 22. It has a nitride semiconductor layer 23. The main surface (growth surface 24) of the group III nitride semiconductor layer 23 is a semi-polar surface, represented by the Miller index (hkml), and l is less than 0.

The plane orientation of the main surface (the surface in contact with the buffer layer 22) of the sapphire substrate 21 is, for example, one of the directions greater than 0 ° and less than 10.5 ° in the direction in which the {10-10} plane is parallel to the a plane. It is a surface that is inclined at an angle. In this case, in the AlN layer (buffer layer 22), the plane orientation of the main plane (the plane in contact with the group III nitride semiconductor layer 23) is from the {-1-12-4} plane and the {-1-12-4} plane. Includes at least one of the surfaces having an off angle within 10 ° and the other surface. The AlN layer is polycrystalline. Other planes include at least one of the {10-10} plane, the {11-21} plane, the {11-22} plane, and the {10-13} plane. The main surface (exposed surface) of the group III nitride semiconductor layer 23 is a surface having an off angle within 10 ° from the {-1-12-4} surface or the {-1-12-4} surface. The group III nitride semiconductor layer is a single crystal. The film thickness of the group III nitride semiconductor layer 23 is 1 μm or more and 20 μm or less.

As shown in the following examples, when a group III nitride semiconductor is epitaxially grown on a growth surface which is a semipolar plane, is represented by a Miller index (hkml), and l exceeds 0, the thickness of the group III nitride semiconductor layer is thick. The thicker the thickness, the worse the crystallinity. As a result, the thicker the group III nitride semiconductor layer, the larger the half-value width of XRC. Therefore, when the growth surface is a semi-polar surface, represented by the Miller index (hkml), and l is more than 0, a group III nitride semiconductor layer having good crystallinity and a thick film is produced. Is difficult.

On the other hand, as shown in the following examples, when a group III nitride semiconductor is epitaxially grown on a growth surface which is a semipolar plane, is represented by a Miller index (hkml), and l is less than 0, the group III nitride semiconductor layer The crystallinity hardly changes even if the thickness of the is increased. In the case of the present embodiment, which is a semipolar plane, represented by the Miller index (hkml), and epitaxially grows a group III nitride semiconductor on a growth plane in which l is less than 0, the crystallinity is good as described above, and the crystallinity is good. A group III nitride semiconductor layer having a thick film (for example, 100 μm or more) can be produced.

As shown in FIG. 5, the group III nitride semiconductor substrate 10 (self-supporting substrate) is composed of a group III nitride semiconductor layer 23 composed of a group III nitride semiconductor crystal. The film thickness of the group III nitride semiconductor substrate 10 (self-supporting substrate) is 100 μm or more. The self-supporting substrate is composed of a group III nitride semiconductor crystal, and the exposed first main surface 11 and the second main surface 12 which are in a front-to-back relationship are both semi-polar surfaces, and one of them is, for example, {-1-. A surface having an off angle within 10 ° from the 12-4} surface or the {-1-12-4} surface.

The growth surface is a semipolar surface on the sapphire substrate, which is represented by a mirror index (hkml), and after epitaxially growing a group III nitride semiconductor in which l exceeds 0, the sapphire substrate is formed from the group III nitride semiconductor layer. When removed, the appearance becomes the same as the group III nitride semiconductor substrate 10 (self-supporting substrate) of the present embodiment shown in FIG. However, in such a substrate and the group III nitride semiconductor substrate 10 (self-supporting substrate) of the present embodiment, the growth surface when epitaxially growing the group III nitride semiconductor is a "semipolar surface, and the Miller index (hkml). ), Or "a semipolar plane, represented by the Miller index (hkml), and l is less than 0".

The difference can be confirmed by observing the relationship between the film thickness and the difference in the half-value width of the XRC on the main surface, which is in a front-to-back relationship.

As described above, it is a semipolar surface, represented by the Miller index (hkml), and when a group III nitride semiconductor is epitaxially grown on a growth surface where l exceeds 0, the thicker the thickness of the group III nitride semiconductor layer, the thicker the layer. The crystallinity deteriorates and the half width of XRC increases. That is, the larger the film thickness, the larger the difference in the half-value width of the XRC on the main surface, which is in a front-to-back relationship.

On the other hand, when a group III nitride semiconductor is epitaxially grown on a growth surface having a semipolar surface, represented by the Miller index (hkml), and l is less than 0, even if the thickness of the group III nitride semiconductor layer becomes thicker. Crystallinity hardly changes. That is, even if the film thickness is increased, the difference in the half-value width of the XRC on the main surface, which is in a front-to-back relationship, is equal to or less than a predetermined level.

From the above, by confirming the difference in the half-value width of the XRC of the main surface, which is in a front-to-back relationship when the film thickness is within the predetermined range, the group III nitride semiconductor substrate is "a semi-polar surface and has a Miller index (Miller index). It is represented by hkml) and is formed by epitaxial growth on a growth plane in which l exceeds 0, or a growth plane in which it is a semipolar plane and is represented by a Miller index (hkml) and l is less than 0. It can be confirmed whether it is formed by epitaxial growth on the top.

Specifically, when "when the film thickness is 300 μm or more, the difference in half-value width of the XRC of the main surface which is in a front-to-back relationship is 100 arcsec or less" is satisfied, "it is a semi-polar surface and the Miller index (hkml) is used. It can be said that this is a group III nitride semiconductor substrate formed by epitaxially growing on a growth surface in which l is less than 0. Then, when "when the film thickness is 300 μm or more, the difference in the half-value width of the XRC of the main surface which is in a front-to-back relationship is larger than 100 arcsec" is satisfied, it is a "semi-polar surface and is represented by the Miller index (hkml)". It can be said that this is a group III nitride semiconductor substrate formed by epitaxial growth on a growth surface in which l exceeds 0.

Next, the action and effect of this embodiment will be described.

According to the method for manufacturing a group III nitride semiconductor substrate of the present embodiment, a group III nitride semiconductor can be grown on a sapphire substrate with the semipolar surface on the N-polar side as a growth surface. As a result, as shown in FIG. 4, the group III nitride semiconductor layer 23 in which the exposed surface (growth surface 24) is a semi-polar surface on the N-polar side is located on the sapphire substrate 21 (group III nitride semiconductor substrate 20 ( Template substrate) is obtained. Further, as shown in FIG. 5, the group III nitride semiconductor substrate 10 (Group III nitride semiconductor substrate 10) composed of the group III nitride semiconductor layer 23 obtained by growing the group III nitride semiconductor with the semipolar surface on the N-polar side as the growth surface. Self-supporting substrate) can be obtained.

Further, according to the method for manufacturing a group III nitride semiconductor substrate of the present embodiment, by controlling the state of the main surface (growth surface) of the AlN layer (buffer layer 22) to a desired state, epitaxial growth is performed on the main surface (growth surface). The plane orientation of the growth surface of the group III nitride semiconductor layer can be controlled to a desired state.

Specifically, at least one of the surface where the main surface of the AlN layer has an off angle within 10 ° from the {-1-12-4} surface and the {-1-12-4} surface, and the other surface. When controlled to include, the main surface of the group III nitride semiconductor layer can be a surface having an off angle within 10 ° from the {-1-12-4} surface or the {-1-12-4} surface. .. The other surfaces included in the main surface of the AlN layer include {10-10} surface, {11-21} surface, {11-22} surface, {10-13} surface and the like.

By forming the device on such a group III nitride semiconductor substrate (template substrate, self-supporting substrate), improvement of internal quantum efficiency is realized.

Further, by using the group III nitride semiconductor substrate (template substrate, self-supporting substrate) of the present embodiment, the device can be formed on the main surface which is the semi-polar surface on the N-polar side in the plane orientation. In such a case, not only the reduction of piezo polarization due to the effect of the semipolar surface but also the reduction of spontaneous polarization is realized. Therefore, the Stark effect caused by the internal electric field can be suppressed.

Further, when the group III nitride semiconductor was grown with the semipolar surface on the N-polar side as the growth surface, the present inventors grew the group III nitride semiconductor with the semipolar surface on the Ga polar side as the growth surface. It has been confirmed that the surface condition tends to be flatter than in the case. When a group III nitride semiconductor is grown with the semi-polar plane on the Ga polar side as the growth plane, pits and facets derived from the m-plane component are likely to occur. In this respect as well, the group III nitride semiconductor substrate (template substrate, self-supporting substrate) of the present embodiment is excellent.

Further, when the group III nitride semiconductor was grown with the semipolar surface on the N-polar side as the growth surface, the present inventors grew the group III nitride semiconductor with the semipolar surface on the Ga polar side as the growth surface. It has been confirmed that the uptake of impurities is smaller than in the case. Specifically, when hole measurements were performed on two types of polar surfaces (semipolar surface on the N-polar side and semipolar surface on the Ga-polar side) grown under the same equipment and under the same growth conditions, the half on the N-polar side was measured. When a group III nitride semiconductor is grown with the polar surface as the growth surface, the carrier concentration is one digit smaller than when the group III nitride semiconductor is grown with the semi-polar surface on the Ga polar side as the growth surface. confirmed. It is presumed that this is because the uptake of O atoms could be reduced. In this respect as well, the group III nitride semiconductor substrate (template substrate, self-supporting substrate) of the present embodiment is excellent.

Further, according to the present embodiment, a group III nitride semiconductor layer formed on a sapphire substrate, which is a semipolar surface, is represented by the Miller index (hkml), and has an exposed main surface in which l is less than 0, A group III nitride semiconductor substrate having a sapphire substrate as a base substrate is provided. Further, by performing crystal growth on the group III nitride semiconductor substrate, the group III nitride semiconductor self-supporting substrate is provided in which the exposed first and second main surfaces, which are in a front-to-back relationship, are both semi-polar surfaces. Will be done.

The exposed first and second main surfaces of the group III nitride semiconductor self-supporting substrate provided by the present embodiment have, for example, one of them 38.0 ° or more in the direction from the c-plane to the a-plane 53. It is a semi-polar surface that is 0.0 ° or less and tilted by -16.0 ° or more and 16.0 ° or less in the m-plane direction, and the other is 38.0 ° or more and 53.0 in the -a-plane direction from the -c plane. It is a semi-polar surface tilted at -16.0 ° or more and 16.0 ° or less in the m-plane direction. The main surface of the group III nitride semiconductor substrate having a sapphire substrate as the base substrate is, for example, 38.0 ° or more and 53.0 ° or less in the a-plane direction from the −c plane and -16.0 ° in the m-plane direction. It is a semi-polar surface tilted by 16.0 ° or less.

In particular, when a light emitting device (LED, LD) is formed on the main surface, the surface tilted by 39.1 ° from the c surface to the a surface ((11-24) surface) is Jpn. J. Appl. Phys. Vol. As shown in Fig. 1 reported in .39 (2000) pp. 413-416, since the piezo electric field becomes 0, the internal quantum efficiency due to the Stark effect equivalent to the m-plane and a-plane of the non-polar plane Power consumption is reduced and luminous efficiency is improved due to the effect of suppressing the decrease in light emission. In addition, the main surface ((-1-12-4) surface) tilted 39.1 ° from the -c plane to the -a plane not only reduces piezo polarization due to the effect of the semipolar plane, but also reduces piezo polarization from nitrogen atoms to gallium. The reduction of spontaneous polarization generated in the direction of atoms is also realized. Therefore, the Stark effect caused by the internal electric field generated in the active layer of the light emitting device (LED, LD) can be further suppressed, so that the performance of the light emitting device (LED, LD) can be further improved.

Both the group III nitride semiconductor layer provided in Patent Document 1 and Patent Document 2 are semipolar planes, are represented by a mirror index (hkml), and have a main plane in which l exceeds 0. Compared to a group III nitride semiconductor layer having a main surface in which l is less than 0 and a group III nitride semiconductor substrate having a sapphire substrate, which is a semipolar plane provided by The internal quantum efficiency of the device is low.

If a group III nitride semiconductor substrate having a sapphire substrate is used as the base substrate provided by the present embodiment, the size of the sapphire substrate is equivalent to that of the sapphire substrate used if the sapphire substrate is removed by some method including well-known techniques and conventional techniques. It is possible to manufacture a group III nitride semiconductor self-supporting substrate that has a large diameter, uniform in-plane crystallinity, surface flatness, impurity concentration, and axial deviation in plane orientation, and does not require precise manufacturing technology. The well-known technique and the conventional technique referred to here are, for example, chemical etching, mechanical polishing, crystal peeling using thermal stress, and the like.

The group III nitride semiconductor self-supporting substrate provided by the methods of Patent Document 3 and Patent Document 4 is formed by joining crystal pieces cut out from a group III nitride semiconductor self-supporting substrate having a c-plane as a main surface in an arbitrary plane direction. This is a group III nitride semiconductor self-supporting substrate whose main surface is a semipolar surface. In order to achieve this, a process of cutting out a large amount of crystal pieces from a bulk crystal and a process of aligning the crystal pieces in the same crystal axis direction with high accuracy and then joining them are required, so that a high yield is realized. A precise technique is required to do this. Further, since the crystal pieces are joined to increase the diameter of the substrate, the atomic position is displaced at the joined portion, and high-density dislocations occur at the bonded portion. Therefore, the crystallinity of the substrate is lowered and the dislocation density is unevenly distributed in the plane. Further, when the joint surface is a c-plane, an m-plane, and a plane inclined from the m-plane toward the c-plane, facet planes such as {11-22} plane and {10-11} plane appear. As shown in 2, large dents and abnormal crystal growth occur, so that the surface flatness is remarkably deteriorated and the bonding strength is insufficient, which makes it difficult to handle the substrate.

Further, in order to solve the remarkable deterioration of the surface flatness caused by the large dents and the abnormal crystal growth as shown in FIG. 2 and the difficulty in handling the substrate due to the insufficient bonding strength, the methods of Patent Documents 3 and 4 are used. Therefore, it is easily conceivable that the joint surface is only the a-plane and the inclined surface from the a-plane. Uneven distribution cannot be resolved. Further, since the crystals are bonded on the a-plane or the a-plane inclined surface, the group III nitride semiconductor self-supporting substrate provided by the present embodiment with the a-plane inclined surface as the main surface cannot be manufactured. ..

Since the first and second main surfaces of the group III nitride semiconductor self-supporting substrate provided by the present embodiment are both inclined surfaces of surface a, for example, they have cleavage surfaces (m surfaces) on the side surfaces. By providing a substrate having a cleavage plane, it becomes possible to easily obtain a reflector surface having excellent flatness in which atoms are regularly and neatly arranged, which is indispensable for optical resonance in a semiconductor laser (LD).

The GaN-based semiconductor laser device provided in Patent Document 5 having the (20-21) plane and the (20-2-1) plane as main planes is cleaved on the side surface because the main plane is an inclined plane of m plane. Has no face. Therefore, it is not possible to obtain a highly flat reflecting mirror surface from which optical resonance can be obtained. Therefore, in manufacturing a product, an advanced and precise technique for flattening the side surface is required, and the manufacturing process is complicated. In addition, since a reflecting mirror surface having inferior flatness is used, the performance is higher than that of a GaN-based semiconductor optical laser device in which a mirror structure is formed by using a cleavage surface.

<First evaluation>
In the first evaluation, the group III nitride semiconductor is satisfied by satisfying all of the above-mentioned "plurality of factors for setting the plane orientation of the growth surface of the group III nitride semiconductor layer to the semi-polar surface on the N-polar side". It was confirmed that the plane orientation of the growth plane of the layer could be set to the semi-polar plane on the N-polar side. Further, when at least one of the above-mentioned "plurality of elements for setting the plane orientation of the growth surface of the group III nitride semiconductor layer to the semi-polar surface on the N-polar side" is not satisfied, the group III nitride It was confirmed that the plane orientation of the growth surface of the semiconductor layer was a semi-polar surface on the Ga polar side.

First, a sapphire substrate was prepared, which is a surface whose main surface is inclined by 2 ° in a direction parallel to the a surface from the m surface ((10-10) surface). The thickness of the sapphire substrate was 430 μm and the diameter was 2 inches.

Then, the heat treatment step S20 was carried out on the prepared sapphire substrate under the following conditions.

Temperature: 1000-1050 ° C
Pressure: 100torr
Carrier gas: H ₂ , N ₂
Heat treatment time: 10 minutes or 15 minutes Carrier gas supply: 15 slm

During the heat treatment step S20, 20 slm of NH ₃ was supplied to perform nitriding treatment.

Then, the pre-emption step S30 was performed under the following conditions.
Temperature: 800-930 ° C
Pressure: 100torr
Trimethylaluminum supply amount, supply time: 90 sccm, 10 seconds Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm

Then, the buffer layer forming step S40 was performed under the following conditions to form an AlN layer.

Growth method: MOCVD method Growth temperature: 800 to 930 ° C.
Pressure: 100torr
Trimethylaluminum supply: 90 sccm
NH ₃ supply: 5 slm
Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm

Then, the growth step S50 was carried out under the following conditions to form a group III nitride semiconductor layer.

Growth method: MOCVD method Pressure: 100torr
TMGa supply: 50-500 sccm (continuous change)
NH ₃ supply amount: 5 to 10 slm (continuous change)
Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm
Growth rate: 10 μm / h or more

The growth temperature of the first sample was controlled to 900 ° C. ± 25 ° C., and the growth temperature of the second sample was controlled to 1050 ° C. ± 25 ° C. That is, the first sample is a sample that satisfies all of the above-mentioned "plurality of elements for setting the plane orientation of the growth plane of the group III nitride semiconductor layer to the semi-polar plane on the N-polar side". The second sample is a part of the above-mentioned "plurality of elements for setting the plane orientation of the growth surface of the group III nitride semiconductor layer to the semi-polar surface on the N-polar side" (growth temperature in the growth step S50). ) Is not satisfied.

The plane orientation of the growth plane of the group III nitride semiconductor layer of the first sample is 8. The surface was inclined by 5 ° or less. On the other hand, the plane orientation of the growth plane of the group III nitride semiconductor layer of the second sample is 8.5 ° in the direction perpendicular to the m plane and 5.0 ° in the a plane direction from the (11-24) plane. It was an inclined surface below. That is, depending on whether or not the above-mentioned "plurality of factors for setting the plane orientation of the growth plane of the group III nitride semiconductor layer to the semi-polar plane on the N-polar side" is satisfied, the plane orientation of the growth plane becomes Ga polarity. It can be seen that it is possible to adjust whether the polarity is N or N.

FIG. 6 shows the XRD pole measurement results of the (-1-12-4) plane or the (11-24) plane in the first sample. It can be confirmed that the diffraction peak is located at a position deviated from the center point of the pole by several degrees. When the angle deviation is measured in detail, it is 5.0 ° in the -a plane direction and 8.5 ° in the direction parallel to the m plane, or 5.0 ° in the a plane direction and 8 in the direction parallel to the m plane. It can be confirmed that the position is 5.5 °.

FIG. 7 shows the result of confirming that the exposed surface (growth surface 24) shown in FIG. 4 in the first sample is N-polar. For comparison, FIG. 8 shows the results of a group III nitride semiconductor self-supporting substrate produced by slicing a thick film-grown GaN free-standing substrate on the + c-plane so as to have a plane orientation equivalent to that of the first sample. Both the first sample and the semi-polar self-supporting substrate formed by slicing from the + c-plane GaN free-standing substrate were subjected to 1.5 μm diamond polishing on both sides (front and back of the substrate), and the phosphate-sulfuric acid mixed solution was kept at 150 ° C. Etching was performed for 30 minutes.

From FIGS. 7 and 8, the etching surface states of the exposed surface (growth surface 24) of the first sample and the back surface (N-polar surface) of the semipolar self-supporting substrate prepared by slicing from the + c-plane GaN free-standing substrate are the same. Can be confirmed. Further, it can be confirmed that the etching surface states of the peeled surface of the first sample and the surface (Ga polar surface) of the semi-polar self-supporting substrate prepared by slicing from the + c-plane GaN free-standing substrate are the same, which is shown in FIG. It can be confirmed that the exposed surface (growth surface 24) is N-polar.

It should be noted that the present inventors do not satisfy the other part of the above-mentioned "plurality of elements for setting the plane orientation of the growth plane of the group III nitride semiconductor layer to the semi-polar plane on the N-polar side". In some cases, and even when all of them are not satisfied, it is confirmed that the plane orientation of the growth surface has Ga polarity.

<Second evaluation>
In the second evaluation, the plane orientation of the growth surface of the group III nitride semiconductor layer is adjusted by adjusting the above-mentioned "plurality for adjusting the plane orientation of the growth surface of the group III nitride semiconductor layer". I confirmed that I could do it.

First, a plurality of sapphire substrates having various surface orientations of the main surface were prepared. The thickness of the sapphire substrate was 430 μm and the diameter was 2 inches.

Then, the heat treatment step S20 was performed on each of the prepared sapphire substrates under the following conditions.

Temperature: 1000-1050 ° C
Pressure: 200torr
Heat treatment time: 10 minutes Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm

Samples were prepared with different nitriding treatments during heat treatment. _{Specifically, both a sample in which 20 slm of NH 3} was supplied during the heat treatment and subjected to the nitriding treatment and a sample in which NH ₃ was not supplied during the heat treatment and the nitriding treatment was not performed were prepared.

Then, the pre-emption step S30 was performed under the following conditions.
Temperature: 880-930 ° C
Pressure: 100torr
Trimethylaluminum supply amount, supply time: 90 sccm, 10 seconds Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm

In addition, both a sample in which the pre-flow step S30 was performed and a sample in which the pre-flow step S30 was not performed were prepared.

Then, a buffer layer (AlN buffer layer) having a thickness of about 150 nm was formed on the main surface (exposed surface) of the sapphire substrate under the following conditions.

Growth method: MOCVD method Pressure: 100torr
V / III ratio: 5184
TMAl supply: 90ccm
NH ₃ supply: 5 slm
Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm

The growth temperature was different for each sample in the range of 700 ° C. or higher and 1110 ° C. or lower.

Then, a group III nitride semiconductor layer (GaN layer) having a thickness of about 15 μm was formed on the buffer layer under the following conditions.

Growth method: MOCVD method Growth temperature: 900 to 1100 ° C
Pressure: 100torr
V / III ratio: 321
TMGa supply: 50-500ccm (lamp up)
NH ₃ supply amount: 5 to 10 slm (lamp up)
Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm

As described above, the group III nitride semiconductor substrate 1 in which the sapphire substrate, the buffer layer, and the group III nitride semiconductor layer are laminated in this order was manufactured.

Tables 1 to 7 show the relationship between "a plurality of elements for adjusting the plane orientation of the growth surface of the group III nitride semiconductor layer" and the plane orientation of the growth plane of the group III nitride semiconductor layer.

In the "Sapphire main surface" column in the table, the surface orientation of the main surface of the sapphire substrate is shown. In the column of "nitriding treatment at the time of temperature rise", the presence / absence ("presence" or "absence") of the nitriding treatment at the time of temperature rise in the heat treatment step S20 is indicated. In the column of "presence / absence of trimethylaluminum pre-sinking process", the presence / absence ("presence" or "absence") of the trimethylaluminum pre-sending process is indicated. In the column of "AlN buffer growth temperature", the growth temperature in the buffer layer forming step is shown. In the column of "GaN growth temperature", the growth temperature in the GaN layer forming step is shown. In the column of "growth surface of group III nitride semiconductor layer", the plane orientation of the growth surface of the group III nitride semiconductor layer is shown.

According to the result, by adjusting the above-mentioned "plurality for adjusting the plane orientation of the growth surface of the group III nitride semiconductor layer", the growth surface of the group III nitride semiconductor layer can be changed to a semipolar surface. Yes, it is expressed by the Miller index (hkml), and it can be seen that it can be adjusted in the plane where l exceeds 0. Then, based on the result of the first evaluation and the result of the second evaluation, "a plurality of elements for setting the plane orientation of the growth plane of the group III nitride semiconductor layer to the semipolar plane on the N-polar side". By adjusting "multiple factors for adjusting the plane orientation of the growth surface of the group III nitride semiconductor layer" after satisfying all of the above, the growth surface of the group III nitride semiconductor layer can be changed to a semipolar surface. It can be seen that it is expressed by the Miller index (hkml) and can be adjusted while l is less than 0.

<Third evaluation>
The crystallinity of the sample prepared by this method was evaluated. Three types of samples were prepared. Sample A was prepared by the method described in the present specification, and the {11-23} plane is used as the growth plane. Samples B and C were comparative samples, and sample B had a {10-10} plane as a growth plane. In sample C, the {11-22} plane was used as the growth plane. The {11-23} plane corresponds to a plane having an off angle within 10 ° from the {-1-12-4} plane.

FIG. 9 shows the XRC half width when X-rays are incident on each sample in parallel with the projection axis of the c-axis of the group III nitride semiconductor crystal at a plurality of GaN film thicknesses and measured. However, in the sample C whose main surface is the {11-23} surface, the X-ray diffraction of the {11-23} surface cannot be obtained due to the annihilation law, so the XRC half width of the {11-22} surface was measured.

From FIG. 9, it can be seen that in sample A, the XRC full width at half maximum hardly changes even if the film thickness of the GaN layer increases. On the other hand, in Samples B and C, it can be seen that the XRC half width increases as the film thickness of the GaN layer increases.

<Fourth evaluation>
According to the method for manufacturing a group III nitride semiconductor substrate of the present embodiment, the plane orientation of the main surface (the surface in contact with the group III nitride semiconductor layer 23) of the AlN layer (buffer layer 22) is {-1-12-4}. And, it is confirmed that at least one of the surfaces having an off angle within 10 ° from the {-1-12-4} surface and the other surface can be included. Further, when the group III nitride semiconductor is epitaxially grown on the AlN layer (buffer layer 22) by the method for manufacturing the group III nitride semiconductor substrate of the present embodiment, the main surface becomes a {-1-12-4} surface. Alternatively, it is confirmed that the group III nitride semiconductor layer 23, which is a surface having an off angle within 10 ° from the {-1-12-4} surface, can be formed.

First, a sapphire substrate was prepared, which is a surface whose main surface is inclined by 2 ° in a direction parallel to the a surface from the m surface ((10-10) surface). The thickness of the sapphire substrate was 430 μm and the diameter was 2 inches.

The heat treatment step S20, the pre-flow step S30, and the buffer layer forming step S40 were performed in this order on the sapphire substrate under the above conditions to form a laminated body in which the sapphire substrate and the AlN layer were laminated. Further, by performing the heat treatment step S20, the pre-flow step S30, the buffer layer forming step S40 and the growth step S50 in this order with respect to the other sapphire substrates under the above conditions, the sapphire substrate, the AlN layer and the group III nitride are formed in this order. A laminate was formed by laminating the physical semiconductor layers in this order.

"Heat treatment step S20"
Temperature: 1000-1050 ° C
Pressure: 100torr
Carrier gas: H ₂ , N ₂
Heat treatment time: 10 minutes or 15 minutes Carrier gas supply: 15 slm
In addition, 20 slm of NH ₃ was supplied and nitriding treatment was performed.

"Pre-emptive process S30"
Temperature: 800-930 ° C
Pressure: 100torr
Trimethylaluminum supply amount, supply time: 90 sccm, 10 seconds Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm

"Buffer layer forming step S40"
Growth method: MOCVD method Growth temperature: 800 to 930 ° C.
Pressure: 100torr
Trimethylaluminum supply: 90 sccm
NH ₃ supply: 5 slm
Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm

"Growth process S50"
Growth method: MOCVD method Growth temperature: 900 ° C ± 25 ° C
Pressure: 100torr
TMGa supply: 50-500 sccm (continuous change)
NH ₃ supply amount: 5 to 10 slm (continuous change)
Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm
Growth rate: 10 μm / h or more Film thickness: About 15 μm

FIG. 12 shows the result ((002) diffraction pole figure) of the pole figure measurement of the main surface (exposed surface) of the AlN layer in the laminated body in which the sapphire substrate and the AlN layer are laminated.

As shown in the figure, the main surface (exposed surface) of the AlN layer is the {10-10} surface in addition to the (-1-12-4) surface and the (-1-12-4) surface [twin]. , {11-21} plane, {11-21} plane [twin] and {11-22} plane. Further, although it does not appear in the result of the figure due to the measurement principle, the inventor has confirmed that the main surface (exposed surface) of the AlN layer further includes the {10-13} surface.

FIG. 13 shows an image of the main surface (exposed surface) of the AlN layer observed with an atomic force microscope. The numbers in the figure are in-plane rotation angles required to direct the side surface ((001 surface) or its inclined surface) of the concave-convex structure downward in the figure. It was consistent with the diffraction angle obtained by the pole figure measurement shown in FIG.

As described above, in both the pole figure measurement and the surface observation, the plane orientation of the main surface (exposed surface) of the AlN layer (buffer layer 22) is the {-1-12-4} plane and the {-1-12-4} plane. It was confirmed that at least one of the surfaces having an off angle within 10 ° and the other surface can be included.

FIG. 14 shows the results of pole figure measurement of the main surface (exposed surface) of the group III nitride semiconductor layer in a laminate in which the sapphire substrate, the AlN layer, and the group III nitride semiconductor layer are laminated in this order ((002). ) Pole diagram) is shown.

As shown in the figure, in the main plane of the group III nitride semiconductor layer, diffraction from a plane other than the {-1-12-4} plane and diffraction from a {-1-12-4} plane [twin] There wasn't. As described above, it was confirmed that the main surface of the group III nitride semiconductor layer is a single layer of {-1-12-4} planes in the pole figure measurement. It is considered that the cause is that the growth rate of the {-1-12-4} plane is higher than that of the other planes, and the growth is prioritized over the other planes.

Further, from the results of FIGS. 12 and 14, growth models as shown in FIGS. 10 and 11 are assumed, but when growth is performed with such a model, the {-1-12-4} plane is the other plane. Growth is carried out in a form that covers the area. That is, partial lateral growth occurs. This is also a feature of the present invention. By including a component of lateral growth during the growth of the group III nitride semiconductor layer, various defects are reduced and the crystallinity of the group III nitride semiconductor layer is improved.

Hereinafter, an example of the reference form will be added.
1. 1. A sapphire substrate whose main surface is inclined at any angle of greater than 0 ° and less than 10.5 ° in the direction in which the {10-10} plane is parallel to the a plane.
At least one of the surfaces located on the main surface of the sapphire substrate, the main surface having an off angle within 10 ° from the {-1-12-4} surface and the {-1-12-4} surface, and the other. A buffer layer that includes faces and
A group III nitride semiconductor layer located above the buffer layer and having a main surface having an off-angle within 10 ° from the {-1-12-4} plane or the {-1-12-4} plane. ,
Group III nitride semiconductor substrate having.
2. In the group III nitride semiconductor substrate according to 1.
The main surface of the buffer layer is a group III nitride semiconductor substrate including a {10-10} surface.
3. 3. In the group III nitride semiconductor substrate according to 1 or 2.
The main surface of the buffer layer is a group III nitride semiconductor substrate including a {11-21} surface.
4. In the group III nitride semiconductor substrate according to any one of 1 to 3.
The main surface of the buffer layer is a group III nitride semiconductor substrate including a {11-22} surface.
5. In the group III nitride semiconductor substrate according to any one of 1 to 4.
The main surface of the buffer layer is a group III nitride semiconductor substrate including a {10-13} surface.
6. In the group III nitride semiconductor substrate according to any one of 1 to 5.
A group III nitride semiconductor substrate having a group III nitride semiconductor layer having a thickness of 1 μm or more and 20 μm or less.
7. In the group III nitride semiconductor substrate according to any one of 1 to 6.
The buffer layer is a group III nitride semiconductor substrate which is an AlN layer.
8. On the main surface of the sapphire substrate, the surface orientation of the main surface is a surface that is inclined at any angle from 0 ° to less than 10.5 ° in the direction parallel to the a plane. , A buffer forming a buffer layer including at least one of a surface having an off angle within 10 ° from the {-1-12-4} surface and the {-1-12-4} surface as the main surface and the other surface. Layer formation process and
A group III nitride semiconductor layer whose main surface is a surface having an off angle within 10 ° from the {-1-12-4} surface or the {-1-12-4} surface is formed on the buffer layer. Growth process and
A method for manufacturing a group III nitride semiconductor substrate.

10 Group III nitride semiconductor substrate 11 First main surface 12 Second main surface 20 Group III nitride semiconductor substrate 21 Sapphire substrate 22 Buffer layer 23 Group III nitride semiconductor layer 24 Growth surface

Claims (8)

A sapphire substrate whose main surface is inclined at any angle of greater than 0 ° and less than 10.5 ° in the direction in which the {10-10} plane is parallel to the a plane.
At least one of the surfaces located on the main surface of the sapphire substrate and having an off angle within 10 ° from the {-1-12-4} surface and the {-1-12-4} surface, and the other. A polycrystalline buffer layer including faces and
A group III nitride semiconductor layer located above the buffer layer and having a main surface having an off-angle within 10 ° from the {-1-12-4} plane or the {-1-12-4} plane. ,
Group III nitride semiconductor substrate having. In the group III nitride semiconductor substrate according to claim 1,
The main surface of the buffer layer is a group III nitride semiconductor substrate including a {10-10} surface. In the group III nitride semiconductor substrate according to claim 1 or 2.
The main surface of the buffer layer is a group III nitride semiconductor substrate including a {11-21} surface. In the group III nitride semiconductor substrate according to any one of claims 1 to 3,
The main surface of the buffer layer is a group III nitride semiconductor substrate including a {11-22} surface. In the group III nitride semiconductor substrate according to any one of claims 1 to 4.
The main surface of the buffer layer is a group III nitride semiconductor substrate including a {10-13} surface. In the group III nitride semiconductor substrate according to any one of claims 1 to 5,
A group III nitride semiconductor substrate having a group III nitride semiconductor layer having a thickness of 1 μm or more and 20 μm or less. In the group III nitride semiconductor substrate according to any one of claims 1 to 6.
The buffer layer is a group III nitride semiconductor substrate which is an AlN layer. On the main surface of the sapphire substrate, the surface orientation of the main surface is a surface that is inclined at any angle from 0 ° to less than 10.5 ° in the direction parallel to the a plane. , A polycrystalline buffer layer containing at least one of the {-1-12-4} plane and the {-1-12-4} plane having an off-angle within 10 ° and the other plane. The buffer layer forming step to be formed and
A group III nitride semiconductor layer whose main surface is a surface having an off angle within 10 ° from the {-1-12-4} surface or the {-1-12-4} surface is formed on the buffer layer. Growth process and
A method for manufacturing a group III nitride semiconductor substrate.

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