JP2016150864A - Group iii nitride semiconductor substrate, and production method of group iii nitride semiconductor substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a new technology in a production method for growing a group III nitride semiconductor by using a substrate containing a plurality of crystal pieces of the group III nitride semiconductor.SOLUTION: There is provided a group III nitride semiconductor substrate 1 having a plurality of crystal pieces 10 of a group III nitride semiconductor arranged with each clearance 30 therebetween, and a binder 20 interposed between each clearance 30, for holding the plurality of crystal pieces 10. The group III nitride semiconductor substrate 1 is utilized as a substrate for growing the group III nitride semiconductor thereon.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a group III nitride semiconductor substrate and a method for manufacturing a group III nitride semiconductor substrate.

  Patent Document 1 discloses a group III in which a plurality of crystal substrates cut out from a group III nitride bulk crystal are arranged adjacent to each other in the lateral direction, and a group III nitride crystal is grown on the substrate. A method for producing a nitride crystal is disclosed. Further, Patent Document 1 discloses that if there is a gap between crystal substrates, the crystallinity of crystals growing on the crystal substrates is lowered, so that the crystal substrates are arranged adjacent to each other.

Japanese Patent No. 5332168

  In the case of the technique described in Patent Document 1, the plurality of crystal substrates constituting the substrate are separated from each other. When a plurality of crystal substrates are separated from each other, it is necessary to hold each of the plurality of crystal pieces and move them when moving the substrate composed of the plurality of crystal substrates. Further, when a substrate composed of a plurality of crystal substrates is set at a predetermined position, each of the plurality of crystal pieces needs to be set at a predetermined position with a predetermined positional relationship. Thus, workability is poor when a plurality of crystal substrates are separated from each other.

  An object of the present invention is to provide a new technique for manufacturing a group III nitride semiconductor substrate.

According to the present invention,
A plurality of group III nitride semiconductor crystal pieces arranged with a gap between each other; and
A binder interposed in the gap and holding a plurality of the crystal pieces;
There is provided a group III nitride semiconductor substrate having:

Moreover, according to the present invention,
An arrangement step of arranging a plurality of group III nitride semiconductor crystal pieces with a gap between each other,
Forming a binder that is interposed in the gap and holds the plurality of crystal pieces; and
There is provided a method for producing a group III nitride semiconductor substrate having:

  According to the present invention, a new technique for manufacturing a group III nitride semiconductor substrate is realized.

It is an example of the cross-sectional schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the cross-sectional schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the cross-sectional schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the cross-sectional schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the plane schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the plane schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the cross-sectional schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the cross-sectional schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the cross-sectional schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the cross-sectional schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the plane schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is an example of the plane schematic diagram of the group III nitride semiconductor substrate of this embodiment. It is a flowchart which shows an example of the manufacturing method of the group III nitride semiconductor substrate of this embodiment. It is a schematic diagram for demonstrating an example of the process which cuts out a crystal piece from a group III nitride semiconductor substrate. It is a schematic diagram for demonstrating an example of the process which cuts out a crystal piece from a group III nitride semiconductor substrate. It is a schematic diagram for demonstrating an example of the process which cuts out a crystal piece from a group III nitride semiconductor substrate. It is a schematic diagram for demonstrating an example of the process which cuts out a crystal piece from a group III nitride semiconductor substrate. It is a schematic diagram for demonstrating an example of the manufacturing method of the group III nitride semiconductor substrate of this embodiment. It is a schematic diagram for demonstrating an example of the manufacturing method of the group III nitride semiconductor substrate of this embodiment. It is a schematic diagram for demonstrating an example of the manufacturing method of the group III nitride semiconductor substrate of this embodiment. It is a schematic diagram for demonstrating an example of the manufacturing method of the group III nitride semiconductor substrate of this embodiment. It is a figure for demonstrating the effect of the group III nitride semiconductor substrate of this embodiment. It is a schematic diagram for demonstrating an example of the manufacturing method of the group III nitride semiconductor substrate of this embodiment. It is a schematic diagram for demonstrating an example of the manufacturing method of the group III nitride semiconductor substrate of this embodiment. It is a schematic diagram for demonstrating an example of the manufacturing method of the group III nitride semiconductor substrate of this embodiment.

  Hereinafter, embodiments of a group III nitride semiconductor substrate and a method for manufacturing a group III nitride semiconductor substrate of the present invention will be described with reference to the drawings. The drawings are only schematic diagrams for explaining the configuration of the invention, and the size, shape, number, and ratio of different member sizes are not limited to those shown in the drawings.

  1 to 4 show an example of a schematic cross-sectional view of a group III nitride semiconductor substrate 1 of the present embodiment. FIGS. 5 and 6 show examples of schematic plan views of the group III nitride semiconductor substrate 1 of FIGS.

  7 to 10 show other examples of schematic cross-sectional views of the group III nitride semiconductor substrate 1 of the present embodiment. FIG. 11 and FIG. 12 show examples of schematic plan views of the group III nitride semiconductor substrate 1 of FIGS.

  As shown in FIGS. 1 to 12, the group III nitride semiconductor substrate 1 of this embodiment includes a plurality of crystal pieces 10 and a binder 20. In addition, the number of the crystal pieces 10 to show in figure is an example, and is not limited to this.

The crystal piece 10 is composed of a single crystal of a group III nitride semiconductor. The plurality of crystal pieces 10 attached to each other through the binder 20 are formed of the same type of group III nitride semiconductor (Al _x Ga _1-xy In _y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) and x and y of the crystal pieces 10 are preferably the same). The crystal piece 10 can be cut from a group III nitride semiconductor substrate, a fragment of the substrate, or the like.

  The crystal piece 10 is a plate-like body having two main surfaces (a first main surface 11 and a second main surface 12) and a side surface 13. The first main surface 11 and the second main surface 12 are in a front-back relationship. The first main surface 11 and the second main surface 12 may be parallel to each other. The shape and size of the first main surface 11 and the second main surface 12 may be the same or different. The shape of the first main surface 11 is, for example, a rectangle as shown in FIGS. 5, 6, 11, and 12, and the size is, for example, 2 mm to 100 mm in length and 2 mm to 100 mm in width. . The first main surface 11 and the second main surface 12 may have other shapes.

  The side surface 13 may be perpendicular to the first main surface 11 and the second main surface 12 as shown in FIGS. 1 to 4 and FIGS. 9 to 12. Although not shown, the angle formed between the side surface 13 and the first main surface 11 and the second main surface 12 may be different from 90 °.

  The thickness of the crystal piece 10 (the distance between the first main surface 11 and the second main surface 12) is, for example, 50 μm or more and 20 mm or less.

  It is preferable that the shape and size of the plurality of crystal pieces 10, particularly the shape and size of the first main surface 11, are aligned. “Shape and size are uniform” is a concept including a state in which the shape and size are completely matched and a state in which there is a shift due to a processing error.

  The first main surface 11 is a surface having a predetermined plane orientation. For example, the first main surface 11 may be a + c plane, an m plane, or an a plane. In addition, the first main surface 11 is a {hk− (h + k) l} surface (h, k, and l are integers), or a surface obtained by inclining the {hk− (h + k) l} surface by a predetermined angle. It may be a surface different from the + c surface, the m surface, and the a surface.

  For example, the first main surface 11 is a + c surface, a surface obtained by inclining a + c surface by a predetermined angle (eg, ± 10 ° or less), a m surface, a surface obtained by inclining a m surface by a predetermined angle (eg, ± 10 ° or less), a Surface, a surface inclined by a predetermined angle (eg, ± 10 ° or less), {11-22} surface, surface {11-22} surface inclined by a predetermined angle (eg: ± 10 ° or less), {11− 24} plane, {11-24} plane tilted by a predetermined angle (eg, ± 10 ° or less), {10-12} plane, {10-12} plane tilted by a predetermined angle (eg, ± 10 ° or less) {10-11} plane, {10-11} plane tilted by a predetermined angle (eg, ± 10 ° or less), {20-21} plane, {20-21} plane by a predetermined angle (eg: Any of the inclined surface, {20-23} surface, and {20-23} surface inclined by a predetermined angle (eg, ± 10 ° or less) may be used. .

  The plane orientations of the first principal surfaces 11 of the plurality of crystal pieces 10 are preferably aligned. “The plane orientation is aligned” means that the plane orientations of the first principal surfaces 11 of the plurality of crystal pieces 10 coincide with each other and / or the desired reference plane orientation and the plurality of crystal pieces 10. This is a concept including a state in which the difference from the plane orientation of each first main surface 11 is ± 0.5 ° or less.

  The plurality of crystal pieces 10 are preferably aligned in the direction in which the first main surface 11 faces. “The direction in which the first main surface 11 faces is aligned” means that the normal directions of the first main surfaces 11 of the plurality of crystal pieces 10 coincide with each other and / or a desired reference direction. And a concept including a state in which the difference between the normal direction of the first main surface 11 of each of the plurality of crystal pieces 10 is ± 0.5 ° or less.

  The plurality of crystal pieces 10 preferably have an orientation accuracy of ± 0.5 ° or less in a direction parallel to the first main surface 11. That is, the plurality of crystal pieces 10 have an orientation accuracy in a direction parallel to the paper surface in FIGS. 5, 6, 11, and 12, in other words, an orientation accuracy adjusted by rotating around a rotation axis perpendicular to the paper surface. Is preferably ± 0.5 ° or less. “Direction accuracy is ± 0.5 ° or less” means that a difference from a desired reference direction is ± 0.5 ° or less.

  As shown in FIGS. 1 to 12, the first main surface 11 is exposed. The first main surface 11 becomes a growth surface (a surface on which a group III nitride semiconductor crystal is grown) of the group III nitride semiconductor substrate 1 of the present embodiment.

  As shown in FIGS. 1 to 12, the plurality of crystal pieces 10 are arranged so as to face the other crystal pieces 10 on the side surfaces 13.

  As shown in FIGS. 3, 4, 9 and 10, the second main surface 12 may be exposed. In addition, as shown in FIGS. 1, 2, 7 and 8, the second main surface 12 is covered with the binder 20 and may not be exposed. Although not shown, the second main surface 12 may be partially covered with the binder 20 and partially exposed.

  The plurality of crystal pieces 10 are preferably arranged according to a predetermined regularity. For example, as shown in FIGS. 5, 6, 11, and 12, the plurality of crystal pieces 10 may be arranged such that the longitudinal directions of the rectangular first main surface 11 are parallel to each other. Further, the plurality of crystal pieces 10 may be arranged so as to be linearly arranged in one or a plurality of rows.

  The plurality of crystal pieces 10 are arranged with a gap 30 between them. The width G of the gap 30 is, for example, 50 μm or more and 10 mm or less. A gap 30 between adjacent crystal pieces 10 is defined as the shortest distance between adjacent crystal pieces 10.

  In FIG. 1 to FIG. 12, the gap 30 exists along the entire outer periphery of the crystal piece 10, but it is sufficient that the gap 30 exists at least at a part along the outer periphery of the crystal piece 10. For example, when the first main surface 11 and the second main surface 12 are rectangular plates, the crystal piece 10 has four side surfaces 13. In this case, the crystal piece 10 only needs to have a gap 30 in front of at least one side surface 13. The other side surface 13 may be in contact with the side surface 13 of another crystal piece 10.

  Naturally, as shown in FIGS. 1 to 12, there may be a gap 30 along the entire outer periphery of the crystal piece 10. In this case, the crystal piece 10 does not contact the other crystal pieces 10 at all.

  As shown in FIGS. 1 to 12, the binder 20 is interposed in the gap 30 between the crystal pieces 10 and holds the plurality of crystal pieces 10. The binder 20 interposed in the gap 30 is in contact with and in close contact with the side surface 13 of the crystal piece 10. The height of the binder 20 interposed in the gap 30 is at least one third of the depth of the gap 30, preferably at least one half, and more preferably at least two thirds.

  The binder 20 is made of a polycrystalline group III nitride semiconductor. The binder 20 may be the same type of group III nitride semiconductor as the crystal piece 10 or may be a different type.

  As shown in FIGS. 1, 2, 7, and 8, the binder 20 may extend from the gap 30 toward the second main surface 12. The binder 20 may be in contact with the crystal piece 10 on the side surface 13 and the second main surface 12, and may be in close contact with each other to hold the plurality of crystal pieces 10. In this case, the thickness M from the second main surface 12 is greater than 0 μm and not greater than 20 mm, more preferably greater than 0 μm and not greater than 1 mm.

  As another example, as shown in FIGS. 3, 4, 9, and 10, the binder 20 exists only in the gap 30 and extends to the first main surface 11 and the second main surface 12. It does not have to be. In this case, the value of M is 0.

  Moreover, the binder 20 may exist so as to enclose the plurality of crystal pieces 10 along the outer periphery of the plurality of crystal pieces 10 as shown in FIGS.

  As another example, as shown in FIGS. 7 to 12, the binder 20 may not exist along the outer periphery of the plurality of crystal pieces 10 but may exist only in the gaps 30 between the crystal pieces 10.

  In the group III nitride semiconductor substrate 1 of this embodiment, as shown in FIGS. 1 to 12, the crystal piece 10 and the binder 20 are exposed on the exposed surface on the side where the first main surface 11 is exposed. .

  As shown in FIGS. 1, 4, 7, and 10, the crystal piece 10 and the binder 20 may be flush with each other. In addition, as shown in FIGS. 2, 3, 8, and 9, the crystal piece 10 may be a convex portion and the binder 20 may be a concave portion.

  In the latter case, the upper limit of the step D between the adjacent crystal piece 10 and the binder 20 can be set to a predetermined value corresponding to the substrate thickness (thickness of the group III nitride semiconductor substrate 1). For example, the step D can be 1 μm or more and (substrate thickness−100) μm or less. That is, when the substrate thickness is 400 μm, the step D is 1 μm to 300 μm, when the substrate thickness is 600 μm, the step D is 1 μm to 500 μm, and when the substrate thickness is 800 μm, the step D is 1 μm to 700 μm. be able to. If it does in this way, the thickness of the binder 20 can be 100 micrometers or more. As a result, the holding power of the plurality of crystal pieces 10 by the binder 20 can be sufficiently increased.

  Next, an example of the manufacturing method of the group III nitride semiconductor substrate 1 of this embodiment is demonstrated using the flowchart of FIG. As shown in the drawing, the method for manufacturing the group III nitride semiconductor substrate 1 of the present embodiment includes a preparation step S10, an arrangement step S20, and a formation step S30.

  In the preparation step S10, a plurality of group III nitride semiconductor crystal pieces 10 are prepared. For example, a plurality of crystal pieces 10 are prepared by cutting out crystal pieces 10 having a predetermined shape from a group III nitride semiconductor substrate or a fragment of the substrate.

  The means for cutting out is not particularly limited, and the crystal piece 10 may be cut out using a band saw, an inner peripheral blade, an outer peripheral blade or the like, or may be cut out by cleaving at a cleavage plane. In addition, the shape and size of the crystal piece 10 may be adjusted by subjecting the cut crystal piece 10 to a process such as polishing.

  An example of the process of cutting the crystal piece 10 from the group III nitride semiconductor substrate will be described with reference to FIGS. 14 and 15. FIG. 14 is a schematic side view of the group III nitride semiconductor substrate 40, and FIG. 15 is a schematic plan view of the group III nitride semiconductor substrate 40. The group III nitride semiconductor substrate 40 may be a substrate obtained by + c-plane growth as shown, or may be other.

  For example, as shown in FIGS. 14 and 15, a plurality of group III nitride semiconductor substrates 40 are separated from each other by a first cut surface 41 parallel to the m-axis direction and a second cut surface 42 perpendicular to the m-axis direction. The crystal piece 10 may be cut out. By adjusting the distance between each of the first cut surface 41 and the second cut surface 42, the first cut surface 41 or the second cut surface is changed to the first main surface 11 of the crystal piece 10. It can be. The second cut surface 42 is an m-plane. By adjusting the inclination of the first cut surface 41 with respect to the + c-axis direction, the surface orientation of the first main surface 11 can be the a-plane or a desired semipolar plane.

  Another example of the process of cutting the crystal piece 10 from the group III nitride semiconductor substrate will be described with reference to FIGS. 16 and 17. FIG. 16 is a schematic side view of the group III nitride semiconductor substrate 40, and FIG. 17 is a schematic plan view of the group III nitride semiconductor substrate 40. The group III nitride semiconductor substrate 40 may be a substrate obtained by + c-plane growth as shown, or may be other.

  For example, as shown in FIGS. 16 and 17, a plurality of group III nitride semiconductor substrates 40 are separated from each other by a first cut surface 41 parallel to the m-axis direction and a second cut surface 42 perpendicular to the m-axis direction. The crystal piece 10 may be cut out. By adjusting the distance between each of the first cut surface 41 and the second cut surface 42, the exposed surface 43 of the group III nitride semiconductor substrate 40 is used as the first main surface 11 of the crystal piece 10. Can do. In the example shown in FIGS. 16 and 17, the first main surface 11 is a + c surface.

  Returning to FIG. 13, in the arranging step S <b> 20, a plurality of group III nitride semiconductor crystal pieces 10 are arranged with a gap 30 therebetween. The width G of the gap 30 is, for example, 50 μm or more and 10 mm or less. In the arrangement step S20, the crystal pieces 10 are arranged in a desired direction.

  For example, as shown in FIG. 18, the plurality of crystal pieces 10 are arranged side by side on the holding member 50. The holding member 50 has a placement surface 51 on which a plurality of crystal pieces 10 are placed. The plurality of crystal pieces 10 are arranged on the mounting surface 51 according to, for example, predetermined regularity.

  23 and 24 show an example of a schematic plan view of FIG. On the holding member 50, there is an adjusting member 53 for aligning the direction in the direction parallel to the first main surface 11 of the crystal piece 10. The adjustment member 53 has an orientation adjustment surface with which a predetermined surface of the crystal piece 10 is in surface contact. As shown in FIGS. 23 and 24, all the crystal pieces 10 are arranged in a “state in which the predetermined side surface 13 is in surface contact with the orientation adjustment surface of the adjustment member 53”. The predetermined side surface 13 is a surface having a predetermined plane orientation. For example, the crystal piece 10 is processed so as to have the side surface 13 having such a predetermined plane orientation.

  According to such an arrangement method, the orientation in the direction parallel to the first main surface 11 of each of the plurality of crystal pieces 10 becomes a desired state. 23, a gap 30 having a width G (eg, 50 μm or more and 10 mm or less) may be provided between the crystal pieces 10 adjacent to each other in a direction parallel to the adjustment member 53. Alternatively, as shown in FIG. 24, in a state where the predetermined side surface 13 is in surface contact with the adjustment member 53, it can be in contact with another crystal piece 10 adjacent to the adjustment member 53 in a direction parallel to the adjustment member 53. You may make the crystal piece 10 adjacent to a direction contact. However, “the state in which the predetermined side surface 13 is in surface contact with the orientation adjustment surface of the adjustment member 53” is prioritized over “contact between the crystal pieces 10 adjacent in the direction parallel to the adjustment member 53”. For this reason, as shown in FIG. 24, when the predetermined side surface 13 is in surface contact with the adjustment member 53 and cannot be in contact with another crystal piece 10 adjacent in a direction parallel to the adjustment member 53, it is parallel to the adjustment member 53. A gap 31 is formed between crystal pieces 10 adjacent to each other in any direction.

  The adjustment member 53 may be removable from the holding member 50. And if the crystal piece 10 is arrange | positioned in a desired state and it fixes to the position, the adjustment member 53 may be removed from the holding member 50 before formation process S30. In this case, after the adjustment member 53 is removed, the space where the adjustment member 53 exists becomes the gap 30. The width of the adjustment member 53 is, for example, 50 μm or more and 10 mm or less.

  The adjustment member 53 may be positioned on the holding member 50 during the formation step S30. In this case, as shown in FIG. 25, the height of the adjustment member 53 is configured to be smaller than the thickness of the crystal piece 10. 25 is an example of a side view of FIGS. 23 and 24 viewed from the left to the right in the drawing. In this case, as illustrated in FIG. 25, a gap 30 having a width of, for example, 50 μm or more and 10 mm or less is formed between the crystal pieces 10 and above the adjustment member 53.

  As another arrangement example, for example, as illustrated in FIG. 19, the holding member 50 may include a plurality of holes 52 into which the crystal pieces 10 having a predetermined shape are fitted. Each of the plurality of crystal pieces 10 may be fitted into each hole 52. In this case, the interval G of the gap 30 of the crystal piece 10 can be adjusted by the interval of the holes 52.

  In the arranging step S20, as shown in FIG. 18 and FIG. 19, the plurality of crystal pieces 10 are formed so that the first main surface 11 faces the mounting surface 51 and the second main surface 12 is exposed. Deploy. Further, the plurality of crystal pieces 10 are arranged so as to face each other at the side surfaces 13.

  The means for holding the crystal pieces 10 on the holding member 50 is not particularly limited. For example, even if a plurality of crystal pieces 10 are bonded and held using an adhesive that does not cause impurity contamination and does not adversely affect the formation of the binder 20. Good. The holding member 50 may be made of, for example, ceramic.

  Returning to FIG. 13, in the formation step S30, the binder 20 made of a polycrystalline group III nitride semiconductor is formed on the plurality of crystal pieces 10 so as to be interposed in the gaps 30 (see FIGS. 20 and 21). . As shown in FIGS. 20 and 21, the binder 20 is formed on the second main surface 12 while being interposed in the gap 30. As a method for forming the binder 20, a vapor phase epitaxial growth method (for example, HVPE method, MOVPE method), a sodium flux liquid phase growth method, an ammonothermal growth method, a sputtering method, a molecular beam epitaxial growth method, a sintering method, and the like can be considered. .

  The formation conditions can be the same as general conditions. In the present embodiment, the gap 30 between the crystal pieces 10 is 50 μm or more. For this reason, for example, when a group III nitride semiconductor crystal is formed under the general growth conditions of the HVPE method, the source gas enters the gap 30 and, for example, the binder 20 interposed in the gap 30 is formed.

  After the formation step S30, the group III nitride semiconductor substrate 1 may be removed from the holding member 50, and then surface processing may be performed by polishing such as CMP and / or etching with a chemical solution. Similarly, the side surface of the group III nitride semiconductor substrate 1 may be processed.

  For example, when the group III nitride semiconductor substrate 1 is removed from the holding member 50 after the state shown in FIG. 20 is obtained by the forming step S30, the state shown in FIG. 1 is obtained. Thereafter, when the binder 20 along the outer periphery is removed by processing such as polishing, the state of FIG. 7 is obtained. Moreover, when the binder 20 by the side of the 2nd main surface 12 is removed by processes, such as grinding | polishing, from the state shown in FIG. 1 and the state shown in FIG. 7, the state shown in FIG.4 and FIG.10 will be obtained.

  In addition, when the group III nitride semiconductor substrate 1 is removed from the holding member 50 after the state shown in FIG. 21 is obtained by the forming step S30, the state shown in FIG. 2 is obtained. Thereafter, when the binder 20 along the outer periphery is removed by processing such as polishing, the state of FIG. 8 is obtained. Further, when the binder 20 on the second main surface 12 side is removed by processing such as polishing from the state shown in FIG. 2 and the state shown in FIG. 8, the state shown in FIG. 3 and FIG. 9 is obtained.

  The order of removing the binder 20 along the outer periphery and the binder 20 on the second main surface 12 side is not limited to this.

  As described above, the group III nitride semiconductor substrate 1 of the present embodiment is obtained. Note that the group III nitride semiconductor substrate 1 of the present embodiment is a self-supporting substrate on which electronic devices and optical devices are formed, and a group III nitride semiconductor layer is formed thereon to obtain a self-supporting substrate. It can be used as an underlying substrate.

  Next, the effect of this embodiment is demonstrated.

  The group III nitride semiconductor substrate 1 of this embodiment is composed of a plurality of crystal pieces 10. There are gaps 30 between the plurality of crystal pieces 10. And the binder 20 exists in the said clearance gap 30 and the crystal piece 10 is hold | maintained. Thus, although the group III nitride semiconductor substrate 1 of this embodiment is comprised by the several crystal piece 10, they are hold | maintained by the binder 20 which exists among each other. That is, the plurality of crystal pieces 10 are in one lump.

  When the plurality of crystal pieces 10 are separated from each other, it is necessary to hold each of the plurality of crystal pieces 10 and move them when moving the substrate made of the plurality of crystal pieces 10. Further, when a substrate made of a plurality of crystal pieces 10 is set at a predetermined position, each of the plurality of crystal pieces 10 needs to be set at a predetermined position with a predetermined positional relationship. Thus, when the several crystal piece 10 is isolate | separated from each other, workability | operativity is bad. In the group III nitride semiconductor substrate 1 of the present embodiment, as described above, the plurality of crystal pieces 10 are bundled together by the binder 20. For this reason, workability at the time of moving the group III nitride semiconductor substrate 1 or setting it to a predetermined position is good.

  Further, if the plurality of crystal pieces 10 remain separated from each other, there is a risk of cracking during the manufacturing process of the substrate made of the plurality of crystal pieces 10 and the handling of the substrate in a subsequent process. In addition, even when the plurality of separated crystal pieces 10 are processed and removed, there is a risk of cracking due to stress concentration on the separated portions. The group III nitride semiconductor substrate 1 of this embodiment can reduce such inconvenience.

  Further, in the group III nitride semiconductor substrate 1 of the present embodiment, the size of the crystal piece 10 can be controlled to a predetermined size. For example, the main surface (the first main surface 11 and the second main surface 12) of the crystal piece 10 can be a rectangle having a length of 2 mm to 100 mm and a width of 2 mm to 100 mm. When the upper limit of the size of the main surface is set in this way, the crystal piece 10 can be held with sufficient strength by the binder 20, and the crystal piece 10 is hardly peeled off. Further, when the lower limit of the size of the main surface is set in this way, the size of the main surface can be made large enough to form a device.

  Further, the thickness of the group III nitride semiconductor substrate 1 can be set to 50 μm or more and 20 mm or less. When the lower limit of the thickness is set in this way, the contact area between the binder 20 existing in the gap 30 between the crystal pieces 10 and the side surface 13 of the crystal piece 10 can be sufficiently increased. As a result, the crystal piece 10 can be held with sufficient strength by the binder 20. Further, when the upper limit of the thickness is set in this way, it is possible to avoid the disadvantage that the thickness of the group III nitride semiconductor substrate 1 becomes unnecessarily thick. As a result, the weight and thickness of the group III nitride semiconductor substrate 1 can be reduced, and the workability when carrying the group III nitride semiconductor substrate 1 can be improved, and the space can be saved during storage. The

  In addition, the group III nitride semiconductor substrate 1 of this embodiment uses the exposed surface from which the 1st main surface 11 is exposed as a growth surface. And in the said exposed surface, not only the 1st main surface 11 but the binder 20 is exposed. When the present inventors have grown a single crystal of a group III nitride semiconductor on such a growth surface, many dislocations are generated above the binder 20, but above the first main surface 11. It was confirmed that the crystallinity was good. That is, according to the group III nitride semiconductor substrate 1 of the present embodiment, an appropriate area on the group III nitride semiconductor substrate 1 (an area above the first main surface 11 having good crystallinity) is selected. Thus, a predetermined device can be formed.

  Moreover, the group III nitride semiconductor substrate 1 of this embodiment can make the shape and magnitude | size of the several crystal piece 10 especially the shape and magnitude | size of the 1st main surface 11 uniform. As described above, when a device is formed on the group III nitride semiconductor substrate 1 of the present embodiment, it is necessary to selectively form the device on a portion where the first main surface 11 is exposed. When the shape and size of the first main surface 11 are uniform and the plurality of crystal pieces 10 are regularly arranged as in the present embodiment, the group III nitride semiconductor substrate 1 is based on the regularity. It is possible to easily specify the position at which the first main surface 11 is exposed on the growth surface. As a result, workability during device creation is improved.

  Further, in the group III nitride semiconductor substrate 1 of the present embodiment, the width G of the gap 30 between the crystal pieces 10 can be set to 50 μm or more and 10 mm or less. When the lower limit of the gap 30 is set in this way, the gas used as the raw material of the binder 20 can sufficiently enter the gap 30 during the process of forming the binder 20. As a result, the binder 20 can be formed in the gap 30. In addition, when the upper limit of the gap 30 is set in this manner, the exposure ratio of the binder 20 on the growth surface of the group III nitride semiconductor substrate 1 can be sufficiently reduced.

  Further, the group III nitride semiconductor substrate 1 of the present embodiment has a configuration in which the binder 20 extends from the gap 30 toward the second main surface 12 as shown in FIGS. 1, 2, 7, and 8. can do. The plurality of crystal pieces 10 can be held by the binder 20 in contact with and closely contacting the crystal pieces 10 on the side surface 13 and the second main surface 12. According to the said structure, the contact area of the crystal piece 10 and the binder 20 becomes large. As a result, the holding force of the crystal piece 10 by the binder 20 is increased, which is preferable.

  Further, in the group III nitride semiconductor substrate 1 of the present embodiment, as shown in FIGS. 3, 4, 9 and 10, the binder 20 extends to the first main surface 11 and the second main surface 12. It can be set as the structure which exists only in the clearance gap 30 not. According to this configuration, the group III nitride semiconductor substrate 1 can be reduced in weight and thickness. Further, when manufacturing a device that requires a back electrode, contact between the crystal piece 10 on the back surface side and the electrode is required. In the case of this configuration, it is not necessary to drop the binder 20, or even if the substrate thickness is reduced. The degree of freedom increases.

  In addition, as shown in FIGS. 1 to 6, the group III nitride semiconductor substrate 1 of the present embodiment is present such that the binder 20 encloses the plurality of crystal pieces 10 along the outer periphery of the plurality of crystal pieces 10. It can also be configured. According to the said structure, the contact area of the crystal piece 10 and the binder 20 becomes large. As a result, the holding force of the crystal piece 10 by the binder 20 is increased, which is preferable.

  Further, in the group III nitride semiconductor substrate 1 of the present embodiment, as shown in FIGS. 7 to 12, the binder 20 does not exist along the outer periphery of the plurality of crystal pieces 10, and only in the gaps 30 between the crystal pieces 10. It can also be configured to exist. According to the said structure, the weight reduction and size reduction (surface area size reduction) of the group III nitride semiconductor substrate 1 are implement | achieved. In addition, device yield can be improved, and orientation flat orientation measurement using the side surface of the group III nitride semiconductor substrate 1 can be performed.

  Further, the group III nitride semiconductor substrate 1 of the present embodiment has a configuration in which the binder 20 extends to the second main surface 12 side, as shown in FIGS. 1, 2, 7, and 8. The thickness M from the second main surface 12 of the binder 20 can be 1 mm or more and 20 mm or less. If it does in this way, the intensity | strength of the binder 20 as a backing layer will become enough. As a result, the strength against bending of the group III nitride semiconductor substrate 1 as a whole is increased, and the inconvenience of the crystal piece 10 being peeled off from the binder 20 can be suppressed.

  Further, in the group III nitride semiconductor substrate 1 of the present embodiment, the height of the binder 20 interposed in the gap 30 is at least one third of the depth of the gap 30, preferably at least one half, more preferably More than two-thirds, more preferably, the exposed surface of the binder 20 and the first main surface 11 of the crystal piece 10 can be in a flush state. Thus, since the binder 20 can be sufficiently interposed in the gap 30, the contact area between the crystal piece 10 and the binder 20 can be increased. As a result, the adhesive force between the crystal piece 10 and the binder 20 can be further increased.

  Further, in the method of manufacturing the group III nitride semiconductor substrate 1 of the present embodiment, all the crystal pieces 10 are “in a state in which the side surface 13 of a predetermined plane orientation is in surface contact with the adjustment member 53” in FIGS. 23 and 24. It is arranged with. Thereby, the direction of the direction parallel to the 1st main surface 11 of each of the some crystal piece 10 will be in a desired state. The group III nitride semiconductor substrate 1 of this embodiment manufactured by such a manufacturing method has a surface in which a plurality of crystal pieces 10 are not in contact with other crystal pieces 10 (a side surface in contact with the adjustment member 53). 13).

  By the way, as a method of arranging a plurality of crystal pieces 10 side by side, a method of arranging adjacent crystal pieces 10 so that their side faces come into surface contact with each other can be considered. In the case of placing with priority on reducing the gap between the crystal pieces 10, the placement method is preferable. However, in the case of this method, the orientation of a certain crystal piece 10 in the direction parallel to the first main surface 11 depends on the state of the other crystal pieces 10 (the orientation of the arrangement of the other crystal pieces 10, There is a problem that it is influenced by the processing accuracy of the parallelism / verticality of the side surface. The influence will be described with reference to FIG.

  An arrow A shown in FIG. 22 is a predetermined axial direction (eg, m-axis direction) of the crystal piece 10. The desired arrangement state is a state in which a predetermined axial direction (eg, m-axis direction) of the crystal piece 10 is parallel to the first direction.

  In the left crystal piece 10 shown in FIG. 22, a predetermined axial direction indicated by an arrow A is parallel to the first direction. However, in the crystal piece 10 on the right side, the predetermined axial direction indicated by the arrow A is not parallel to the first direction. This is due to the fact that the processing accuracy of the right side surface of the left crystal piece 10 is inferior and is cut slightly diagonally, and that the side surface of the right crystal piece 10 is placed in surface contact with the side surface. .

  Thus, when arranging a plurality of crystal pieces 10 in a state where the side surfaces are in contact with each other, when the orientation of the arrangement of the crystal pieces 10 is deviated at a certain point, Due to the presence of processing accuracy such as perpendicularity, the state of other crystal pieces 10 is affected. Furthermore, as the number of the crystal pieces 10 increases, the number of contact portions increases, and the influence of the state of the crystal pieces 10 is accumulated, so that the possibility that the misalignment increases is increased. As a result, there are many crystal pieces 10 whose orientation in the direction parallel to the first main surface 11 is deviated from a desired state.

  In the case of the present embodiment, all the crystal pieces 10 are arranged in a “state in which the side surface 13 of a predetermined plane orientation is in surface contact with the orientation adjustment surface of the adjustment member 53”. For this reason, the above inconveniences can be avoided. As a result, the orientation accuracy in the direction parallel to the first main surface 11 of the plurality of crystal pieces 10 can be ± 0.5 ° or less. According to the group III nitride semiconductor substrate 1 having such orientation accuracy, the crystallinity of the group III nitride semiconductor grown on the group III nitride semiconductor substrate 1 is improved.

  In the present embodiment, the binder 20 can be composed of a polycrystalline group III nitride semiconductor. In this case, the binder 20 having a desired thickness can be formed in a shorter time compared to the case where the binder 20 is formed of a single crystal group III nitride semiconductor.

  In the case of this embodiment, the crystal piece 10 can be cut out from a single crystal group III nitride semiconductor fragment or the like. Such debris has been conventionally discarded. According to the present embodiment, it is possible to use debris that has been conventionally discarded, which is advantageous in terms of cost.

  Further, the group III nitride semiconductor substrate 1 of this embodiment is used as a self-supporting substrate or a base substrate. In any case, a group III nitride semiconductor may be grown on the group III nitride semiconductor substrate 1. The inventors of the present invention have grown a group III nitride semiconductor on a substrate in which a plurality of crystal pieces are in contact with each other, and joined the group III nitride semiconductor grown from each crystal piece to form a group III nitride semiconductor layer. When formed, it has been confirmed that a large amount of dislocations occurs immediately above the interface between the crystal pieces.

  In addition, as the thickness of the group III nitride semiconductor layer increases, the large amount of dislocations tends to propagate and propagate in a traveling direction that is bent due to a rough growth morphology. For this reason, dislocations do not exist locally on the exposed surface (growth surface) of the group III nitride semiconductor layer, but are widely distributed. As a result, it is difficult to obtain an area with few dislocations on the exposed surface.

  In the present embodiment, when the predetermined gap 30 is provided between the crystal pieces 10 as in the present embodiment, dislocations generated immediately above the interface between the crystal pieces 10 increase the thickness of the group III nitride semiconductor layer. It has been confirmed that the inconvenience that the traveling direction is bent and spreads can be reduced. Therefore, dislocations concentrate on the exposed surface of the group III nitride semiconductor layer formed on the group III nitride semiconductor substrate 1, just above the interface between the crystal pieces 10, that is, above the binder 20. As a result, dislocations are reduced in a portion other than just above the interface, for example, an area immediately above the center of the exposed surface of the crystal piece 10. For this reason, a device can be selectively formed on the area.

  Further, in the group III nitride semiconductor substrate 1 of this embodiment, as shown in FIGS. 2, 3, 8, and 9, the crystal piece 10 becomes a convex portion on the growth surface of the group III nitride semiconductor substrate 1. The binder 20 may be a recess. In this case, when a single crystal group III nitride semiconductor is epitaxially grown on the exposed surface, it is possible to reduce the occurrence of inconvenience such as abnormal growth at the interface between the crystal piece 10 and the binder 20. For example, even if a polycrystal is formed in the recess during the growth process, the polycrystal is prevented from protruding upward from the projection. As a result, the influence on the lithography process at the time of device fabrication is reduced. Further, the crystals grown from each of the two convex portions adjacent to each other across the concave portion are bonded to each other so as to cover the crystal grown from the concave portion between them. As a result, the crystal grown from the convex portion is covered with the crystal grown from the concave portion. For this reason, the disadvantage that the crystal grown from the recess appears on the growth surface can be reduced. That is, it is possible to reduce the inconvenience that a crystal grown from a polycrystalline group III nitride semiconductor (binder 20) appears on the growth surface.

  Further, in the group III nitride semiconductor substrate 1 of the present embodiment, the step D between the adjacent crystal piece 10 and the binder 20 can be 1 μm or more (substrate thickness (μm) −100 (μm)) μm or less. By setting the step D to be 1 μm or more, it is possible to suppress the above-described polycrystal on the concave portion from protruding from the convex portion, or to obtain a state where the crystal grown from the convex portion covers the crystal grown from the concave portion. It becomes easy. Moreover, the thickness of the binder 20 can be 100 micrometers or more by making the level | step difference D into (board | substrate thickness -100) micrometers or less. As a result, it is possible to obtain effects such as preventing substrate breakage during handling and suppressing crystal fragments from being divided when reducing the substrate thickness during device fabrication.

Hereinafter, examples of the reference form will be added.
1. A plurality of group III nitride semiconductor crystal pieces arranged with a gap between each other; and
A binder interposed in the gap and holding a plurality of the crystal pieces;
A group III nitride semiconductor substrate having:
2. In the group III nitride semiconductor substrate according to 1,
The group III nitride semiconductor substrate, wherein the plurality of crystal pieces have a surface not in contact with the other crystal pieces.
3. In the group III nitride semiconductor substrate according to 2,
The crystal piece has two main surfaces in a front-back relationship, and a side surface, and the side surface is arranged to face the side surface of the other crystal piece,
The plurality of crystal pieces are group III nitride semiconductor substrates having an orientation accuracy of ± 0.5 ° or less in a direction parallel to the first main surface.
4). In the group III nitride semiconductor substrate according to 3,
A group III nitride semiconductor substrate in which the first main surface serves as a growth surface for growing a group III nitride semiconductor crystal.
5. In the group III nitride semiconductor substrate according to any one of 1 to 4,
The crystal piece has two main surfaces in a front-back relationship, and a side surface, and the side surface is arranged to face the side surface of the other crystal piece,
The group III nitride semiconductor substrate, wherein the binder is in contact with the side surface through the gap and extends to one of the main surfaces to be in contact with the main surface.
6). In the group III nitride semiconductor substrate according to any one of 1 to 5,
The binder is a group III nitride semiconductor substrate composed of a polycrystalline group III nitride semiconductor.
7). In the group III nitride semiconductor substrate according to any one of 1 to 6,
The group III nitride semiconductor substrate, wherein the crystal piece and the binder are exposed on the first exposed surface of the group III nitride semiconductor substrate, the crystal piece is a convex portion, and the binder is a concave portion.
8). In the group III nitride semiconductor substrate according to 7,
A group III nitride semiconductor substrate in which a step between the adjacent crystal piece and the binder is 1 μm or more (thickness of group III nitride semiconductor substrate (μm) −100 (μm)) μm or less.
9. In the group III nitride semiconductor substrate according to 7 or 8,
A group III nitride semiconductor substrate in which the first exposed surface serves as a growth surface for growing a group III nitride semiconductor crystal.
10. An arrangement step of arranging a plurality of group III nitride semiconductor crystal pieces with a gap between each other,
Forming a binder that is interposed in the gap and holds the plurality of crystal pieces; and
A method for producing a group III nitride semiconductor substrate having:

DESCRIPTION OF SYMBOLS 1 III group nitride semiconductor substrate 10 Crystal piece 11 1st main surface 12 2nd main surface 13 Side surface 20 Binder 30 Crevice 31 Gap 40 Group III nitride semiconductor substrate 41 1st cut surface 42 2nd cut surface 43 Exposed surface 50 Holding member 51 Placement surface 52 Hole 53 Adjusting member

Claims (10)

A plurality of group III nitride semiconductor crystal pieces arranged with a gap between each other; and
A binder interposed in the gap and holding a plurality of the crystal pieces;
A group III nitride semiconductor substrate having: In the group III nitride semiconductor substrate according to claim 1,
The group III nitride semiconductor substrate, wherein the plurality of crystal pieces have a surface not in contact with the other crystal pieces. In the group III nitride semiconductor substrate according to claim 2,
The crystal piece has two main surfaces in a front-back relationship, and a side surface, and the side surface is arranged to face the side surface of the other crystal piece,
The plurality of crystal pieces are group III nitride semiconductor substrates having an orientation accuracy of ± 0.5 ° or less in a direction parallel to the first main surface. In the group III nitride semiconductor substrate according to claim 3,
A group III nitride semiconductor substrate in which the first main surface serves as a growth surface for growing a group III nitride semiconductor crystal. In the group III nitride semiconductor substrate according to any one of claims 1 to 4,
The crystal piece has two main surfaces in a front-back relationship, and a side surface, and the side surface is arranged to face the side surface of the other crystal piece,
The group III nitride semiconductor substrate, wherein the binder is in contact with the side surface through the gap and extends to one of the main surfaces to be in contact with the main surface. In the group III nitride semiconductor substrate according to any one of claims 1 to 5,
The binder is a group III nitride semiconductor substrate composed of a polycrystalline group III nitride semiconductor. In the group III nitride semiconductor substrate according to any one of claims 1 to 6,
The group III nitride semiconductor substrate, wherein the crystal piece and the binder are exposed on the first exposed surface of the group III nitride semiconductor substrate, the crystal piece is a convex portion, and the binder is a concave portion. In the group III nitride semiconductor substrate according to claim 7,
A group III nitride semiconductor substrate in which a step between the adjacent crystal piece and the binder is 1 μm or more (thickness of group III nitride semiconductor substrate (μm) −100 (μm)) μm or less. In the group III nitride semiconductor substrate according to claim 7 or 8,
A group III nitride semiconductor substrate in which the first exposed surface serves as a growth surface for growing a group III nitride semiconductor crystal. An arrangement step of arranging a plurality of group III nitride semiconductor crystal pieces with a gap between each other,
Forming a binder that is interposed in the gap and holds the plurality of crystal pieces; and
A method for producing a group III nitride semiconductor substrate having:

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