JP2022013255A - Manufacturing method for junction type semiconductor wafer, and manufacturing method for junction type semiconductor element - Google Patents

Abstract

To provide a manufacturing method for a junction type semiconductor wafer by which the manufacturing cost can be reduced, and a manufacturing method for a junction type semiconductor element by which the manufacturing cost can be reduced.SOLUTION: A manufacturing method for a junction type semiconductor wafer includes the steps of: epitaxially growing a sacrificial layer on a departure substrate; epitaxially growing a compound semiconductor function layer on the sacrificial layer; forming a trench so that the sacrificial layer is exposed in a partial region of the compound semiconductor function layer by a selective etching method; forming a protection film in an exposed part of the sacrificial layer and a surface of the trench; forming an opening in the protection film by opening a part of the protection film covering the sacrificial layer; bonding a supporting substrate with a material different from that of the compound semiconductor function layer to the compound semiconductor function layer through a bonding material; and supplying etchant from the opening of the protection film and etching the sacrificial layer, thereby separating the departure substrate and the compound semiconductor function layer.SELECTED DRAWING: Figure 6

Description

The present invention relates to a method for manufacturing a bonded semiconductor wafer and a method for manufacturing a bonded semiconductor element.

Various bonded semiconductor devices have been proposed as new functional substrates obtained by bonding the characteristics of compound semiconductors to other functional substrates.

In the IoT sensor, a solar cell (PV) is used as a power receiving unit, a photodiode (PD) is used as a signal receiving unit, and a laser diode (LD) or a light emitting diode (LED) is used as a signal transmitting unit on a silicon substrate having a drive substrate. Can be implemented to realize a functional chip.

As the light emitting diode, an LED in which a light emitting layer is bonded to a silicon substrate by metal bonding or an LED in which a light emitting layer is bonded to a transparent sapphire substrate by a transparent adhesive has been proposed.

Each structure has a feature that materials having different physical properties such as a linear expansion coefficient and a refractive index are joined to each other to realize the structure.

When joining dissimilar materials, the physical property values are different, which increases restrictions in terms of thermal design and optical design. When manufacturing an optical element, the difference in physical properties between the support substrate and the semiconductor layer appears as a difference in refractive index, and appears as a large total reflection angle at the junction interface, which increases the restrictions on optical design. ..

In order to reduce the total reflection angle, it is possible to change to a material with a small difference in refractive index, but as a result, the material may not be able to be optically designed because it has a large light absorption coefficient and does not transmit light. ..

Therefore, a chip structure has been proposed in which a reflective film is provided between the semiconductor and the support substrate to cause light reflection at the bonding interface regardless of the optical characteristics of the support substrate, thereby increasing the degree of freedom in optical design. ing.

The method of providing a metal reflective film at the bonding interface to realize the bonding has the advantages of increasing the degree of freedom in optical design and increasing the mechanical strength by replacing the substrate with a substrate having strong mechanical strength. However, on the other hand, after bonding, the starting substrate used for epitaxially growing the semiconductor functional layer is completely dissolved and removed.

Etching the starting substrate is easy with InP or GaAs, but the starting substrate is lost by etching in a single junction.

The InP substrate and GaAs substrate used as the starting substrate are more expensive than the transferred support substrate, and occupy about 10 to 20% of the material cost. Therefore, the measure for completely melting and removing the starting substrate has a problem that the manufacturing cost of the wafer increases.

Japanese Unexamined Patent Publication No. 9-63951 Japanese Unexamined Patent Publication No. 2001-102668 Japanese Unexamined Patent Publication No. 2017-228569 Japanese Unexamined Patent Publication No. 2005-72422

The present invention has been made to solve the above problems, and a method for manufacturing a bonded semiconductor wafer capable of reducing the manufacturing cost and a method for manufacturing a bonded semiconductor element capable of reducing the manufacturing cost are provided. The purpose is to provide.

In order to achieve the above object, the present invention is a method for manufacturing a bonded semiconductor wafer.
The process of epitaxially growing the sacrificial layer on the starting substrate,
A step of epitaxially growing a compound semiconductor functional layer on the sacrificial layer,
A step of forming a trench in a part of the compound semiconductor functional layer by a selective etching method so that the sacrificial layer is exposed, and
A step of forming a protective film on the surface of the trench and the exposed portion of the sacrificial layer, and
A step of opening a part of the protective film covering the sacrificial layer to form an opening in the protective film.
A step of joining a support substrate made of a material different from that of the compound semiconductor functional layer to the compound semiconductor functional layer via a bonding material.
Provided is a method for manufacturing a bonded semiconductor wafer, which comprises a step of separating the starting substrate and the compound semiconductor functional layer by supplying an etching liquid from the opening and etching the sacrificial layer. ..

In such a manufacturing method, a trench portion is formed so that the sacrificial layer is exposed on the compound semiconductor functional layer before joining the compound semiconductor functional layer and the support substrate, and the surface of the trench and the exposed portion of the sacrificial layer are formed. By forming a protective film and further opening a part of the protective film that covers the sacrificial layer, an opening that enables selective etching of the sacrificial layer is formed, and an etching solution is supplied from this opening to supply the sacrificial layer. By performing etching, the starting substrate and the compound semiconductor functional layer can be separated without etching the starting substrate, so that the starting substrate can be reused, and the manufacturing cost can be significantly reduced.

For example, a substrate made of InP can be used as the starting substrate, and In _x (Gay Al _{1-y ) 1-x} As (0.4 ≦ x) having a thickness of 0.1 μm or more can be used as the compound semiconductor functional layer. A layer containing ≦ 0.6, 0 ≦ y ≦ 1) and a layer made of InP having a thickness of 0.1 μm or more can be epitaxially grown.

With such a manufacturing method, the more expensive InP substrate can be reused, so that the manufacturing cost can be further reduced.

For example, the support substrate is at least one material selected from the group consisting of AlN, Al ₂ O ₃ , Cu, GaAs, GaN, GaP, InP, Si, SiC and SiO ₂ , and is crystalline or amorphous. Materials with a quality structure can be used.

The above-mentioned one can be preferably used as the support substrate.

For example, as the bonding material, a material containing at least one kind of metal selected from the group consisting of Au, Ag, Al, Ga, In, Ni, Pt and Ti can be used.

The above-mentioned materials can be preferably used as the bonding material.

Further, in the present invention, it is a method for manufacturing a bonded semiconductor device.
A bonded semiconductor wafer is manufactured by the method for manufacturing a bonded semiconductor wafer of the present invention.
Provided is a method for manufacturing a bonded semiconductor element, which comprises dividing the bonded semiconductor wafer along the trench to obtain a bonded semiconductor element.

With such a manufacturing method, a bonded semiconductor wafer is manufactured by the method for manufacturing a bonded semiconductor wafer of the present invention, and the bonded semiconductor wafer is divided along a trench to obtain a bonded semiconductor element. Since it can be used, the manufacturing cost of the junction type semiconductor element can be significantly reduced.

As described above, the method for manufacturing a bonded semiconductor wafer of the present invention can reuse the starting substrate, which is expensive and occupies a large proportion of the manufacturing cost, so that the manufacturing cost can be significantly reduced. A junction type semiconductor wafer can be manufactured.

Further, according to the method for manufacturing a bonded semiconductor device of the present invention, the starting substrate, which is expensive and occupies a large proportion of the manufacturing cost, can be reused, so that the manufacturing cost can be significantly reduced and the bonded semiconductor can be manufactured. The element can be manufactured.

It is a schematic sectional drawing which shows one process of an example of the manufacturing method of the junction type semiconductor wafer of this invention. It is a schematic sectional drawing which shows one process of an example of the manufacturing method of the junction type semiconductor wafer of this invention. It is a schematic sectional drawing which shows one process of an example of the manufacturing method of the junction type semiconductor wafer of this invention. It is a schematic sectional drawing which shows one process of an example of the manufacturing method of the junction type semiconductor wafer of this invention. It is a schematic sectional drawing which shows one process of an example of the manufacturing method of the junction type semiconductor wafer of this invention. It is a schematic sectional drawing which shows one process of an example of the manufacturing method of the junction type semiconductor wafer of this invention. It is a schematic sectional drawing which shows one process of an example of the manufacturing method of the junction type semiconductor wafer of this invention. It is a schematic sectional drawing which shows one process of an example of the manufacturing method of the junction type semiconductor wafer of this invention. It is a schematic sectional drawing which shows one process of an example of the manufacturing method of the junction type semiconductor wafer of this invention. It is a schematic sectional drawing which shows the junction type semiconductor wafer obtained by an example of the manufacturing method of the junction type semiconductor wafer of this invention. It is a schematic sectional drawing which shows the junction type semiconductor element obtained by the manufacturing method of the junction type semiconductor element of this invention. It is a schematic cross-sectional view which shows the light receiving element obtained in the comparative example. It is a graph which shows the relative material cost of an Example based on a comparative example. It is a graph which shows the defective rate of an Example and a comparative example.

As described above, there has been a demand for the development of a method for manufacturing a bonded semiconductor wafer that can reduce the manufacturing cost and a method for manufacturing a bonded semiconductor element that can reduce the manufacturing cost.

As a result of diligent studies on the above problems, the present inventors have formed a trench portion so that the sacrificial layer is exposed in the compound semiconductor functional layer of the epitaxial wafer before the bonding between the compound semiconductor functional layer and the support substrate. A protective film is formed on the surface of the trench and the exposed portion of the sacrificial layer, and a part of the protective film covering the sacrificial layer is opened to form an opening that enables selective etching of the sacrificial layer. We have found that the starting substrate and the compound semiconductor functional layer can be separated without etching the starting substrate by supplying the etching solution from the etching solution to etch the sacrificial layer, and the starting substrate can be reused. Was completed.

That is, the present invention is a method for manufacturing a junction type semiconductor wafer.
The process of epitaxially growing the sacrificial layer on the starting substrate,
A step of epitaxially growing a compound semiconductor functional layer on the sacrificial layer,
A step of forming a trench in a part of the compound semiconductor functional layer by a selective etching method so that the sacrificial layer is exposed, and
A step of forming a protective film on the surface of the trench and the exposed portion of the sacrificial layer, and
A step of opening a part of the protective film covering the sacrificial layer to form an opening in the protective film.
A step of joining a support substrate made of a material different from that of the compound semiconductor functional layer to the compound semiconductor functional layer via a bonding material.
It is a method for manufacturing a bonded semiconductor wafer, which comprises a step of separating the starting substrate and the compound semiconductor functional layer by supplying an etching liquid from the opening and etching the sacrificial layer.

Further, the present invention is a method for manufacturing a bonded semiconductor device.
A bonded semiconductor wafer is manufactured by the method for manufacturing a bonded semiconductor wafer of the present invention.
A method for manufacturing a junction-type semiconductor element, which comprises dividing the junction-type semiconductor wafer along the trench to obtain a junction-type semiconductor element.

In Patent Document 1, an etching removal layer is formed on a compound semiconductor substrate, a compound semiconductor adhesive layer is formed on the compound semiconductor adhesive layer, the compound semiconductor adhesive layer is adhered on a silicon substrate, and then an etching removal layer is provided. A method for manufacturing a semiconductor substrate, which is removed by etching and then a device forming layer is formed on a compound semiconductor adhesive layer, is disclosed. However, Patent Document 1 does not disclose forming a trench in the device cambium. Further, in Patent Document 1, a device forming layer is formed after the etching removal layer is removed. In Patent Document 1, a compound semiconductor (compound semiconductor adhesive layer) is directly bonded to a silicon substrate.

Further, in Patent Document 2, after joining the layers obtained by epitaxial growth to each other, the Aly Ga _{1-y As} layer provided under one layer is etched to separate the epitaxial layer and the starting substrate. The method is disclosed. However, in Patent Document 2, the epitaxial layer and the silicon substrate which is the support substrate are directly bonded.

Further, Patent Document 3 discloses an avalanche photodiode in which a substrate having a heat sink function is bonded to an avalanche photodiode (APD) mesa via an adhesive layer. However, in Cited Document 3, the substrate on which the APD mesa is formed, that is, the starting substrate, is left behind.

Further, Patent Document 4 describes a method for separating an epitaxial layer of a semiconductor element for separating a base material portion and an epitaxial layer from a semiconductor element having an etch stop layer between the base material portion and the epitaxial layer. However, in the method disclosed in Patent Document 4, not the epitaxial layer but a part of the base material portion is selectively etched from the back surface side until it reaches the etch stop layer, and at least one etching window is opened. ..

Hereinafter, the present invention will be described in detail, but the present invention is not limited thereto.

<Manufacturing method of junction type semiconductor wafer>
The method for manufacturing a bonded semiconductor wafer of the present invention is as follows.
The process of epitaxially growing the sacrificial layer on the starting substrate,
The process of epitaxially growing a compound semiconductor functional layer on the sacrificial layer,
A process of forming a trench so that the sacrificial layer is exposed in a part of the compound semiconductor functional layer by the selective etching method.
The process of forming a protective film on the surface of the trench and the exposed part of the sacrificial layer,
The process of opening a part of the protective film that covers the sacrificial layer to form an opening in the protective film,
A process of joining a support substrate made of a material different from that of the compound semiconductor functional layer to the compound semiconductor functional layer via a bonding material,
It is characterized by having a step of separating the starting substrate and the compound semiconductor functional layer by supplying an etching solution from the opening of the protective film and etching the sacrificial layer.

Hereinafter, each step will be described in order.

[Step of epitaxially growing the sacrificial layer on the starting substrate]
First, the sacrificial layer is epitaxially grown on the starting substrate.
The starting substrate is not particularly limited as long as it can epitaxially grow the sacrificial layer and the compound semiconductor functional layer on the sacrificial layer.

In the method for manufacturing a bonded semiconductor wafer of the present invention, the starting substrate can be reused, so that even if a more expensive and high-quality InP substrate is used as a support substrate, the manufacturing cost can be further reduced.

As the sacrificial layer, a layer that can be etched with an etching solution that does not etch the starting substrate can be used. As the sacrificial layer, for example, a layer of i-In _x Ga _1-x As _z P _1-z (0.4 ≦ x ≦ 0.6, 0.8 ≦ z ≦ 1) having a thickness of 0.3 μm is used. be able to.

[Step of epitaxially growing a compound semiconductor functional layer on a sacrificial layer]
Next, the compound semiconductor functional layer is epitaxially grown on the sacrificial layer.
The compound semiconductor functional layer to be epitaxially grown is not particularly limited as long as it can achieve the desired function in the semiconductor device. For example, as a compound semiconductor functional layer, an In _x (Gay Al _{1-y ) 1-x} As (0.4 ≦ x ≦ 0.6, 0 ≦ y ≦ 1) layer having a thickness of 0.1 μm or more can be used. Those containing a layer made of InP having a thickness of 0.1 μm or more can be epitaxially grown.

[Step of forming a trench]
Next, a trench is formed in a part of the compound semiconductor functional layer by the selective etching method so that the sacrificial layer is exposed. The trench formed here can be formed according to the size of the planned device area. When the trench is formed in this way, the junction-type semiconductor element can be easily manufactured by dividing the manufactured junction-type semiconductor wafer along the trench in the subsequent process.

Both wet etching and dry etching methods can be used to form the trench.

In the case of wet etching, a trench can be formed by forming a resist pattern by photolithography and then selectively etching each layer constituting the compound semiconductor functional layer along the resist pattern. Specific examples will be described in the subsequent embodiments.

In the case of dry etching, etching is possible by gas etching in an atmosphere in which a chlorine-based gas such as Cl ₂ and a plasma stabilizing gas such as Ar are mixed. When dry etching is selected, there is an advantage that the shape of the trench side wall is not uneven, but it is difficult to automatically stop etching at the sacrificial layer due to the low etching selectivity, so the thickness of the sacrificial layer is wet. It needs to be thicker than in the case of etching, and it is preferably 0.3 μm or more.

[Step of forming a protective film]
Next, a protective film is formed on the surface of the trench and the exposed portion of the sacrificial layer. The protective film can be formed by any method such as sol-gel method, dip method, RF-EB, sputtering, CVD, etc. as long as the protective film can be formed. For example, a material system in which TEOS and O ₂ are combined. The SiO ₂ film can be formed by using the p-CVD method. Since the TEOS-based SiO ₂ has good coverage coverage, it covers well even if there are irregularities on the side wall of the trench, and is therefore suitable as a protective film forming method. The thickness of the SiO ₂ protective film can be, for example, 0.3 μm.

[Step of forming an opening in the protective film]
Next, a part of the protective film covering the sacrificial layer is opened to form an opening in the protective film. For the opening of the protective film, for example, a resist pattern as a resist mask is formed on the surface of the protective layer by a photolithography method, and a part of the protective film covering the sacrificial layer is opened by using this resist mask to open the opening. (Opening pattern) can be formed.

For example, a hydrofluoric acid-based etchant can be used for aperture pattern etching. However, aperture etching is not limited to wet etching. In the case of dry etching, similar results can be obtained by using a fluorine-based gas (NF ₃ , SF ₆ , etc.).

[Joining process]
Next, a support substrate made of a material different from that of the compound semiconductor functional layer is bonded to the compound semiconductor functional layer via a bonding material.

The support substrate to be joined is not particularly limited. The support substrate is at least one material selected from the group consisting of AlN, Al ₂ O ₃ , Cu, GaAs, GaN, GaP, InP, Si, SiC and SiO ₂ , and is crystalline or amorphous. A material having a structure can be used. In the present invention, the above-mentioned one can be preferably used as the support substrate.

It is preferable to use a support substrate having higher mechanical strength than the starting substrate.

The joining material used is not particularly limited. For example, as the bonding material, a material containing at least one kind of metal selected from the group consisting of Au, Ag, Al, Ga, In, Ni, Pt and Ti can be used. That is, the compound semiconductor functional layer and the support substrate can be bonded by the bonding material layer containing one or more kinds of metals.

The bonding material layer may be composed of a plurality of connecting metal layers. For example, connecting metal layers may be provided on the compound semiconductor functional layer side and the support substrate side, respectively, and these connecting metal layers may be thermocompression bonded to each other.

The joining temperature is preferably 350 ° C. or higher. Further, it is preferable to join the joining pressure portion at 50 N / cm ² or more. The above conditions are suitable conditions for obtaining sufficient bonding strength, and are not limited to these conditions.

By the above-mentioned bonding, it is possible to obtain a bonded wafer in which the support substrate and the compound semiconductor functional layer are bonded via a bonding material.

[Step of separating the starting substrate and the compound semiconductor functional layer by etching the sacrificial layer]
Next, the starting substrate and the compound semiconductor functional layer are separated by supplying an etching solution from the opening of the protective film and etching the sacrificial layer.

The etching solution used is not particularly limited as long as it can selectively etch the sacrificial layer. Further, the specific method of supplying the etching solution from the opening of the protective film is not particularly limited.

By this selective etching, the starting substrate can be separated from the bonded wafer. The separated starting substrate can be reused for making another epitaxial wafer.

[Other processes]
The method for manufacturing a bonded semiconductor wafer of the present invention may include steps other than the above steps. For a specific example, refer to the embodiment shown in the latter part.

<Manufacturing method of junction type semiconductor element>
The method for manufacturing a bonded semiconductor device of the present invention is as follows.
A bonded semiconductor wafer is manufactured by the method for manufacturing a bonded semiconductor wafer of the present invention.
It is characterized in that a bonded semiconductor wafer is divided along the trench to obtain a bonded semiconductor element.

The specific method of division is not particularly limited, but the bonded semiconductor wafer can be divided by, for example, dicing, scribe / braking method, or the like.

Next, one embodiment of the method for manufacturing a bonded semiconductor wafer and the method for manufacturing a bonded semiconductor element of the present invention will be described in detail with reference to FIGS. 1 to 11. However, the present invention is not limited to the following embodiments.

(Embodiment)
In this embodiment, as an example of the present invention, a method for manufacturing the bonded semiconductor wafer 1000 shown in FIG. 10 and a method for manufacturing the bonded semiconductor element 2000 shown in FIG. 11 will be described.

First, the epitaxial wafer 100 shown in FIG. 1 is prepared. Here, first, an i-InP buffer layer is formed on a semi-insulating InP substrate with a thickness of, for example, 0.5 μm, and the starting substrate 1 is prepared. Next, an i-In _x Ga _1-x As (0.4 ≤ x ≤ 0.6) sacrificial layer (hereinafter, i-InGaAs sacrificial layer or sacrificial layer) 2 having a thickness of, for example, 0. It is formed by epitaxial growth at 3 μm. Next, an i-InP etch stop layer 3 is formed on the sacrificial layer 2 with a thickness of, for example, 0.3 μm, and then an i-In _x Ga _1-x As (0.4 ≦ x ≦ 0.6) contact layer ( Hereinafter, the i-InGaAs contact layer) 11 is formed by epitaxial growth at a thickness of, for example, 0.1 μm, and then the i-InP cap layer 12 is formed by epitaxial growth at a thickness of, for example, 0.1 μm, and then i-In _x Ga _1- . The _xAs (0.4≤x≤0.6) absorption layer (hereinafter, i-InGaAs absorption layer) 13 is formed by epitaxial growth having a thickness of, for example, 3.0 μm, and then the n-InP layer 14 is formed, for example, with a thickness of 1. It is formed by epitaxial growth at 0 μm. As a result, on the sacrificial layer 2, the etch stop layer 3 and the compound semiconductor functional layer 10 including the i-InGaAs contact layer 11, the i-InP cap layer 12, the i-InGaAs absorption layer 13 and the n-InP layer 14 are formed. The epitaxial wafer 100 is obtained.

Next, as shown in FIG. 2, a trench 4 is formed in the compound semiconductor functional layer 10 along the planned device area size. As the means for forming the trench 4, as described above, either wet etching or dry etching can be used.

In the case of wet etching, for example, the trench 4 can be formed by the following procedure. First, a resist pattern is formed on the surface of the compound semiconductor functional layer 10, that is, the surface of the n-InP layer 14 by a photolithography method. Next, the n-InP layer 14 is selectively etched with a chlorine-based etchant using the resist pattern as a mask. After the selective etching of the n-InP layer 14, the i-InGaAs absorption layer 13 is selectively etched by switching to the sulfuric acid superwater type etchant. Next, the i-InP cap layer 12 is selectively etched by switching to the chlorine-based etchant. Then, the i-InGaAs contact layer 11 is selectively etched by switching to the sulfuric acid superwater etchant. Next, the i-InP etching stop layer 3 is selectively etched by switching to the chlorine-based etchant. By going through the above steps, it is possible to form a trench 4 in which a part of the i-InGaAs sacrificial layer 2 is exposed at the bottom.

Further, in the case of dry etching, as described above, etching is possible by gas etching in an atmosphere in which a chlorine-based gas such as Cl ₂ and a plasma stabilizing gas such as Ar are mixed. When dry etching is selected, there is an advantage that unevenness does not occur in the side wall shape of the trench 4, but since the etching selectivity is low, it is difficult for the sacrificial layer 2 to automatically stop etching. Therefore, the sacrificial layer 2 has an advantage. The thickness needs to be thicker than that in the case of wet etching, and is preferably 0.3 μm or more.

Next, as shown in FIG. 3, a protective film 5 is formed on the surface of the trench 4 and the exposed portion of the sacrificial layer 2. As described above, the protective film 5 can be formed by any method such as sol-gel method, dip method, RF-EB, sputtering, CVD, etc. as long as the protective film 5 can be formed. For example, a SiO ₂ film can be formed by using the p-CVD method in a material system in which TEOS and O ₂ are combined. Since the TEOS-based SiO ₂ has good coverage coverage, it covers well even if the side wall portion of the trench 4 has irregularities, and is therefore suitable as a method for forming the protective film 5. The thickness of the SiO ₂ protective film can be, for example, 0.3 μm.

Next, a resist pattern is formed on the surface of a part of the protective film 5 covering the sacrificial layer 2 by a photolithography method, and the formed resist pattern is used as a resist mask to partially cover the sacrificial layer 2. To form the opening (opening pattern) 5A shown in FIG.

As mentioned above, a hydrofluoric acid-based etchant can be used for aperture pattern etching. However, aperture etching is not limited to wet etching. In the case of dry etching, similar results can be obtained by using a fluorine-based gas (NF ₃ , SF ₆ , etc.).

On the other hand, a Si substrate is prepared as the support substrate 30, and the bonded metal layer 21 is formed on the surface of the Si substrate 30 as shown in FIG.

The support substrate 30 is not limited to the Si substrate, and the same effect can be obtained by selecting a material having higher mechanical strength than the InP substrate, such as _{Al2O3 ,} AlN, and GaAs.

For the bonded metal layer 21, Al or Ti can be selected in addition to Pt for the layer in contact with the support substrate 30. In addition to Au, Al, Ag, Ga, In and the like can be selected as the bonding interface layer.
The thickness of the connecting metal layer 21 can be, for example, 0.1 μm for the Pt layer and 1 μm for the Au layer.

Next, as shown in FIG. 5, the bonded metal layer 22 is formed on the n-InP layer 14 included in the non-trench portion 15 of the epitaxial wafer 100.

In the bonded metal layer 22, Pt can be arranged on the layer in contact with the compound semiconductor functional layer 10, and Au can be arranged on the bonded interface. In addition to Pt, Al, Ti, Ni, Au, or the like can be selected as the layer in contact with the compound semiconductor functional layer 10. The bonded metal layer 22 can be selected from any combination of materials as long as it has a structure capable of bonding in the next step and is a material system resistant to etching of the sacrificial layer in the subsequent step.
The thickness of the connecting metal layer 22 can be, for example, 0.1 μm for the Pt layer and 1 μm for the Au layer.

Next, as shown in FIG. 6, the support substrate 30 and the epitaxial wafer 100 are bonded by thermocompression bonding the bonded metal layers 21 and 22 to each other to form a bonded wafer 200. The bonded metal layers 21 and 22 are pressure-bonded to each other to form a bonded material layer 20.

As described above, the joining temperature is preferably 350 ° C. or higher. Further, it is preferable to join the joining pressure portion at 50 N / cm ² or more. The above conditions are suitable conditions for obtaining sufficient bonding strength, and are not limited to these conditions.

Next, the bonding wafer 200 is immersed in an etching solution, for example, a sulfuric acid superwater-based etchant. As a result, the etching solution enters the trench 4 from a direction perpendicular to the paper surface of FIG. 6, for example, passes through the trench 4, and is supplied to the sacrificial layer 2 from the opening 5A of the protective layer 5. The i-InGaAs sacrificial layer 2 is sandwiched between the InP layer (i-InP etch stop layer 3 and the i-InP buffer layer of the starting substrate 1), and the sulfated superwater has etching selectivity with respect to InP (InP). Because the protective layer 5 covers the surface of the trench 4, only the i-InGaAs sacrificial layer 2 is etched, and as shown in FIG. 7, the InP starting substrate 1 and the compound semiconductor functional layer are etched. Separated from 10.

After separation, as shown in FIG. 7, the compound semiconductor functional layer 10 is left on the support substrate 30 in an isolated island-like pattern. On the other hand, the separated starting substrate 1 can be reused for manufacturing another bonded wafer.

Next, the i-InP etch stop layer 3 is selectively etched with a chlorine-based etchant. Since the i-InP etch stop layer 3 is removed, a part of the protective layer 5 protrudes to the surface of the compound semiconductor functional layer 10, and it is easy to peel off in the next step or later, which causes a decrease in yield. The protruding portion of the protective layer 5 is partially peeled off by such means. As a result, as shown in FIG. 8, one main surface of the i-InGaAs contact layer 11 is exposed, and the end portion of the protective layer 5 is aligned with the exposed main surface of the i-InGaAs contact layer 11. After peeling, Zn is diffused on the surface of the i-InGaAs contact layer 11 to form a p-type layer on the surface of the i-InGaAs contact layer 11.

Next, the protective film 5 is formed again on the surface of the i-InGaAs contact layer 11. The same process as the protective film 5 formed on the trench 4 and the sacrificial layer 2 can be applied to the formation of the protective film 5. Then, as shown in FIG. 9, an opening pattern 5B is formed on a part of the formed protective film 5. Further, Zn is diffused in the opening pattern 5B.

Next, as shown in FIG. 10, an electrode 6 is formed in the opening pattern 5B so as to be in contact with the i-InGaAs contact layer 11A, and an electrode 7 is also formed on the back surface side of the support substrate 30. After forming the electrodes 6 and 7, as also shown in FIG. 10, a part of the i-InGaAs contact layer 11 is removed to form the aperture portion 11A. After forming the aperture portion 11A, a protective layer such as SiN _x (0 <x ≦ 2) is formed, and the portion of the protective layer corresponding to the electrode portion and the dicing portion is removed.

By going through the above steps, the junction type semiconductor wafer 1000 shown in FIG. 10 can be obtained.

Next, the junction-type semiconductor wafer 1000 is divided along the trench 4 by, for example, dicing or a scribe / braking method to form the junction-type semiconductor element 2000, which is an individual element shown in FIG.

The bonded semiconductor element 2000 shown in FIG. 11 is a light receiving element, but the bonded semiconductor element that can be manufactured by the manufacturing method of the bonded semiconductor element 2000 of the present invention is not limited to the light receiving element.

The i-InGaAs contact layer 11 and the i-InGaAs absorption layer 13 used in the above embodiment are replaced with Al instead of i-In _x Ga _1-x As (0.4 ≦ x ≦ 0.6). It may be i-In _x (Gay Al _{1-y ) 1-x} As (0.4 ≦ x ≦ 0.6, 0 <y ≦ 1) including. Further, the i-InGaAs sacrificial layer 2 used in the above embodiment contains P instead of i-In _x Ga _1-x As (0.4 ≦ x ≦ 0.6), i-In _x Ga ₁ It may be a layer of _−x As _z P _1-z (0.4 ≦ x ≦ 0.6, 0.8 ≦ z <1).

Hereinafter, the present invention will be specifically described with reference to Examples and Comparative Examples, but the present invention is not limited thereto.

(Example)
In the embodiment, the bonded semiconductor wafer 1000 having the same structure as shown in FIG. 10 and the bonded semiconductor element 2000 having the same structure as shown in FIG. 11 were manufactured by the following procedure.

First, the epitaxial wafer 100 shown in FIG. 1 was prepared by the following procedure. First, an i-InP buffer layer having a thickness of 0.5 μm was formed on the semi-insulating InP substrate, and the starting substrate 1 was prepared. Next, an i-InGaAs sacrificial layer 2 having a thickness of 0.3 μm was formed on the starting substrate 1 by epitaxial growth. Next, on the sacrificial layer 2, an i-InP etch stop layer 3 having a thickness of 0.3 μm, an i-InGaAs contact layer 11 having a thickness of 0.1 μm, an i-InP cap layer 12 having a thickness of 0.1 μm, and a thickness of 0.1 μm are placed on the sacrificial layer 2. A 3.0 μm i-InGaAs absorption layer 13 and a 1.0 μm thick n-InP layer 14 were sequentially formed by epitaxial growth. As a result, on the sacrificial layer 2, the etch stop layer 3 and the compound semiconductor functional layer 10 including the i-InGaAs contact layer 11, the i-InP cap layer 12, the i-InGaAs absorption layer 13 and the n-InP layer 14 are formed. Manufactured an epitaxial wafer 100 which was epitaxially grown.

Next, as shown in FIG. 2, a trench was formed in the compound semiconductor functional layer 10 so that a part of the sacrificial layer 2 was exposed along the planned device area size. Trench formation was performed by wet etching according to the following procedure. First, a resist pattern was formed on the surface of the compound semiconductor functional layer 10 by a photolithography method. Next, using the resist pattern as a mask, the n-InP layer 14 was selectively etched with a chlorine-based etchant. After the selective etching of the n-InP layer 14, the i-InGaAs absorption layer 13 was selectively etched by switching to the sulfuric acid superwater type etchant. Then, the i-InP cap layer 12 was selectively etched by switching to the chlorine-based etchant. Then, the i-InGaAs contact layer 11 was selectively etched by switching to the sulfuric acid superwater etchant. Then, the i-InP etching stop layer 3 was selectively etched by switching to the chlorine-based etchant. Through the above steps, a trench 4 in which a part of the i-InGaAs sacrificial layer 2 was exposed was formed at the bottom.

Next, a protective film was formed on the surface of the trench 4 and the exposed portion of the sacrificial layer 2. Specifically, a SiO ₂ film having a thickness of 0.3 μm was formed as the protective film 5 by using the p-CVD method in a material system in which TEOS and O ₂ were combined.

Next, a resist pattern is formed on the surface of a part of the protective film 5 that covers the sacrificial layer 2 by a photolithography method, and the formed resist pattern is used as a resist mask, and a protective film that covers the sacrificial layer 2 with hydrofluoric acid. A part of No. 5 was opened to form the opening (opening pattern) 5A shown in FIG.

On the other hand, a Si substrate as a support substrate 30 having a bonded metal layer 21 composed of Pt (0.1 μm) and Au (1 μm) formed on the surface thereof as shown in FIG. 4 was prepared.

Next, as shown in FIG. 5, a bonded metal layer 22 composed of Pt (0.1 μm) and Au (1 μm) was formed on the n—InP layer 14 included in the non-trench portion 15 of the epitaxial wafer 100.

Next, the support substrate 30 and the epitaxial wafer 100 were bonded by thermocompression bonding the bonded metal layers 21 and 22 to each other at a temperature of 400 ° C. and a pressure of 100 N / cm ² , to obtain a bonded wafer shown in FIG. The bonded metal layers 21 and 22 were crimped to form a bonded layer 20.

Next, the bonded wafer 200 was immersed in a sulfuric acid-based etchant as an etching solution. As a result, the etching solution was supplied to the sacrificial layer 2 through the opening 5A of the protective layer 5 through the trench 4. As a result, only the sacrificial layer 2 was selectively etched by the etching solution, and the InP starting substrate 1 and the compound semiconductor functional layer 10 were separated as shown in FIG. 7.

The separated InP starting substrate 1 was reused in the production of other epitaxial wafers.

Next, the InP etch stop layer 3 was selectively etched with a chlorine-based etchant to expose one main surface of the i-InGaAs contact layer 11 as shown in FIG. Next, Zn was diffused on the exposed surface of the i-InGaAs contact layer 11 to form a p-type layer on this surface.

Next, the protective film 5 was formed again on the surface of the i-InGaAs contact layer 11, and the opening pattern 5B was formed on a part of the formed protective film 5 as shown in FIG. Further, Zn was diffused in the opening pattern 5B.

Next, as shown in FIG. 10, an electrode 6 was formed in the opening pattern 5B so as to be in contact with the i-InGaAs contact layer 11A, and an electrode 7 was also formed on the back surface side of the support substrate 30. After forming the electrodes 6 and 7, as also shown in FIG. 10, a part of the i-InGaAs contact layer 11 was removed to form the aperture portion 11A. After forming the aperture portion 11A, a protective layer such as SiN _x (0 <x ≦ 2) was formed, and the portion of the protective layer corresponding to the electrode portion and the dicing portion was removed.

As a result, the junction type semiconductor wafer 1000 shown in FIG. 10 was obtained.

Next, the bonded semiconductor wafer 1000 was divided along the trench 4 by dicing to form a bonded semiconductor element (light receiving element) 2000, which is an individual element shown in FIG.

(Comparative example)
In the comparative example, the light receiving element 2000'shown in FIG. 12 was manufactured by the following procedure.

First, a compound semiconductor functional layer (epitaxial functional layer) 10'was formed on a starting substrate 30'including an N-type InP substrate. The compound semiconductor functional layer 10'was laminated in the following order.

An i-InP buffer layer having a thickness of 0.5 μm was formed on an N-type InP substrate to form a starting substrate 30'. On the starting substrate 30', a 1.0 μm thick n-InP clad layer 14', a 3.0 μm thick i-InGaAs absorption layer 13', and a 0.1 μm thick i-InP cap layer 12', And i-InGaAs contact layer 11'with a thickness of 0.1 μm was formed by epitaxial growth in order. As a result, the compound semiconductor functional layer 10 including the n-InP clad layer 14', the i-InGaAs absorption layer 13', the i-InP cap layer 12', and the i-InGaAs contact layer 11'on the starting substrate 30'. 'Epitaxially grown epitaxial wafer 100' was manufactured.

Next, a protective film 5'was formed on the surface of the i-InGaAs contact layer 11'. Next, a resist pattern was formed on the surface of the protective film 5'by a photolithography method, and this resist pattern was used as a resist mask to form an opening pattern on the protective film 5'.

Next, Zn was diffused on the surface of the i-InGaAs contact layer 11'through the opening pattern of the protective film 5'to form a p-type layer on the surface.

Next, an electrode 6'composed of a Ti layer of 0.1 μm and an Au layer of 1.0 μm was formed in the opening pattern portion.

After forming the electrode 6', a protective layer of SiN _x (0 <x ≦ 2) was formed, and the portion corresponding to the electrode portion and the dicing portion was removed.

Then, the back surface contact electrode 7'was formed on the surface of the starting substrate 30'on the side opposite to the compound semiconductor functional layer 10'of the N-type InP substrate with the same structure and material as described above.

After forming the back surface contact electrode 7', it was separated into individual elements by dicing to form the light receiving element 2000' shown in FIG.

(evaluation)
FIG. 13 shows the effect of reducing the material cost in the example using the comparative example as a reference (100%). From FIG. 13, it can be seen that in the examples, the material cost was reduced to about half as compared with the comparative example in which the starting substrate was not separated. This is due to the fact that by reusing the starting substrate, the material cost of the starting substrate can be substantially reduced to a negligible level. In this method, a trench is formed in the compound semiconductor functional layer before being bonded to the support substrate, the surface of the trench is covered with a protective film, the support substrate and the compound semiconductor functional layer are bonded, and then the protective film leading to the sacrificial layer is formed. This was achieved for the first time by the manufacturing method of the present invention in which the etching solution is supplied through the opening of the above and the sacrificial layer is selectively etched to separate the starting substrate and the compound semiconductor functional layer. In particular, it is extremely difficult to achieve this effect with an InP / InGaAs material system other than the production method of the present invention.

FIG. 14 shows data on the chip cracking defect rate in Examples and Comparative Examples. As is clear from FIG. 14, the crack defect was improved in the examples as compared with the comparative example in which the starting substrate was used as it was as the support substrate. This is because the strength of the chip against heat and stress in the packaging processing process was increased by replacing the brittle InP substrate with the Si substrate, so that the mechanical strength was improved.

The present invention is not limited to the above embodiment. The above-described embodiment is an example, and any of the above-described embodiments having substantially the same configuration as the technical idea described in the claims of the present invention and having the same effect and effect is the present invention. Is included in the technical scope of.

1 ... starting substrate, 2 ... sacrificial layer, 3 ... etch stop layer, 4 ... trench, 5 and 5'... protective film, 5A ... opening, 5B ... opening pattern, 6, 6'and 7 ... electrodes, 7'... Backside contact electrodes, 10 and 10'... compound semiconductor functional layers, 11 and 11' ... contact layers, 11A ... apertures, 12 and 12'... cap layers, 13 and 13'... absorption layers, 14 ... n-InP layers, 14'... clad layer, 15 ... non-trench part, 20 ... bonding material layer, 21 ... bonded metal layer, 22 ... bonded metal layer, 30 ... support substrate, 30'... starting substrate, 100 and 100'... epitaxial wafer, 200 ... bonded wafer, 1000 ... bonded semiconductor wafer, 2000 ... bonded semiconductor element (light receiving element), 2000'... light receiving element.

Claims (5)

It is a manufacturing method of a junction type semiconductor wafer.
The process of epitaxially growing the sacrificial layer on the starting substrate,
A step of epitaxially growing a compound semiconductor functional layer on the sacrificial layer,
A step of forming a trench in a part of the compound semiconductor functional layer by a selective etching method so that the sacrificial layer is exposed, and
A step of forming a protective film on the surface of the trench and the exposed portion of the sacrificial layer, and
A step of opening a part of the protective film covering the sacrificial layer to form an opening in the protective film.
A step of joining a support substrate made of a material different from that of the compound semiconductor functional layer to the compound semiconductor functional layer via a bonding material.
A method for manufacturing a bonded semiconductor wafer, which comprises a step of separating the starting substrate and the compound semiconductor functional layer by supplying an etching liquid from the opening and etching the sacrificial layer. A substrate made of InP is used as the starting substrate, and In _x (Gay Al _{1-y ) 1-x} As (0.4 ≦ x ≦ 0.6,) having a thickness of 0.1 μm or more is used as the compound semiconductor functional layer. The method for manufacturing a bonded semiconductor wafer according to claim 1, wherein a layer including a layer of 0 ≦ y ≦ 1) and a layer made of InP having a thickness of 0.1 μm or more is epitaxially grown. The support substrate is at least one material selected from the group consisting of AlN, Al ₂ O ₃ , Cu, GaAs, GaN, GaP, InP, Si, SiC and SiO ₂ , and is crystalline or amorphous. The method for manufacturing a bonded semiconductor wafer according to claim 1 or 2, wherein a material having a structure is used. Claims 1 to 3 are characterized in that, as the bonding material, a material containing at least one kind of metal selected from the group consisting of Au, Ag, Al, Ga, In, Ni, Pt and Ti is used. The method for manufacturing a junction type semiconductor wafer according to any one of the above. It is a manufacturing method of a bonded semiconductor device.
A bonded semiconductor wafer is manufactured by the method for manufacturing a bonded semiconductor wafer according to any one of claims 1 to 4.
A method for manufacturing a bonded semiconductor device, which comprises dividing the bonded semiconductor wafer along the trench to obtain a bonded semiconductor element.

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