JP5182189B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  A nitride semiconductor semiconductor device typified by GaN (gallium nitride) is useful as a high-voltage / high-speed electronic device and a light-emitting device because of excellent material characteristics. Examples of high breakdown voltage / high speed electronic devices include field effect transistors, particularly HEMTs (High Electron Mobility Transistors), and there are two types of structures, horizontal and vertical. Moreover, as a light emitting device, a GaN semiconductor laser can be cited, and similarly, two types of structures of a horizontal type and a vertical type have been devised.

On the other hand, as a growth substrate for forming a GaN-based nitride semiconductor layer containing GaN, a sapphire (Al ₂ O ₃ ) substrate, a SiC (silicon carbide) substrate, or the like is usually used from the viewpoint of crystal growth.

  In the case of a horizontal semiconductor device, an SiC substrate having high thermal conductivity is mainly used due to its characteristics. However, since the SiC substrate is expensive, a semiconductor device using the SiC substrate becomes expensive. . Therefore, after manufacturing a semiconductor device using a SiC substrate, the region portion of the semiconductor device formed from the SiC substrate is peeled off and replaced with another high thermal conductivity material substrate, thereby reusing the SiC substrate. There is a way to reduce costs. Further, when a sapphire substrate is used as a growth substrate, the sapphire substrate has a problem in performance of a semiconductor device to be manufactured because the thermal conductivity is low. For this reason, after manufacturing a semiconductor device using a sapphire substrate, the semiconductor device region formed from the sapphire substrate is peeled off and replaced with another high thermal conductivity material semiconductor device. A method of manufacturing is expected.

  On the other hand, in the case of a vertical semiconductor device, it is necessary to form an electrode on the back surface, and a sapphire substrate with low conductivity cannot be used. Therefore, a low resistance such as a conductive SiC substrate or an n-type GaN free-standing substrate is used. It is necessary to use a suitable growth substrate. Even in this case, after producing a semiconductor device using a SiC substrate or the like, by peeling off the region of the semiconductor device formed from the SiC substrate and replacing it with a substrate of another low-resistance material with high thermal conductivity, A method for reducing the cost is expected.

JP 2005-64188 A JP 2008-135419 A

  However, when the nitride semiconductor layer to be the formed semiconductor device is peeled from the growth substrate, the nitride semiconductor layer to be peeled is wide in the surface direction of the growth substrate and is extremely thin. Therefore, it is difficult to peel off the growth substrate in a short time without impairing the function as a semiconductor device.

  Therefore, there is a demand for a manufacturing method that can be peeled off in a short time without impairing the function of the nitride semiconductor layer to be a semiconductor device formed from the growth substrate and can be replaced with another substrate.

  According to one aspect of the present embodiment, a sacrificial layer forming step of forming a sacrificial layer of the first nitride semiconductor on the substrate, forming a second nitride semiconductor layer on the sacrificial layer, and A laminated semiconductor forming step of forming a laminated nitride semiconductor layer in which a nitride semiconductor layer is laminated on the second nitride semiconductor layer, and the second nitride semiconductor layer and the laminated layer until the surface of the sacrificial layer is exposed. Forming a trench by etching the nitride semiconductor layer, and forming a connection electrode on the surface of the trench and the laminated nitride semiconductor layer; and immersing the substrate on which the connection electrode is formed in an electrolytic solution And a sacrificial layer removing step of applying a potential to the connection electrode with respect to the electrolytic solution, removing the sacrificial layer, and peeling the substrate.

  According to the disclosed method for manufacturing a semiconductor device, a nitride semiconductor layer to be an electronic device and a light-emitting device can be easily peeled from a growth substrate in a short time, and can be replaced with another substrate. Can be manufactured at low cost.

Process drawing (1) of the manufacturing method of the semiconductor device in 1st Embodiment Process drawing (2) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (3) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (4) of the manufacturing method of the semiconductor device in the first embodiment Configuration diagram of vertical GaN-HEMT manufactured in the first embodiment Process explanatory diagram of photoelectrochemical etching in the first embodiment Explanatory diagram of photoelectrochemical etching Process drawing (1) of the manufacturing method of the semiconductor device in 2nd Embodiment Process drawing (2) of the manufacturing method of the semiconductor device in 2nd Embodiment Process drawing of the manufacturing method of the semiconductor device in 2nd Embodiment (3) Process drawing (4) of the manufacturing method of the semiconductor device in 2nd Embodiment Configuration diagram of lateral GaN-HEMT manufactured in the second embodiment Process drawing (1) of the manufacturing method of the semiconductor device in 3rd Embodiment Process drawing (2) of the manufacturing method of the semiconductor device in 3rd Embodiment Process drawing of the manufacturing method of the semiconductor device in 3rd Embodiment (3) Process drawing (4) of the manufacturing method of the semiconductor device in 3rd Embodiment Process drawing (5) of the manufacturing method of the semiconductor device in 3rd Embodiment Process explanatory diagram of photoelectrochemical etching in the third embodiment Sectional drawing cut | disconnected by the broken line 18A-18B in FIG. Process drawing (1) of the manufacturing method of the semiconductor device in 4th Embodiment Process drawing (2) of the manufacturing method of the semiconductor device in 4th Embodiment Process explanatory diagram of photoelectrochemical etching in the fourth embodiment Sectional drawing cut | disconnected by the broken line 22A-22B in FIG.

  The form for implementing is demonstrated below.

[First Embodiment]
The manufacturing method of the semiconductor device in the first embodiment is a manufacturing method of a vertical GaN-HEMT that is a vertical semiconductor device.

  A method for manufacturing a vertical GaN-HEMT will be described with reference to FIGS.

  First, as shown in FIG. 1A, after both surfaces of a sapphire substrate 11 serving as a growth substrate are polished, a nitride semiconductor layer is laminated. Specifically, by MOCVD (Metal Organic Chemical Vapor Deposition) method, the AlN layer 12 is 2 nm, the n-GaN layer 13 is 1 μm, the p-GaN layer 14 is 1 μm, and the n-GaN layer 15 is 1 μm on the sapphire substrate 11. Then, the AlN layer 16 is formed to a thickness of 100 nm.

Next, an opening 17 is formed in the AlN layer 16 as shown in FIG. Specifically, after applying a photoresist on the AlN layer 16 and performing pre-baking or the like, exposure and development are performed by an exposure apparatus, whereby a region to be the opening 17 formed in the AlN layer 16 is formed. A resist pattern having an opening is formed. Thereafter, the opening 17 is formed by dry etching the AlN layer 16 by RIE (Reactive Ion Etching) using the formed resist pattern as a mask. The conditions for RIE performed at this time are Cl ₂ gas as an etching gas, RF power of 100 W, bias power of 10 W, and pressure in the chamber of the RIE apparatus is 1 Pa. Thereafter, the formed resist pattern is removed.

Next, as shown in FIG. 1C, an n-GaN layer 18 having a thickness of 2 μm and an n-AlGaN layer 19 having a thickness of 30 nm are formed on the AlN layer 16 in which the opening 17 has been formed by MOCVD. The n-AlGaN layer 19 is doped with Si as a dopant, and has a doping concentration of 5 × 10 ¹⁸ cm ⁻³ .

  Next, as shown in FIG. 1D, the SiN layer 20 is formed. Specifically, the SiN layer 20 having a thickness of 5 to 500 nm is formed by a CVD (Chemical Vapor Deposition) method.

  Next, an opening 21 is formed in the SiN layer 20 as shown in FIG. A source electrode is formed in the opening 21 as will be described later. Specifically, after applying a photoresist on the SiN layer 20 and performing pre-baking or the like, exposure and development are performed by an exposure apparatus, whereby a region to be the opening 21 formed in the SiN layer 20 is formed. A resist pattern having an opening is formed. Thereafter, an opening 21 is formed by dry etching the SiN layer 20 by RIE using the formed resist pattern as a mask, and then the formed resist pattern is removed.

  Next, as shown in FIG. 2F, a source electrode 22 is formed in the opening 21 of the SiN layer 20. Specifically, after applying a photoresist on the SiN layer 20 in which the opening 21 is formed and performing pre-baking or the like, exposure and development are performed by an exposure apparatus, thereby forming SiN on which the source electrode 22 is formed. A resist pattern having an opening is formed in the opening 21 of the layer 20. Then, 30 nm of Ti (titanium) and 100 nm of Al (aluminum) are formed by vacuum deposition. Thereafter, Ti and Al on the region where the resist pattern is formed are removed together with the resist pattern by a lift-off method using an organic solvent or the like, so that the source electrode 22 on which Ti and Al are laminated is formed on the SiN layer 20. The opening 21 is formed. Thereafter, the source electrode 22 is brought into ohmic contact with the n-AlGaN layer 19 by performing heat treatment at 400 to 1000 ° C. in a nitrogen atmosphere. In this embodiment, the heat treatment is performed at a heat treatment temperature of 600 ° C.

  Next, an opening 23 is formed in the SiN layer 20 as shown in FIG. A gate electrode is formed in the opening 23 as will be described later. Specifically, after applying a photoresist on the SiN layer 20 and performing pre-baking or the like, exposure and development are performed by an exposure apparatus, whereby a region to be the opening 23 formed in the SiN layer 20 is formed. A resist pattern having an opening is formed. Thereafter, the SiN layer 20 is dry-etched by the RIE method using the formed resist pattern as a mask to form an opening 23, and then the formed resist pattern is removed.

  Next, as shown in FIG. 2H, a gate electrode 24 is formed in the opening 23 of the SiN layer 20. Specifically, a photoresist is applied on the SiN layer 20 in which the opening 23 is formed, prebaked, etc., and then exposed and developed by an exposure apparatus, whereby SiN on which the gate electrode 24 is formed. A resist pattern having an opening is formed in the opening 23 of the layer 20. Thereafter, Ni (nickel) is deposited in a thickness of 10 nm and Au (gold) is deposited in a thickness of 200 nm by vacuum deposition. Thereafter, Ni and Au on the region where the resist pattern is formed are removed together with the resist pattern by a lift-off method using an organic solvent or the like, whereby the gate electrode 24 in which Ni and Au are stacked is formed on the SiN layer 20. An opening 23 is formed.

  Next, as shown in FIG. 2I, the SiN layer 25 is formed. Specifically, the SiN layer 25 is formed by a CVD method so as to cover the surfaces of the source electrode 22 and the gate electrode 24.

  Next, as shown in FIG. 3 (j), openings 26 are formed in the SiN layer 20 and the SiN layer 25. Specifically, after applying a photoresist on the SiN layer 25 and performing pre-baking or the like, exposure and development are performed by an exposure apparatus, thereby forming the openings 26 formed in the SiN layer 20 and the SiN layer 25. A resist pattern having an opening is formed on the region. Thereafter, the SiN layer 20 and the SiN layer 25 are dry-etched by the RIE method using the formed resist pattern as a mask to form the opening 26, and then the formed resist pattern is removed.

Next, as shown in FIG. 3K, trenches 27 are formed in the p-GaN layer 14, the n-GaN layer 15, the AlN layer 16, the n-GaN layer 18 and the n-AlGaN layer 19. Specifically, the p-GaN layer 14, the n-GaN layer 15, the AlN layer 16, the n-GaN layer 18, and the n-GaN layer are formed by RIE using the SiN layer 20 and the SiN layer 25 in which the opening 26 is formed as a mask. The trench 27 is formed by etching the AlGaN layer 19. The conditions of RIE performed at this time are Cl ₂ gas as an etching gas, RF power 200 W, bias power 30 W, pressure in the chamber of the RIE apparatus is 1 Pa, and until the surface of the n-GaN layer 13 is exposed. Perform dry etching.

  Next, as shown in FIG. 3L, the connection electrode 28 is formed in the opening 26 and the trench 27 and on the surface of the SiN layer 25. Specifically, the connection electrode 28 is formed on the surface of the opening 26 and the trench 27 and the surface of the SiN layer 25 by forming a 100 nm Ti and 500 nm Au layer by sputtering.

  Next, as shown in FIG. 3M, a Ni layer 29 is formed on the surface of the connection electrode 28 by Ni plating. The formed Ni layer 29 has a film thickness of 100 μm. As will be described later, the Ni layer 29 needs to have a film thickness that can maintain sufficient strength when peeled from the sapphire substrate 11, and the formed film thickness is 100 μm or more.

  Next, as shown in FIG. 3 (n), by removing the n-GaN layer 13 by photoelectrochemical etching, the n-GaN layer 15, which is the device layer 40, the AlN layer 16, n, are removed from the sapphire substrate 11. The film including the -GaN layer 18 and the n-AlGaN layer 19 is peeled off. The removed n-GaN layer 13 is a sacrificial layer and is an n-type nitride semiconductor. Details of the photoelectrochemical etching will be described later.

Next, as shown in FIG. 4 (o), the p-GaN layer 14 is removed. Specifically, the p-GaN layer 14 is removed by performing dry etching by the RIE method. The conditions for RIE performed at this time are Cl ₂ gas as an etching gas, RF power of 100 W, bias power of 10 W, and pressure in the chamber of the RIE apparatus is 1 Pa.

  Next, as shown in FIG. 4P, the drain electrode 30 is formed. Specifically, 30 nm of Ti and 100 nm of Au are stacked on the surface of the n-GaN layer 15 exposed by removing the p-GaN layer 14 by sputtering. Thereafter, the drain electrode 30 is brought into ohmic contact with the n-GaN layer 15 by performing heat treatment at 400 to 1000 ° C. in a nitrogen atmosphere.

  Next, as shown in FIG. 4 (q), a low-resistance Si substrate 31 that serves as a support is bonded to the drain electrode 30. Specifically, the drain electrode 30 and the low-resistance Si substrate 31 are bonded between the drain electrode 30 and the low-resistance Si substrate 31 via a brazing material (not shown) such as Cu or Ag. The brazing material has conductivity, and the low-resistance Si substrate 31 and the drain electrode 30 are electrically connected.

  Next, as shown in FIG. 4R, the connection electrodes 28 on the surfaces of the Ni layer 29 and the SiN layer 25 are removed. Specifically, the Ni layer 29 is removed by wet etching using sulfuric acid, and the connection electrode 28 on the surface of the SiN layer 25 is removed by dry etching using ion milling.

  Next, as shown in FIG. 4 (s), the region including the trench 27 is cut as a scribe line by a dicing saw to separate each chip.

  Through the above steps, a vertical GaN-HEMT as shown in FIG. 5 can be manufactured. Specifically, the drain electrode 30, the n-GaN layer 15, the AlN layer 16, the n-GaN layer 18, and the n-AlGaN layer 19 are stacked on the low-resistance Si substrate 31, and the source electrode 22, A vertical GaN-HEMT in which the gate electrode 24 is formed can be manufactured. In the vertical GaN-HEMT, current flows substantially perpendicularly to the low-resistance Si substrate 31 in the n-GaN layer 15 and the n-GaN layer 18 that are nitride semiconductor layers during operation.

  In the present embodiment, the sapphire substrate 11 is used as the growth substrate, but the same production can be performed using a SiC substrate.

(Photoelectrochemical etching)
Next, the photoelectrochemical etching in FIG. In this electrochemical etching, the n-GaN layer 13 serving as a sacrificial layer is removed by immersing the sapphire substrate 11 in which a nitride semiconductor layer or the like is laminated in an alkaline solution.

  FIG. 6 is an explanatory diagram of photoelectrochemical etching in the present embodiment. In the electrochemical etching in the present embodiment, the sapphire substrate 11 on which the nitride semiconductor layer or the like is laminated is immersed in the KOH solution 41, irradiated with ultraviolet light from the light source 42, and the Ni layer 29 and the positive electrode of the power source 43 are applied. The negative electrode of the power source 43 is connected to the electrode terminal 44. The Ni layer 29 is connected to the n-GaN layer 13 through the connection electrode 28. The electrode terminal 44 is placed in a KOH solution 41 that is an electrolytic solution. The density | concentration of the KOH solution 41 of the alkaline solution which is electrolyte solution is 0.0001-10 mol / L, and the electrode terminal 44 is formed of Pt. Further, i-line (wavelength: 365 nm) of a mercury lamp light source is used as the light source 42, and light irradiation is performed from the surface side of the sapphire substrate 11. In addition, a voltage of 0 to +2 V is applied by the power supply 43.

The n-GaN layer 13 is etched by irradiating ultraviolet light from the light source 42 in a state where the sapphire substrate 11 in which the nitride semiconductor layer or the like is laminated in the KOH solution 41 that is an electrolytic solution is immersed. Specifically, as shown in FIG. 7, the n-GaN layer 13 is irradiated with ultraviolet light from the light source 43 to generate electrons and holes, and the generated holes contribute to the etching. proceed. That is, in the n-GaN layer 13 that is in contact with the KOH solution 41, reactions shown in the formulas (1) and (2) occur, and etching proceeds by Ga oxidation and oxide dissolution.

2GaN + 6OH ⁻ + 6h ⁺ → Ga ₂ O ₃ + N ₂ + 3H ₂ O (1)

Ga ₂ O ₃ + 6OH ⁻ → 2GaO ₃ ^{3 −} + 3H ₂ O (2)

In order to further promote this reaction, a power source 43 is provided and electrons are extracted from the n-GaN layer 13 connected via the connection electrode 28, and a hydrogen reduction reaction at the electrode terminal 44 serving as the counter electrode results in a reduction in the n-GaN layer 13. Suppresses recombination of electrons and holes. As a result, the n-GaN layer 13 can be etched at a high speed, and the etching proceeds in the direction indicated by the white arrow in the figure.

  In the present embodiment, when the concentration of the KOH solution 41 as the electrolyte is 2 mol / L and the voltage at the power source 43 is +1 V, the etching rate of the n-GaN layer 13 is about 5 μm / min. Note that the p-GaN layer 14 formed in contact with the sacrificial n-GaN layer 13 is a p-type nitride semiconductor, and thus is difficult to be etched and becomes an etching stop layer. Thereby, the n-GaN layer 15, AlN layer 16, n-GaN layer 18, n-AlGaN layer 19 and the like which are the device layers 40 are not etched.

  In the present embodiment, since the n-GaN layer 13 which is a sacrificial layer is connected to the power source 43 with a low resistance by the Ni layer 29 and the connection electrode 28, electrons can be easily extracted, and n− The etching rate of the GaN layer 13 can be accelerated. Thereby, it can peel from the growth board | substrate 11 in a short time, it becomes possible to shorten the manufacturing time of vertical GaN-HEMT which is a semiconductor device, and can reduce manufacturing cost.

  Moreover, it is also possible to manufacture a vertical GaN-semiconductor laser by a method similar to the manufacturing method in the present embodiment. Specifically, using a SiC or sapphire substrate as a growth substrate, a region to be a semiconductor laser part including a nitride semiconductor layer is formed via a sacrificial layer, and then the sacrificial layer is removed by photoelectrochemical etching. Thus, the region to be the semiconductor laser portion is peeled off from the growth substrate. Thereafter, a semiconductor laser having a nitride semiconductor layer can be manufactured at low cost by bonding the peeled region to be a semiconductor laser portion to a low-resistance Si substrate. Similar to the vertical GaN-HEMT, this vertical GaN-semiconductor laser oscillates by applying a current in a substantially vertical direction to a bonded low-resistance Si substrate.

[Second Embodiment]
The method for manufacturing a semiconductor device in the second embodiment is a method for manufacturing a lateral GaN-HEMT that is a lateral semiconductor device.

  A method for manufacturing a lateral GaN-HEMT will be described with reference to FIGS.

First, as shown in FIG. 8A, after both surfaces of a sapphire substrate 111 serving as a growth substrate are polished, a nitride semiconductor layer is stacked. Specifically, by MOCVD, the AlN layer 112 is 2 nm, the n-GaN layer 113 is 1 μm, the p-GaN layer 114 is 1 μm, the i-GaN layer 115 is 3 μm, and the n-AlGaN layer 116 is formed on the sapphire substrate 111. A 30 nm layer is formed. The n-AlGaN layer 116 is doped with Si as a dopant, and has a doping concentration of 5 × 10 ¹⁸ cm ⁻³ .

  Next, as shown in FIG. 8B, a SiN layer 117 is formed. Specifically, the SiN layer 117 having a thickness of 5 to 500 nm is formed by a CVD method.

  Next, as shown in FIG. 8C, an opening 118 is formed in the SiN layer 117. Note that a source electrode and a drain electrode are formed in the opening 118 as described later. Specifically, after applying a photoresist on the SiN layer 117 and performing pre-baking or the like, exposure and development are performed by an exposure apparatus, whereby a region that becomes the opening 118 formed in the SiN layer 117 is formed. A resist pattern having an opening is formed. Thereafter, the SiN layer 117 is dry-etched by RIE using the formed resist pattern as a mask to form an opening 118, and thereafter, the formed resist pattern is removed.

  Next, as shown in FIG. 8D, the source electrode 119 and the drain electrode 120 are formed in the opening 118 of the SiN layer 117. Specifically, a photoresist is applied on the SiN layer 117 in which the opening 118 is formed, prebaked or the like, and then exposed and developed by an exposure apparatus, whereby the opening 118 in the SiN layer 117 is formed. Then, a resist pattern having an opening is formed. Thereafter, a Ti layer of 30 nm and an Al layer of 100 nm are formed by vacuum deposition. Thereafter, Ti and Al on the region where the resist pattern is formed are removed together with the resist pattern by a lift-off method using an organic solvent or the like, and the source electrode 119 and the drain electrode 120 on which Ti and Al are laminated are formed in the SiN layer. It is formed in the opening 118 of 117. Thereafter, a heat treatment is performed at 400 to 1000 ° C. in a nitrogen atmosphere to bring the source electrode 119 and the drain electrode 120 into ohmic contact with the n-AlGaN layer 116.

  Next, as shown in FIG. 9E, an opening 121 is formed in the SiN layer 117. A gate electrode is formed in the opening 12 as will be described later. Specifically, after applying a photoresist on the SiN layer 117 and performing pre-baking or the like, exposure and development are performed by an exposure apparatus, so that an area to be the opening 121 formed in the SiN layer 117 is formed. A resist pattern having an opening is formed. Thereafter, the SiN layer 117 is dry-etched by RIE using the formed resist pattern as a mask to form the opening 121, and thereafter, the formed resist pattern is removed.

  Next, as shown in FIG. 9F, a gate electrode 122 is formed in the opening 121 of the SiN layer 117. Specifically, after applying a photoresist on the SiN layer 117 in which the opening 121 is formed and performing pre-baking or the like, exposure and development are performed by an exposure apparatus, thereby forming SiN on which the gate electrode 122 is formed. A resist pattern having an opening is formed in the opening 121 of the layer 117. Thereafter, a Ni layer of 10 nm and an Au layer of 200 nm are formed by vacuum deposition. Thereafter, Ni and Au on the region where the resist pattern is formed are removed together with the resist pattern by a lift-off method using an organic solvent or the like, so that the gate electrode 122 on which Ni and Au are laminated is formed on the SiN layer 117. The opening 121 is formed.

  Next, as shown in FIG. 9G, the SiN layer 123 is formed. Specifically, the SiN layer 123 is formed by a CVD method so as to cover the surfaces of the source electrode 119, the drain electrode 120, and the gate electrode 122.

  Next, as shown in FIG. 9H, openings 124 are formed in the SiN layer 117 and the SiN layer 123. Specifically, after applying a photoresist on the SiN layer 123 and performing pre-baking or the like, exposure and development are performed by an exposure apparatus, thereby forming the openings 124 formed in the SiN layer 117 and the SiN layer 123. A resist pattern having an opening is formed on the region. Thereafter, the SiN layer 117 and the SiN layer 123 are dry-etched by RIE using the formed resist pattern as a mask to form an opening 124, and then the formed resist pattern is removed. Thereby, a part of the source electrode 119 or the drain electrode 120 is exposed. Since this RIE method is selective etching, the source electrode 119 or the drain electrode 120 is not removed.

Next, as shown in FIG. 9I, a trench 125 is formed in the p-GaN layer 114, the i-GaN layer 115, and the n-AlGaN layer 116. Specifically, the p-GaN layer 114, the i-GaN layer 115, and the n-AlGaN layer 116 are dry-etched by RIE using the SiN layer 117 and the SiN layer 123 in which the opening 124 is formed as a mask. 125 is formed. The conditions of RIE performed at this time are Cl ₂ gas as an etching gas, RF power 200 W, bias power 30 W, pressure in the chamber of the RIE apparatus is 1 Pa, and until the surface of the n-GaN layer 113 is exposed. Perform dry etching.

  Next, as illustrated in FIG. 10J, the connection electrode 126 is formed in the opening 124 and the trench 125 and on the surface of the SiN layer 123. Specifically, the connection electrode 126 is formed on the surface of the SiN layer 123 in the opening 124 and the trench 125 by stacking 100 nm of Ti and 500 nm of Au by sputtering. As a result, the connection electrode 126 connected to the source electrode 119 is formed.

  Next, as shown in FIG. 10 (k), a Ni layer 127 is formed on the surface of the connection electrode 126 by Ni plating. The Ni layer 127 to be formed has a film thickness of 100 μm. As will be described later, the Ni layer 127 needs to have a film thickness that can maintain sufficient strength when peeled from the sapphire substrate 111, and the formed film thickness is 100 μm or more.

  Next, as shown in FIG. 10L, by removing the n-GaN layer 113 by photoelectrochemical etching, the p-GaN layer 114, i-GaN layer, which is a nitride semiconductor layer, is removed from the sapphire substrate 111. The film including 115 and the n-AlGaN layer 116 is peeled off. The n-GaN layer 113 to be removed is a sacrificial layer, and this photoelectrochemical etching is the same as the method described in the first embodiment.

  Next, as shown in FIG. 10 (m), a back electrode 128 is formed on the surface of the p-GaN layer 114. Specifically, a Ti layer of 30 nm and an Au layer of 100 nm are stacked on the surface of the peeled p-GaN layer 114 by sputtering. As a result, a back electrode 128 electrically connected to the connection electrode 126 is formed on the surface of the p-GaN layer 114.

  Next, as shown in FIG. 10N, a low-resistance Si substrate 129 is bonded to the back electrode 128. Specifically, a low-resistance Si substrate 129 is bonded to the back electrode 128 by placing a brazing material (not shown) such as Cu or Ag between the back electrode 128 and the low-resistance Si substrate 129 and heating. .

  Next, as shown in FIG. 11 (o), the connection electrodes 126 on the surfaces of the Ni layer 127 and the SiN layer 123 are removed. Specifically, the Ni layer 127 is removed by wet etching using sulfuric acid and the connection electrode 126 on the surface of the SiN layer 123 is removed by polishing. As a result, the connection electrode 126 remains in the opening 124 and the trench 125.

  Next, as shown in FIG. 11 (p), the SiN layer 130 is formed. Specifically, the SiN layer 123 is formed by a CVD method so as to cover the exposed surface of the connection electrode 126. As a result, a lateral GaN-HEMT can be manufactured, and if necessary, the low-resistance Si substrate 129 is separated for each chip by a dicing saw.

  By this method, a lateral GaN-HEMT as shown in FIG. 12 can be manufactured. Specifically, a back electrode 128, a p-GaN layer 114, an i-GaN layer 115, and an n-AlGaN layer 116 are stacked on a low-resistance Si substrate 129, and further, a source electrode 119, a drain electrode 120, and a gate electrode 122. A lateral GaN-HEMT in which is formed can be manufactured. In operation, the lateral GaN-HEMT is substantially parallel to the low-resistance Si substrate 129 in the i-GaN layer 115 which is a nitride semiconductor layer, that is, the current flows in the plane direction of the low-resistance Si substrate 129. Flows.

  In the present embodiment, the sapphire substrate 111 is used as the growth substrate, but it can be similarly manufactured even if an SiC substrate is used.

  In this embodiment, since the sacrificial n-GaN layer 113 is connected to the low resistance by the Ni layer 127 and the connection electrode 126, electrons can be easily extracted from the n-GaN layer 113. The etching rate of the n-GaN layer 113 can be accelerated. Thereby, it can peel from the growth board | substrate 111 in a short time, it becomes possible to shorten the manufacturing time of horizontal type GaN-HEMT which is a semiconductor device, and can reduce manufacturing cost.

  Further, it is also possible to manufacture a lateral GaN semiconductor laser by a method similar to the manufacturing method in the present embodiment. Specifically, using a SiC or sapphire substrate as a growth substrate, a region to be a semiconductor laser part including a nitride semiconductor layer is formed via a sacrificial layer, and then the sacrificial layer is removed by photoelectrochemical etching. Thus, the region to be the semiconductor laser portion is peeled off from the growth substrate. Thereafter, a semiconductor laser having a nitride semiconductor layer can be manufactured at low cost by bonding the peeled region to be a semiconductor laser portion to a low-resistance Si substrate. Similar to the lateral GaN-HEMT, this lateral GaN-semiconductor laser functions when the current flows substantially parallel to the bonded low-resistance Si substrate, that is, in the surface direction of the low-resistance Si substrate. .

[Third Embodiment]
Next, a method for manufacturing a semiconductor device in the third embodiment will be described. The present embodiment is a method for manufacturing a horizontal semiconductor device, which is a method for manufacturing a semiconductor device in which the peeling time is further reduced.

  The present embodiment will be described with reference to FIGS.

  First, as shown in FIG. 13A, after polishing both surfaces of a sapphire substrate 211 serving as a growth substrate, a nitride semiconductor layer is stacked. Specifically, the AlN layer 212 is 2 nm, the n-GaN layer 213 is 1 μm, the p-GaN layer 214 is 1 μm, the i-GaN layer 215 is 3 μm, and the n-AlGaN layer 216 is formed on the sapphire substrate 211 by MOCVD. Are stacked to 30 nm. Further, the drain electrode 218, the gate electrode 219, and the source electrode 220 are formed on the n-AlGaN layer 216, and the SiN layer 217 is formed so as to cover them. A trench 221 is formed in the p-GaN layer 214, the i-GaN layer 215, the n-AlGaN layer 216, and the SiN layer 217, and a Ti film and an Au film are laminated on the surfaces of the trench 221 and the SiN layer 217. A connection electrode 222 is formed. The connection electrode 222 is in contact with the n-GaN layer 213 in the trench 221. The detailed formation method is the same as the formation method in the second embodiment.

  Next, as shown in FIG. 13B, an opening 223 is formed in a part of the connection electrode 222 formed on the surface of the SiN layer 217. Specifically, after applying a photoresist on the surface of the connection electrode 222 and performing pre-baking or the like, exposure and development are performed by an exposure apparatus, thereby forming an opening 223 formed in the connection electrode 222. A resist pattern 224 having an opening is formed. Thereafter, ion milling is performed using the formed resist pattern 224 as a mask, and the connection electrode 222 in the region where the resist pattern 224 is not formed is removed. Thereby, an opening 223 is formed in the connection electrode 222.

Next, as illustrated in FIG. 14C, an electrolyte penetration groove 225 is formed in the p-GaN layer 214, the i-GaN layer 215, and the n-AlGaN layer 216. Specifically, using the resist pattern 224 as a mask, the p-GaN layer 214, the i-GaN layer 215, the n-AlGaN layer 216, and the SiN layer 217 are dry-etched by the RIE method to form the electrolyte penetration groove 225. . In the dry etching by the RIE method, Cl ₂ gas is used until the surface of the n-GaN layer 213 is exposed. After the dry etching is completed, the resist pattern 224 is removed.

  Next, as shown in FIG. 14D, a SiN film 226 is formed. Specifically, the SiN film 226 is formed on the surface of the connection electrode 222 and the inside of the electrolyte solution penetration groove 225 by the CVD method. The reason why the SiN film 226 is formed in this way is to prevent the nitride semiconductor layer from being etched from the side surface in the electrolyte solution permeation groove 225. The film thickness of the SiN film 226 formed in the present embodiment is 100 nm.

Next, as shown in FIG. 15E, the SiN film 226 formed on the surface of the connection electrode 222 and the surface of the n-GaN layer 213 is removed by the RIE method. Specifically, 15 sccm of SF ₆ and 15 sccm of CHF ₃ are supplied as etching gases, the RF power is 500 W, the bias power is 50 W, the pressure in the chamber is 1 Pa, and the surface of the connection electrode 222 and the surface of the n-GaN layer 213 are Perform dry etching until exposed. Thereby, the SiN film 226 remains on the side surface of the electrolytic solution permeation groove 225.

  Next, as shown in FIG. 15F, by removing the n-GaN layer 213 by photoelectrochemical etching, the p-GaN layer 214 and the i-GaN layer which are nitride semiconductor layers from the sapphire substrate 211 are removed. 215, the film including the n-AlGaN layer 216 is peeled off. The removed n-GaN layer 213 becomes a sacrificial layer. This photoelectrochemical etching is the same as the method described in the first embodiment. However, in this embodiment, as described later, by providing an electrolyte solution penetration groove 225, electrolysis is performed from the electrolyte solution penetration groove 225. Since the liquid enters, peeling can be performed in a shorter time.

  FIG. 18 shows a state in the middle of the process of FIG. FIG. 19A is a cross-sectional view of the entire sapphire substrate 211 cut along a broken line 18A-18B in FIG. 18, and FIG. 19B is an enlarged view of a region surrounded by the broken line in FIG. is there.

  As shown in the figure, the electrolyte solution penetration groove 225 is provided for each semiconductor device of one chip. For this reason, when immersed in the KOH solution 230 that is the electrolytic solution, the KOH solution 230 that is the electrolytic solution enters from the electrolytic solution penetration groove 225 provided for each chip, and in a short time n-GaN. Layer 213 can be removed. Thereby, the growth substrate 211 can be peeled off in a short time. Note that since the SiN film 226 is formed on the side surface of the electrolyte penetration groove 225, the p-GaN layer 214, the i-GaN layer 215, the n-AlGaN layer 216, and the like, which are nitride semiconductor layers, are etched from the side surface. Never happen. In addition, the region of the connection electrode 222 formed in the trench 221 corresponds to a scribe line for dicing, as will be described later, and this region can be separated for each chip by cutting with a dicing saw. it can.

  Next, as shown in FIG. 16G, the polycrystalline SiC substrate 231 is bonded to the surface separated by photoelectrochemical etching, that is, the surface where the p-GaN layer 214 is formed. Specifically, it adheres to a polycrystalline SiC substrate 231 which is a high thermal conductivity material through a brazing material such as Cu or Ag.

  Next, as shown in FIG. 16H, the connection electrode 222 is removed. Specifically, the Au film in the connection electrode 222 is removed by an etchant containing iodine and ammonium iodide, and the Ti film is removed by sulfuric acid hydrolysis. Thereby, the connection electrode 222 in the trench 221 is also removed.

  Next, as shown in FIG. 17 (i), the polycrystalline SiC substrate 231 in the region where the trench 221 is formed is cut by a dicing saw with the region including the connection electrode 222 as a scribe line. To separate.

  In this embodiment, by providing the electrolyte penetration groove 225 for each chip, the n-GaN layer 213 can be removed at a high speed, and the nitride semiconductor layer is peeled from the growth substrate 211 in a short time. Therefore, it becomes possible to manufacture at a lower cost.

[Fourth Embodiment]
Next, a method for manufacturing a semiconductor device in the fourth embodiment will be described. The present embodiment is a method for manufacturing a horizontal semiconductor device, and is a method for manufacturing a semiconductor device in which the peeling time is shortened by a method different from that of the third embodiment.

  The present embodiment will be described with reference to FIGS.

  First, as shown in FIG. 20A, both surfaces of a sapphire substrate 311 serving as a growth substrate are polished, and then a nitride semiconductor layer is stacked. Specifically, the AlN layer 312 is 2 nm, the n-GaN layer 313 is 1 μm, the p-GaN layer 314 is 1 μm, the i-GaN layer 315 is 3 μm, and the n-AlGaN layer 316 is formed on the sapphire substrate 311 by MOCVD. Are stacked to 30 nm. Further, the drain electrode 318, the gate electrode 319, and the source electrode 320 are formed on the n-AlGaN layer 316, and the SiN layer 317 is formed so as to cover them. A trench 321 is formed in the p-GaN layer 314, the i-GaN layer 315, the n-AlGaN layer 316, and the SiN layer 317, and a Ti film and an Au film are stacked on the surfaces of the trench 321 and the SiN layer 317. A connection electrode 322 is formed. The connection electrode 322 is in contact with the n-GaN layer 313 and is electrically connected to the source electrode 320. The p-GaN layer 314, the i-GaN layer 315, and the n-AlGaN layer 316 are formed with an electrolyte penetration groove 325, and an SiN film 326 is formed on the inner wall of the electrolyte penetration groove 325. The formation method is the same as that in the third embodiment. The detailed formation method other than the above is the same as the formation method in the second embodiment.

  Next, as shown in FIG. 20B, after the In plate 330 is pressure bonded to the side where the connection electrode 322 is formed, the n-GaN layer 313 is removed by photoelectrochemical etching. Thereby, the film including the p-GaN layer 314, the i-GaN layer 315, the n-AlGaN layer 316, and the like, which are nitride semiconductor layers, is peeled from the sapphire substrate 311. Although this photoelectrochemical etching is the same as the method described in the first embodiment, in this embodiment, as described later, by providing an electrolyte penetration groove 325, the electrolyte penetration groove 325 performs electrolysis. Since the liquid enters, peeling can be performed in a shorter time. The n-GaN layer 313 to be removed becomes a sacrificial layer.

  FIG. 22 shows a state in the middle of the process of FIG. As shown in the figure, the KOH solution 331 that is the electrolyte enters from the electrolyte penetration groove 325 and the n-GaN layer 313 is removed.

  23A is a cross-sectional view of the entire sapphire substrate 311 cut along a broken line 22A-22B in FIG. 22, and FIG. 23B is an enlarged view of a region surrounded by the broken line in FIG. is there. As shown in the figure, the electrolyte solution penetration groove 325 is provided so as to surround the periphery of the semiconductor device of one chip, and is formed corresponding to a scribe line for dicing. By cutting the region where the electrolyte solution permeation groove 325 is formed with a dicing saw as a scribe line, it can be separated for each chip. For this reason, when immersed in the KOH solution 331 that is the electrolytic solution, the KOH solution 331 that is the electrolytic solution penetrates from the electrolytic solution penetration groove 325 that is formed in the peripheral portion of each chip. The n-GaN layer 313 is removed at high speed. As a result, the sapphire substrate 311 can be peeled off in a short time.

  Next, as shown in FIG. 21C, a low-resistance conductive substrate 333 is attached to the surface from which the growth substrate 311 has been peeled, with an Ag paste 332 interposed therebetween. Examples of the conductive substrate 333 include a low-resistance Si substrate and a metal substrate such as Cu.

  Next, as shown in FIG. 21D, the In plate 330 is peeled off, and the connection electrode 322 formed on the surface of the SiN layer 317 is removed by polishing. Thereafter, the conductive substrate 333 is cut by a dicing saw with the region where the electrolyte solution permeation groove 325 is formed as a scribe line, so that each chip is separated.

  In this embodiment, by providing the electrolyte penetration groove 325 in a region that becomes a scribe line of a dicing saw for cutting every chip, the n-GaN layer 313 can be removed at high speed, and in a short time. Since the nitride semiconductor layer can be peeled off from the growth substrate 311, it can be manufactured at a lower cost.

  Although the embodiment has been described in detail above, it is not limited to the specific embodiment, and various modifications and changes can be made within the scope described in the claims.

11 Sapphire substrate 12 AlN layer (growth substrate)
13 n-GaN layer (sacrificial layer)
14 p-GaN layer 15 n-GaN layer 16 AlN layer 17 opening 18 n-GaN layer 19 n-AlGaN layer 20 SiN layer 21 opening 22 source electrode 23 opening 24 gate electrode 25 SiN layer 26 opening 27 trench 28 Connection electrode 29 Ni layer 30 Drain electrode 31 Low resistance Si substrate

Claims (5)

A sacrificial layer forming step of forming a first nitride semiconductor sacrificial layer on the substrate;
A laminated semiconductor forming step of forming a second nitride semiconductor layer on the sacrificial layer, and forming a laminated nitride semiconductor layer in which the nitride semiconductor layer is laminated on the second nitride semiconductor layer;
A trench is formed by etching the second nitride semiconductor layer and the stacked nitride semiconductor layer until the surface of the sacrificial layer is exposed, and a connection electrode is formed on the surface of the trench and the stacked nitride semiconductor layer Connecting electrode forming step,
A sacrificial layer removing step of immersing the substrate on which the connection electrode is formed in an electrolyte, applying a potential to the connection electrode with respect to the electrolyte, removing the sacrificial layer, and peeling the substrate;
A method for manufacturing a semiconductor device, comprising:   2. The semiconductor device according to claim 1, further comprising a substrate bonding step of bonding a support to the second nitride semiconductor layer and the stacked nitride semiconductor layer separated from the substrate by the sacrificial layer removing step. Manufacturing method. After the connection electrode formation step, the second nitride semiconductor layer and the laminated nitride semiconductor layer are etched until a surface of the sacrificial layer is exposed to form a solution groove formation step. ,
The method for manufacturing a semiconductor device according to claim 1, wherein the sacrificial layer removing step is performed after the penetration groove forming step. After the substrate bonding step, it has a cutting step of cutting for each chip by a dicing saw,
4. The method of manufacturing a semiconductor device according to claim 3, wherein the solution penetration groove is provided for each of the chips.   The sacrificial layer of the first nitride semiconductor is n-type, the second nitride semiconductor is p-type, the potential is positive, and the sacrificial layer removing step is performed while irradiating light. The method for manufacturing a semiconductor device according to claim 1, wherein the method is a semiconductor device manufacturing method.

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