JP2005097045A - Method for manufacturing group iii nitride wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a group III nitride wafer by which a substrate part and the group III nitride wafer can be uniformly separated. <P>SOLUTION: The method for manufacturing the group III nitride wafer 20 comprises separating the wafer 1000 having the substrate part 10 in which an electroconductive group III nitride layer 30 is formed between the substrate part 10 and the group III nitride wafer 20 comprising at least one group III nitride layer, into the substrate part 10 and the group III nitride wafer 20 by decomposing the electroconductive group III nitride layer 30 by passing an electric current through the electroconductive group III nitride layer 30 in an electrolytic solution. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a group III nitride wafer, and more particularly to a method for manufacturing a group III nitride that separates a group III nitride wafer from a substrate portion.

  In order to obtain a group III nitride wafer without a substrate, a thickness of 10 μm to 150 μm is formed by epitaxial growth on a sapphire substrate or a GaN substrate using a HVPE (Hydride Vapor Epitaxy) method. It has been proposed to peel off the GaN layer from the substrate by a laser lift-off technique (see Non-Patent Document 1).

However, in the laser lift-off, since a high-power laser having a wavelength of 355 nm, which is absorbed by GaN, is used, a defect occurs in the GaN layer due to thermal shock at the time of laser lift-off. Further, in the laser lift-off, there is no method for uniformly irradiating the front surface of a disk having a diameter of 5.08 cm (2 inches), which is a normal size of the GaN wafer, and it is difficult to uniformly peel off the GaN wafer.
T. Paskova and 4 others, “Growth and separation related properties of HVPE-GaN free-standing film”, J. Crystal. Growth, Netherlands, Elsevier Science, 246, Dec. 2002, p.207-214

  It is an object of the present invention to provide a method for producing a group III nitride wafer capable of uniformly separating a substrate part and a group III nitride wafer even in a group III nitride wafer with a large area substrate part. .

  The method for producing a group III nitride wafer according to the present invention includes a substrate part in which a conductive group III nitride layer is formed between the substrate part and a group III nitride wafer comprising one or more group III nitride layers. The attached wafer is separated into a substrate part and a group III nitride wafer by flowing a current through the group III nitride layer in an electrolytic solution and decomposing the group III nitride layer. And

In the method for producing a group III nitride wafer according to the present invention, the conductive group III nitride layer has a specific resistance of 10 ⁻¹ Ω · cm or less, and the wafer side adjacent layer adjacent to the conductive group III nitride layer In addition, the specific resistance of the substrate portion side adjacent layer can be 100 times or more the specific resistance of the conductive group III nitride layer. Moreover, it can be set as the aqueous solution containing the basic compound which dissociates electrolyte solution, and the density | concentration of the basic compound can be 0.01N-10N. Furthermore, an electrode can be formed on the conductive group III nitride layer of the wafer with the substrate portion.

  According to the present invention, since the conductive group III nitride layer is decomposed by passing a current through the conductive group III nitride layer in the electrolytic solution, even in the group III nitride wafer with a large area substrate, The substrate portion and the group III nitride wafer can be separated uniformly.

  Referring to FIG. 1, a method for producing a group III nitride wafer according to the present invention includes a conductive group III nitride between a substrate portion 10 and a group III nitride wafer 20 composed of one or more group III nitride layers. The substrate portion-provided wafer 1000 on which the physical layer 30 is formed is passed through the conductive group III nitride layer 30 in the electrolytic solution 1 to decompose the conductive group III nitride layer 30, thereby It is characterized by being separated into a part 10 and a group III nitride wafer 20. With this manufacturing method, the group III nitride wafer 20 uniformly separated from the substrate portion 10 is obtained.

  Here, the substrate portion refers to a substrate portion for growing a target group III nitride layer. Specifically, in addition to a heterogeneous substrate such as a sapphire substrate, a group III nitride that is the same type substrate is used. A physical substrate is included. Further, the substrate portion may be composed of a single substrate layer or may be composed of two or more substrate layers.

  The group III nitride wafer refers to a wafer formed of one or more group III nitride layers, and a group III nitride having a certain function such as a group III nitride optical device or a group III nitride electronic device. Layer stacks are also included.

The conductive group III nitride layer refers to a group III nitride layer whose conductivity is improved by adding an impurity such as Si. In order to facilitate the decomposition of the conductive group III nitride in the electrolytic solution, the specific resistance of the conductive group III nitride layer is preferably 10 ⁻¹ Ω · cm or less, more preferably 10 ⁻² Ω · cm. cm or less, more preferably 10 ⁻³ Ω · cm or less.

The electrolytic solution is an aqueous solution containing a dissociating basic compound or acidic compound. Examples of basic compounds include KOH and NaOH, and examples of acidic compounds include H ₂ SO ₄ , HNO ₃ , and H ₃ PO ₄ . From the viewpoint of low corrosivity, a basic compound is preferable. When an aqueous solution containing a basic compound is used as the electrolytic solution, the concentration of the basic compound is preferably 0.01N to 10N. If the concentration of the basic compound is less than 0.01N, it takes time to decompose the conductive group III nitride layer, and if it exceeds 10N, the selectivity of the decomposition of the conductive group III nitride layer decreases, and the decomposition reaction is controlled. This is because it becomes difficult.

  In the method for producing a group III nitride wafer according to the present invention, referring to FIG. 1, the specific resistance of the wafer side adjacent layer 21 adjacent to the conductive group III nitride layer 30 and the substrate portion side adjacent layer 11 is The specific resistance of the conductive group III nitride layer 30 is preferably 100 times or more. If the specific resistance of the wafer side adjacent layer and the substrate portion side adjacent layer is less than 100 times the specific resistance of the conductive group III nitride layer, the selectivity of the conductive group III nitride layer decomposition is reduced, and the decomposition reaction of This is because control becomes difficult.

  Moreover, in the manufacturing method of the group III nitride wafer concerning this invention, the electrode 2 is formed in the electroconductive group III nitride layer 30 of the wafer 100 with a substrate part with reference to FIGS. Is preferred. It is possible to easily pass a current through the conductive group III nitride layer 30. Here, the material of the electrode 2 is not particularly limited, but Ti—Al alloy, In metal, and the like are preferably used.

  The present invention will be described more specifically based on examples.

(Example 1)
Referring to FIG. 2, a GaN amorphous layer 109 having a thickness of 20 nm as a low-temperature buffer layer and a conductive GaN layer 300 having a thickness of 10 μm to which Si is added as a conductive layer are formed on a sapphire substrate 110 having a thickness of 420 μm by HVPE. Then, a GaN layer 200 having a thickness of 300 μm was sequentially formed as a group III nitride wafer. At this time, the growth conditions of the GaN amorphous layer 109 are an atmosphere temperature of 500 ° C., a source gas of 500 sccm of NH ₃ gas, 5 sccm of HCl gas at 850 ° C., GaCl gas obtained by contacting metal Ga, and a carrier gas. N ₂ gas was added and the total flow rate of the gas was set to 5000 sccm. The growth conditions of the conductive GaN layer 300 and the GaN layer 200 are as follows: the atmospheric temperature is 1050 ° C., the source gas is 500 sccm NH ₃ gas, and 50 sccm HCl gas is contacted with metal Ga at 850 ° C. N ₂ gas was added as a carrier gas, and the total flow rate of the gas was set to 5000 sccm. Further, the addition concentration of Si in the conductive GaN layer 300 was set to 1 × 10 ¹⁸ cm ⁻³ . Here, sccm is a unit of gas flow rate and means a gas flow rate of cm ³ / min in the standard state of gas (0 ° C., 1013 hPa).

  Thereafter, an electrode 2 made of a Ti—Al alloy was formed on the side surface of the conductive GaN layer 300 and subjected to ohmic contact at 600 ° C. for 1 minute to obtain a wafer 2000 with a substrate part. In wafer 2000 with a substrate portion, since the layer thickness of the conductive GaN layer is small, electrode 2 may be formed across the sapphire substrate and the GaN layer. Since the specific resistance is larger than that, almost all current flows through the conductive GaN.

When the specific resistance of the sapphire substrate 110, the conductive GaN layer 300, and the GaN layer 200 of the wafer 2000 with the substrate portion obtained as described above was measured by a four-terminal method, it was 1 × 10 ¹⁶ Ω · cm, × 10 ⁻² Ω · cm and 1 × 10 ³ Ω · cm. Further, since the GaN amorphous layer 109 is extremely thin, it is difficult to measure its specific resistance.

2 and 1 are compared, the conductive GaN layer 300 is the conductive group III nitride layer 30, the sapphire substrate 110 is the substrate portion side adjacent layer 11 in the substrate portion 10, and the GaN layer 200 is the group III. This corresponds to the wafer-side adjacent layer 21 in the nitride wafer 20. Here, it is considered that the GaN amorphous layer 109 is adjacent to the conductive GaN layer 300 on the substrate side, but this GaN amorphous layer 109 is extremely thin, and from the viewpoint of electrical resistance, the conductive group III Since the function as the substrate portion side adjacent layer 11 for enhancing the selectivity of the nitride layer decomposition is poor, the sapphire substrate 110 may be considered as the substrate portion side adjacent layer 11 as described above, ignoring the GaN amorphous layer 109. it can. Then, in this example, the specific resistance of the substrate-side adjacent layer 11 is 10 ¹⁸ times and the specific resistance of the wafer-side adjacent layer 21 is 10 ⁵ times the specific resistance of the conductive group III nitride layer. . Table 1 summarizes the composition, layer thickness, electrical characteristics, and the like of each layer of the wafer with the substrate portion in this example.

  Next, with reference to FIG. 1 and FIG. 2, the wafer with substrate portion 2000 is immersed in a 1N KOH aqueous solution as the electrolytic solution 1 to correspond to the conductive group III nitride layer 30 of the wafer with substrate portion. The Ti—Al electrode, which is the electrode 2 formed on the conductive GaN layer 300, serves as the anode, and the Pt electrode, which is the other electrode 3 in the electrolytic solution 1, serves as the cathode. For about 2 hours. Then, the conductive GaN layer 300 which is the conductive group III nitride layer 30 is decomposed, and the sapphire substrate 110 and the GaN layer 200 are separated, and the GaN layer 200 having a uniform separation surface as the group III nitride wafer 20 is separated. was gotten.

(Example 2)
Referring to FIG. 3A, a GaN amorphous layer 109 having a thickness of 20 nm as a low-temperature buffer layer is formed on a sapphire substrate 110 having a thickness of 420 μm by a HVPE method in the same manner as in the first embodiment. A conductive GaN layer 300 (Si addition concentration 1 × 10 ¹⁸ cm ⁻³ ) having a thickness of 50 μm to which Si was added was formed as a physical layer. Thereafter, an SiO ₂ layer was formed as a mask 40 at the end of the conductive GaN layer 300.

Next, referring to FIG. 3B, a GaN layer 200 having a thickness of 300 μm is formed as a group III nitride wafer on the conductive GaN layer 300 on which the mask 40 is not formed in the same manner as in the first embodiment. Formed. At this time, the SiO ₂ layer, since the nitride layer does not grow, the SiO ₂ layer is left exposed. Thereafter, the SiO ₂ layer, which is the mask 40, is removed by etching with hydrofluoric acid, and the electrode 2 made of a Ti—Al alloy is formed on the exposed surface of the conductive GaN layer, which is subjected to ohmic contact at 600 ° C. for 1 minute. A wafer 3000 with a substrate portion was obtained. In this embodiment, since the electrode 2 is formed on the surface of the conductive GaN layer 300, it is more possible to pass a current through the conductive GaN layer than in the first embodiment in which the electrode 2 is formed on the side surface of the conductive GaN layer 300. It becomes easy.

When the specific resistances of the sapphire substrate 110, the conductive GaN layer 300, and the GaN layer 200 of the wafer 3000 with the substrate portion obtained as described above were measured by a four-terminal method, 1 × 10 ¹⁶ Ω · cm, × 10 ⁻² Ω · cm and 1 × 10 ³ Ω · cm. Further, since the GaN amorphous layer 109 is extremely thin, it is difficult to measure its specific resistance.

3 and 1 are compared, the conductive GaN layer 300 is the conductive group III nitride layer 30, the sapphire substrate 110 is the substrate portion side adjacent layer 11 in the substrate portion 10, and the GaN layer 200 is the group III. This corresponds to the wafer-side adjacent layer 21 in the nitride wafer 20. Here, as described in the first embodiment, the GaN amorphous layer 109 is extremely thin, and is adjacent to the substrate portion so as to enhance the selectivity of the conductive group III nitride layer decomposition from the viewpoint of electrical resistance. Since the function as the layer 11 was poor, it was excluded. Therefore, in this embodiment, the specific resistance of the substrate-side adjacent layer 11 is 10 ¹⁸ times and the specific resistance of the wafer-side adjacent layer 21 is 10 ⁵ times the specific resistance of the conductive group III nitride layer. . Table 2 summarizes the composition, layer thickness, electrical characteristics, and the like of each layer of the wafer with the substrate portion in this example.

  Next, referring to FIG. 1 and FIG. 3, similarly to Example 1, the wafer with substrate 3000 is immersed in a 1N KOH aqueous solution, and a current of 1 mA is passed through the conductive GaN layer 300 for about 2 hours. Then, the conductive GaN layer 300 was decomposed, and the sapphire substrate 110 and the GaN layer 200 were separated, and the GaN layer 200 having a uniform separation surface as the group III nitride wafer 20 was obtained.

(Example 3)
Referring to FIG. 4A, a conductive GaN layer 300 having a thickness of 50 μm to which Si was added as a conductive group III nitride layer was formed on a GaN substrate 101 having a thickness of 420 μm by HVPE. The growth condition of the conductive GaN layer at this time is an atmosphere temperature of 1050 ° C., a source gas of 500 sccm of NH ₃ gas, a gas of 50 sccm of HCl gas brought into contact with metal Ga at 850 ° C., and a carrier gas. N ₂ gas was added and the total flow rate of the gas was set to 5000 sccm. Further, the addition concentration of Si in the conductive GaN layer 300 was set to 1 × 10 ¹⁸ cm ⁻³ . Thereafter, an SiO ₂ layer was formed as a mask 40 at the end of the conductive GaN layer 300.

Next, referring to FIG. 4B, a GaN layer 200 having a thickness of 300 μm is formed as a group III nitride wafer on the conductive GaN layer 300 on which the mask 40 is not formed in the same manner as in the first embodiment. Formed. At this time, the SiO ₂ layer, since the nitride layer does not grow, the SiO ₂ layer is left exposed. Thereafter, the SiO ₂ layer that is the mask 40 is removed by etching with hydrofluoric acid, and the electrode 2 made of a Ti—Al alloy is formed on the exposed surface of the conductive GaN layer, which is subjected to ohmic contact at 600 ° C. for 1 minute. Thus, a wafer with a substrate 4000 was obtained.

  In this example, since the GaN substrate 101 which is a group III nitride is used as the substrate, the group III nitride layer is formed unlike the examples 1 and 2 using the sapphire substrate. Therefore, a GaN amorphous layer that is a low-temperature buffer layer is not necessary, and the conductive GaN layer 300 is formed directly on the GaN substrate 101.

When the specific resistances of the GaN substrate 101, the conductive GaN layer 300, and the GaN layer 200 of the wafer with substrate 4000 thus obtained were measured by the four-terminal method, they were 1 × 10 ³ Ω · cm and 1 × 10 respectively. ^-2 Ω · cm, 1 × 10 ³ Ω · cm.

4 and 1 are compared, the conductive GaN layer 300 is the conductive group III nitride layer 30, the GaN substrate 101 is the substrate portion side adjacent layer 11 in the substrate portion 10, and the GaN layer 200 is the group III. This corresponds to the wafer-side adjacent layer 21 in the nitride wafer 20. Therefore, in this embodiment, the specific resistance of the substrate-side adjacent layer 11 is 10 ⁵ times and the specific resistance of the wafer-side adjacent layer 21 is 10 ⁵ times the specific resistance of the conductive group III nitride layer. . Table 3 summarizes the composition, layer thickness, electrical characteristics, and the like of each layer of the wafer with the substrate portion in this example.

  Next, referring to FIG. 1 and FIG. 4, similarly to Example 1, the wafer with a substrate 4000 is immersed in a 1N KOH aqueous solution, and a current of 1 mA is passed through the conductive GaN layer 300 for about 2 hours. Then, the conductive GaN layer 300 was decomposed, and the GaN substrate 101 and the GaN layer 200 were separated, and the GaN layer 200 having a uniform separation surface as the group III nitride wafer 20 was obtained.

Example 4
Referring to FIG. 5A, a GaN amorphous layer 109 having a thickness of 20 nm as a low-temperature buffer layer is formed on a sapphire substrate 110 having a thickness of 420 μm by a HVPE method in the same manner as in Example 1. A conductive GaN layer 300 having a thickness of 3.5 μm to which Si was added was formed as a physical layer. However, in this example, the Si addition concentration in the conductive GaN layer 300 was 5 × 10 ¹⁸ cm ⁻³ . After that, a SiO ₂ layer was formed as a mask 40 at the end of the conductive GaN layer 300.

Next, referring to FIG. 5B, on the conductive GaN layer 300 where the mask 40 is not formed, the GaN layer 201 having a thickness of 1 μm and the n-type contact are formed by the HVPE method in the same manner as in the first embodiment. A Si-doped GaN layer 202 having a thickness of 2 μm was formed as a layer. However, in this example, the Si addition concentration in the Si-added GaN layer 202 was 5 × 10 ¹⁸ cm ⁻³ .

Then, using MOCVD, on the Si-doped GaN layer 202, a first In _0.01 Ga _0.99 N layer 203 having a thickness of 15 nm as a first barrier layer and an In _0.15 Ga _0.85 N layer having a thickness of 2 nm as a well layer are formed. 204, a second In _0.01 Ga _0.99 N layer 205 having a thickness of 15 nm as a second barrier layer, and an Mg-added Al _0.15 Ga _0.85 N layer 206 having a thickness of 20 nm as a p-type cladding layer (Mg added concentration is 5 × 10 ^17). cm ⁻³ ) and a Mg-doped GaN layer 207 (Mg addition concentration 1 × 10 ¹⁸ cm ⁻³ ) having a thickness of 50 nm were sequentially formed as a p-type contact layer. At this time, during the growth of the first In _0.01 Ga _0.99 N layer 203, the In _0.15 Ga _0.85 N layer 204 and the second In _0.01 Ga _0.99 N layer 205, TMG (trimethylgallium) and TMI (trimethyl) are used as group III sources. Indium), NH ₃ as an N source, N ₂ gas as a carrier gas, a growth temperature of 800 ° C., and a growth pressure of 100 kPa. In the growth of the Mg-added Al _0.15 Ga _0.85 N layer 206, TMG, TMA (trimethylaluminum) as a group III source, NH ₃ as an N source, and Cp ₂ Mg (biscyclopentadiethylmagnesium) as an Mg source The carrier gas was H ₂ gas, the growth temperature was 1100 ° C., and the growth pressure was 100 kPa. In the growth of the Mg-added GaN layer 207, TMG is used as a group III source, NH ₃ is used as an N source, Cp ₂ Mg is used as an Mg source, H ₂ gas is used as a carrier gas, a growth temperature is 1100 ° C., and a growth pressure is 100 kPa. did.

During the formation of the nitride layer on the conductive GaN layer, the SiO ₂ layer, since the nitride layer does not grow, the SiO ₂ layer is left exposed. Thereafter, the SiO ₂ layer that is the mask 40 is removed by etching with hydrofluoric acid, and the electrode 2 made of a Ti—Al alloy is formed on the exposed surface of the conductive GaN layer, which is subjected to ohmic contact at 600 ° C. for 1 minute. Thus, a wafer with a substrate part 5000 was obtained.

When the specific resistances of the sapphire substrate 110, the conductive GaN layer 300, the GaN layer 201, and the Si-added GaN layer 202 of the wafer 5000 with the substrate portion thus obtained were measured by a four-terminal method, 1 × 10 4 respectively. They were ¹⁶ Ω · cm, 1.25 × 10 ⁻² Ω · cm, 5 × 10 ⁴ Ω · cm, and 1.25 × 10 ⁻² Ω · cm. The GaN amorphous layer 109, the first In _0.01 Ga _0.99 N layer 203, the In _0.15 Ga _0.85 N layer 204, the second In _0.01 Ga _0.99 N layer 205, the Mg-added Al _0.15 Ga _0.85 N layer 206, and the Mg-added GaN Since the layer 207 is extremely thin, it has been difficult to measure its specific resistance.

5 and 1 are compared, the conductive GaN layer 300 is the conductive group III nitride layer 30, the sapphire substrate 110 is the substrate portion side adjacent layer 11 in the substrate portion 10, and the GaN layer 201 is the group III. This corresponds to the wafer-side adjacent layer 21 in the nitride wafer 20. Here, as described in the first embodiment, the GaN amorphous layer 109 is extremely thin, and is adjacent to the substrate portion so as to enhance the selectivity of the conductive group III nitride layer decomposition from the viewpoint of electrical resistance. Since the function as the layer 11 was poor, it was excluded. Then, in this embodiment, the specific resistance of the substrate-side adjacent layer 11 is 8 × 10 ¹⁷ times the specific resistance of the conductive group III nitride layer, and the specific resistance of the wafer-side adjacent layer 21 is 4 × 10. ⁶ times. Table 4 summarizes the composition, layer thickness, electrical characteristics, and the like of each layer of the wafer with the substrate portion in this example.

Next, referring to FIG. 1 and FIG. 5, when the wafer with a substrate 5000 is immersed in a 1N KOH aqueous solution and a current of 10 mA is passed through the conductive GaN layer 300 for about 2 hours as in the first embodiment. Then, the conductive GaN layer 300 is decomposed, and the sapphire substrate 110 and the GaN layer 201 are separated, and the GaN layer 201, the Si-added GaN layer 202, and the first group III nitride wafer 20 having a uniform separation surface are formed. SQW (Single Quantum Well) comprising In _0.01 Ga _0.99 N layer 203, In _0.15 Ga _0.85 N layer 204, second In _0.01 Ga _0.99 N layer 205, Mg-added Al _0.15 Ga _0.85 N layer 206 and Mg-added GaN layer 207; A group III nitride optical device having a (single quantum well) structure was obtained.

Here, the Si-added GaN layer 202 has a specific resistance of 1.25 × 10 ⁻² Ω · cm, which is equivalent to that of the conductive GaN layer, but the electrode 2 is not formed, and a direct current flows. Therefore, even when immersed in the 1N KOH aqueous solution as the electrolytic solution, it was hardly recognized that the Si-added GaN layer 202 was decomposed. That is, in the present invention, even if there are two or more layers having high conductivity, by flowing current only through the conductive layer formed at the position to be separated, only the conductive layer is decomposed, A III-nitride wafer separated at a desired position can be obtained.

  In this embodiment, an example of a group III nitride optical device having an SQW (Single Quantum Well) structure as the group III nitride wafer 20 has been described. The present invention is not limited to group nitride optical devices, and can be widely applied to the production of group III nitride optical devices having an MQW (Multiple Quantum Well) structure and other group III nitride electronic devices.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  As described above, the present invention makes it possible to uniformly separate a substrate portion and a group III nitride wafer even in a group III nitride wafer with a substrate portion having a large area. The present invention can be widely used for manufacturing a group nitride wafer alone.

It is a figure explaining the isolation | separation method of the group III nitride wafer and a board | substrate part in the manufacturing method of the group III nitride wafer concerning this invention. It is a figure which shows one wafer with a board | substrate part used in this invention. It is a figure which shows the manufacturing process of another wafer with a board | substrate part used in this invention. It is a figure which shows the manufacturing process of another wafer with a board | substrate part used in this invention. It is a figure which shows the manufacturing process of another wafer with a board | substrate part used in this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Electrolyte solution, 2 electrodes, 3 other electrodes, 10 board | substrate part, 11 board | substrate side adjacent layer, 12 board | substrate parts other than board | substrate side adjacent layer, 20 group III nitride wafer, 21 wafer side adjacent layer, 22 wafer side Group III nitride wafer other than adjacent layer, 30 conductive group III nitride layer, 101 GaN substrate, 109 GaN amorphous layer, 110 sapphire substrate, 200, 201 GaN layer, 202 Si-added GaN layer, 203 1st In _0.01 Ga _0.99 N layer, 204 In _0.15 Ga _0.85 N layer, 205 Second In _0.01 Ga _0.99 N layer, 206 Mg-added Al _0.15 Ga _0.85 N layer, 207 Mg-added GaN layer, 300 Conductive GaN layer, 1000, 2000, 3000, 4000, 5000 Wafer with substrate.

Claims (5)

  A wafer with a substrate part in which a conductive group III nitride layer is formed between a substrate part and a group III nitride wafer composed of one or more group III nitride layers is made of the conductive group III in an electrolytic solution. A method of manufacturing a group III nitride wafer, wherein an electric current is passed through the nitride layer to decompose the conductive group III nitride layer, thereby separating the substrate portion and the group III nitride wafer. The method for producing a group III nitride wafer according to claim 1, wherein the specific resistance of the conductive group III nitride layer is 10 ^-1 Ω · cm or less.   The specific resistance of the wafer side adjacent layer and the substrate part side adjacent layer adjacent to the conductive group III nitride layer is 100 times or more the specific resistance of the conductive group III nitride layer. A method for producing a group III nitride wafer of   The method for producing a group III nitride wafer according to any one of claims 1 to 3, wherein the electrolytic solution is an aqueous solution containing a dissociating basic compound, and the concentration of the basic compound is 0.01N to 10N. .   The method for producing a group III nitride wafer according to any one of claims 1 to 4, wherein an electrode is formed on the conductive group III nitride layer of the wafer with a substrate portion.

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