KR100629210B1 - light emitting diode with vertical electrode and manufacturing method of the same - Google Patents

Abstract

Sapphire base substrate including a first via hole formed to penetrate up and down, a plurality of nitride-based semiconductor layer formed on the base substrate, the nitride-based semiconductor layer exposed through the first via hole of the sapphire base substrate is formed on the exposed surface A first oxide layer comprising a first electrode to be formed, an ohmic electrode layer formed on the nitride-based semiconductor layer, and a second via hole formed on the ohmic electrode layer to expose a portion of the ohmic electrode layer, and the second via hole A first electrode metal layer formed on the first oxide layer and a second electrode formed on one surface thereof to be connected to the ohmic electrode layer through the second electrode layer, and a second eutectic metal layer formed on the other surface thereof to be bonded to the first eutectic metal layer A vertical light emitting diode comprising a receptor substrate is provided.

Light emitting diode, vertical electrode structure, oxide film, sapphire, via hole, nitride semiconductor

Description

Light emitting diode with vertical electrode and manufacturing method of the same

1 is a graph showing the etching rates of sapphire and GaN by ICP / RIE dry etching.

2 is a cross-sectional view and a plan view of a vertical light emitting diode according to a first embodiment of the present invention.

3 is a graph showing an etching rate when wet etching sapphire and GaN with a mixed solution of sulfuric acid and phosphoric acid.

4 is a graph showing the etch rate of sapphire and GaN according to the temperature of the mixed solution of sulfuric acid and phosphoric acid.

FIG. 5 is a photograph of the surface of the sapphire substrate after forming a specific pattern on the sapphire substrate by the wet etching method and then etching the sapphire substrate by the wet etching method.

6 is a photograph of the surface of the buffer layer after removing the sapphire substrate by a wet etching method.

7A to 7J illustrate an intermediate process of manufacturing a vertical light emitting diode according to a second exemplary embodiment of the present invention.

8 is a cross-sectional view and a plan view of a vertical light emitting diode according to a third embodiment of the present invention.

9 is a view showing a cross section and a plane of a vertical light emitting diode according to a fourth embodiment of the present invention.

10 is a cross-sectional view and a plan view of a vertical light emitting diode according to a fifth embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

11 Sapphire Base Board

12 buffer layer

13 first ohmic contact layer

14 First Cladding Layer

15 light emitting layer

16 Second cladding layer

17 second ohmic contact layer

18 second oxide film

19 Ohmic Electrode

20 first oxide film

21st Eutectic Metal

22 second eutectic metal

23 receptor board

24 First Via Hole

25 first electrode

26 Second electrode

27 Second Via Hole

28 Transparent Electrode

31 Dicing or Wall Improvement

The present invention relates to a light emitting diode having a vertical electrode structure and a method of manufacturing the same.

A light emitting diode is a type of photodiode that generates light when a constant current of a constant magnitude flows. The light emitting diode is a light emitting diode that emits red or green light by using a pin bonded structure of compound semiconductors such as indium phosphorus (InP), gallium arsenide (GaAs), and gallium phosphorus (GaP), and also emits blue and ultraviolet light. Light emitting diodes have been developed and widely used in display devices, light source devices, and environmental application devices. Recently, color conversion light emitting diodes using white, red, green, and blue chips or white phosphors have been developed, and the application range of the lighting devices has been expanded.

In the case of using a nitride-based light emitting material as a thin film structure in such a light emitting diode, sapphire similar in lattice constant and crystal structure is used as a base substrate to reduce crystal defects during epitaxial growth.

However, since sapphire is an insulator, both the first electrode and the second electrode had to be formed on the growth surface of the epi layer. Thus, if both electrodes are formed on the same surface, the area of electrodes required for wire bonding must be secured. Therefore, the chip area of the light emitting diode is also over a certain size, which hinders the improvement of chip production per wafer, and uses an insulator as a substrate. Therefore, it is difficult to discharge static electricity flowing from the outside, which causes device defects due to static electricity. This leads to several limitations in the packaging process, such as lowering device reliability and incorporating zener diodes.

In addition, since sapphire has low thermal conductivity, it is difficult to dissipate heat generated while driving a light emitting diode to the outside, and thus there is a limit to applying a large current for high power.

In particular, since the light emitting diodes are manufactured by wet or dry etching the sapphire substrate, the nitride semiconductor layer and the electrode should not be damaged during sapphire etching and the chip performance should not be affected.

1 is a graph showing the etching rates of sapphire and GaN by ICP / RIE dry etching. As shown in FIG. 1, as a result of experimenting at 100 sccm of BCl 3, 1800 W of inductive power, and 10 mTorr of chamber pressure, sapphire and nitride semiconductors have increased etching speeds as ICP and RIE powers are increased. It can be seen that the etching ratio between the sapphire and the nitride semiconductor (Al ₂ O ₃ etching rate vs. GaN etching rate) is decreasing. These results indicate that when the sapphire substrate 11 is etched by the ICP / RIE technique, which is a dry etching technique, it is difficult to stop the etching in the buffer layer 12 made of nitride-based semiconductor. In order to stop the etching in the buffer layer 12, an optical analysis is performed. Techniques such as methods or residual gas analysis methods should be used. Even with these analytical techniques, the probability of success is low.

Dicing equipment commonly used to separate semiconductor devices uses diamond blades. Cutting a sapphire substrate is rather cumbersome and reduces productivity.

Therefore, research for developing a light emitting diode structure having a vertical electrode structure is continuing in the art.

An object of the present invention is to provide a light emitting diode having a vertical electrode structure using a sapphire substrate etching technique and a method of manufacturing the same.

It is an object of the present invention to provide a light emitting diode having a vertical electrode structure having a new sapphire base substrate and an internal connection structure, particularly in a light emitting diode using a receptor substrate to advantageously perform a multi-step process. .

In order to achieve the above object, the present invention proposes the following light emitting diode.

First, the present invention provides a method for forming a semiconductor device, comprising: a. Forming a plurality of nitride based semiconductor layers on a sapphire base substrate; b. forming an ohmic electrode layer on the nitride based semiconductor layer; c. forming a first oxide layer on the ohmic electrode layer, and forming a via hole to expose the ohmic electrode layer on the first oxide layer; d. forming a first eutectic metal layer on the first oxide layer to be electrically connected to the ohmic electrode layer through a via hole of the first oxide layer; e. forming a second eutectic metal layer on one side of the receptor substrate; f. adhering the first and second eutectic metal layers; g. after processing the sapphire base substrate to a predetermined thickness, etching to expose at least a portion of the nitride based semiconductor layer; h. forming a first electrode on the exposed nitride based semiconductor layer; And i. Forming a second electrode on the other side surface corresponding to the one side surface on which the second eutectic metal is formed on the receptor substrate.

Preferably, the step a is to form a buffer layer on the sapphire base substrate and a plurality of nitride-based semiconductor layers on the buffer layer, the step g is to etch the base substrate and the buffer layer together It is characterized by.

In addition, preferably a1. The method may further include forming a second oxide layer on the nitride based semiconductor layer and etching the second oxide layer to leave only a part thereof, wherein in step b, the ohmic electrode layer is formed of the nitride based semiconductor layer and the first oxide layer. 2 may be formed on the oxide layer.

In this case, the second oxide layer etched and left in step a1 may be formed on the same vertical line as the portion exposed through the sapphire base substrate of the nitride-based semiconductor layer. More preferably, the via hole is formed in the second oxide layer. And it is more preferably formed on the same vertical line as the exposed portion of the nitride-based semiconductor layer.

Also preferably, g1. The method may further include forming a transparent electrode layer on the sapphire base substrate, wherein in step h, the first electrode is formed on the transparent electrode layer. In this case, the transparent electrode layer may be formed of any one of indium tin oxide (ITO), ZnB, ZnO, InO, and SnO.

Also preferably, in the g step, the sapphire base substrate is etched and completely removed.

Preferably, the ohmic electrode layer is formed by depositing at least one of Pd, Rh, Ta, Ni, Cr, Au, Ti, wherein the first and second eutectic metal layers are Ti, Al, It is formed by depositing at least one of Rd, Pt, Ta, Ni, Cr, Au, Ag.

Also preferably, the first and second eutectic metal layers are bonded for 1 minute to 40 minutes at a pressure of 1 to 6 MP at a temperature of 200 to 500 degrees Celsius, and the bonding step (f) is performed by Ar, He It is preferable to proceed in the gas atmosphere of any one of Kr, Xe, and Rn.

Also preferably, the etching of the sapphire base substrate in step g is sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ) and aloe etch (4H ₃ PO ₄ + 4CH ₃ COOH + HNO ₃ + H ₂ O It may be performed by a wet etching method using an etching solution containing at least one of. Also preferably, in step g, at least part of the nitride based semiconductor layer may be etched and simultaneously formed cleavage lines for separating the base substrate into individual chips through etching.

In another aspect, the present invention, the sapphire base substrate including a first via hole formed to penetrate up and down; A plurality of nitride based semiconductor layers formed on the base substrate; A first electrode formed on the exposed surface of the nitride based semiconductor layer exposed through the first via hole of the sapphire base substrate; An ohmic electrode layer formed on the nitride based semiconductor layer; A first oxide layer formed on the ohmic electrode layer and including a second via hole formed to expose a portion of the ohmic electrode layer; A first eutectic metal layer formed on the first oxide layer to be connected to the ohmic electrode layer through the second via hole; And a receptacle substrate having a second electrode formed on one surface thereof, and a second eutectic metal layer formed on the other surface thereof to be bonded to the first eutectic metal layer.

Preferably, a second oxide layer is formed on a portion of the nitride semiconductor layer opposite to the contact surface of the sapphire base substrate, and the ohmic electrode layer is formed on the nitride semiconductor layer and the second oxide layer. In this case, the second oxide layer may be formed on the same vertical line as the first via hole formed on the sapphire base substrate, and the second via hole may be formed on the same vertical line as the second oxide layer and the first via hole. More preferably.

Also preferably, a buffer layer is formed between the sapphire base substrate and the nitride semiconductor layer, and the first via hole is formed over the sapphire base substrate and the buffer layer. The transparent electrode layer may be formed over the sapphire base substrate and the first via hole, and the first electrode may be formed on the transparent electrode layer. At this time, the transparent electrode is more preferably formed of at least one of ITO, ZnB, ZnO, InO, SnO.

In addition, the nitride-based semiconductor layer is composed of In _x (Al _y Ga _1-y ) N nitride-based semiconductor, x and y has a value of 1≥x≥0, 1≥y≥0, x + y> 0 It is preferable. In this case, the ohmic electrode includes at least one of Pd, Rh, Ta, Ni, Cr, Au, Ti, and the first and second eutectic metals include Ti, Al, Rd, Pt, Ta, Ni, Cr, It is preferable to contain at least one of Au and Ag.

Preferably, the receptor substrate includes at least one of conductive semiconductor substrates such as Si, GaAs, InP, InAs, conductive conductive films such as ITO, ZrB, ZnO, CuW, Mo, Au, Al, Cu, and the like. And, the receptor substrate is characterized in that using a p-type silicon substrate. In this case, the second eutectic metal may be at least one of Ti, Au, Ni, and Pt. Also preferably, the first electrode includes at least one of Al, Pt, Ta, Ni, Cr, Au, Ti. Also preferably, a cleavage line may be additionally formed on the sapphire base substrate to separate the base substrate by individual chips through etching.

Hereinafter, a vertical light emitting diode according to the present invention and a manufacturing method thereof will be described in detail.

Formation of Nitride Semiconductor Layer

In _x (Ga _y Al _1-y ) N nitride semiconductor layer is grown on metal sapphire base substrate (Sapphire, Al ₂ O ₃ ) of about 430um thickness using metal organic chemical vapor deposition (MOCVD). . The composition ratio of the nitride semiconductor is 1≥x≥0, 1≥y≥0, and x + y> 0. The nitride-based semiconductor layer may include metal organic chemical vapor deposition, liquid phase epitaxy, hydrogen vapor phase epitaxy, molecular beam epitaxy, and MOVPE. It is also possible to grow with (metal organic vapor phase epitaxy).

The growing nitride semiconductor layer may be grown in a single layer or in multiple layers according to the type of device to be manufactured, and any one or a plurality of elements of Si and Mg groups may be added as impurities to have a conductive property. Si may be added to form an n-type nitride semiconductor layer, and Mg may be added to form a p-type nitride semiconductor layer. The doping concentration depends on the type of device to be manufactured and may be doped at about 10 ¹⁵ / cm ³ to 10 ²¹ / cm ³ .

Therefore, depending on the doping concentration, the nitride semiconductor is classified into a high resistor or a conductive material. In the case of a high resistor, the contact resistance is preferably 10 ³ Ωcm ² or more, and in the case of conductive, 10 ^-1 Ωcm ² or less.

Buffer layer + undoped In _x (Al _y Ga _1-y ) N (12), n-type conductive contact layer (13), n-type cladding on sapphire substrate (11) to fabricate vertical electrode type light emitting diode In _x (Al _y Ga _1-y ) N nitride semiconductor layers of the layer 14, the light emitting layer 15, the p-type cladding layer 16, and the p-type conductive contact layer 17 were grown. That is, each layer 12, 13, 14, 15, 16, 17 can be formed of AlGaN, INGaN, AlGaInN or the like. In particular, the light-emitting layer _{(15) In x (Al y} Ga 1-y) N in the barrier layer and the _{In x (Al y Ga 1-} y) may have a single quantum well structure or a multiple quantum well structure comprising a well layer of N By controlling the composition ratio of In, Ga, and Al, it is possible to freely fabricate from a long wavelength having an InN (˜2.2 eV) band gap to a short wavelength light emitting diode having an AlN (˜6.4 eV) band gap.

Although not illustrated in the drawings, a light emitting diode including a buffer layer may be grown after forming a fine cluster of any one of SiO ₂ and SiN groups having a thickness of about 10 μs or a combination thereof on a sapphire base substrate. The SiN or SiO ₂ microstructure minimizes the stress between the sapphire base substrate and the nitride semiconductor layer, thereby improving the nitride semiconductor film quality and may be used as a stop layer for wet etching when removing the sapphire substrate using wet etching. The wafer coverage of the SiN or SiO ₂ microstructure covering the sapphire base substrate should be 90% or less. This is because when the SiN or SiO ₂ microstructure covers the entire sapphire substrate, the nitride semiconductor is not exposed because the sapphire on which the nitride is to be grown is not exposed, and the nitride semiconductor is not grown on the SiN or SiO _2. to be.

Hereinafter, exemplary embodiments of a light emitting diode having a vertical electrode structure according to the present invention will be described in detail with reference to the accompanying drawings.

Example 1

2 is a cross-sectional view and a plan view of a light emitting diode having a vertical electrode structure according to a first embodiment of the present invention. As shown in FIG. 2, characteristics of the light emitting diode manufactured in the first embodiment are as follows.

In the first embodiment, the vertical electrode diode comprises a receptor substrate 23 on which the second electrode 26 is formed, a second eutectic metal 22 formed on the receptor substrate 23, and a first oxide film layer. The first and second eutectic metals 21, 21 and 22 are formed by thermocompression bonding. The ohmic electrode 19 is connected to the ohmic electrode 19 through the second via hole 27 of the first oxide film 20, and the second ohmic contact layer 17, the second cladding layer 16, and the emission layer are disposed on the ohmic electrode 19. 15, a first cladding layer 14, a first ohmic contact layer 13, a buffer layer 12, and a first electrode 25 are present, and the first electrode 25 is a sapphire substrate 11. And the buffer layer 12 is electrically connected to the first ohmic contact layer 13 through the first via hole formed by etching.

Here, the first electrode 25 covers a part of the inner surface of the first via hole of the sapphire base substrate, is in contact with the first ohmic contact layer 13 through the first via hole, and the first via hole. (via hole) 24 is formed to fill a certain depth.

The first ohmic contact layer may be n-type, and the second ohmic contact layer may be p-type. The first ohmic electrode is covered with the passivation layer 20, and the second via hole 27 for electrically connecting the ohmic electrode 19 and the first eutectic metal 21 exists on the passivation layer 18, and sapphire is etched. The first via hole 24 thus formed is preferably present on the cross line with the second via hole 27.

On the sapphire substrate 11, the buffer layer 12 and the n-type and p-type conductive contact layers 13 and 17, the n-type and p-type cladding layers 14 and 16, and the light emitting layer 15 are In _x (Al _y Ga). _1-y ) N nitride semiconductor, and x and y have values of 1 ≧ x ≧ 0, 1 ≧ y ≧ 0, and x + y> 0. The n-type conductive contact layer 13 is doped with a Si impurity of 10 ¹⁸ or more to have a contact resistance of 1x10 ^-2 Ωcm ² or less, and the p-type contact layer 17 is doped with a Mg impurity of 10 ¹⁹ or more. It was made to have a contact resistance of 1x10 <^{-2> (} ohm) cm <^2> or less.

The total thickness of the nitride-based semiconductor thin film preferably has a thickness of 1 μm to 20 μm in order to minimize the cracking of the nitride semiconductor due to stress when removing the sapphire substrate, and to improve the current diffusion and etching selectivity, 13), the thickness of 2 μm or more and the p-type contact layer 17 is preferably 0.2 μm or more.

After that, the ohmic metal 19 is deposited and heat treated. In order to obtain a conductive material having low contact resistance and excellent light reflectivity, the ohmic metal 19 is formed by depositing any one of Pd, Rh, Pt, Ta, Ni, Cr, Au, Ti or an alloy of these metals to improve external quantum efficiency. Can be increased. Heat treatment was performed for 2 minutes at a temperature of 450 ° C to 700 ° C under an oxygen or nitrogen atmosphere.

After the heat treatment, the first oxide film 20 is deposited by plasma enhanced chemical vapor deposition (PECVD) and photo-etched to form a second via hole 27. The second via hole serves to electrically connect the first eutectic metal and the ohmic electrode, and the first oxide film 20 is formed of the nitride semiconductor layers 12, 13, 14, 15, 16, and 17 when etching the sapphire substrate. Used as a shield.

Subsequently, the first eutectic metal 21 is deposited on the semiconductor substrate and the second eutectic metal 22 is deposited on the receptor substrate 23. The first and second eutectic metals 21 and 22 may be any one of Ti, Al, Rd, Pt, Ta, Ni, Cr, Au, Ag, or an alloy of these metals in order to obtain excellent adhesion between the oxide film and the receptor substrate. And the like, by vapor deposition and heat treatment at a temperature between 300 ° C. and 700 ° C. in a furnace containing nitrogen. Preferably the heat treatment at a temperature of 400 ℃ to 600 ℃.

Since the operating voltage of the light emitting diode is greatly influenced by the contact resistance between the metal and the semiconductor layer, the second eutectic metal 22 is in ohmic contact with the receptor substrate 23 so as to obtain a low contact resistance.

The second eutectic metal 22 depends on the type of receptor substrate, and when the p-type silicon substrate 23 is used as a receptor substrate, it is a combination of any one or more of Ti, Au, Ni, and Pt, and is heat treated to form a silicon substrate. It improved the adhesiveness with.

Thereafter, the first and second eutectic metals were thermocompression-bonded to each other.

The receptor substrate serves as a passage for the support and the current flow, so that the conductive semiconductor substrates such as Si, GaAs, InP, and InAs, conductive conductive films such as indium tin oxide (ITO), ZrB, and ZnO, CuW, Mo, It is formed by including any one or more of metals such as Au, Al, Cu, and about 1MP at a temperature of 200 ℃ to 500 ℃ in a combination of any one or more of In, Pd, Sn, Au, Pt, Ti, Ge It is preferable to bond for 1 to 40 minutes at a pressure of 6 MP (Mega pascal).

In order to prevent the first and second eutectic metals 21 and 22 from being oxidized in the thermocompression bonding process, the contact resistance between the semiconductor thin film and the metal is increased in a gas atmosphere such as Ar, He, Kr, Xe, and Rn. To lower it.

Subsequently, the sapphire substrate 11 was wrapped and polished. At this time, the thickness of the sapphire substrate 11 is preferably as thin as possible in order to minimize the etching process time, but if too thin, the sapphire substrate 11 is wheel-worn or difficult to handle, preferably 10 μm to 200 μm. . In addition, since the roughness of the surface of the sapphire substrate 11 is transferred to the nitride semiconductor layers 12, 13, 14, 15, 16, and 17 as it is, the nitride semiconductor structure may be damaged. Roughness was made to be 20 micrometers or less.

The lapping of the sapphire substrate 11 is performed by chemical mechanical polishing (CMP), ICP / RIE dry etching, mechanical polishing using alumina (Al ₂ O ₃ ) powder or hydrochloric acid (HCl), nitric acid (HNO ₃ ), potassium hydroxide (KOH). ), Sodium hydroxide (NaOH), sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), chromium oxide (CrO ₃ ), potassium hydroxide (KOH), potassium hydrogen sulphate (KHSO ₄ ) and aloe etch (4H ₃ PO ₄ + 4CH ₃ COH + HNO ₃ + H ₂ O) proceeds by wet etching using a mixed solution of at least one or a combination thereof as an etchant. At this time, any one of BCL ₃ , Cl ₂ , HBr, Ar, or a mixed gas thereof is used as an etching gas of ICP / RIE or RIE.

Thereafter, the sapphire substrate was etched to expose the buffer layer 12 to secure a contact area of the first ohmic contact layer. The wet etching of the sapphire substrate 11 for exposing the buffer layer 12 is performed in the following manner. The etching rate of the sapphire substrate 11 by the etching solution mixed with sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) at a temperature of 200 ° C. to 400 ° C. was measured to add 5 μm to the thickness of the sapphire substrate 11. Immerse in the etching solution for enough time to etch the thickness.

When the etching solution used herein, the etching rate of the GaN nitride semiconductor was 1/10 or less than that of the sapphire substrate 11. That is, the etching selectivity of the nitride based semiconductor layers 12, 13, 14, 15, 16, and 17 with respect to the sapphire base substrate 11 is 10 or more. Therefore, even though the etching process is performed for a time remaining after the sapphire base substrate 11 is completely etched, the etching speed of the nitride semiconductor layers 12, 13, 14, 15, 16, and 17 is slow, so that the nitride semiconductor layers 12, 13, 14, 15, 16, 17) are less likely to be damaged.

On the other hand, it is preferable to maintain the temperature of the etching solution at 100 ℃ or more in order to shorten the etching time. The heating for maintaining the temperature of the etching solution above 100 ℃ may be a direct heating method to put the solution on the heater or directly contact the heater and the indirect heating method using light absorption.

An ICP / RIE technique may be used for etching the sapphire base substrate 11 for forming the first electrode 25. In order to quickly etch the sapphire substrate 11, it is desirable to increase the ICP and RIE power as much as possible, but care must be taken because it may damage the epi layer.

3 is a graph showing the etching rate when wet etching sapphire and GaN with a mixture solution of sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ). As shown in FIG. 3, sulfuric acid and phosphoric acid The sapphire etching rate for the nitride-based semiconductor of the mixed solution depends on the mixing ratio of sulfuric acid and phosphoric acid, and is rapidly etched as sulfuric acid increases. The etching rate of GaN nitride semiconductor also depends on the mixing ratio of sulfuric acid, and it can be seen that the etching selectivity with sapphire becomes more than 20 at a specific temperature.

These results indicate that the nitride semiconductor layers 12 and 13 can be effectively used as an etch stop layer of the sapphire substrate 11, and as shown in FIG. 4, an etching selectivity of 20 or more can be obtained at a high temperature of 100 ° C. there was.

5 is a photograph of the surface of the sapphire substrate after forming a specific pattern on the sapphire substrate by the wet etching method and etching the sapphire substrate by the wet etching method. Referring to FIG. The sapphire substrate 11 was etched at 2325 um for 20 minutes at 325 ° C., showing an etching rate of 1.1 um / min. This etching rate is remarkable, and considering the mass production is not a problem at all, wet etching is not limited by the productivity of the equipment can be said to have many advantages over any method in terms of mass production.

The sapphire substrate 11 etching technology may be used to form a dicing line or cleve, brake line of the device at the same time as the via hole is formed. When the sapphire substrate was etched with a mixture of sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) for a pattern having various line widths, the etched depth was different according to the open pattern width. The wider the pattern, the deeper the pattern and the narrower the line width.

In other words, in wet etching, the sapphire substrate is oriented in wet etching and the etching depth depends on the patterned line width. The base substrate 11 of sapphire mainly used is the C plane of (0001), and when the wet etching is performed, the angle of the etching surface forms an inclined surface of 54 ° or 25 ° depending on the M plane, the R plane, and the A plane. . This phenomenon is due to the difference in etching speed between C surface of (0001), M surface of (10-10), R surface of (-1012) and A-etched facet surface of (11-20). Because. In other words, the surface orientation dependence of sapphire etching speed is the order of C plane> R plane> M plane> A plane.In conclusion, the etching depth is determined by the open line width. This means that you can control the depth of etching by yourself.

As shown in FIG. 6, when the surface was etched under a microscope, the surface morphology was very clean and no large thickness deviation could be observed. Etching the (0001) side of the sapphire substrate to a certain depth gave the etched cross section a V-grooved shape, making it cleaner than any diamond pen made a cleavage line. The dicing line should be 20μm wide enough and the etch stops at a certain depth during the via hole etching to automatically form a scribing line, so it is possible to form a dicing line to separate into individual chips after forming vias. Can be.

By combining a wet or dry method with one or more methods, dicing lines can be formed at the place where the device is to be separated, and the device can be easily separated, and a clean mirror surface can be made.

When the sapphire wet etching technology is applied to mass production, another important factor is to secure process conditions for increasing the etching selectivity between the sapphire substrate 11 and the nitride semiconductor layers 12 and 13, and in particular, the nitride semiconductor layer ( 12, 13) is effective as a sapphire etch stop layer. As the nitride semiconductor layers 12 and 13, an In _x (Ga _y Al _1-y ) N (1≥x≥0, 1≥y≥0, x + y> 0) series may be used, and preferably Al It is effective to increase the composition ratio of or to use p-type GaN doped with Mg, and if necessary, before forming the nitride semiconductor layer 12 on the sapphire substrate 11, a protective film such as SiO ₂ or SiNx is locally applied. It may be formed separately to form an etch stop layer. In particular, SiO ₂ has a high wet etching selectivity to sapphire.

6 is a photograph of the surface of the nitride semiconductor layer 12 after the sapphire substrate is removed by a wet etching method. As can be seen in FIG. 6, even after the sapphire substrate 11 was removed, almost no crack or damage of the thin film due to stress was found, and the surface of the nitride semiconductor layer 12 was also very clean.

Thereafter, the buffer layer 12 is dry etched using RIE to expose the first ohmic contact layer 13, and the first electrode 25 is formed to be heat-treated. In order to obtain low contact resistance, the first electrode 25 is heat-treated by depositing any one of Al, Pt, Ta, Ni, Cr, Au, Ti, or an alloy of these metals. The heat treatment was performed for 2 minutes at a nitrogen atmosphere of 300 ℃ to 600 ℃ temperature.

Thereafter, the receptor substrate 23 was polished and mirror-polished on CMP or back. The receptor substrate is preferably thinned to 50 μm to 100 μm for dicing (substrate cutting or cleavage). When forming the via holes for dicing the substrate, SiO ₂ was patterned to remove sapphire in the portion to be diced. This is a common dicing equipment that uses a diamond blade (blade), cutting the sapphire substrate is rather cumbersome and productivity is reduced. In order to solve this problem, the dicing line 31 was formed at the same time when the via hole was formed, and the device can be separated through the cleavage process without using the dicing equipment as well as the advantage of reducing the process time and the process cost. Therefore, manufacturing cost is reduced.

Example 2

7 is a view showing a light emitting diode having a vertical electrode structure and a manufacturing process thereof according to a second embodiment of the present invention. A vertical light emitting diode manufactured by the method according to the present embodiment has the following structure. .

The vertical electrode type diode includes a receptor substrate 23 having a second electrode 26 formed thereon, a second eutectic metal 22 formed on the opposite side of the second electrode 22 of the receptor substrate 23, and a first eutectic metal. And the second eutectic metal are bonded to each other by thermal compression, and the first eutectic metal is connected to the ohmic electrode 19 through the second via hole 27 of the first oxide film 20, and the ohmic electrode 19. On the second oxide film 18, the second ohmic contact layer 17, the second cladding layer 16, the light emitting layer 15, the first cladding layer 14, the first ohmic contact layer 13, the buffer layer 12 and a first electrode 25 are present, and the first electrode 25 has a first ohmic contact layer 13 through a first via hole formed by etching the sapphire substrate 11 and the buffer layer 12. It is inter-connected with.

Here, the first electrode 25 covers a part of the inner surface of the first via hole, penetrates the first via hole, and contacts the first ohmic contact layer 13, and controls the via hole. It is formed to fill up to a certain depth. At this time, it is preferable that the via hole has a form in which the width becomes narrower toward the bottom. In addition, the horizontal cross-sectional shape of the via hole may be variously modified, such as a circle or a square, and the number of via holes may be formed as well as a plurality of via holes. In this structure, light is generated in the light emitting layer 15 and emitted to the outside through the sapphire substrate 11.

The first ohmic contact layer may be n-type, and the second ohmic contact layer may be p-type. The ohmic electrode formed on the second oxide film 18 is covered with the first oxide film 20, and the second via hole 27 for electrically connecting the ohmic electrode 19 and the first eutectic metal 21 is formed as a second electrode. The first via hole 24, which is alternate with the oxide film 18 and formed by sapphire etching, is present on the same line as the second oxide film 18.

7 is a diagram illustrating an intermediate manufacturing process of a light emitting diode having a vertical electrode structure according to a second embodiment of the present invention. As shown in FIG. 7A, after the growth of the nitride based semiconductor layers 12, 13, 14, 15, 16, and 17 on the sapphire substrate 11 is completed, an SiO ₂ oxide layer on the second ohmic contact layer 17 ( 18) is deposited by about 1 μm, and then patterned by photolithography to expose a portion of the sapphire substrate, and the second oxide layer 18 is etched with a buffer oxide etchant (BOE) to leave only a portion of the second oxide layer 18.

The second oxide film 18 is used as a protective film of the nitride semiconductors 12, 13, 14, 15, 16, and 17 when etching the sapphire substrate 11. Only part of the second oxide film 18 is left to protect the semiconductor thin film during the wet process. That is, the oxide film 18 of SOG (spin on glass) or SiO ₂ is used as a protective film of the nitride semiconductors 12, 13, 14, 15, 16, and 17 when wet etching the sapphire substrate 11. That is, if the nitride semiconductor is protected by only the eutectic metal without the second oxide film 18, a micro pipe is formed due to the metal crust formed during the metal deposition, thereby providing a passage through which the etching solution flows. By penetrating into the p-type conductive semiconductor contact layer to etch the semiconductor thin film, the nitride-based semiconductor light emitting device cannot be stably fabricated by wet etching.

In order to solve this problem, when an oxide film of SiO ₂ is formed opposite the portion where the via hole is to be formed, hydrochloric acid (HCl), nitric acid (HNO ₃ ), potassium hydroxide (KOH), and sodium hydroxide are formed through a micro pipe of eutectic metal. (NaOH), sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), chromium oxide (CrO ₃ ), potassium hydroxide (KOH), potassium hydrogen sulphate (KHSO ₄ ) and aluene (4H ₃ PO ₄ + Since the mixed etching solution of at least one of 4CH ₃ COOH + HNO ₃ + H ₂ O) or a combination thereof penetrates into the eutectic metal, an oxide film of SiO ₂ resistant to the etching solution covers the semiconductor thin film. During etching, damage to the semiconductor thin film can be avoided.

That is, the oxide film of SiO ₂ is hydrochloric acid (HCl), nitric acid (HNO ₃ ), potassium hydroxide (KOH), sodium hydroxide (NaOH), sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), To at least one or a combination of chromium oxide (CrO ₃ ), potassium hydroxide (KOH), potassium hydrogen sulfate (KHSO ₄ ) and aloe etch (4H ₃ PO ₄ + 4CH ₃ COOH + HNO ₃ + H ₂ O) Is hardly etched into the mixed solution, and has a very strong adhesion to the nitride semiconductor. The oxide film of SiO ₂ is preferably deposited on the semiconductor thin film by PECVD, low pressure chemical vapor deposition (LPCVD), thermal CVD, and more preferably, a high quality oxide film having almost no pin holes is obtained. Oxide film of high quality SiO ₂ without pinhole is hardly etched in the etching solution and protects the semiconductor thin film because the etching solution coming in through the pinhole of the eutectic metal does not come into contact with the semiconductor thin film.

In particular, when sapphire is etched and the nitride semiconductor thin film is exposed to an etchant, crystal defects formed during semiconductor crystal growth, in particular, penetrating crystal defects are hydrochloric acid (HCl), nitric acid (HNO ₃ ), potassium hydroxide (KOH), and sodium hydroxide (NaOH). , Sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), chromium oxide (CrO ₃ ), potassium hydroxide (KOH), potassium hydrogen sulfate (KHSO ₄ ) and aloe etch (4H ₃ PO ₄ + 4CH ₃ COOH It is weak to the mixed solution containing at least one of + HNO ₃ + H ₂ O) and can damage the entire surface of the semiconductor thin film. By forming an oxide film on the opposite side of the via hole, the process can be more stably achieved by blocking the contact of the etching solution. There is an advantage.

In this case, the via hole is preferably formed on the opposite oxide film and exposes a semiconductor thin film of a smaller size than the oxide film. In addition, since the interconnection portion 27 is formed of only the ohmic electrode and the eutectic metal, the interconducting portion 27 is formed to be narrow as long as there is no problem in electrical conduction. The ohmic metal and the eutectic metal themselves are hydrochloric acid (HCl), nitric acid (HNO ₃ ), Potassium hydroxide (KOH), sodium hydroxide (NaOH), sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), chromium oxide (CrO ₃ ), potassium hydroxide (KOH), potassium hydrogen sulfate (KHSO ₄ ) and alu It is preferable to have a structure including any one of Pt and Au which are not damaged by an etching solution containing at least one of etch (4H ₃ PO ₄ + 4CH ₃ COOH + HNO ₃ + H ₂ O).

That is, when the nitride semiconductor is protected by only the eutectic metal without the second oxide film 18, a micro pipe is formed due to the metal crust formed during the metal deposition, and the micro pipe provides a passage through which the etching solution can flow. The etching solution penetrates into the nitride semiconductor layer, thereby damaging the ohmic metal 19 and the second ohmic contact layer 17.

On the sapphire substrate 11, the buffer layer 12 and the n-type and p-type conductive contact layers 13 and 17, the n-type and p-type cladding layers 14 and 16, and the light emitting layer 15 are In _x (Al _y Ga). _1-y ) N nitride semiconductor and x and y have values of 1≥x≥0, 1≥y≥0, and x + y> 0. The n-type conductive contact layer 13 is doped with a Si impurity of 10 ¹⁸ or more to have a contact resistance of 1x10 ^-2 Ωcm ² or less, and the p-type conductive contact layer 17 has a concentration of Mg impurity of 10 ¹⁹ or more. Doped so as to have a contact resistance of 1x10 ^-2 Ωcm ² or less.

The total thickness of the nitride-based semiconductor thin film preferably has a thickness of 1 μm to 20 μm in order to minimize the cracking of the nitride semiconductor due to stress upon removal of the sapphire substrate, and the n-type ohmic contact layer 13 to improve current diffusion and etching selectivity. It is preferable that the thickness of the p-type contact layer 17 be 2 micrometers or more and 0.2 micrometers or more thick.

Thereafter, as shown in FIG. 7B, the ohmic electrode 19 is deposited and heat treated. In order to obtain a conductive material having excellent low contact resistance and light reflectivity, the ohmic electrode 19 increases the external quantum efficiency by depositing any one of Pd, Rh, Pt, Ta, Ni, Cr, Au, Ti, or an alloy of these metals. You can. The heat treatment was carried out for 2 minutes at a temperature of 450 ℃ to 700 ℃ under oxygen or nitrogen atmosphere.

After the heat treatment, the first oxide film 20 is deposited by plasma enhanced chemical vapor deposition (PECVD) and photo-etched to form a second via hole (FIG. 7C). The via hole serves to electrically connect the first eutectic metal and the ohmic electrode, and the first oxide film 20 is formed of the nitride semiconductor layers 12, 13, 14, 15, 16, and 17 when etching the sapphire substrate. Used as a shield.

Subsequently, a first eutectic metal 21 is deposited on the first oxide film layer 20, and a second eutectic metal 22 is deposited on the receptor substrate 23 (Fig. 7 (d)). The first and second eutectic metals 21 and 22 were obtained by depositing at least one of Ti, Al, Rd, Pt, Ta, Ni, Cr, Au, Ag in order to obtain excellent adhesion between the oxide film and the receptor substrate. The furnace was heat-treated at a temperature between 300 ° C. and 700 ° C. in a furnace containing nitrogen. Preferably the heat treatment at a temperature of 400 ℃ to 600 ℃.

Since the operating voltage of the light emitting diode is greatly influenced by the contact resistance between the metal and the semiconductor layer, the second eutectic metal 22 is in ohmic contact with the receptor substrate 23 so as to obtain a low contact resistance. The second eutectic metal 22 depends on the type of the receptor substrate. When the p-type silicon substrate 23 is used as the receptor substrate, at least one of Ti, Au, Ni, and Pt is heat-treated to form a silicon substrate. Adhesion was improved. Thereafter, as shown in FIG. 7 (e), the first and second eutectic metals were thermocompression-bonded to each other.

The receptor substrate serves as a passage for the support and the current flow, so that the conductive semiconductor substrates such as Si, GaAs, InP, and InAs, conductive conductive films such as indium tin oxide (ITO), ZrB, and ZnO, CuW, Mo, At least one of metals such as Au, Al, Cu, and the like, and at a temperature of about 200 ° C. to 500 ° C. with at least one combination of In, Pd, Sn, Au, Pt, Ti, and Ge when the substrate is bonded. It is preferable to bond for 1 to 40 minutes at a pressure of 1MP to 6MP (Mega pascal).

In order to prevent the first and second eutectic metals 21 and 22 from being oxidized in the thermocompression bonding process, the contact resistance between the semiconductor thin film and the metal may be formed in a gas atmosphere such as Ar, He, Kr, Xe, and Rn. To lower it.

Subsequently, as shown in FIG. 7E, the sapphire substrate 11 was wrapped and polished, and a SiO ₂ etching mask was deposited about 1 μm. At this time, the thickness of the sapphire substrate 11 is preferably as thin as possible in order to minimize the etching process time, but if too thin, the sapphire substrate 11 is wheel-worn or difficult to handle, preferably 10 μm to 200 μm. .

In addition, since the roughness of the surface of the sapphire substrate 11 is transferred to the nitride semiconductor layers 12, 13, 14, 15, 16, and 17 as it is, the nitride semiconductor structure may be damaged. Roughness was made to be 20 micrometers or less. The lapping of the sapphire substrate 11 is performed by chemical mechanical polishing (CMP), ICP / RIE dry etching, mechanical polishing using alumina (Al ₂ O ₃ ) powder or hydrochloric acid (HCl), nitric acid (HNO ₃ ), potassium hydroxide ( KOH), sodium hydroxide (NaOH), sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), chromium oxide (CrO ₃ ), potassium hydroxide (KOH), potassium hydrogen sulfate (KHSO ₄ ) and aloe It proceeds by wet etching with an etchant containing at least one of 4H ₃ PO ₄ + 4CH ₃ COOH + HNO ₃ + H ₂ O). In this case, at least one of BCL ₃ , Cl ₂ , HBr, and Ar may be used as an etching gas of ICP / RIE or RIE.

Thereafter, the sapphire substrate was etched to expose the buffer layer 12 to secure the first electrode contact area (Fig. 7 (h)). The wet etching of the sapphire substrate 11 for exposing the buffer layer 12 is performed in the following manner. The etching rate of the sapphire substrate 11 by the etching solution mixed with sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) at a temperature of 200 ° C. to 400 ° C. was measured, and the thickness of the sapphire substrate 11 was about 5 μm. Immerse the etch solution for the time to etch the thickness plus thickness. When the etching solution used herein, the etching rate of the GaN nitride semiconductor was 1/10 or less than that of the sapphire substrate 11. That is, the etching selectivity of the nitride based semiconductor layers 12, 13, 14, 15, 16, and 17 with respect to the sapphire base substrate 11 is 10 or more. Therefore, even though the etching process is performed for a time remaining after the sapphire base substrate 11 is completely etched, the etching rate of the nitride semiconductor layers 12, 13, 14, 15, 16, and 17 is slow, so that the nitride semiconductor layers 12, 13, and 14 , 15, 16, 17) are less likely to be damaged.

On the other hand, it is preferable to maintain the temperature of the etching solution at 100 ℃ or more in order to shorten the etching time. The heating for maintaining the temperature of the etching solution above 100 ℃ may be a direct heating method to put the solution on the heater or directly contact the heater and the indirect heating method using light absorption.

ICP / RIE technology may be used for etching the sapphire base substrate 11 for forming the first electrode 25. In order to quickly etch the sapphire substrate 11, it is desirable to increase the ICP and RIE power as much as possible, but care must be taken because it may damage the epi layer.

The sapphire substrate 11 etching technology may be used to form a dicing line or cleve, brake line of the device at the same time as the via hole is formed. When the sapphire substrate was etched with a mixture of sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) for a pattern having various line widths, the etched depth was different depending on the open pattern width. The wider the pattern, the deeper the pattern and the narrower the line width. In other words, in wet etching, the sapphire substrate is oriented in wet etching and the etching depth depends on the patterned line width. The base substrate 11 of sapphire mainly used is the C plane of (0001), and when the wet etching is performed, the angle of the etching surface forms an inclined surface of 54 ° or 25 ° depending on the M plane, the R plane, and the A plane. . This phenomenon is due to the difference in etching speed between C surface of (0001), M surface of (10-10), R surface of (-1012) and A-etched facet surface of (11-20). Because. In other words, the surface orientation dependence of sapphire etching speed was found to be C plane> R plane> M plane> A plane, and as a result, the etch depth is determined by the open line width. This means that you can control the depth of etching by yourself.

As shown in FIG. 6, when the surface was etched under a microscope, the surface morphology was very clean and no large thickness deviation could be observed. Etching the (0001) side of the sapphire substrate to a certain depth gave the etched cross section a V-grooved shape, making it cleaner than any diamond pen made a cleavage line. The dicing line should be 20μm wide enough and the etch stops at a certain depth during the via hole etching to automatically form a scribing line, so it is possible to form a dicing line to separate into individual chips after forming vias. Can be.

As shown in Fig. 7 (h), by dividing the element into a place where the element is to be separated by a method combining one or more of a wet or dry method, the element can be easily separated, and the cut surface You can make a clean mirror. When the sapphire wet etching technology is applied to mass production, another important factor is to secure process conditions for increasing the etching selectivity between the sapphire substrate 11 and the nitride semiconductor layers 12 and 13, and in particular, the nitride semiconductor layer ( 12, 13) is effective as a sapphire etch stop layer. As the nitride semiconductor layers 12 and 13, an In _x (Ga _y Al _1-y ) N (1≥x≥0, 1≥y≥0, x + y> 0) series may be used, and preferably Al It is effective to increase the composition ratio of or to use p-type GaN doped with Mg, and if necessary, before forming the nitride semiconductor layer 12 on the sapphire substrate 11, a protective film such as SiO ₂ or SiNx. By forming a etch stop layer may be formed separately. In particular, SiO ₂ has a sapphire and a high wet etching selectivity.

Subsequently, as shown in FIG. 7 (j), the buffer layer 12 is dry etched using RIE to expose the first ohmic contact layer 13, and the first electrode 25 is formed to be heat treated. In order to obtain low contact resistance, the first electrode 25 is heat-treated by depositing any one of Al, Pt, Ta, Ni, Cr, Au, Ti, or an alloy of these metals. The heat treatment was performed at 300 ° C. to 600 ° C. for 2 minutes under nitrogen atmosphere.

Thereafter, the receptor substrate 23 was polished and mirror-polished on CMP or back. For dicing (substrate cutting or cleavage) it is desirable to thin as 50 μm to 100 μm.

As shown in FIGS. 7 (h) to 7 (i), when forming a via hole for dicing a substrate, SiO ₂ was patterned to remove sapphire of a portion to be diced. The dicing equipment is generally used diamond blades, cutting the sapphire substrate is rather cumbersome and productivity is reduced. In order to solve this problem, the dicing line 31 was formed at the same time when the via hole was formed. This not only reduces the processing time and the processing cost but also the cleavage process without dicing equipment. This reduces the manufacturing cost.

Example 3

8 is a cross-sectional view and a plan view of a light emitting diode having a vertical electrode structure according to a third embodiment of the present invention. As shown in FIG. 8, the manufacturing method of the vertical light emitting diode is similar to that of the second embodiment, but the position of the second via hole 27 for electrical connection between the ohmic electrode and the first eutectic metal is different.

That is, when the sapphire etching is etched, the second via hole 27 electrically connecting through the vias of the second oxide film 18 protecting the semiconductor substrate and the first oxide film 20 covering the second ohmic electrode is perpendicular to each other. The protective film 18 and the first via hole 24 also exist on a perpendicular line. This is because the ohmic electrode 19 does not effectively protect the nitride semiconductor layer in the sapphire etching solution, and the SiO ₂ oxide film is locally deposited only at the sapphire via hole formation position. SiO ₂ has an extremely high etching selectivity of 20 or more in the etching solution used in the present invention.

The characteristics of the light emitting diodes manufactured in the third embodiment are summarized as follows. The vertical electrode type diode includes a receptor substrate 23 on which a second electrode 26 is formed, a second eutectic metal 22 formed on the receptor substrate 23, a first eutectic metal and a second eutectic. The metal is bonded by thermocompression bonding, and the first eutectic metal is connected to the ohmic electrode 19 through the via 27 of the oxide film 20, and the oxide film 18 and the second ohmic electrode 19 are formed on the second ohmic electrode 19. 2 ohmic contact layer 17, second cladding layer 16, light emitting layer 15, first cladding layer 14, first ohmic contact layer 13, buffer layer 12 and first electrode 25 ) And the first electrode 25 is electrically connected to the first ohmic contact layer 13 through a via hole formed by etching the sapphire substrate 11 and the buffer layer 12. . Here, the first electrode 25 covers a part of the inner surface of the via hole, contacts the first ohmic contact layer 13 through the via hole, and fills the via hole to a predetermined depth. It is formed in the form.

At this time, it is preferable that the via hole has a form in which the width becomes narrower toward the bottom. The first ohmic contact layer may be n-type, and the second ohmic contact layer may be p-type. The ohmic electrode formed on the second oxide film 18 is covered with the protective film 20, and the via hole 27 for electrically connecting the ohmic electrode 19 and the first eutectic metal 21 is the second oxide film 18. The via hole 24 formed above and formed by etching sapphire is present on the same line as the second oxide film 18.

Example 4

9 is a cross-sectional view and a plan view of a light emitting diode having a vertical electrode structure according to a fourth embodiment of the present invention.

As shown in FIG. 9, the vertical electrode type diode includes a receptor substrate 23 having a second electrode 26 formed thereon, and a second eutectic metal 22 formed on the receptor substrate 23 formed thereon. ), The first eutectic metal and the second eutectic metal are bonded by thermal compression, and the first eutectic metal is connected to the ohmic electrode 19 through the vias 27 of the first oxide film 20. The second ohmic contact layer 17, the second cladding layer 16, the light emitting layer 15, the first cladding layer 14, the first ohmic contact layer 13, and the buffer layer 12 are disposed on the ohmic electrode 19. ), A transparent electrode 28 and a first electrode 25 are present, and the transparent electrode 28 has a first ohmic contact layer through a first via hole formed by etching the sapphire substrate 11 and the buffer layer 12. It is electrically connected to (13). Here, the transparent electrode 28 covers the inner surface of the first via hole and contacts the first ohmic contact layer 13 through the first via hole, and the first electrode 25 is a transparent electrode ( 28) is formed on.

In this case, it is preferable that the first via hole has a form in which the width thereof is narrowed slightly downward. In this structure, light is generated in the light emitting layer 15 and emitted to the outside through the sapphire substrate 11. The first ohmic contact layer may be n-type, and the second ohmic contact layer may be p-type. The ohmic electrode is covered with the first oxide film 20, and the second via hole 27 for electrically connecting the ohmic electrode 19 and the first eutectic metal 21 exists on the second oxide film 18, and sapphire The first via hole 24 formed by etching is preferably present on a line intersected with the second via hole 27.

The detailed manufacturing method of the fourth embodiment is as follows. The nitride semiconductor layers 12, 13, 14, 15, 16 and 17 were grown on the sapphire substrate 11. The buffer layer 12 on the sapphire substrate 11 and the n-type and p-type conductive contact layers 13 and 17, the n-type and p-type cladding layers 14 and 16, and the light emitting layer 15 are In _x (Al _y). Ga _1-y ) N nitride semiconductor, and x and y have values of 1≥x≥0 and 1≥y≥0. The n-type conductive contact layer 13 is doped with a Si impurity of 10 ¹⁸ or more to have a contact resistance of 1E-2Ωcm-2 or less, and the p-type contact layer 17 is doped with a Mg impurity of 10 ¹⁹ or more to 1E. The contact resistance was less than -2Ωcm-2.

The total thickness of the nitride-based semiconductor thin film preferably has a thickness of 1 μm to 20 μm in order to minimize cracking of the nitride semiconductor due to stress when removing the sapphire substrate, and the n-type ohmic contact layer 13 to improve the current diffusion and etching selectivity. It is preferable to make the thickness of 2 mu m or more and the thickness of the p-type contact layer 17 thicken 0.2 mu m or more.

After that, the ohmic electrode 19 is deposited and heat-treated to have a predetermined size by photo etching. In order to obtain a conductive material having low contact resistance and excellent light reflectivity, the ohmic electrode 19 may increase external quantum efficiency by depositing at least one of Pd, Rh, Pt, Ta, Ni, Cr, Au, and Ti. The heat treatment was carried out for 2 minutes at a temperature of 450 ℃ to 700 ℃ under oxygen or nitrogen atmosphere.

After the heat treatment, the first oxide film 20 is deposited by plasma enhanced chemical vapor deposition (PECVD) and photo-etched to form a second via hole 27. The second via hole 27 serves to electrically connect the first eutectic metal and the ohmic electrode, and the first oxide layer 20 may form the nitride semiconductor layer 12, 13, 14, 15, 16, when etching the sapphire substrate. 17) is used as a shield.

Subsequently, the first eutectic metal 21 is deposited on the semiconductor substrate, and the second eutectic metal 22 is deposited on the receptor substrate 23. The first and second pneumatic metals 21 and 22 may be any one of Ti, Al, Rd, Pt, Ta, Ni, Cr, Au, Ag, Sn or these metals in order to obtain excellent adhesion between the oxide film and the receptor substrate. It was obtained by depositing an alloy of and the like, and heat-treated at a temperature between 300 ℃ to 700 ℃ in a furnace (furnace) containing an atmosphere containing nitrogen.

Preferably the heat treatment at a temperature of about 400 ℃ to 600 ℃. The second eutectic metal 22 depends on the type of receptor substrate. When the p-type silicon substrate 23 is used as a receptor substrate, the second eutectic metal 22 is formed by a combination of any one or more of Ti, Au, Ni, and Pt, Adhesion was improved.

Thereafter, the first and second eutectic metals were thermocompression-bonded to each other. Since the receptor substrate serves as a passage for the support and the current flow, conductive semiconductor substrates such as Si, GaAs, InP, InAs, conductive conductive films such as ITO, ZrB, ZnO, CuW, Mo, Au, Al, At least one of metals such as Cu, and at least one combination of at least one of In, Pd, Sn, Au, Pt, Ti, and Ge at a temperature of 200 ° C. to 500 ° C. (Mega pascal) It is preferable to adhere | attach for 1 to 40 minutes at the pressure of).

This thermocompression process is performed in a gas atmosphere such as Ar, He, Kr, Xe, and Rn in order to prevent the first and second eutectic metals 21 and 22 from being oxidized, thereby improving the contact resistance between the semiconductor thin film and the metal. To lower it.

Subsequently, the sapphire substrate 11 was wrapped and polished. At this time, the thickness of the sapphire substrate 11 is preferably as thin as possible in order to minimize the etching process time, but if too thin, the sapphire substrate 11 is wheel-worn or difficult to handle, preferably about 10 μm to 200 μm. In addition, since the roughness of the surface of the sapphire substrate 11 is transferred to the nitride semiconductor layers 12, 13, 14, 15, 16, and 17 as it is, the nitride semiconductor structure may be damaged. Roughness was made to be 20 micrometers or less.

The lapping of the sapphire substrate 11 is performed by chemical mechanical polishing (CMP), ICP / RIE dry etching, mechanical polishing using alumina (Al ₂ O ₃ ) powder or hydrochloric acid (HCl), nitric acid (HNO ₃ ), potassium hydroxide (KOH). ), Sodium hydroxide (NaOH), sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), chromium oxide (CrO ₃ ), potassium hydroxide (KOH), potassium hydrogen sulphate (KHSO ₄ ) and aloe etch (4H ₃ PO ₄ + 4CH ₃ COH + HNO ₃ + H ₂ O) proceeds by wet etching using a mixed solution of at least one or a combination thereof as an etchant. At this time, any one of BCL ₃ , Cl ₂ , HBr, Ar, or a mixed gas thereof is used as an etching gas of ICP / RIE or RIE.

Thereafter, the sapphire substrate was etched to expose the buffer layer 12 to secure the first electrode contact area. The wet etching of the sapphire substrate 11 for exposing the buffer layer 12 is performed in the following manner. The etching rate of the sapphire substrate 11 by the etching solution mixed with sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) at a temperature of 200 ° C. to 400 ° C. was measured to measure about 5 μm from the thickness of the sapphire substrate 11. Immerse in the etching solution for an additional amount of time to etch.

An ICP / RIE technique may be used for etching the sapphire base substrate 11 for forming the first electrode 25. In order to quickly etch the sapphire substrate 11, it is desirable to increase the ICP and RIE power as much as possible, but care must be taken because it may damage the epi layer.

Thereafter, the buffer layer 12 is dry etched using RIE to expose the first ohmic contact layer 13, and the transparent electrode 28 is deposited to be heat-treated. In order to obtain a low contact resistance and a transparent electrode, any one of Ti, Pt, Ni, Cr, Au, and Al or an alloy of these metals is deposited and heat-treated. The heat treatment was performed for 2 minutes at a nitrogen atmosphere of 300 ℃ to 700 ℃ temperature.

In the case of forming the transparent electrode 28, transparent conductors such as ITO, ZrB, ZnO, InO, and SnO were formed as ohmic layers and heat-treated at a temperature of 300 ° C to 700 ° C in an atmosphere containing oxygen or nitrogen.

Thereafter, the receptor substrate 23 was polished and mirror-polished on CMP or back. Lapping was 50 μm to 100 μm thick for dicing (substrate cutting or cleavage). When forming the via hole for dicing the substrate, the dicing line 31 was simultaneously formed when the via hole was formed by patterning SiO ₂ to remove sapphire of the portion to be diced.

Example 5

10 is a cross-sectional view and a plan view of a light emitting diode having a vertical electrode structure according to a fifth embodiment of the present invention. As shown in FIG. 10, the characteristics of the light emitting diode are summarized as follows.

The vertical diode includes a receptor substrate 23 having a second electrode 26 formed thereon, a second eutectic metal 22 formed on the receptor substrate 23, a first eutectic metal and a second eutectic. The metal is adhered by thermocompression bonding, and the first eutectic metal is connected to the ohmic electrode 19 through the via hole 27 of the first oxide film 20, and the second ohmic contact layer is formed on the ohmic electrode 19. 17), the second cladding layer 16, the light emitting layer 15, the first cladding layer 14, the first ohmic contact layer 13 and the first electrode 25 is present, the first electrode The sapphire base substrate was completely removed and formed on the first ohmic contact layer. The first ohmic contact layer may be n-type, and the second ohmic contact layer may be p-type.

The ohmic electrode is covered with the first oxide film 20, and the second via hole 27 for electrically connecting the ohmic electrode 19 and the first eutectic metal 21 exists on the first oxide film 20, and sapphire The etched first via hole 24 is preferably present on the line crossed with the second via hole 27 of the oxide film.

The detailed manufacturing method of the fifth embodiment is the same as the first embodiment, but the etching degree of the sapphire substrate is different. In the fifth embodiment, all of the sapphire substrates are etched to expose the buffer layer 12 to secure the first electrode contact area. Thereafter, the buffer layer 12 is dry-etched using RIE to expose the first ohmic contact layer 13 and to deposit and heat the first electrode 25.

As described above, in the vertical light emitting diode having the structure of the present invention, since the first electrode 25 and the second electrode 26 are formed separately on the upper and lower surfaces of the chip, the light emitting diode having the vertical electrode structure can be manufactured. The chip area can be reduced, which greatly improves chip yield per wafer.

In addition, since a via hole is formed in the sapphire substrate 11 and the first electrode 25 is formed of metal, heat and static electricity are efficiently discharged through the first electrode and the second electrode, thereby improving reliability of the device. Contributes greatly. In addition, since the current flows uniformly through the entire area of the chip, driving is possible even at a large current, and high light output can be obtained even in a single device.

The characteristics of such devices satisfy the high luminance characteristic, which is an essential requirement for the back light unit of lighting and liquid crystal display devices.

In the present invention, since the sapphire substrate is removed using back grinding and dry or wet etching, productivity is greatly improved, and thermal damage that an epitaxial layer can receive in the case of a laser lift-off method can be prevented. In addition, by utilizing the etching selectivity between the sapphire substrate and the nitride semiconductor can be easily improved the reproducibility of the process, and the standardized process is possible to facilitate mass production.

While the invention has been shown and described with respect to particular embodiments, it will be understood that various changes and modifications can be made in the art without departing from the spirit or scope of the invention as set forth in the claims below. It will be appreciated that those skilled in the art can easily know.

Claims (29)

a. forming a plurality of nitride based semiconductor layers on the sapphire base substrate; a1. Forming a second oxide layer on the nitride based semiconductor layer and etching the second oxide layer to leave only a part thereof; b. forming an ohmic electrode layer on the nitride based semiconductor layer and the second oxide layer; c. forming a first oxide layer on the ohmic electrode layer, and forming a via hole to expose the ohmic electrode layer on the first oxide layer; d. forming a first eutectic metal layer on the first oxide layer to be electrically connected to the ohmic electrode layer through a via hole of the first oxide layer; e. forming a second eutectic metal layer on one side of the receptor substrate; f. adhering the first and second eutectic metal layers; g. after processing the sapphire base substrate to a predetermined thickness, etching to expose at least a portion of the nitride based semiconductor layer, and simultaneously forming a cleavage line for separating the base substrate by individual chips through etching; h. forming a first electrode on the exposed nitride based semiconductor layer; And i. forming a second electrode on the other side of the receptor substrate, the second side of which is formed with the second eutectic metal; The second oxide layer etched and left in step a1 is formed on the same vertical line as the portion exposed through the sapphire base substrate of the nitride based semiconductor layer, and the via hole is exposed to the second oxide layer and the nitride based semiconductor layer. A vertical light emitting diode manufacturing method, characterized in that formed on the same vertical line as the portion. The method of claim 1, wherein the step a includes forming a buffer layer on the sapphire base substrate and forming a plurality of nitride based semiconductor layers on the buffer layer, and the step g includes the base substrate and the buffer layer together. Vertical light emitting diode manufacturing method, characterized in that for etching. delete delete delete The method of claim 2, g1. The method may further include forming a transparent electrode layer on the sapphire base substrate. In this case, in the h step, the first electrode is formed on the transparent electrode layer, characterized in that the vertical light emitting diode manufacturing method. The method of claim 6, wherein the transparent electrode layer is formed of any one of indium tin oxide (ITO), ZnB, ZnO, InO, and SnO. The method of claim 2, wherein in the g step, the sapphire base substrate is etched and completely removed. The method of claim 2, wherein the ohmic electrode layer is formed by depositing at least one of Pd, Rh, Ta, Ni, Cr, Au, and Ti. The vertical type light emitting diode according to claim 2, wherein the first and second eutectic metal layers are formed by depositing at least one of Ti, Al, Rd, Pt, Ta, Ni, Cr, Au, Ag. Diode manufacturing method. The vertical light emitting diode of claim 2, wherein the first and second eutectic metal layers are bonded for 1 minute to 40 minutes at a pressure of 1 to 6 MP at a temperature of 200 to 500 degrees Celsius. Way. The method of claim 11, wherein the bonding step (f) is performed in a gas atmosphere of any one of Ar, He, Kr, Xe, and Rn. The method of claim 2, wherein the etching of the sapphire base substrate in step g is sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ) and aloe etch (4H ₃ PO ₄ + 4CH ₃ COOH + HNO ₃ + H ₂ Method for manufacturing a vertical light emitting diode, characterized in that the wet etching method using an etching solution containing at least one of O). delete A sapphire base substrate including a first via hole formed to penetrate up and down and an cleavage line for separating the base substrate by individual chips through etching; A plurality of nitride based semiconductor layers formed on the base substrate; A second oxide layer formed on a portion of the nitride semiconductor layer opposite the contact surface of the sapphire base substrate and formed on the same vertical line as the first via hole formed on the sapphire base substrate; An ohmic electrode layer formed on the nitride based semiconductor layer and the second oxide layer; A first electrode formed on the exposed surface of the nitride based semiconductor layer exposed through the first via hole of the sapphire base substrate; A first oxide layer formed on the ohmic electrode layer and including a second via hole formed to expose a portion of the ohmic electrode layer on the same vertical line as the second oxide layer and the first via hole; A first eutectic metal layer formed on the first oxide layer to be connected to the ohmic electrode layer through the second via hole; And And a receptacle substrate having a second electrode formed on one surface thereof, and a second eutectic metal layer formed on the other surface thereof to be bonded to the first eutectic metal layer. delete delete delete 16. The vertical light emitting diode of claim 15, wherein a buffer layer is formed between the sapphire base substrate and the nitride semiconductor layer, and the first via hole is formed over the sapphire base substrate and the buffer layer. 16. The vertical light emitting diode of claim 15, wherein a transparent electrode layer is formed over the sapphire base substrate and the first via hole, and the first electrode is formed on the transparent electrode layer. The light emitting diode of claim 20, wherein the transparent electrode is formed of at least one of ITO, ZnB, ZnO, InO, and SnO. The nitride-based semiconductor layer according to any one of claims 15 to 20, wherein the nitride-based semiconductor layer is formed of an In _x (Al _y Ga _1-y ) N nitride-based semiconductor, wherein x and y are 1≥x≥0, 1≥y A vertical light emitting diode having a value of ≧ 0, x + y> 0. 23. The vertical light emitting diode of claim 22, wherein the ohmic electrode includes at least one of Pd, Rh, Ta, Ni, Cr, Au, and Ti. 23. The vertical light emitting diode of claim 22, wherein the first and second eutectic metals comprise at least one of Ti, Al, Rd, Pt, Ta, Ni, Cr, Au, Ag. 23. The method of claim 22, wherein the receptor substrate comprises a conductive semiconductor film of Si, GaAs, InP, InAs, a conductive conductive film of ITO, ZrB, ZnO, CuW, Mo, Au, Al, Cu, at least one of the metal Vertical light emitting diodes characterized in that. 23. The vertical light emitting diode of claim 22, wherein the receptor substrate is a p-type silicon substrate. 27. The vertical light emitting diode of claim 26, wherein the second eutectic metal is at least one of Ti, Au, Ni, and Pt. 23. The vertical light emitting diode of claim 22, wherein the first electrode comprises at least one of Al, Pt, Ta, Ni, Cr, Au, and Ti. delete

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