KR100663321B1 - light emitting diode with vertical electrode and manufacturing method of the same - Google Patents

Abstract

A plurality of nitride based semiconductor layers having a first electrode formed on one side thereof, an ohmic electrode formed on the other side of the nitride based semiconductor layer, a receptor substrate having via holes formed on the ohmic electrodes and penetrating up and down, and the receptor A vertical electrode type light emitting diode including a substrate and a second electrode formed over the via hole is provided.

Light emitting diode, vertical electrode structure, oxide film, sapphire, via hole, nitride semiconductor

Description

Light emitting diode with vertical electrode and manufacturing method of the same

1A to 1D are diagrams illustrating an intermediate process of manufacturing a vertical electrode type light emitting diode according to a first embodiment of the present invention.

2A to 2E illustrate an intermediate manufacturing process of a vertical electrode light emitting diode according to a second embodiment of the present invention.

3A to 3G illustrate an intermediate process of manufacturing a vertical electrode light emitting diode according to a third embodiment of the present invention.

4 is a cross-sectional view of a vertical electrode light emitting diode according to a fourth embodiment of the present invention.

5 is a cross-sectional view of a vertical electrode light emitting diode according to a fifth embodiment of the present invention.

6 is a cross-sectional view of a vertical electrode type light emitting diode according to a sixth embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

11 Sapphire Base Board 12 Buffer Layer

13 first ohmic contact layer 14 first cladding layer

15 Light emitting layer 16 Second cladding layer

17 Second ohmic contact layer 19 Ohmic electrode

20 oxide 21 first eutectic metal

22 Second Eutectic Metal 23 Receptacle Board

24 Protective film (oxide) 25 First electrode

26 Second electrode 27 Via hole

28 Transparent or transparent electrode

The present invention relates to a light emitting diode having a vertical electrode structure and a method of manufacturing the same.

A light emitting diode is a type of photodiode that generates light when a constant current of a constant magnitude flows. The light emitting diode is a light emitting diode that emits red or green light by using a pin bonded structure of compound semiconductors such as indium phosphorus (InP), gallium arsenide (GaAs), and gallium phosphorus (GaP), and also emits blue and ultraviolet light. Light emitting diodes have been developed and widely used in display devices, light source devices, and environmental application devices. Recently, color conversion light emitting diodes using white, red, green, and blue chips or white phosphors have been developed, and the application range of the lighting devices has been expanded.

In the case of using a nitride-based light emitting material as a thin film structure in such a light emitting diode, sapphire similar in lattice constant and crystal structure is used as a base substrate to reduce crystal defects during epitaxial growth.

However, since sapphire is an insulator, both the first electrode and the second electrode had to be formed on the growth surface of the epi layer. Thus, if both electrodes are formed on the same surface, the area of electrodes required for wire bonding must be secured. Therefore, the chip area of the light emitting diode is also over a certain size, which hinders the improvement of chip production per wafer, and uses an insulator as a substrate. Therefore, it is difficult to discharge static electricity flowing from the outside, which causes device defects due to static electricity. This leads to several limitations in the packaging process, such as lowering device reliability and incorporating zener diodes.

In addition, since sapphire has low thermal conductivity, it is difficult to dissipate heat generated while driving a light emitting diode to the outside, and thus there is a limit to applying a large current for high power. In particular, since the light emitting diodes are manufactured by wet or dry etching the sapphire substrate, the nitride semiconductor layer and the electrode should not be damaged during sapphire etching and the chip performance should not be affected.

When the sapphire substrate 11 is etched by the ICP / RIE technique, which is a dry etching technique, it is difficult to stop etching in the buffer layer 12 made of nitride-based semiconductor, and in order to stop etching in the buffer layer 12, an optical analysis method or residual gas analysis is performed. You have to use the same technique. Even with these analytical techniques, the probability of success is low.

Dicing equipment commonly used to separate semiconductor devices uses diamond blades. Cutting a sapphire substrate is rather cumbersome and reduces productivity.

Therefore, research for developing a light emitting diode structure having a vertical electrode structure is continuing in the art. In order to make a light emitting diode having a vertical electrode structure, the sapphire base substrate must be etched and removed. In this case, an auxiliary substrate is required to support the nitride semiconductor layer.

If the auxiliary substrate is an insulator, the first electrode and the second electrode may be difficult to be electrically connected, and thus a problem may occur in that a light emitting diode having a vertical electrode structure may not be manufactured. There is a problem that only the metal cannot effectively protect the nitride semiconductor layer.

An object of the present invention is to provide a light emitting diode having a vertical electrode structure using a sapphire substrate etching technique and a method of manufacturing the same.

It is an object of the present invention to provide a light emitting diode having a vertical electrode structure having a new receptor substrate and an internal connection structure, particularly in the case of using a receptor substrate to advantageously perform a multi-step process.

In particular, it is an object of the present invention to provide a light emitting diode having a vertical electrode structure by allowing the first electrode and the second electrode to be electrically connected even when the receptor substrate is an insulator.

In order to achieve the above object, the present invention proposes the following light emitting diode.

First, the present invention includes a plurality of nitride-based semiconductor layers having a first electrode formed on one side thereof; An ohmic electrode layer formed on the other side of the nitride based semiconductor layer; An auxiliary substrate layer formed on the ohmic electrode layer and having a via hole; And a second electrode formed over the auxiliary substrate layer and the via hole.

Preferably, the auxiliary substrate layer is a SiO ₂ oxide layer formed to a predetermined thickness, characterized in that the ohmic electrode layer is formed to be connected to the second electrode through the via hole.

Also preferably, the auxiliary substrate layer may include a first substrate metal layer formed on the ohmic electrode layer, and a receptor substrate on which one side of the second substrate metal layer adhered to the first vegetable metal layer is formed. The via hole is formed so as to expose the first eutectic metal layer through the second eutectic metal layer and the receptor substrate.

Also preferably, the auxiliary substrate layer may include an oxide layer formed on the ohmic electrode layer; A first eutectic metal layer formed on the oxide film layer; And a receptacle substrate on which one side of the second eutectic metal layer is formed, the second substrate being bonded to the first eutectic metal layer, wherein the via hole includes the oxide layer, the first eutectic metal layer, the second eutectic metal layer, and the second substrate. It is formed so as to penetrate the receptor substrate up and down, characterized in that the ohmic electrode layer is formed to expose.

Preferably, the light transmitting electrode or the transparent electrode is formed on one side of the nitride-based semiconductor layer, the first electrode is characterized in that formed on the light transmitting electrode or the transparent electrode. More preferably, the transparent electrode is formed of indium tin oxide (ITO) or ZnO. Also preferably, the light transmissive electrode is formed to include at least one of Ni, Au, Pt, Al, Ti.

Also preferably, the ohmic electrode layer includes at least one of Pd, Rh, Pt, Ta, Ni, Cr, Au, Ti, and Cu. Also preferably, the first electrode includes at least one of Al, Pt, Ta, Ni, Cr, Au, and Ti. Also preferably, the first or second metal element layer includes at least one of Ti, Al, Rd, Pt, Ta, Ni, Cr, Au, and Ag.

Also preferably, the receptor substrate may be formed of a p-type silicon substrate, and the second eutectic metal layer may include at least one of Ti, Au, Ni, and Pt. Also preferably, the receptor substrate may include at least one of conductive semiconductor substrates such as Si, GaAs, InP, InAs, and metals such as CuW, Mo, Au, Al, and Cu. Also preferably, the nitride semiconductor layer is composed of an In _x (Al _y Ga _1-y ) N nitride semiconductor, where x and y are 1≥x≥0, 1≥y≥0, and x + y> 0. Has

The vertical electrode light emitting diode of the structure comprises the steps of forming a plurality of nitride-based semiconductor layer on the sapphire base substrate; Forming an ohmic electrode layer on the nitride based semiconductor layer; Forming an oxide layer on the ohmic electrode layer; After processing the sapphire base substrate to a predetermined thickness, etching the nitride-based semiconductor layer to be exposed; Forming a first electrode on the exposed nitride based semiconductor layer; Etching the oxide layer to form a via hole to expose the ohmic electrode layer; And forming a second electrode over the oxide layer and the via hole.

Preferably forming a plurality of nitride-based semiconductor layer on the sapphire base substrate; Forming an ohmic electrode layer on the nitride based semiconductor layer; Forming a first eutectic metal layer on the ohmic electrode layer; Forming a second eutectic metal layer on one side of the receptor substrate, and forming a via hole penetrating through the receptor substrate and the second eutectic metal layer; Adhering the first eutectic metal layer and the second eutectic metal layer; Forming a passivation layer over the receptor substrate and the via hole; And processing the sapphire base substrate to a predetermined thickness, and then etching the nitride-based semiconductor layer to be exposed. Forming a first electrode on the exposed nitride based semiconductor layer; Completely etching the passivation layer to expose the via hole; And forming a second electrode over the receptor substrate and the via hole.

Also preferably forming a plurality of nitride-based semiconductor layer on the sapphire base substrate; Forming an ohmic electrode layer on the nitride based semiconductor layer; Forming an oxide layer on the ohmic electrode layer; Forming a first eutectic metal layer on the oxide layer, and etching the first eutectic metal layer to form via holes to expose the oxide layer; Forming a second eutectic metal layer on one side of the receptor substrate, and forming a via hole penetrating through the receptor substrate and the second eutectic metal layer at a position coincident with the via hole on the first eutectic metal layer; Adhering the first eutectic metal layer and the second eutectic metal layer; After processing the sapphire base substrate to a predetermined thickness, etching the nitride-based semiconductor layer to be exposed; Forming a first electrode on the exposed nitride based semiconductor layer; Etching the exposed oxide film through the via holes of the first and second eutectic metal layers and the receptor substrate; And forming a second electrode over the receptor substrate and the via hole.

The method may further include forming a light transmissive electrode or a transparent electrode on the exposed nitride semiconductor layer after exposing the nitride semiconductor layer, and forming a first electrode on the light transmissive electrode or the transparent electrode. Characterized in that. More preferably, the transparent electrode is characterized in that the indium tin oxide (ITO) or ZnO. Also preferably, the light transmissive electrode is formed to include at least one of Ni, Au, Pt, Al, Ti.

Also preferably, the forming of the ohmic electrode layer may include at least one of Pd, Rh, Pt, Ta, Ni, Cr, Au, and Ti, and may be 450 ° C. to 700 in an furnace containing oxygen or nitrogen. Heat treatment for 2 minutes at a temperature of ℃. Also preferably, the bonding of the first and second eutectic metal layers is carried out in a gas atmosphere including at least one of Ar, He, Kr, Xe, and Rn. Also preferably, the step of etching the sapphire base substrate may be performed by wet etching with a mixed solution of sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ).

<Formation of nitride based semiconductor layer>

Buffer layer + undoped In _x (Al _y Ga _1-y ) N (12), n-type on sapphire base substrate (Sapphire, Al ₂ O ₃ ) of 430μm thickness to fabricate vertical electrode type light emitting diode In _x (Ga _y Al _1-y ) N of the conductive contact layer 13, the n-type cladding layer 14, the light emitting layer 15, the p-type cladding layer 16, and the p-type conductive contact layer 17. The nitride semiconductor layer was grown. That is, each layer 12, 13, 14, 15, 16, 17 can be formed of AlGaN, InGaN, AlGaInN or the like. The composition ratio of the nitride semiconductor is 1≥x≥0, 1≥y≥0, and x + y> 0.

The nitride semiconductor layer (In _x (Ga _y Al _1-y ) N) was grown using metal organic chemical vapor deposition (MOCVD). The nitride semiconductor layer may include metal organic chemical vapor deposition, liquid phase epitaxy, hydrogen vapor phase epitaxy, molecular beam epitaxy, and MOVPE. It can also grow with (metal organic vapor phase epitaxy).

The growing nitride semiconductor layer may be grown in a single layer or in multiple layers depending on the type of device to be manufactured, and any one or a plurality of elements of Si, Mg, and Zn groups may be added as impurities to have a conductive property. Si may be added to form an n-type nitride semiconductor layer, and Mg may be added to form a p-type nitride semiconductor layer. The doping concentration depends on the type of device to be manufactured and may be doped at about 10 ¹⁵ / cm ³ to 10 ²¹ / cm ³ . Therefore, the nitride semiconductor is classified into a high resistor or a conductive material according to the doping concentration, and in the case of a high resistor, the resistivity is preferably 1x10 ⁰ Ωcm or more and 1x10 ^-1 Ωcm or less in the case of the conductive material.

In particular, the light-emitting layer _{(15) In x (Ga y} Al 1-y) barrier layers of N and _{In x (Ga y Al 1-} y) single quantum well structure comprising a well layer of the N or, have a multiple quantum well structure By controlling the composition ratio of In, Ga, and Al, it is possible to freely fabricate from the long wavelength having the InN (˜1.8 eV) band gap to the short wavelength light emitting diode having the AlN (˜6.4 eV) band gap.

<First Embodiment>

1A to 1D are diagrams illustrating an intermediate process of manufacturing a vertical electrode light emitting diode according to a first embodiment of the present invention. The vertical geometry light emitting diode of this embodiment has the following structure.

The first ohmic contact layer 13, the first cladding layer 14, the light emitting layer 15, the second cladding layer 16, the second ohmic contact layer 17, and the ohmic electrode 19 are sequentially formed. The oxide film 20 is formed on the ohmic electrode 19, and the first electrode 25 is formed on the first ohmic contact layer 13 by removing all the sapphire base substrates. The first ohmic contact layer may be n-type, and the second ohmic contact layer may be p-type. The second electrode 26 is formed on the via hole 27 and the oxide film 20 to be electrically connected to the ohmic electrode 19. In the present invention, the oxide film 20 itself serves as a receptor substrate.

As shown in FIG. 1A, nitride semiconductor layers 12, 13, 14, 15, 16, and 17 are sequentially formed on the sapphire base substrate 11, and then an ohmic electrode 19 is deposited and an oxide film serving as a receptor substrate ( 20) was formed.

The buffer layer 12 and the n-type and p-type conductive contact layers 13 and 17, the n-type and p-type cladding layers 14 and 16, and the emission layer 15 are formed of In _x (Al _y Ga _1-y ) N nitride. And x and y have values of 1 ≧ x ≧ 0, 1 ≧ y ≧ 0, and x + y> 0. The n-type conductive contact layer 13 is doped with a Si impurity of 10 ¹⁸ cm ⁻³ or more to have a resistivity of ¹ × 10 ⁻¹ Ωcm or less, and the p-type contact layer 17 has a Mg impurity of 10 ¹⁸ cm ⁻³ or more Doped to a concentration to have a resistivity of less than ¹ × 10 ⁻¹ Ωcm.

The total thickness of the nitride-based semiconductor thin film is preferably 1 μm to 20 μm in order to minimize the cracking of the nitride semiconductor due to stress when removing the sapphire substrate, and to improve the current diffusion and etching selectivity, 13), the thickness of 2 μm or more and the p-type contact layer 17 is preferably 0.2 μm or more.

Thereafter, the ohmic electrode 19 is deposited and heat treated. In order to obtain a conductive material having excellent low contact resistance and light reflectivity, the ohmic electrode 19 increases the external quantum efficiency by depositing any one of Pd, Rh, Pt, Ta, Ni, Cr, Au, Ti, or an alloy of these metals. You can. The heat treatment is preferably performed at a temperature of 450 ° C. to 700 ° C. for 2 minutes in an atmosphere containing oxygen or nitrogen.

After the heat treatment, the oxide film 20 is deposited by plasma enhanced chemical vapor deposition (PECVD). The oxide film 20 serves as a protective film for the nitride semiconductor layers 12, 13, 14, 15, 16, and 17 when etching the sapphire substrate, and also functions as a receptor substrate in this embodiment.

Subsequently, the sapphire substrate 11 was wrapped and polished. At this time, the thickness of the sapphire substrate 11 is preferably as thin as possible in order to minimize the etching process time, but if too thin, the sapphire substrate 11 is wheel-worn or difficult to handle, preferably 10 μm to 200 μm. . In addition, since the roughness of the surface of the sapphire substrate 11 is transferred to the nitride semiconductor layers 12, 13, 14, 15, 16, and 17 as it is, the nitride semiconductor structure may be damaged. Roughness was made to be 20 micrometers or less.

The lapping of the sapphire substrate 11 is performed by chemical mechanical polishing (CMP), ICP / RIE dry etching, alumina (Al ₂ O ₃ ), mechanical polishing using diamond powder or hydrochloric acid (HCl), nitric acid (HNO ₃ ), potassium hydroxide (KOH), sodium hydroxide (NaOH), sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), chromium oxide (CrO ₃ ), potassium hydroxide (KOH), potassium hydrogen sulfate (KHSO ₄ ) and aloe _{(4H 3 PO 4 + 4CH 3} COOH + HNO 3 + H 2 O) at least one of or proceeds by the wet etching to the mixed solution by a combination of the etchant. At this time, any one of BCL ₃ , Cl ₂ , HBr, Ar, or a mixed gas thereof is used as an etching gas of ICP / RIE or RIE.

Thereafter, the sapphire substrate 11 was etched to expose the buffer layer 12, and the buffer layer 12 was etched again to secure the contact area of the first ohmic contact layer 13. The wet etching of the sapphire substrate 11 for exposing the buffer layer 12 is performed in the following manner.

The etching rate of the sapphire substrate 11 by the etching solution mixed with sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) at a temperature of 200 ° C. to 400 ° C. was measured to be 1 μm to 5 μm greater than the thickness of the sapphire substrate 11. Soak in the etching solution for enough time to etch the additional thickness. When the etching solution used herein, the etching rate of the GaN nitride semiconductor was 1/10 or less than that of the sapphire substrate 11. That is, the etching selectivity of the nitride based semiconductor layers 12, 13, 14, 15, 16, and 17 with respect to the sapphire base substrate 11 is 10 or more. Therefore, even though the etching process is performed for a time remaining after the sapphire base substrate 11 is completely etched, the etching rate of the nitride semiconductor layers 12, 13, 14, 15, 16, and 17 is slow, so that the nitride semiconductor layers 12, 13, and 14 , 15, 16, 17) are less likely to be damaged.

On the other hand, it is preferable to maintain the temperature of the etching solution at 100 ℃ or more in order to shorten the etching time. The heating for maintaining the temperature of the etching solution above 100 ℃ may be a direct heating method to put the solution on the heater or directly contact the heater and the indirect heating method using light absorption.

An ICP / RIE technique may be used for etching the sapphire base substrate 11 for forming the first electrode 25. In order to quickly etch the sapphire substrate 11, it is desirable to increase the ICP and RIE power as much as possible, but care must be taken because it may damage the epi layer.

The oxide film 20 of SiO ₂ is used as a protective film of the nitride semiconductors 12, 13, 14, 15, 16, and 17 when wet the sapphire substrate 11. The oxide film of SiO ₂ is hydrochloric acid (HCl), nitric acid (HNO ₃ ), potassium hydroxide (KOH), sodium hydroxide (NaOH), sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), oxidation By at least one of chromium (CrO ₃ ), potassium hydroxide (KOH), potassium hydrogen sulfate (KHSO ₄ ) and aloe etch (4H ₃ PO ₄ + 4CH ₃ COOH + HNO ₃ + H ₂ O) or a combination thereof It is hardly etched into the mixed solution and also has a very strong adhesion to the nitride semiconductor.

The SiO ₂ oxide film 20 is preferably deposited on the semiconductor thin film by PECVD, low pressure chemical vapor deposition (LPCVD), thermal CVD, and it is more preferable to obtain a high quality oxide film having little pin holes. . Oxide film of high quality SiO ₂ without pinhole is hardly etched in the etching solution and can protect the semiconductor thin film because the etching solution is not in contact with the semiconductor thin film.

In particular, when the sapphire is etched to expose the nitride semiconductor thin film to the etchant, crystal defects formed during semiconductor crystal growth, in particular, the through crystal defects are hydrochloric acid (HCl), nitric acid (HNO ₃ ), potassium hydroxide (KOH), sodium hydroxide ( NaOH), sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), chromium oxide (CrO ₃ ), potassium hydroxide (KOH), potassium hydrogen sulphate (KHSO ₄ ) and aloe etch (4H ₃ PO ₄ + 4CH ₃ COOH + HNO ₃ + H ₂ O) is weak to the mixed solution containing at least one of the semiconductor thin film may damage the entire surface, there is an advantage that the process can be more stably achieved by blocking the contact of the etching solution.

The sapphire substrate was completely etched to expose the buffer layer 12 to secure the first electrode contact area. Thereafter, the buffer layer 12 is dry etched using RIE to expose the first ohmic contact layer 13, and the first electrode 25 is deposited to be thermally treated (FIG. 1B). In order to expose the first ohmic contact layer 13, the buffer layer 12 may be etched entirely or only a portion thereof, as shown in FIG. 1D.

Thereafter, as illustrated in FIG. 1C, the oxide film 20 is photographed to form a via hole 27. Since the oxide film 20 is an insulator, a via hole 27 must be formed in the oxide film 20 to electrically connect the first electrode 25 and the second electrode 26.

Thereafter, as shown in FIG. 1D, when the second electrode 26 is formed and diced into the device size, device fabrication is completed. The second electrode 26 is formed over the oxide film 20 and the via hole 27 and is electrically connected to the first electrode 25 through the via hole 27.

Second Embodiment

2A to 2E illustrate an intermediate manufacturing process of the vertical electrode type light emitting diode according to the second embodiment of the present invention. The vertical electrode type light emitting diode of this embodiment has the following structure.

The second eutectic metal 22, the first and second metals 21 and 22, which are formed on the receptor substrate 23, are bonded to each other by thermocompression bonding. The ohmic electrode 19 is formed on (). The second ohmic contact layer 17, the second cladding layer 16, the light emitting layer 15, the first cladding layer 14, the first ohmic contact layer 13, and the first ohmic contact layer 17 are disposed on the ohmic electrode 19. An electrode 25 exists, and the first electrode 25 is formed on the first ohmic contact layer 13 by removing all the sapphire base substrates. The first ohmic contact layer may be n-type, and the second ohmic contact layer may be p-type. The second electrode 26 is formed on the via hole 27 and the receptor substrate 23 to be electrically connected to the ohmic electrode 19.

As shown in FIG. 2A, nitride-based semiconductor layers 12, 13, 14, 15, 16, and 17 are sequentially formed on the sapphire base substrate 11, and then the ohmic electrode 19 and the first eutectic metal 21 are deposited. did.

On the sapphire substrate 11, the buffer layer 12 and the n-type and p-type conductive contact layers 13 and 17, the n-type and p-type cladding layers 14 and 16, and the light emitting layer 15 are In _x (Al _y Ga). _1-y ) N nitride semiconductor, and x and y have values of 1 ≧ x ≧ 0, 1 ≧ y ≧ 0, and x + y> 0. n-conductivity type contact layer 13 is Si impurity is 10 ¹⁸ cm ^-3 is doped has a specific resistance of 1x10 ^-1 Ωcm or less, p-type contact layer 17 is doped with Mg impurity is more than 10 ¹⁸ cm ^-3 concentration It is desirable to have a specific resistance of ¹ × 10 ⁻¹ Ωcm or less.

The total thickness of the nitride-based semiconductor thin film preferably has a thickness of 1 μm to 20 μm to minimize the cracking of the nitride semiconductor due to stress when removing the sapphire substrate, and the n-type conductive contact layer to improve current diffusion and etching selectivity. (13) is preferably at least 2 m and the thickness of the p-type contact layer 17 is at least 0.2 m.

Thereafter, the ohmic electrode 19 is deposited and heat treated. In order to obtain a conductive material having excellent low contact resistance and light reflectivity, the ohmic electrode 19 increases the external quantum efficiency by depositing any one of Pd, Rh, Pt, Ta, Ni, Cr, Au, Ti, or an alloy of these metals. You can. Heat treatment was performed for 2 minutes at a temperature of 450 ℃ to 700 ℃ in an atmosphere containing oxygen or nitrogen.

Subsequently, the first eutectic metal 21 is deposited on the semiconductor substrate, and the second eutectic metal 22 is deposited on the receptor substrate 23. The first and second eutectic metals 21 and 22 preferably deposit any one of Ti, Al, Rd, Pt, Ta, Ni, Cr, Au, Ag, or an alloy of these metals in order to obtain excellent adhesion. And heat treatment at a temperature between 300 ° C. and 700 ° C. in a furnace containing nitrogen. More preferably, the heat treatment is performed at a temperature of 400 ° C to 600 ° C.

Since the operating voltage of the light emitting diode is greatly affected by the contact resistance between the metal and the semiconductor layer, it is preferable that the second eutectic metal 22 is in ohmic contact with the receptor substrate 23 so as to obtain a low contact resistance. Since it is important to obtain ohmic contact with the second substrate 22, the second substrate 22 is deposited by a combination of any one of Ti, Au, Ni, and Pt, and then heat-treated when the Si substrate is used as the receptor substrate 23. It is desirable to improve the adhesion to the silicon substrate and ohmic characteristics. In particular, in order to prevent damage to the device during sapphire substrate etching, it is preferable to set Ti / Pt / Au.

The receptor substrate 23 forms the via holes 27 before the second eutectic metal 22 is deposited. Since the first electrode 25 and the second electrode 26 are electrically connected through the via hole 27, the receptor substrate 23 may use an insulator or a conductor. As an example, the receptor substrate 23 may be formed by including any one or more of metals such as conductive semiconductor substrates such as Si, GaAs, InP, InAs, CuW, Mo, Au, Al, Cu, and the like.

When bonding the substrate, it is preferable to bond 1 to 60 minutes at a pressure of about 1 MP to 6 MP (Mega pascal) at a temperature of 200 to 500 ° C. using a combination of any one or more of In, Pd, Sn, Au, Pt, Ti, and Ge. Do.

Thereafter, as shown in FIG. 2B, the first and second eutectic metals 21 and 22 metal were thermocompression-bonded to each other. In order to prevent the first and second eutectic metals 21 and 22 from being oxidized in the thermocompression bonding process, the contact resistance between the semiconductor thin film and the metal is increased in a gas atmosphere such as Ar, He, Kr, Xe, and Rn. It is desirable to be able to lower.

After the heat treatment, as shown in FIG. 2C, the SiO ₂ protective film 24 is deposited by plasma enhanced chemical vapor deposition (PECVD) over the via hole 27 and the receptor substrate 23. The protective film 24 of SiO ₂ is used as a protective film of the nitride semiconductor layers 12, 13, 14, 15, 16, and 17 when etching the sapphire substrate.

SiO ₂ protective film 24 is hydrochloric acid (HCl), nitric acid (HNO ₃ ), potassium hydroxide (KOH), sodium hydroxide (NaOH), sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO _{4 used in the present invention} ), Chromium oxide (CrO ₃ ), calcium hydroxide (KOH), potassium hydrogen sulfate (KHSO ₄ ), and allues (4H ₃ PO ₄ + 4CH ₃ COOH + HNO ₃ + H ₂ O) or these It is hardly etched into the mixed solution by the combination of and has a very strong adhesion to the nitride semiconductor.

The protective film 24 of SiO ₂ is preferably deposited on the semiconductor thin film by PECVD, low pressure chemical vapor deposition (LPCVD), thermal CVD, and more preferably, a high quality oxide film having little pinholes is obtained. . Oxide film of high quality SiO ₂ without pinhole is hardly etched in the etching solution and can protect the semiconductor thin film because the etching solution is not in contact with the semiconductor thin film.

In particular, when sapphire is etched and the nitride semiconductor thin film is exposed to an etchant, crystal defects formed during semiconductor crystal growth, in particular, penetrating crystal defects are hydrochloric acid (HCl), nitric acid (HNO ₃ ), potassium hydroxide (KOH), and sodium hydroxide (NaOH). , Sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), chromium oxide (CrO ₃ ), potassium hydroxide (KOH), potassium hydrogen sulfate (KHSO ₄ ) and aloe etch (4H ₃ PO ₄ + 4CH ₃ COOH It is weak to the mixed solution containing at least one of + HNO ₃ + H ₂ O) and may damage the entire surface of the semiconductor thin film. The advantage is that the process can be more stably achieved by forming an oxide film to block the contact of the etching solution. .

That is, when the nitride semiconductor is protected by only the eutectic metal without the oxide film 24, a micro pipe is formed due to the metal crust formed during the metal deposition, and the micro pipe provides an passage through which the etching solution can flow. Penetrating into the nitride semiconductor layer damages the ohmic electrode 19 and the second ohmic contact layer 17.

Subsequently, the sapphire substrate 11 was wrapped and polished. At this time, the thickness of the sapphire substrate 11 is preferably as thin as possible in order to minimize the etching process time, but if too thin, the sapphire substrate 11 is wheel-worn or difficult to handle, preferably 10 μm to 200 μm. . In addition, since the roughness of the surface of the sapphire substrate 11 is transferred to the nitride semiconductor layers 12, 13, 14, 15, 16, and 17 as it is, the nitride semiconductor structure may be damaged. Roughness was made to be 20 micrometers or less.

The lapping of the sapphire substrate 11 is performed by chemical mechanical polishing (CMP), ICP / RIE dry etching, mechanical polishing using alumina (Al ₂ O ₃ ) powder or hydrochloric acid (HCl), nitric acid (HNO ₃ ), potassium hydroxide (KOH). ), Sodium hydroxide (NaOH), sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), chromium oxide (CrO ₃ ), potassium hydroxide (KOH), potassium hydrogen sulphate (KHSO ₄ ) and aloe etch (4H ₃ PO ₄ + 4CH ₃ COH + HNO ₃ + H ₂ O) proceeds by wet etching using a mixed solution of at least one or a combination thereof as an etchant. At this time, any one of BCL ₃ , Cl ₂ , HBr, Ar, or a mixed gas thereof is used as an etching gas of ICP / RIE or RIE.

Thereafter, as shown in FIG. 2D, the sapphire substrate 11 is etched to expose the buffer layer 12 to secure the contact area of the first ohmic contact layer 13 and to expose the first electrode 25 on the exposed first ohmic contact layer 13. ) Was formed. The first electrode 25 includes at least one of Al, Pt, Ta, Ni, Cr, Au, and Ti.

The wet etching of the sapphire substrate 11 for exposing the buffer layer 12 is performed in the following manner. The etching rate of the sapphire substrate 11 by the etching solution mixed with sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) at a temperature of 200 ° C. to 400 ° C. was measured to be 1 μm to 5 μm than the thickness of the sapphire substrate 11. Soak in the etching solution for enough time to etch the additional thickness.

When the etching solution used herein, the etching rate of the GaN nitride semiconductor was 1/10 or less than that of the sapphire substrate 11. That is, the etching selectivity of the nitride based semiconductor layers 12, 13, 14, 15, 16, and 17 with respect to the sapphire base substrate 11 is 10 or more. Therefore, even though the etching process is performed for a time remaining after the sapphire base substrate 11 is completely etched, the etching rate of the nitride semiconductor layers 12, 13, 14, 15, 16, and 17 is slow, so that the nitride semiconductor layers 12, 13, and 14 , 15, 16, 17) are less likely to be damaged.

On the other hand, it is preferable to maintain the temperature of the etching solution at 100 ℃ or more in order to shorten the etching time. The heating for maintaining the temperature of the etching solution above 100 ℃ may be a direct heating method to put the solution on the heater or directly contact the heater and the indirect heating method using light absorption.

An ICP / RIE technique may be used for etching the sapphire base substrate 11 for forming the first electrode 25. In order to quickly etch the sapphire substrate 11, it is desirable to increase the ICP and RIE power as much as possible, but care must be taken because it may damage the epi layer.

 The sapphire substrate was completely etched to expose the buffer layer 12 to secure the first electrode contact area. Thereafter, the buffer layer 12 is dry-etched using RIE to expose the first ohmic contact layer 13, and the first electrode 25 is deposited to be heat-treated. In order to expose the first ohmic contact layer 13, the buffer layer 12 may be etched entirely or only a portion of the buffer layer 12 as shown in FIG. 2D.

Thereafter, the oxide film 24 is etched and completely removed to expose the via hole 27 and the receptor substrate 23. Thereafter, as shown in FIG. 2E, the second electrode 26 is formed. The second electrode 26 is formed over the receptor substrate 23 and the via hole 27 and is electrically connected to the first eutectic metal 21 through the via hole 27.

Afterwards, dicing to element size completes device fabrication. At this time, the heat treatment after forming the second electrode is preferable to lower the contact resistance, and when the receptor substrate is made of metal, since the receptor substrate 23 itself acts as the second electrode, a via hole for electrical connection is formed. There is no need to do it.

Third Embodiment

3A to 3G illustrate a light emitting diode having a vertical electrode structure and a manufacturing process thereof according to a third embodiment of the present invention. The vertical electrode type light emitting diode of this embodiment has the following structure.

The second eutectic metal 22, the first and second metals 21 and 22, which are formed on the receptor substrate 23, are bonded to each other by thermocompression bonding. ), An ohmic electrode 19 and an oxide film 20 are formed. A second ohmic contact layer 17, a second cladding layer 16, a light emitting layer 15, a first cladding layer 14, a first ohmic contact layer 13, and a first electrode on the oxide film 20. 25 is present, and the first electrode 25 is formed on the first ohmic contact layer 13 by removing all the sapphire base substrates. The first ohmic contact layer may be n-type, and the second ohmic contact layer may be p-type. The second electrode 26 is formed on the via hole 27 and the receptor substrate 23, and is electrically connected to the ohmic electrode 19.

After the nitride-based semiconductor layers 12, 13, 14, 15, 16 and 17 are sequentially formed on the sapphire base substrate 11 as shown in FIG. 3A, the ohmic electrode 19, the oxide film 20 and the first eutectic metal are formed. (21) was deposited.

The buffer layer 12 on the sapphire substrate 11 and the n-type and p-type conductive contact layers 13 and 17, the n-type and p-type cladding layers 14 and 16, and the light emitting layer 15 are In _x (Al _y). Ga _1-y ) N nitride semiconductor, and x and y have values of 1 ≧ x ≧ 0, 1 ≧ y ≧ 0, and x + y> 0. The n-type conductive contact layer 13 is doped with a Si impurity of 1x10 ¹⁸ cm ^-3 or more to have a resistivity of 1x10 ^-1 Ωcm or less, and the p-type contact layer 17 has a Mg impurity of 1x10 ¹⁹ cm ^-3 or more It is desirable to have a resistivity of less than ¹ × 10 ⁻¹ Ωcm, doped to a concentration.

The total thickness of the nitride-based semiconductor thin film preferably has a thickness of 1 μm to 20 μm in order to minimize the cracking of the nitride semiconductor due to stress when the sapphire substrate is removed, and the n-type conductive contact layer ( 13), the thickness of 2 μm or more and the p-type contact layer 17 is preferably 0.2 μm or more.

Thereafter, the ohmic electrode 19 is deposited and heat treated. In order to obtain a conductive material having excellent low contact resistance and light reflectivity, the ohmic electrode 19 is formed by depositing any one of Pd, Rh, Pt, Ta, Ni, Cr, Au, Ti, Cu, or an alloy of these metals. Can be increased. The heat treatment is preferably performed at a temperature of 450 ° C to 700 ° C for 2 minutes in an atmosphere containing oxygen or nitrogen. After the heat treatment, the SiO ₂ oxide film 20 is deposited by plasma enhanced chemical vapor deposition (PECVD). The oxide film 20 is used as a protective film of the nitride semiconductor layers 12, 13, 14, 15, 16, and 17 when etching the sapphire substrate.

Subsequently, the first eutectic metal 21 is deposited on the semiconductor substrate, and the second eutectic metal 22 is deposited on the receptor substrate 23. The first and second eutectic metals 21 and 22 may be formed of Ti, Al, Rd, Pt, Ta, Ni, Cr, Au to obtain excellent adhesion and light reflection characteristics between the oxide film 20 and the receptor substrate 23. It can be obtained by depositing any one of Ag, an alloy or a combination thereof, and heat-treated at a temperature between 300 ° C and 700 ° C in a furnace containing nitrogen. Preferably the heat treatment at a temperature of 400 ℃ to 600 ℃.

Since the operating voltage of the light emitting diode is greatly affected by the contact resistance between the metal and the semiconductor layer, the second eutectic metal 22 is in ohmic contact with the receptor substrate 23 to obtain a low contact resistance.

The second eutectic metal 22 depends on the type of receptor substrate, and when the p-type silicon substrate is used as the receptor substrate, it is made of any one of Ti, Au, Ni, Pt, or an alloy thereof, and heat treated. Its adhesion and ohmic properties are improved. In particular, in order to prevent damage to the device during sapphire substrate etching, it is preferable to set Ti / Pt / Au.

The first eutectic metal 21 is deposited on the semiconductor substrate to form the via holes 27 as shown in FIG. 3B. In addition, after forming a pattern for opening a predetermined portion of the second eutectic metal 22 on the receptor substrate 23, the receptor substrate 23 is etched to form a via hole 27 (FIG. 3C). In this case, the via hole may be formed on the receptor substrate 23, and then the second eutectic metal 22 may be formed. As shown in FIG. 3D, the via holes formed on the receptor substrate 23 and the second eutectic metal 22 are thermally compressed by the first and second eutectic metals. It is connected to form a single via hole (27).

Since the first electrode 25 and the second electrode 26 are electrically connected to each other through the via hole 27, the receptor substrate 23 may use a conductor or a non-conductor. As an example, the acceptor substrate 23 may include any one or more of metals such as Si, GaAs, InP, InAs, SiC, and AlN, and CuW, Mo, Au, Al, and Cu.

When the substrate is bonded, any one or a combination of In, Pd, Sn, Au, Pt, Ti, and Ge may be bonded for 1 minute to 60 minutes at a pressure of about 1MP to 6MP (Mega pascal) at a temperature of 200 ° C to 500 ° C. It is preferable.

Thereafter, the first and second eutectic metals 21 and 22 were thermocompressed and bonded (FIG. 3D). In order to prevent the first and second eutectic metals 21 and 22 from being oxidized in this thermocompression bonding process, the contact resistance between the semiconductor thin film and the metal is increased in a gas atmosphere such as Ar, He, Kr, Xe, and Rn. It is desirable to be able to lower.

Subsequently, the sapphire substrate 11 was wrapped and polished. At this time, the thickness of the sapphire substrate 11 is preferably as thin as possible in order to minimize the etching process time, but if too thin, the sapphire substrate is broken or difficult to handle, preferably about 10 μm to 200 μm. In addition, since the roughness of the surface of the sapphire substrate 11 is transferred to the nitride semiconductor layers 12, 13, 14, 15, 16, and 17 as it is, the nitride semiconductor structure may be damaged. Roughness was made to be 20 micrometers or less.

At this time, in the lapping step, the sapphire base substrate may be wrapped before the thermocompression bonding of the receptor substrate 23. Thus, the substrate may be warped due to the difference in thermal expansion coefficient between the receptor substrate and the sapphire substrate when bonding the receptor substrate. There is an advantage that can be solved.

The lapping of the sapphire substrate 11 is performed by chemical mechanical polishing (CMP), ICP / RIE dry etching, mechanical polishing using alumina (Al ₂ O ₃ ) powder, or hydrochloric acid (HCl), nitric acid (HNO ₃ ), potassium hydroxide ( KOH), sodium hydroxide (NaOH), sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), chromium oxide (CrO ₃ ), potassium hydroxide (KOH), potassium hydrogen sulfate (KHSO ₄ ) and aloe etch ( 4H ₃ PO ₄ + 4CH ₃ COOH + HNO ₃ + H ₂ O) by a wet etching using at least any one of them, or a mixture solution thereof as an etching solution. At this time, any one of BCL ₃ , Cl ₂ , HBr, Ar, or a mixed gas thereof is used as an etching gas of ICP / RIE or RIE.

Thereafter, the sapphire substrate 11 was etched to expose the buffer layer 12 to secure the contact area of the first ohmic contact layer. The wet etching of the sapphire substrate 11 for exposing the buffer layer 12 is performed in the following manner. The etching rate of the sapphire substrate 11 by the etching solution mixed with sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) at a temperature of 200 ° C. to 400 ° C. was measured to add 5 μm to the thickness of the sapphire substrate 11. Immerse in the etching solution for enough time to etch the thickness.

Using the etching solution used herein, the etching rate of the GaN nitride semiconductor was 1/10 or less than that of the sapphire substrate 11. That is, the etching selectivity of the nitride based semiconductor layers 12, 13, 14, 15, 16, and 17 with respect to the sapphire base substrate 11 is 10 or more. Therefore, even though the etching process is performed for a time remaining after the sapphire base substrate 11 is completely etched, the etching rate of the nitride semiconductor layers 12, 13, 14, 15, 16, and 17 is slow, so that the nitride semiconductor layers 12, 13, and 14 , 15, 16, 17) are less likely to be damaged.

On the other hand, it is preferable to maintain the temperature of the etching solution at 100 ℃ or more in order to shorten the etching time. Experimental results show that the sapphire etch rate is highly dependent on the temperature of the solution, and the higher the temperature, the faster the etching. Heating for maintaining the temperature of the etching solution above 100 ℃ may be a direct heating method to put the solution on the heater or to contact the heater directly to the solution and indirect heating method using light absorption.

An ICP / RIE technique may be used to etch the sapphire base substrate 11 for forming the via hole on the sapphire substrate to form the first electrode 25. At this time, in order to quickly etch the sapphire substrate 11, it is preferable to increase the ICP and RIE power as much as possible, but it is preferable to be careful because it may damage the epi layer.

The oxide film 20 of SiO ₂ is deposited to serve as a protective film of the nitride semiconductors 12, 13, 14, 15, 16, and 17 when wet the sapphire substrate 11. That is, if the nitride semiconductor is protected by only the eutectic metal without the oxide film 20, the microcluster is formed due to the metal crust formed during the metal deposition, thereby providing a passage through which the etching solution can flow, and the etching solution is a p-type conductive material. Since the semiconductor thin film penetrates into the semiconductor contact layer to etch the semiconductor thin film, the nitride-based semiconductor light emitting device cannot be stably manufactured by using wet etching.

In order to solve this problem, when the oxide film 20 of SiO ₂ is formed, hydrochloric acid (HCl), nitric acid (HNO ₃ ), potassium hydroxide (KOH), sodium hydroxide (NaOH), and sulfuric acid are formed through a micro pipe of eutectic metal. (H ₂ SO ₄ ), Phosphoric Acid (H ₃ PO ₄ ), Chromium Oxide (CrO ₃ ), Potassium Hydroxide (KOH), Potassium Hydrogen Sulfate (KHSO ₄ ) and Aloech (4H ₃ PO ₄ + 4CH ₃ COOH + HNO _{Even if} the mixed etching solution of at least one of ₃ + H ₂ O) or a combination thereof penetrates into the eutectic metal, the SiO ₂ oxide film 20 resistant to the etching solution covers the semiconductor thin film and thus is etched. Damage to the semiconductor thin film can be avoided in the meantime.

That is, the SiO ₂ oxide film is hardly etched in the etching solution used in the present invention, and also has a very strong adhesive force with the nitride semiconductor.

The SiO ₂ oxide film 20 is preferably deposited on the semiconductor thin film by PECVD, low pressure chemical vapor deposition (LPCVD), thermal CVD, and more preferably, a high quality oxide film having little pinholes is obtained. . An oxide film of high quality SiO ₂ having no pinhole is hardly etched in the etching solution, and the semiconductor thin film can be protected because the etching solution introduced through the pinhole of the eutectic metal does not come into contact with the semiconductor thin film.

In particular, when the sapphire is etched and the nitride semiconductor thin film is exposed to the etchant, crystal defects formed during semiconductor crystal growth, in particular, the through crystal defects are hydrochloric acid (HCl), nitric acid (HNO ₃ ), potassium hydroxide (KOH), and sodium hydroxide (NaOH). ), Sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), chromium oxide (CrO ₃ ), potassium hydroxide (KOH), potassium hydrogen sulfate (KHSO ₄ ) and aloe etch (4H ₃ PO ₄ + 4CH ₃₎ It is weak to the mixed solution containing at least one of COOH + HNO ₃ + H ₂ O) and can damage the entire surface of the semiconductor thin film. The advantage of being able to achieve the process more stably by forming an oxide film to block the contact of the etching solution. have.

That is, when the nitride semiconductor is protected by only the eutectic metal without the oxide film 20, a micro pipe is formed due to the metal crust formed at the time of metal deposition, and the micro pipe provides an passage through which the etching solution can flow. Penetrating into the nitride semiconductor layer damages the ohmic electrode 19 and the second ohmic contact layer 17.

Even if the nitride-based semiconductor layer is protected by the oxide film 20, since the ohmic electrode 19 and the eutectic metal itself may be damaged by the etching solution, the ohmic electrode and the eutectic metal are not damaged by the etching solution. It is more preferable to set it as the structure containing at least any one of these.

The sapphire substrate was completely etched to expose the buffer layer 12 to secure the first electrode contact area. Thereafter, the buffer layer 12 is dry-etched using ICP / RIE or RIE to expose the first ohmic contact layer 13 and the first electrode 25 is deposited to be heat treated (FIG. 3E). The first electrode 25 includes at least one of Al, Pt, Ta, Ni, Cr, Au, and Ti.

In order to expose the first ohmic contact layer 13, the buffer layer 12 may be etched to expose the first ohmic contact layer 13 as shown in FIG. 3g, and the first electrode 25 may contact the ohmic contact. You can also expose only the parts you want to do. After that, the surface of the receptor substrate 23 was back-polished to a thickness of about 100 μm to make a mirror surface.

Thereafter, as illustrated in FIG. 3F, the oxide layer 20 is etched to form a via hole electrically connected to the via hole 27. Since the oxide film 20 is an insulator, in order to electrically connect the first electrode and the second electrode, a via hole connected to the via hole 27 must be formed in the oxide film 20.

Thereafter, as shown in FIG. 3G, the second electrode 26 is formed. The second electrode 26 is formed over the receptor substrate 23 and the via hole 27 and is electrically connected to the ohmic electrode 19 through the via hole 27. After dicing the wafer into the device size, the manufacturing of the light emitting device is completed.

Fourth Embodiment

 4 is a view illustrating an intermediate manufacturing process of a vertical electrode light emitting diode according to a fourth embodiment of the present invention. The vertical geometry light emitting diode of this embodiment has the following structure.

The first ohmic contact layer 13, the first cladding layer 14, the light emitting layer 15, the second cladding layer 16, the second ohmic contact layer 17, and the ohmic electrode 19 are sequentially formed. The oxide film 20 is formed on the ohmic electrode 19, and the light transmissive electrode or the transparent electrode 28 is formed on the exposed first ohmic contact layer 13 by removing all the sapphire base substrates. The first electrode 25 is formed on the transparent electrode or the transparent electrode 28. The first ohmic contact layer may be n-type, and the second ohmic contact layer may be p-type. The second electrode 26 is formed on the via hole 27 and the oxide film 20 to be electrically connected to the ohmic electrode 19. In this embodiment, the oxide film 20 itself serves as a receptor substrate.

The vertical electrode type light emitting diode of the fourth embodiment is formed of the nitride semiconductor layer 12, 13, 14, 15, 16, 17, deposition of the ohmic electrode 19 and the eutectic metals 21, 22, and a sapphire base substrate. The detailed manufacturing process of lapping and etching (11) and the formation of the second electrode is the same as in the first embodiment, and after the sapphire base substrate is etched and removed, the light-transmissive electrode or the transparent electrode 28 is formed and the light-transmissive electrode or the transparent Forming the first electrode 25 on the electrode 28 is different from the first embodiment. After etching the sapphire base substrate, the buffer layer is etched to expose the first ohmic contact layer 13 and the light transmissive electrode or the transparent electrode 28 is deposited. At this time, the transparent electrode 28 is preferably made of ITO, ZnO, and serves to facilitate current diffusion and increase light extraction efficiency. When the light transmissive electrode 28 is formed, at least one of Ni, Au, Pt, Al, and Ti is formed.

Fifth Embodiment

5 is a cross-sectional view of a vertical electrode light emitting diode according to a fifth embodiment of the present invention. The vertical electrode type light emitting diode of this embodiment has the following structure.

The second eutectic metal 22, the first eutectic metal 21 and the second eutectic metal 22 formed on the receptor substrate 23 are bonded by thermocompression bonding, and the first eutectic metal 21 The ohmic electrode 19 is formed on (). On the ohmic electrode 19, a second ohmic contact layer 17, a second cladding layer 16, a light emitting layer 15, a first cladding layer 14, a first ohmic contact layer 13, a light transmission An electrode or transparent electrode 28 and a first electrode 25 exist, and the light transmissive electrode or transparent electrode 28 is formed on the first ohmic contact layer 13 by removing all the sapphire base substrates. The first ohmic contact layer may be n-type, and the second ohmic contact layer may be p-type. The second electrode 26 is formed on the via hole 27 and the receptor substrate 23 to be electrically connected to the ohmic electrode 19.

The vertical electrode type light emitting diode of the fifth embodiment is formed of nitride semiconductor layers 12, 13, 14, 15, 16, 17, deposition of ohmic electrodes 19 and eutectic metals 21, 22, sapphire base substrates. The detailed manufacturing process of lapping and etching (11), and the formation of the second electrode is the same as in the second embodiment, and after the sapphire base substrate is etched and removed, the light-transmissive electrode or the transparent electrode 28 is formed and the light-transmissive electrode or the transparent Forming the first electrode 25 on the electrode 28 is different from the second embodiment. After etching the sapphire base substrate, the buffer layer is etched to expose the first ohmic contact layer 13 and the light transmissive electrode or the transparent electrode 28 is deposited. At this time, the transparent electrode 28 is preferably made of ITO, ZnO, and serves to facilitate current diffusion and increase light extraction efficiency. When the light transmissive electrode 28 is formed, at least one of Ni, Au, Pt, Al, and Ti is formed.

Sixth Embodiment

6 is a cross-sectional view of a light emitting diode having a vertical electrode structure according to a sixth embodiment of the present invention. The vertical electrode type light emitting diode of this embodiment has the following structure.

The second eutectic metal 22, the first and second metals 21 and 22, which are formed on the receptor substrate 23, are bonded by thermocompression bonding, and the first eutectic metal 21 ), An ohmic electrode 19 and an oxide film 20 are formed. A second ohmic contact layer 17, a second cladding layer 16, a light emitting layer 15, a first cladding layer 14, a first ohmic contact layer 13, and a light transmissive electrode on the oxide film 20. Alternatively, the transparent electrode 28 and the first electrode 25 exist, and the light transmissive electrode or the transparent electrode 28 is formed on the first ohmic contact layer 13 by removing all the sapphire base substrates. The first ohmic contact layer may be n-type, and the second ohmic contact layer may be p-type. The second electrode 26 is formed on the via hole 27 and the receptor substrate 23, and is electrically connected to the ohmic electrode 19.

The vertical electrode type light emitting diode of the sixth embodiment is formed of the nitride semiconductor layers 12, 13, 14, 15, 16, 17, deposition of the ohmic electrode 19 and the eutectic metals 21, 22, and a sapphire base substrate. The detailed manufacturing process of lapping and etching (11), and forming the second electrode is the same as in the third embodiment, and after the sapphire base substrate is etched and removed, the light transmitting electrode or the transparent electrode 28 is formed and the light transmitting electrode or the transparent Forming the first electrode 25 on the electrode 28 is different from the third embodiment. After etching the sapphire base substrate, the buffer layer is etched to expose the first ohmic contact layer 13 and the light transmissive electrode or the transparent electrode 28 is deposited. At this time, the transparent electrode 28 is preferably made of ITO, ZnO, and serves to facilitate current diffusion and increase light extraction efficiency. When the light transmissive electrode 28 is formed, at least one of Ni, Au, Pt, Al, and Ti is formed.

As described above, in the vertical electrode light emitting diode having the same structure as the present invention, since the first electrode 25 and the second electrode 26 are formed on both upper and lower sides of the chip, the light emitting diode having the vertical electrode structure can be manufactured. As a result, the chip area can be reduced, thereby greatly improving the chip yield per wafer.

In addition, since a via hole is formed in the receptor substrate 23 to electrically connect the first electrode and the second electrode, an insulator can be used as a receptor substrate. Even if the conductor is used as the receptor substrate, a SiO ₂ film is used to form a nitride system. There is an advantage that the semiconductor layer can be effectively protected from the etching solution of the sapphire base substrate.

In addition, since a via hole is formed in the receptor substrate 23 and the first electrode 25 is formed of metal, heat and static electricity are efficiently discharged through the first electrode 25 and the second electrode 26. It greatly contributes to improving the reliability of the device. In addition, since the current flows uniformly through the entire area of the chip, driving is possible even at a large current, and high light output can be obtained even in a single device.

The characteristics of such devices satisfy the high luminance characteristic, which is an essential requirement for the back light unit of lighting and liquid crystal display devices.

In the present invention, since the sapphire substrate is removed using back grinding and dry or wet etching, productivity is greatly improved, and thermal damage that an epitaxial layer can receive in the case of a laser lift-off method can be prevented. In addition, by utilizing the etching selectivity between the sapphire substrate and the nitride semiconductor can be easily improved the reproducibility of the process, and the standardized process is possible to facilitate mass production.

While the invention has been shown and described with respect to particular embodiments, it will be understood that various changes and modifications can be made in the art without departing from the spirit or scope of the invention as set forth in the claims below. It will be appreciated that those skilled in the art can easily know.

Claims (27)

delete delete delete delete delete delete delete delete delete delete delete delete delete a. forming a plurality of nitride based semiconductor layers on the sapphire base substrate; b. forming an ohmic electrode layer on the nitride based semiconductor layer; c. forming an oxide layer on the ohmic electrode layer; d. after the sapphire base substrate is processed to a predetermined thickness, wet etching with a mixed solution of sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) to expose the nitride-based semiconductor layer; dry etching a buffer layer of the nitride based semiconductor layer exposed using a d1.RIE technique; e. forming a first electrode on the exposed nitride based semiconductor layer; f. forming a via hole to expose the ohmic electrode layer by etching the oxide layer; And g. forming a second electrode over the oxide layer and the via hole. a. forming a plurality of nitride based semiconductor layers on the sapphire base substrate; b. forming an ohmic electrode layer on the nitride based semiconductor layer; c. forming a first eutectic metal layer on the ohmic electrode layer; d. forming a second eutectic metal layer on one side of the receptor substrate, and forming a via hole penetrating the receptor substrate and the second eutectic metal layer; e. adhering the first eutectic metal layer and the second eutectic metal layer; f. forming a passivation layer over the receptor substrate and the via hole; And g. after the sapphire base substrate is processed to a predetermined thickness, wet etching with a mixed solution of sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) to expose the nitride semiconductor layer; dry etching a buffer layer of the nitride based semiconductor layer exposed using a g1.RIE technique; h. forming a first electrode on the exposed nitride based semiconductor layer; i. completely etching the passivation layer to expose the via hole; And j. forming a second electrode over the receptor substrate and the via hole. a. forming a plurality of nitride based semiconductor layers on the sapphire base substrate; b. forming an ohmic electrode layer on the nitride based semiconductor layer; c. forming an oxide layer on the ohmic electrode layer; d. forming a first eutectic metal layer on the oxide layer, and forming a via hole to expose the oxide layer by etching the first eutectic metal layer; e. forming a second eutectic metal layer on one side of the receptor substrate, and forming a via hole penetrating through the receptor substrate and the second eutectic metal layer at a position coincident with the via hole on the first eutectic metal layer; f. adhering the first eutectic metal layer and the second eutectic metal layer; g. after the sapphire base substrate is processed to a predetermined thickness, wet etching with a mixed solution of sulfuric acid (H ₂ SO ₄ ) and phosphoric acid (H ₃ PO ₄ ) to expose the nitride semiconductor layer; dry etching a buffer layer of the nitride based semiconductor layer exposed using a g1.RIE technique; h. forming a first electrode on the exposed nitride based semiconductor layer; i. Etching the exposed oxide film through the via holes of the first and second eutectic metal layer and the receptor substrate; And j. forming a second electrode over the receptor substrate and the via hole. The method of claim 14, and d2. forming a light transmissive electrode or a transparent electrode on the exposed nitride-based semiconductor layer, wherein the step e is to form a first electrode on the light transmissive electrode or the transparent electrode. Manufacturing method of polar light emitting diode. The method of claim 15 or 16, further comprising g2. Forming a light transmissive electrode or a transparent electrode on the exposed nitride-based semiconductor layer, wherein step h is a first on the light transmissive electrode or transparent electrode A method of manufacturing a vertical electrode type light emitting diode, characterized in that to form an electrode. 18. The method of claim 17, wherein the transparent electrode is made of indium tin oxide (ITO) or ZnO. 19. The method of claim 18, wherein the transparent electrode is made of indium tin oxide (ITO) or ZnO. 18. The method of claim 17, wherein the light transmissive electrode is formed of at least one of Ni, Au, Pt, Al, and Ti. 19. The method of claim 18, wherein the light transmissive electrode is formed of at least one of Ni, Au, Pt, Al, and Ti. The method of claim 14, wherein the step b includes at least one of Pd, Rh, Pt, Ta, Ni, Cr, Au, and Ti, and includes oxygen or nitrogen. A method of manufacturing a vertical electrode type light emitting diode, characterized in that the heat treatment for 2 minutes at a temperature of 450 ℃ to 700 ℃ in the furnace. The method of claim 15, wherein the step e is performed in a gas atmosphere including at least one of Ar, He, Kr, Xe, and Rn. The method of claim 16, wherein the step f is performed in a gas atmosphere including at least one of Ar, He, Kr, Xe, and Rn. delete delete

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