JP2629625B2 - Method for growing semiconductor layer on heterogeneous substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for growing a high quality semiconductor single crystal layer on a heterogeneous semiconductor single crystal substrate, and more particularly to a method for growing a semiconductor single crystal layer on a heterogeneous semiconductor substrate having a different lattice constant. Things.

[0002]

2. Description of the Related Art In recent years, Ge / Si, GaAs / Si, I
Attempts have been actively made to heteroepitaxially grow a semiconductor single crystal layer on a crystal substrate having a different lattice constant such as nP / GaAs. This is because, if such a structure can be formed, an optoelectronic integrated circuit composed of, for example, an InP-based long-wavelength optical element having a different lattice constant from a GaAs-based ultra-high-speed element can be realized, and is free from the restrictions imposed by the lattice constant of the substrate crystal. Therefore, a mixed crystal semiconductor layer having an arbitrary composition (lattice constant) that is advantageous for high performance or the like can be used as a device layer.

Further, a non-polar group IV semiconductor single crystal substrate typified by Si is formed on a non-polar group IV semiconductor single crystal substrate typified by GaAs or InP.
If a -V compound semiconductor can be grown, a III-V high-performance device can be manufactured on an inexpensive Si substrate, and the performance of an optical device and the like can be improved by the high thermal conductivity of Si. Also, if a Si ultra-high-integrated circuit and a III-V compound semiconductor ultra-high-speed device or optical device can be formed on the same substrate, it is expected that a path to the development of a new high-performance device will be opened.

However, in heteroepitaxial growth of a lattice-mismatched system, a large number of misfit dislocations are generated at a lattice-misaligned interface, and in general, most of the misfit dislocations penetrate to an upper device layer, so that crystallinity is significantly reduced.

[0005] Further, on a nonpolar Si substrate, for example, III
Ga, a polar crystal composed of two kinds of elements of group V and group V
When growing As, Si (100) which is usually used is used.
On the substrate, a region where the arrangement of the group III and group V is out of phase and the polarity is inverted, a so-called anti-phase domain (AP)
D) is easy to do.

[0006] This problem is caused, for example, by the magazine "Japanese
Journal of Applied Physics (Jpn.
J. Appl. Phys. ) "Vol. 24, No. 6 (198
5 years) on page L391-393, a method called "two-stage growth method", that is, from (100) to <
A fine polycrystalline or amorphous GaAs buffer layer of about 20 nm is first deposited at a low temperature of 450 ° C. or less using a Si substrate turned off in the <011> direction, and then a normal growth temperature. A method of growing a GaAs single crystal thin film at 600 ° C. can be avoided for the time being, and a single domain single crystal thin film can be obtained. However, this method utilizes a mechanism in which only one of the domains becomes dominant as the crystal grows. Since APD is generated near the Si / GaAs interface, high-density crystal defects are generated at the stage of APD generation. It penetrates to the upper part together with the misfit dislocation, and the effect of suppressing the occurrence of dislocation cannot be expected.

The two-step growth method is effective as a method for obtaining a flatter surface and good crystallinity as compared with conventional direct growth even in general lattice-mismatched heteroepitaxial growth. However, the dislocation density is about 10 ⁸ cm on the growth surface having a thickness of several μm in any case including on a nonpolar substrate.
^-2 .

Therefore, when GaAs is subsequently grown on the Si substrate, a strained superlattice intermediate layer and a thermal cycle annealing method are introduced (they may be used in combination), and these are used in about 10 ^6. The dislocation density improved rapidly to cm ⁻² (Applied Physics Letters, Magazine 54, No. 1 (1989), pp. 24-26). However, a result of ^less than about 10 ⁶ cm ^-2 is not easily obtained, and the cause was pointed out by a problem of a difference in thermal expansion coefficient between the Si substrate and the III-V compound semiconductor ("Applied Physics Letters magazine"). Vol. 56, No. 22 (1990),
Pp. 2225-2227). That is, at the growth temperature (650 ° C.) due to the introduction of thermal cycle annealing, etc., 1
Although the dislocation density has decreased to 0 ⁵ cm ^-2 or less, during cooling after growth, the dislocation density is reduced by 10 ⁶ due to stress due to a difference in thermal expansion coefficient.
cm- ² dislocations are introduced. It is considered that this is because a large number of dislocations remaining near the interface with the Si substrate rise due to thermal strain. Note that 45
At a growth temperature of about 0 ° C. or lower (in the case of GaAs), the movement speed of the dislocation decreases, so that the introduction of the dislocation decreases, and the dislocation remains as a large residual thermal strain.

Now, in order to fundamentally avoid the problem of the difference in the coefficient of thermal expansion, it is sufficient to grow at a low temperature. For example, the magazine "Japanese Journal of Applied Physics", Vol. 30, No. 4B (1991), L668-6
In the example described on page 71 in which a strained superlattice intermediate layer is formed by using a migration enhanced epitaxial growth method (MEE method) in which Ga atoms and As atoms are alternately supplied in a high vacuum, a temperature of 580 ° C. GaAs is grown at a low temperature of 300 ° C. except for annealing. At a low temperature, the dislocation movement speed is reduced, and the introduction of the strained superlattice intermediate layer allows the threading dislocation to be effectively bent toward the interface. As a result, the dislocation density has been reduced to 7 × 10 ⁴ cm ^-2 by breaking through the 10 ⁶ cm ^-2 wall.

[0010] The magazine "Japanese Journal.
Of Applied Physics, Vol. 31, No. 5B (1
992), pages L628-631.
In the method of growing GaAs on Si by a two-step growth (200 ° C./580° C.) method and then irradiating it with atomic hydrogen (hydrogen radicals) at a low temperature of 330 ° C., the GaAs is grown in the crystal. Threading dislocations are bent or pinned by any action of the incorporated hydrogen, again resulting in a low dislocation density of 7 × 10 ⁴ cm ⁻² . However, in the example in which Ge is grown on a Si substrate by MBE while irradiating it with atomic hydrogen at a low temperature of 400 ° C. or less, two-dimensional growth has been successfully obtained, but reduction of dislocation density has been required. Not reached (Magazine "Applied Physics Letters" Vol. 64 No. 1 (1994
Pp. 52-54).

On the other hand, when InP is grown on a Si substrate (typically, a GaAs buffer layer is inserted),
Even when a strained superlattice intermediate layer or a thermal cycle annealing method, which has achieved certain results when GaAs is grown on Si, is introduced, the dislocation density is considerably high at about 10 ⁷ cm ^-2 (Journal "Journal. Of Crystal Growth, Vol. 99 (1
990), 365-370). The same applies to the growth of InP on a GaAs substrate having a smaller difference in thermal expansion coefficient and no problem of APD generation (Japanese magazine “Japanese Journal of Applied Physics” No. 32).
Vol. 1B (1993), pp. 614-617). Therefore, when InP is grown on a Si or GaAs substrate, a dislocation reduction effect cannot be sufficiently obtained by introducing a strained superlattice intermediate layer or thermal cycle annealing before a thermal strain problem due to a difference in thermal expansion coefficient. Conceivable.

By the way, in heteroepitaxial growth on a heterogeneous substrate, a layer having a large lattice mismatch is not suddenly grown but a gradient composition buffer layer for gradually changing the composition (lattice constant) continuously or stepwise is sandwiched. Has been known for a long time. For example, relatively recently
JP-A-61-26 using an nAlAs lattice mismatch buffer layer
The method described in 8069 JP, The In _x Ga _1-x
There is a method described in JP-A-3-46241 using an As gradient composition layer. More recently, an In _x Ga _{1 -x} As graded composition layer has been interposed at a low temperature on a GaAs substrate.
_In the case of growing _0.5 Ga _0.5 As, a very low dislocation density of 10 ⁴ cm ⁻² or less has been reported (Journal of Journal of Applied Physics, Vol. 72, No. 5).
(1992), pp. 1752-1757).

[0013]

The above prior art employed for obtaining a good quality semiconductor film on a non-polar or crystal substrate having a different lattice constant still has the following problems.

In the above-mentioned method of obtaining a crystal having a low dislocation density by introducing a strained superlattice intermediate layer by the low-temperature MEE technique, Ga atoms and As atoms are grown in a high vacuum in order to obtain a sufficiently two-dimensional growth.
It is necessary to supply the atoms alternately, and there is a problem that the substantial growth rate is remarkably slow as compared with the ordinary simultaneous supply method, and the shutter mechanism is heavily used, which tends to cause a breakdown. In addition, during growth at low temperature, the dislocation movement speed is reduced. Therefore, when the dislocation movement is increased to a normal growth temperature of about 600 ° C. where the movement of the dislocation is active, the dislocation density is again reduced to about 10 ⁶ cm ^{−2 due} to thermal strain. Proliferate to

The method of irradiating atomic hydrogen (hydrogen radicals) is also a phenomenon at a low temperature in which the dislocation movement speed is reduced. Further, since the dislocation movement is suppressed by the action of hydrogen, the lattice mismatch strain is reduced. The relaxation does not proceed, and the residual thermal strain increases greatly. Further, when heated to about 400 ° C. or more, the hydrogen taken into the crystal rapidly desorbs or changes its form, so that there is a problem in that the dislocation density increases greatly to about 10 ⁸ cm ⁻² due to residual thermal strain. Was.

Further, the above-mentioned report that the growth of MB by the MBE method while irradiating Ge with atomic hydrogen at a low temperature on a Si substrate has little effect on the reduction of dislocation density (see Applied Physics. Letters, Vol. 64, No. 1, (1994), pp. 52-54), it is thought that the transition density cannot be effectively reduced simply by irradiation with atomic hydrogen at a low temperature.

On the other hand, In _x Ga _{1 -x is formed} on GaAs at a low temperature.
In the method of sandwiching the As graded composition layer, In is changed from In _0.5 Ga _0.5 As to In _0.53 Ga _0.47 As lattice-matched to InP.
When the composition is increased, there is a problem that the dislocation density rapidly increases. Moreover, excluding the report of In _0.5 Ga _0.5 As / GaAs, the method described in JP-A-61-268069 and JP-A-3-46241 includes the method of sandwiching the gradient composition layer at 10 ⁶ cm ^−2. There is no report that a dislocation density lower than. Further, conventionally, in this method, a cross hatch is observed on the growth surface, and sufficient surface flatness is not obtained.

The present invention has been made in view of such a situation, and an object of the present invention is to provide a method for growing a high-quality semiconductor single crystal layer on heterogeneous semiconductor single crystal substrates having different lattice constants. It is.

[0019]

To achieve the above object, according to the first aspect of the present invention, (1) growing a lattice mismatch buffer layer on a semiconductor substrate directly or via a substrate-side buffer layer. And (2) growing a semiconductor device layer directly or on the device layer side buffer layer after forming it on the lattice mismatch buffer layer,
Wherein when growing the lattice mismatch buffer layer and / or the device layer side buffer layer, 1
A layer formed by irradiating atomic hydrogen between the semiconductor substrate or the substrate side buffer layer and the semiconductor device layer by irradiating atomic hydrogen a plurality of times and a layer formed without irradiating atomic hydrogen are mixed. A method of growing a semiconductor layer on a heterogeneous substrate, characterized by growing these layers as described above.

Preferably, the growth of the lattice mismatch buffer layer is performed at a low temperature of 400 ° C. or less, and the crystal plane orientation of the semiconductor substrate is set to around (100) within one degree of error. In addition, the lattice mismatch buffer layer may be any one of a continuous gradient composition part in which a lattice constant changes continuously, a discontinuous gradient composition part in which a lattice constant changes stepwise, and a strained superlattice layer. It is configured to include the combination.

According to the second aspect of the present invention, GaAs
s in (GaP) substrate or GaAs (GaP) buffer _{layer, In x Al y Ga 1-} xy As (In x Al y G
a _1-xy P) to In _z Al _1-z As (In _z Al _1-z
Growing a gradient composition buffer layer up to P) and growing a semiconductor device layer thereon, wherein the GaAs (GaP) substrate or the GaAs
The plane orientation of the (GaP) buffer layer is adjusted within (10 degrees)
0) is set near, the composition ratio x of In is changed continuously or stepwise from 0 to z, the composition ratio y of Al is changed continuously or stepwise from 0 to 1-z, and Growing the gradient composition buffer layer at a low temperature of 400 ° C. or lower, a method for growing a semiconductor layer on a heterogeneous substrate is provided.

[0022]

For example, when an In _x Ga _{1 -x} As graded composition layer is grown on GaAs by MBE, the substrate temperature is set to a low value of about 450 ° C. or less, and the composition (lattice constant) change rate is reduced. If it is set smaller, two-dimensional growth can be obtained, and the RHEED pattern on the surface can maintain almost streak. Strictly, however, a slight undulation occurs, which is observed as a cross hatch on the growth surface. According to the growth experiments and evaluation results of the present inventor, most of threading dislocations occurred in the cross hatch portion, that is, the waviness portion. That is, in order to reduce threading dislocations, it is necessary to further improve the two-dimensional growth.

The irradiation effect of atomic hydrogen, besides the effect of bending and pinning of threading dislocations, has not yet been fully elucidated, but has a function of further improving two-dimensionality. Is Ge on the aforementioned Si substrate.
Is also described in an example of MBE growth and JP-A-63-117989.

Therefore, in the present invention, when the gradient composition layer is grown by, for example, the MBE method, the two-dimensionality of the growth is further improved by simultaneously irradiating atomic hydrogen. In the gradient composition layer formed in this manner, the undulation observed as a cross hatch can be significantly reduced, and thus threading dislocations can be greatly reduced. The irradiation technique of atomic hydrogen can also be applied to the case where a threaded dislocation is bent toward an interface by introducing a strained superlattice intermediate layer.

That is, by combining the optimization of the growth conditions and the irradiation of atomic hydrogen, the same two-dimensional growth can be performed without employing the growth method by the MEE method. Here, the growth temperature is 400
By controlling the temperature to not more than ℃, the two-dimensional growth can be made more complete. In addition, when the plane orientation of the substrate crystal is in the vicinity of the (100) plane, the use of the (100) plane that is as accurate as possible becomes more two-dimensional in growth with strain. (10
It is desirable to use the 0) plane.

Thus, when the crystal is grown at a low temperature while irradiating with atomic hydrogen, the movement of the dislocation is largely suppressed, possibly due to the pinning action by the hydrogen taken into the crystal. Although this action also contributes to the reduction of threading dislocations,
On the other hand, it also suppresses generation of dislocations in the inward direction of the lattice mismatch interface, which is originally required for relaxing lattice mismatch strain. Therefore, in the present invention, the irradiation is performed only on a part of the upper and lower layers including the lattice mismatch interface, instead of irradiating the entire surface with irradiation with atomic hydrogen. As a result, dislocations necessary for alleviating lattice mismatch strain can be introduced into the crystal, residual thermal strain can be reduced, and re-generation of threading dislocations can be suppressed by annealing after growth. It is effective that the irradiation of atomic hydrogen is performed only on the upper layer side across the lattice mismatch interface. Therefore, for example, in the case of a step-like gradient composition structure, irradiation of atomic hydrogen is performed only at the beginning of growth of each layer.

As described above, by combining the lattice mismatch buffer layer and the partial irradiation of atomic hydrogen, the two-dimensional growth can be improved and the pinning effect of threading dislocation can be utilized. The transition necessary for relaxing the lattice mismatch strain can be introduced into the crystal to reduce the residual stress.

Further, on a GaAs (GaP) substrate or G
When a heterogeneous semiconductor device layer is grown on the aAs (GaP) buffer layer, In _x Al _y G
_{a 1-xy As (In x} Al y Ga 1-xy P) from In _z
By interposing a gradient composition buffer layer reaching Al _{1 -z} As (In _z Al _{1 -z} P) and optimizing the growth conditions of the gradient composition buffer layer, a good quality crystal with few dislocations can be obtained. .

[0029]

Embodiments of the present invention will be described below in detail with reference to the drawings. [First Embodiment] FIG. 1A is a cross-sectional view of an epitaxial growth substrate formed according to a first embodiment of the present invention, and FIG. 1B is an enlarged view of a main part thereof. In this embodiment, irradiation of atomic hydrogen is possible, and arsine (AsH ₃ )
And phosphine (PH ₃ ) cracking (pyrolysis)
GaAs using a gas source MBE device
InP was grown on the substrate with the In _x Al _y Ga _1-xy As gradient composition buffer layer interposed therebetween.

As shown in FIG. 1A, GaAs (10
0) Eight stages (0.2 μm each) on just substrate 1
m) In _x Al _y Ga _1-xy A with changed In composition
s gradient composition buffer layer 2 and 1 μm thick InP
The device layer 3 was grown. _{In x Al y Ga 1-xy} A
The lattice constant of the s-graded composition buffer layer 2 is changed stepwise from near GaAs until it almost matches InP.
Was added from the 4th stage, and the final 8th stage was In _x Al _1-x As which almost matched InP.

Specifically, (x, y) = (0.15,
0), (0.2, 0), (0.3, 0), (0.35,
0.1), (0.4, 0.2), (0.45, 0.
3), (0.5, 0.4) and (0.52, 0.48) were changed in eight steps. FIG. 1B shows the fourth stage In.
_0.35 Al _0.1 Ga _0.55 As layer 4 and fifth stage In _0.4
The Al _0.2 Ga _0.4 As layer 5 and the sixth stage of In _0.45 Al
_0.3 Ga _0.25 As layer 6 is shown.

As shown in FIG. 1B, the irradiation of atomic hydrogen was performed only in the first half of each step of the In _x Al _y Ga _1-xy As gradient composition buffer layer 2 at 0.1 μm. The growth temperature at the first stage was 380 ° C., the temperature was lowered by 10 ° C. in each stage, and the final eighth stage was grown at 300 ° C. InP device layer 3
Was grown at 480 ° C.

Photoluminescence (PL) measurement performed to examine the crystal quality of the obtained InP device layer 3 showed emission intensity comparable to that of the growth layer on the InP substrate. As a result of the measurement of the etch pit density (EPD) and the observation by the transmission electron microscope (TEM), the dislocation density was 1
It was found that good crystal quality was obtained at 0 ⁵ cm ^-2 or less.

A similar structure was grown without irradiation with atomic hydrogen. In this case, the dislocation density was about 10 ⁶ c.
At about m- ² , good results were obtained as compared with the conventional example. In other words, the dislocation density in the case of directly growing InP in two stages directly on a conventional GaAs substrate is limited to about 10 ⁷ cm ⁻² , but the graded composition buffer layer having an appropriate composition is selected and the growth conditions are optimized. The crystal quality could be significantly improved only by changing the crystallinity.

In this embodiment, In _x A is deposited on a GaAs substrate.
l _y Ga _1-xy As
Has been described as an example in which GaP or Ga is grown.
When GaAs or InP is grown on an As substrate with an In _x Al _y Ga _1-xy P gradient composition buffer layer interposed therebetween, or when these are combined, the In
When P is grown, when further grown on a Si substrate, or when In is not lattice-matched with InP or GaAs, etc.
The same applies to a case where a crystal layer having an intermediate composition such as Ga (Al) As, InGa (Al) P, or GaAsP is used as a device layer.

[Second Embodiment] FIG. 2A is a sectional view of an epitaxial growth substrate formed according to a second embodiment of the present invention, and FIG. 2B is an enlarged view of a main part thereof. .
In this embodiment, a GaAs buffer layer and InGaAs / GaAs are formed on a Si substrate using a gas source MBE device.
A GaAs device layer was grown with the strained superlattice layer interposed.

As shown in FIG. 2A, Si (100)
A GaAs buffer layer 22 having a thickness of 1 μm is grown on a 2 ° off substrate 21 by a two-step growth method (300 ° C./480° C.), and then the substrate temperature is lowered to 300 ° C. and InGaAs is formed.
/ GaAs strained superlattice layer 23, also at 300 ° C.
A 5 μm upper GaAs buffer layer 24 was grown, and finally, the substrate temperature was raised to 550 ° C. to grow a 1 μm thick GaAs device layer 25.

InGaAs / GaAs strained superlattice layer 23
Is, as shown in FIG. 2B, a 10 nm-thick In film.
It is composed of 10 periods of a _0.2 Ga _0.8 As layer 26 and a GaAs layer 27 having a thickness of 20 nm. Irradiation of atomic hydrogen is performed by using InGaAs / G as shown in FIG.
The first six periods of the aAs strained superlattice layer 23 and the upper GaAs
This was performed when the s buffer layer 24 was grown.

The formed sample was evaluated by EPD measurement and TEM observation. As a result, it was found that the dislocation density in the GaAs device layer 25 was 10 ⁵ cm ⁻² or less and good crystal quality was obtained.

In this embodiment, the GaAs buffer layer is formed with GaAs with an InGaAs / GaAs strained superlattice layer interposed.
The case where the s layer is grown has been described as an example, but InGaP /
GaAs, GaAsP / GaAs, and InGaAs /
An AlAs strained superlattice layer or the like may be used. GaAs
Not only the lattice matching system but also an InP system or a mixed crystal system having an intermediate composition may be used as a basis, and an appropriate strained superlattice layer can be used. Also, instead of the strained superlattice layer, InGaAs
For example, a single thin constant composition strain layer, a continuous gradient composition strain layer, or a step gradient gradient composition strain layer may be used.

[Third Embodiment] FIG. 3 is a sectional view of an epitaxial growth substrate formed according to a third embodiment of the present invention. In the present embodiment, a GaP buffer layer and In _x Ga
_A GaAs layer was grown with a _1-x P continuous gradient composition buffer layer interposed therebetween.

As shown in FIG. 3, Si (100) 2 ° o
0.5 μm thick GaP buffer layer 3 on ff substrate 21
1 is grown by a two-step growth (300 ° C./400° C.) method, and then the substrate temperature is lowered to 300 ° C. and a 1 μm thick In
_x Ga _1-x P continuous gradient composition buffer layer 32, also 30
A 0.5 μm thick upper GaAs buffer layer 24 is grown at 0 ° C., and finally, the substrate temperature is increased to 550 ° C. and the thickness is reduced to 1 μm.
A m GaAs device layer 25 was grown. The composition x of In in the continuously gradient composition buffer layer 32 was continuously changed at a constant rate from 0 to a value almost lattice-matched to GaAs. Irradiation of atomic hydrogen is applied to the upper GaAs buffer layer 24.
Made only when growing.

The formed sample was evaluated by EPD measurement and TEM observation. As a result, it was found that the dislocation density in the GaAs device layer 25 was 10 ⁵ cm ⁻² or less and good crystal quality was obtained.

This embodiment can also be applied to any crystal system other than the above combination. Irradiation of atomic hydrogen can be performed once or more times on the side of the In _x Ga _{1 -x} P continuous gradient composition buffer layer 32. Upper G
In the aAs buffer layer 24, the irradiation may be performed only in the In _x Ga _1-x P continuous gradient composition buffer layer 32 without irradiating atomic hydrogen.

[Fourth Embodiment] FIG. 4A is a sectional view of an epitaxial growth substrate formed according to a fourth embodiment of the present invention, and FIG. 4B is an enlarged view of a main part thereof. .
In this embodiment, GaAs is used by using a gas source MBE device.
InP was grown on the substrate with the (InAs) _m (GaAs) _n short-period strained superlattice layer interposed therebetween.

As shown in FIG. 4A, GaAs (10
0) (InAs) ₁ (GaAs) ₅ short-period strain superlattice layer 41 each having a thickness of 0.2 μm on just substrate 1
(InAs) ₁ (GaAs) ₂ short-period strained superlattice layer 42,
A (InAs) ₁ (GaAs) ₁ short-period strained superlattice layer 43 is sequentially grown at a growth temperature of 300 ° C., and further an InGaAs / InAlAs superlattice layer 4 having a thickness of 0.3 μm at 300 ° C.
4 (In _0.53 Ga _0.47 As: 30 nm, In _0.52 Al
_0.48 As: 30 nm, _x5 cycles).

As shown in FIG. 4B, the irradiation of atomic hydrogen is performed on the 0.15 μm of the three short-period strain superlattice layers 41, 42, 43 in the initial stage of growth, and the superlattice layer 44. went. Finally, an InP device layer 3 having a thickness of 1 μm was grown at a growth temperature of 480 ° C.

The formed sample was evaluated by EPD measurement and TEM observation. As a result, it was found that the dislocation density in the InP device layer 3 was 10 ⁵ cm ⁻² or less and good crystal quality was obtained.

This embodiment can also be applied to any crystal system other than the above combination.
P) _m (GaP) _n GaAs sandwiching the short-period strained superlattice layer
Alternatively, InP may be grown. Also, InGaAs
Irradiation of atomic hydrogen on the / InAlAs superlattice layer 44 may be partially performed, or may not be performed on this superlattice layer.

[Modifications of Embodiments] Although the preferred embodiments have been described above, the present invention is not limited to these embodiments, but can be appropriately modified within the scope described in the claims. It is. For example, in the embodiment, as the lattice mismatch buffer layer, a continuous gradient composition buffer layer, a stepwise gradient composition buffer layer, a strain superlattice layer, a short-period strain superlattice layer, and the like are used. These buffer layers may be used in combination, such as forming a strained superlattice layer in a part of them.

In the embodiment, on the Si substrate or III-
Although the growth of a lattice-mismatched group III-V compound semiconductor on a group V compound semiconductor substrate has been described, the substrate may be Ge or II.
Group VI compound semiconductor, and a group IV mixed crystal semiconductor such as SiGe or ZnS, ZnS
The present invention can be applied to a case where a II-VI group compound semiconductor such as e is used.

Also, an example in which the (100) plane which is generally used is used as the plane orientation of the crystal has been described. However, other planes such as (111) plane, higher-order planes such as (211) and (311), and furthermore, From these, almost the same effect can be expected even if the surface is turned off by an appropriate angle, although the degree is different.

The growth apparatus is a gas source MBE.
Although an example using the apparatus has been described, the present invention is not limited to this, as long as growth at a low temperature is possible. For example, a normal all-metal source MBE device can be used. However, in this case, a special device is required for the P source having a high vapor pressure. Further, a MOMBE apparatus or a MOCVD apparatus using a group III organic metal material may be used. In this case, it is desirable to select an organometallic material that is easily thermally decomposed so that the lattice mismatch buffer layer can be grown at 400 ° C. or lower.

[0054]

As described above, the method of growing a semiconductor layer on a heterogeneous substrate according to the present invention grows a buffer layer such as a lattice mismatch buffer layer while partially irradiating it with atomic hydrogen. As a result, a semiconductor layer with less threading dislocation can be obtained by realizing growth excellent in two-dimensionality, and a dislocation necessary for relaxation of lattice mismatching strain is introduced into the crystal to achieve residual thermal strain in the crystal. Can be reduced. Therefore, according to the present invention, a high-quality semiconductor single crystal layer can be grown on a heterogeneous semiconductor single crystal substrate.

Further, on a GaAs (GaP) substrate or G
When a device layer of a heterogeneous semiconductor is grown on the aAs (GaP) buffer layer, In _x Al _y Ga
_{1-xy As (In x Al} y Ga 1-xy P) from an In _z A
By interposing a gradient composition buffer layer reaching l _{1 -z} As (In _z Al _{1 -z} P) and optimizing the growth conditions of the gradient composition buffer layer, a high-quality crystal with few dislocations can be obtained. it can.

[Brief description of the drawings]

FIG. 1 is a sectional view of an epitaxial growth substrate formed according to a first embodiment of the present invention.

FIG. 2 is a sectional view of an epitaxial growth substrate formed according to a second embodiment of the present invention.

FIG. 3 is a sectional view of an epitaxial growth substrate formed according to a third embodiment of the present invention.

FIG. 4 is a sectional view of an epitaxial growth substrate formed according to a fourth embodiment of the present invention.

[Explanation of symbols]

1 GaAs (100) just substrate _{2 In x Al y Ga 1-} xy As graded composition buffer layer 3 InP device layer 4 In _0.35 Al _0.1 Ga _0.55 As layer (4 _{stage) 5 In 0.4 Al 0.2 Ga 0.4} As layer (5 Stage 6 In _0.45 Al _0.3 Ga _0.25 As layer (Sixth stage) 21 Si (100) 2 ° off substrate 22 GaAs buffer layer 23 InGaAs / GaAs strained superlattice layer 24 Upper GaAs buffer layer 25 GaAs device layer 26 In _0.2 Ga _0.8 As layer 27 GaAs layer 31 GaP buffer layer 32 In _x Ga _{1 -x} P continuous gradient composition buffer layer 41 (InAs) ₁ (GaAs) ₅ short-period strained superlattice layer 42 (InAs) ₁ (GaAs) ₂ short-period Strained superlattice layer 43 (InAs) ₁ (GaAs) ₁ Short-period strained superlattice layer 44 InGaAs / InAlAs superlattice layer

Claims (7)

(57) [Claims] (1) a step of growing a lattice mismatch buffer layer directly on a semiconductor substrate or via a substrate-side buffer layer; and (2) a step of growing a lattice mismatch buffer layer directly or on a device layer-side buffer layer. Forming a semiconductor device layer on the heterogeneous substrate after forming the semiconductor device layer on the heterogeneous substrate. A layer formed by irradiating atomic hydrogen between the semiconductor substrate or the substrate side buffer layer and the semiconductor device layer by irradiating atomic hydrogen a plurality of times and a layer formed without irradiating atomic hydrogen are mixed. A method for growing a semiconductor layer on a heterogeneous substrate, characterized by growing these layers. 2. The growth of the lattice mismatch buffer layer is performed by 40
2. The method for growing a semiconductor layer on a heterogeneous substrate according to claim 1, wherein the method is performed at a low temperature of 0 ° C. or less. 3. The semiconductor layer on a heterogeneous substrate according to claim 1, wherein the crystal plane orientation of the semiconductor substrate or the substrate-side buffer layer is set near (100) within one degree of error. Growth method. 4. The method for growing a semiconductor layer on a heterogeneous substrate according to claim 1, wherein a lattice constant of said semiconductor substrate or said substrate-side buffer layer matches that of said semiconductor device layer. 5. The strain-matched buffer layer, wherein the lattice-matched buffer layer is a continuously-graded composition part in which the lattice constant changes continuously, a discontinuously-graded composition part in which the lattice constant changes stepwise, or a strained superlattice layer. Or a combination thereof, wherein the lattice constant of the lowermost layer coincides with that of the semiconductor substrate or the buffer layer on the substrate side, and the lattice constant of the uppermost layer coincides with that of the semiconductor device layer. The method for growing a semiconductor layer on a heterogeneous substrate according to claim 1. 6. GaX (where, X is As or P) on the substrate or GaX buffer layer, In _x Al _y Ga
_A method for growing a semiconductor layer on a heterogeneous substrate, comprising growing a gradient composition buffer layer from _1-xy X to In _z Al _1-z X and growing a semiconductor device layer thereon, wherein the GaX substrate or the The plane orientation of the GaX buffer layer is set to be close to (100) within 1 degree of error, the composition ratio x of In is changed continuously or stepwise from 0 to z, and the composition ratio y of Al is 0 to 1−1. A method for growing a semiconductor layer on a heterogeneous substrate, wherein the gradient composition buffer layer is grown at a low temperature of 400 ° C. or lower while continuously or stepwise changing to z. 7. The method of growing a semiconductor layer on a heterogeneous substrate according to claim 6, wherein atomic hydrogen is irradiated during growth of at least a part of the gradient composition buffer layer.