JPH0461286A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0461286A JPH0461286A JP2171751A JP17175190A JPH0461286A JP H0461286 A JPH0461286 A JP H0461286A JP 2171751 A JP2171751 A JP 2171751A JP 17175190 A JP17175190 A JP 17175190A JP H0461286 A JPH0461286 A JP H0461286A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- gaas
- compound semiconductor
- impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 150000001875 compounds Chemical class 0.000 claims abstract description 30
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000012535 impurity Substances 0.000 claims abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 16
- 229910052710 silicon Inorganic materials 0.000 abstract description 16
- 239000010703 silicon Substances 0.000 abstract description 16
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 abstract description 2
- 238000010030 laminating Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 29
- 238000000034 method Methods 0.000 description 8
- 239000013078 crystal Substances 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 229910052738 indium Inorganic materials 0.000 description 5
- 229910052733 gallium Inorganic materials 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 238000005253 cladding Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 241000700560 Molluscum contagiosum virus Species 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 150000002344 gold compounds Chemical class 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 238000005382 thermal cycling Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
- Led Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体装置に関し、特にシリコン基板上に化合
物半導体層を形成した半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a compound semiconductor layer is formed on a silicon substrate.
（発明の背景）
ＧａＡｓなどの化合物半導体は、その優れた特徴を活か
して高性能、高機能デバイスに利用されつつあるか、化
合物半導体結晶は一般に高価てあり、大面積の高品質基
板結晶を得に（いという問題か付き纏う。一方、シリコ
ン基板は比較的安価で大面積化か可能であり、近時は、
このようなシリコン基板１に、Ｇ ａ、 Ａ ｓなどの
化合物半導体層を形成して各種デバイスを形成すること
か試みられている。(Background of the Invention) Compound semiconductors such as GaAs are being used for high-performance, high-performance devices by taking advantage of their excellent characteristics. Compound semiconductor crystals are generally expensive, and it is difficult to obtain large-area, high-quality substrate crystals. On the other hand, silicon substrates are relatively cheap and can be made into large areas, and these days,
Attempts have been made to form various devices by forming compound semiconductor layers such as Ga and As on such a silicon substrate 1.
例えばシリコン基板上に、Ｇａ Ａ ｓ層を形成する際
に、あらかじめ予備堆積層を形成しておき、次に通常の
成長条件下でＧａＡＳ層をエビタギシャル成長するいわ
ゆる二段階成長法である。二段階成長法によれば、まず
、シリコン基板を９００°Ｃ程度の温度で熱処理した後
、シリコン基板ＦにＭＯＣＶＤ法あるいはＭＢＥ法を用
いて４００′Ｃ程度の比較的低温で約１００人の予備堆
積層としてのＧａＡｓ層などを形成し、次に通常のＧａ
ＡＳのエピタキシャル成長温度（６００〜７５０”Ｃ）
まで基板を昇温した後、ＧａＡｓ層を所望厚み成長させ
る。For example, when forming a GaAs layer on a silicon substrate, it is a so-called two-step growth method in which a predeposition layer is formed in advance, and then a GaAS layer is epitaxially grown under normal growth conditions. According to the two-step growth method, first, the silicon substrate is heat-treated at a temperature of about 900°C, and then the silicon substrate F is subjected to MOCVD or MBE at a relatively low temperature of about 400'C, with approximately 100 layers of heat treated. A GaAs layer etc. is formed as a deposited layer, and then a normal GaAs layer is formed.
AS epitaxial growth temperature (600-750”C)
After raising the temperature of the substrate to a temperature of 100.degree. C., a GaAs layer is grown to a desired thickness.
ＧａＡｓ膜などから成る予備堆積層を形成した場合も、
ＳｉとＧａＡｓの界面領域では、ＳｉとＧａＡｓの格子
定数の差（〜４％）により高密度の不整合転位が発生し
、その一部は成長中に成長方向に伝播し、成長層を貫通
する。特に成長終１′後成長温度から室温への降温中シ
リコン基板とにａＡｓ層間の熱膨張係数の大きな相違に
よる応力は成長方向への転位の伝播を大きく作用するた
め、転位は表面近傍の活性層形成領域まで到達しＧａＡ
ｓ層にデバイスを作成する場合に最もデバイス性能を左
右する。Even when a pre-deposited layer made of a GaAs film or the like is formed,
In the interface region between Si and GaAs, a high density of mismatched dislocations occurs due to the difference in lattice constants between Si and GaAs (~4%), some of which propagate in the growth direction during growth and penetrate the grown layer. . In particular, during the cooling from the growth temperature to room temperature 1' after the end of growth, the stress due to the large difference in thermal expansion coefficient between the silicon substrate and the aAs layer greatly affects the propagation of dislocations in the growth direction, so dislocations are generated in the active layer near the surface. GaA reaches the formation region
This has the greatest effect on device performance when creating a device in the S layer.
ＳｉとＧａＡｓの界面領域で発生した不整合転位の密度
は約１０Ｉ２ｅｒｎ”あり、ＧａＡｓを３μｍ積層した
後のＧａＡｓ表面まで到達した転位の密度は約１０”ｃ
ｍ−”程度の高転位密度であることが知られている。転
位は少数キャリアの再結合中心として作用するため、高
密度転位を有する結晶中では、少数キャリア寿命の大幅
な減少を引き起こす。したがって、半導体発光素子など
の少数キャリアを用いる化合物半導体装置では、電気的
および光学的にその性能を著しく低下させることになる
。The density of mismatched dislocations generated in the interface region between Si and GaAs is approximately 10I2ern", and the density of dislocations that have reached the GaAs surface after stacking 3 μm of GaAs is approximately 10"c.
It is known that the dislocation density is as high as 1.0 m. Since dislocations act as recombination centers for minority carriers, the lifetime of minority carriers is significantly reduced in crystals with high density dislocations. In a compound semiconductor device using minority carriers, such as a semiconductor light emitting device, the electrical and optical performance thereof is significantly reduced.
また、シリコン基板上、に形成したＧａＡｓ層の結晶性
を高める試みの一つとして次のような方法が試みられて
いる。Furthermore, the following method has been attempted as an attempt to improve the crystallinity of a GaAs layer formed on a silicon substrate.
すなわち、表面近傍にまで到達する転位の密度を低減さ
せるため１．第２図に示すように、シリコン基板１１と
ＧａＡｓ膜１２との界面と表面近傍層の間にＩ ｎ Ｇ
ａ、 Ａ ｓ ／ Ｇ ａ Ａ ｓ歪超格子Ｉ２を介
挿する方法である。歪超格子とは格子定数か異なる２種
類の半導体薄膜を交互に積層した構造であり、−層毎の
層厚が薄いので格子は歪ながらも連続的に接続される性
質を持つ。この不整合により生じる格子の歪応力か転位
線の伝播を阻止するように作用すると考えられている。That is, in order to reduce the density of dislocations that reach the vicinity of the surface, 1. As shown in FIG. 2, there is an I n G layer between the interface between the silicon substrate 11 and the GaAs film 12 and the layer near the surface.
a, A s / G a As strained superlattice I2 is inserted. A strained superlattice is a structure in which two types of semiconductor thin films with different lattice constants are alternately laminated, and since each layer is thin, the lattice has the property of being continuously connected even though it is strained. It is believed that the lattice strain stress caused by this mismatch acts to prevent the propagation of dislocation lines.
すなわち、半導体の上に格子定数の異なる半導体を極く
薄く成長させた場合、上層の半導体の格子定数は歪応力
を受けながらも下層の半導体の格子に連続的に接続する
。この場合、下層の半導体も歪応力を受けており下層の
半導体を伝播する転位は、この歪応力により横方向に曲
げられて上層の半導体に伝播する。そして上層の半導体
の層厚が増すにともなって歪応力も大きくなり、転位の
曲かりも大きくなり、特に上層の半導体の層厚を格子不
整合転位を発生する臨界層厚以下に制御することによっ
て、相対する転位か繋がる機会か多くなり、転位か低減
する。That is, when semiconductors with different lattice constants are grown extremely thinly on top of a semiconductor, the lattice constant of the upper layer semiconductor is continuously connected to the lattice of the lower layer semiconductor even though it is subjected to strain stress. In this case, the lower layer semiconductor is also subjected to strain stress, and dislocations propagating in the lower layer semiconductor are bent laterally by this strain stress and propagate to the upper layer semiconductor. As the layer thickness of the upper layer semiconductor increases, the strain stress also increases, and the bending of dislocations also increases. , the opportunities for opposing dislocations to connect increase, and the number of dislocations decreases.
しかし、上述のような方法によってＧａＡｓ膜を形成し
たとしても、転位密度は３Ｘ１０”ｅｍ−２が限界であ
り、それ以上下げることはできなかった。However, even if a GaAs film is formed by the method described above, the dislocation density is limited to 3.times.10"em@-2 and cannot be lowered further.
本発明は、このような背景のもとに案出されたものであ
り、シリコン基板上に化合物半導体層をヘテロエピタキ
シャル成長させたとき、化合物半導体層中に残留する転
位密度を一層低減させて高品質の化合物半導体装置を提
供することを目的とするものである。The present invention was devised against this background, and when a compound semiconductor layer is heteroepitaxially grown on a silicon substrate, the dislocation density remaining in the compound semiconductor layer is further reduced to achieve high quality. The object of the present invention is to provide a compound semiconductor device.
（問題点を解決するための手段）
本発明によれば、半導体基板上に■−Ｖ族化合物半導体
層を形成するとともに、この■−■族化合物半導体層内
に少なくともＸ ｎ Ｘ Ｇ ａ ＋−８Ａｓ膜、ｉｎ
、Ｇａ＋−ｒ Ｐ膜またはＩ ｎ ｘ Ｇ ａ ＋ −
ｘ Ｐ膜とＩｎを不純物として含有するＧａＡｓ膜とを
交互に積層した歪超格子層を具備して成る半導体装置か
提供され、そのことにより上記目的か達成される。(Means for Solving the Problems) According to the present invention, a ■-V group compound semiconductor layer is formed on a semiconductor substrate, and at least X n X Ga +- is formed in this ■-■ group compound semiconductor layer. 8As film, in
, Ga + - r P film or In x Ga + -
There is provided a semiconductor device comprising a strained superlattice layer in which a xP film and a GaAs film containing In as an impurity are alternately laminated, thereby achieving the above object.
（作用）
上記のように構成することにより、歪超格子層内に、歪
超格子層を形成する異種半導体膜の格子定数の差に起因
する内部応力を発生させて、転位をまげてループ化した
り横に逃がしたりして、貫通転位密度を低減させる。も
って、半導体発光素子として用いた場合に長寿命化が図
れるとともに発光効率も向上する。(Function) By configuring as described above, internal stress caused by the difference in lattice constant of the different semiconductor films forming the strained superlattice layer is generated in the strained superlattice layer, and dislocations are bent into loops. or laterally to reduce the threading dislocation density. Therefore, when used as a semiconductor light emitting device, it is possible to achieve a longer life and also to improve luminous efficiency.
（実施例） 以下、本発明を添付図面に基づき詳細に説明する。(Example) Hereinafter, the present invention will be explained in detail based on the accompanying drawings.
第１図は、本発明に係る半導体発光素子の一実施例を示
す断面図であり、ｌはシリコン基板、２は第１のＩ−Ｖ
族化合物半導体層、３は歪超格子層、４は第２の■−■
族化合物半導体層である。FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor light emitting device according to the present invention, l is a silicon substrate, 2 is a first I-V
group compound semiconductor layer, 3 is a strained superlattice layer, 4 is a second ■-■
This is a group compound semiconductor layer.
前記シリコン基板１は、（１００）面から（００１）面
に２°オフして切り出しなＷ結晶シリづン基板で構成さ
れ、例えばアンチモン（Ｓ ｂ）などから成るドナーを
１０１７個／ ｃ ｒｎ ３程度含有（２゜ている。The silicon substrate 1 is composed of a W crystal silicon substrate cut off by 2° from the (100) plane to the (001) plane, and has 1017 donors/c rn 3 made of, for example, antimony (Sb). Contains a certain degree (2 degrees).
前記シリコン基板１十には、第１のＩＩＩ−Ｖ族化合物
半導体層２が形成されている。この第１Ｑ）■−■族化
合物半導体層２は、例えばドナーを１０１ｇ個／ｃｒｎ
’程度含有し、たＧａＡｓ膜などて構成され、２段階成
長法や熱サイクル法を適宜適用（２゜たＭ ＯＣＶ Ｄ
法て厚み１〜１．５μｍ程度に形成される。すなわち、
Ｍ ＯＣＶ Ｄ装置内を９（）０〜。A first III-V compound semiconductor layer 2 is formed on the silicon substrate 10 . This first Q) ■-■ group compound semiconductor layer 2 contains, for example, 101 g/crn of donors.
It is composed of a GaAs film, etc., containing about
It is formed to have a thickness of about 1 to 1.5 μm. That is,
MOCV D inside the device 9()0~.
１０００°Ｃて一旦加熱し７だ後に、４００〜４５０°
Ｃに下げてＧ ａ Ａ Ｓ膜を成長させるどともに６０
０〜６５０°（ｊにトげてＧａＡｓ膜を成長（２段階成
長法）させ、次に３００〜９００℃で温度を土工させ（
熱サイクル法）、熱膨張係数に起因する内部応力を発生
させる。このように２段階成長法や熱シイクル法で第１
の■−■族化合物半導体層２を形成することにより、半
導体基板１と第１のＩｆｆ−Ｖ族化合物半導体層２どの
ミスフィツトをある程度低減できる１、
前記第１の■−■族化合物半導体層２」、に、歪超格Ｐ
層３を形成する。この歪超格ｒ層３は、Ｉｎ、Ｇａ、＋
−，Ａｓ膜とｉｎを不純物として含有するＧ ａ Ａ、
ｓ膜とを交互に存する複数層で構成される。このよう
に、歪超格子層をＩｎ、Ｇａ＋−８ＡＳ膜とＩｎを不純
物として含有するＧ ａ Ａ、 ｓ膜とを交互に有する
複数層で構成することにより、格子゛定数の差に起因す
る内部応力か発生して転位を曲げるものと考えられる。Once heated to 1000°C and heated to 400-450° after 7 days.
The temperature was lowered to 60°C to grow the GaAs film.
0 to 650°C (j) to grow a GaAs film (two-step growth method), then lower the temperature to 300 to 900°C (
thermal cycling method), which generates internal stress due to the coefficient of thermal expansion. In this way, the two-step growth method and heat cycle method
By forming the ■-■ group compound semiconductor layer 2, the misfit between the semiconductor substrate 1 and the first If-V group compound semiconductor layer 2 can be reduced to some extent.1. ”, to distortion super case P
Form layer 3. This strain superlattice r layer 3 includes In, Ga, +
-, Ga A containing an As film and in as an impurity,
It is composed of multiple layers that alternate with S films. In this way, by configuring the strained superlattice layer with multiple layers that alternately include In, Ga+-8 AS films and Ga A, s films containing In as an impurity, internal It is thought that stress is generated and bends the dislocation.
また、Ｉ ｎ ＊ Ｇ ａ ＋−ｘＡ、 ｓ膜どＩｎを
不純物どして含有するＧａＡｓ膜とを交互に有する複数
層で歪超格子層を形成した場合に、エッチビット密度の
低減か著しいのは、Ｉｎをドーピングすることによって
Ｇ ａ Ａ ｓの強度か増加し、歪量を増していっても
、新たな転位か発生することなく転位密度を減少させる
ことかできるものと考えられる。Furthermore, when a strained superlattice layer is formed with multiple layers alternately including In*Ga+-xA, s films and GaAs films containing In as an impurity, the etch bit density is significantly reduced. It is thought that by doping with In, the strength of GaAs increases, and even if the amount of strain is increased, the dislocation density can be decreased without generating new dislocations.
Ｉ ｎ ｘ Ｇ ａ ＋ −＊ Ａｓの混晶比Ｘは、Ｏ
＜ｘ＜１の範囲で適宜選択することができる。また、Ｇ
ａＡ、 ｓ ｆｆｊ中には、Ｉｎ元素をＩ Ｏ＋９．、
＝ １０２０個／Ｃｍ３程度含有するように含イＪさぜ
第１ばよい。I n x Ga + −* The mixed crystal ratio X of As is O
It can be selected as appropriate within the range <x<1. Also, G
aA, s ffj, In element is I O+9. ,
= 1020 pieces/Cm3 should be included in the first place.
」−記のような歪超格子層：３は、７゛２０°Ｃの成長
温度で、キャリアガスどしてｉ（２ガスを用いるととも
に、原料ガスとしてＡ ｓ ｉ（３ガス、Ｔ Ｍ Ｇ
ａ（Ｍａ） 、ＴＭＩ ｎ （Ｍａ）ガスを用いるＭＯ
ＣＶＤ法により形成される。この場合、ＴＭＧａガスど
ＴＭＩｎガスとの流量比でインジウム（Ｉｎ）の混晶比
Ｘを決定すればよい。また、Ｉｎを不純物として含有す
るＧａＡｓ膜は、Ｇ ａ Ａ ｓ膜を形成する際に、Ｇ
ａＡｓ膜中のＩｎ元素の含有量が１０ ＋ｓ〜Ｉ Ｏ２
０個／ｃｒｎ３程度となるように、トリメチルインジウ
ム（ＴＭＩ ｎ）ガスの流量比を設定して形成すればよ
い。- Strained superlattice layer: 3 is grown at a growth temperature of 7°C to 20°C, using i(2 gas as carrier gas, and A s i(3 gas, TMG
MO using a(Ma), TMI n (Ma) gas
It is formed by CVD method. In this case, the mixed crystal ratio X of indium (In) may be determined by the flow rate ratio of TMGa gas or TMIn gas. In addition, when forming a GaAs film, a GaAs film containing In as an impurity is
The content of In element in the aAs film is 10+s~I O2
The flow rate ratio of trimethylindium (TMI n) gas may be set so that the number of particles is about 0 pieces/crn3.
なお、ＩｎヨＧａ、−８Ａｓ膜とＩｎを不純物として含
有するＧａＡｓ膜はそれぞれ２００Å以下の膜厚に形成
される。Note that the In/Ga, -8As film and the GaAs film containing In as an impurity are each formed to a thickness of 200 Å or less.
また、Ｉ ｎ、Ｇａ＋−ｘ Ａｓ膜に代えて、Ｇａ。In addition, Ga is used instead of the In, Ga+-x As film.
Ａｓ膜−ｙＰ膜またはＩ ｎ ｍ Ｇ ａ １−ｘ Ｐ
膜などを用いても良い。As film-yP film or In m Ga 1-x P
A membrane or the like may also be used.
前記歪超格子層３上に、第２の■−■族化合物゛ｆ、導
体層４を形成する。この第２の■−■族化自物下導体層
４も、第１の■−■族化合物半導体層２と同様に、例え
ばトナーを１０１９個、／ Ｃｍ ３程度含有したＧ
ａ、 Ａ ｓ膜なとて構成され、厚み１〜１．５μｍ程
度に形成される。On the strained superlattice layer 3, a second {circle over (1)--} group compound f, conductor layer 4 is formed. Similarly to the first ■-■ group compound semiconductor layer 2, this second ■-■ group compound self-material lower conductor layer 4 is also made of G containing, for example, about 1019 toner particles/Cm3.
It is composed of a and As films, and is formed to have a thickness of about 1 to 1.5 μm.
本発明に係る半導体装置を応用した発光素子は、第２の
■−Ｖ族化族化合物半導体上４上例えば図示しないクラ
ッド層、発光層、クラッド層、逆導電型■−Ｖ属化金化
合物半導体層成して、半導体基板１の裏面側と逆導電型
■−■族化合物半導体層上に、電極を形成して、この電
極間に電流を流して、発光層部分で電子と正孔を再結合
させて発光させる。すなわち、上述の第１の■−■族化
合物半導体層２、歪超格子層３、および第２の■−■族
化合物半導体層は、半導体発光素子のバッファ層として
用いられる。A light emitting element to which the semiconductor device according to the present invention is applied includes a second ■-V group compound semiconductor, a cladding layer (not shown), a light emitting layer, a cladding layer, a reverse conductivity type ■-V group gold compound semiconductor, etc. An electrode is formed on the reverse conductivity type ■-■ group compound semiconductor layer of the semiconductor substrate 1, and a current is passed between the electrodes to regenerate electrons and holes in the light emitting layer. Combine and emit light. That is, the first ■-■ group compound semiconductor layer 2, the strained superlattice layer 3, and the second ■-■ group compound semiconductor layer described above are used as a buffer layer of a semiconductor light emitting device.
（発明の効果）
以上のように、本発明に係る半導体装置によれば１．半
導体基板上に■−ｖ族化合物半導体層を形成するととも
に、このＩ−Ｖ族化合物半導体装置に少なくともｉｎ、
Ｇａｐ−ｘＡｓ膜、ＧａｘＡｓ１−ｙ Ｐ膜またはＩｎ
、Ｇａ、、−、Ｐ膜とＩｎを不純物として含有するＧ
ａ、 Ａ ｓ膜とを交互に形成した歪超格子層を具備す
ることから、エッヂビット密度を８Ｘ１０’ｅｒｎ−”
まて低減させることかてき、。(Effects of the Invention) As described above, according to the semiconductor device according to the present invention, 1. A ■-V group compound semiconductor layer is formed on the semiconductor substrate, and at least in
Gap-xAs film, GaxAs1-yP film or In
, Ga, -, G containing P film and In as an impurity
Since it is equipped with a strained superlattice layer in which A and As films are formed alternately, the edge bit density can be increased to 8X10'ern-''.
Well, let's reduce it.
もって半導体発光素子などを形成する場合、長寿命化し
た半導体発光素子を提供できるとともに、発光効率の高
い半導体発光素子を提供できる。When a semiconductor light emitting device or the like is formed using the present invention, it is possible to provide a semiconductor light emitting device with a long life and also a semiconductor light emitting device with high luminous efficiency.
第１図は本発明に係る半導体発光素子の一実施例を示す
断面図、第２図は従来の半導体発光素子を示す断面図で
ある。
Ｉ；シリコン基板
２．４：Ｉ［［−Ｖ族化合物半導体層
３：歪超格子層FIG. 1 is a sectional view showing an embodiment of a semiconductor light emitting device according to the present invention, and FIG. 2 is a sectional view showing a conventional semiconductor light emitting device. I; silicon substrate 2.4: I[[-V group compound semiconductor layer 3: strained superlattice layer
Claims (1)
とともに、このIII−Ｖ族化合物半導体層内に少なくと
もＩｎ＿ｘＧａ＿１＿−＿ｘＡｓ膜、Ｇａ＿ｙＡｓ＿１
＿−＿ｙＰ膜またはＩｎ＿２Ｇａ＿１＿−＿２Ｐ膜とＩ
ｎを不純物として含有するＧａＡｓ膜とを交互に積層し
た歪超格子層を具備して成る半導体装置。A III-V compound semiconductor layer is formed on a semiconductor substrate, and at least an In_xGa_1_-_xAs film and a Ga_yAs_1 film are formed in this III-V group compound semiconductor layer.
____yP film or In_2Ga_1_-_2P film and I
A semiconductor device comprising a strained superlattice layer in which GaAs films containing n as an impurity are alternately laminated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2171751A JPH0461286A (en) | 1990-06-28 | 1990-06-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2171751A JPH0461286A (en) | 1990-06-28 | 1990-06-28 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0461286A true JPH0461286A (en) | 1992-02-27 |
Family
ID=15929018
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2171751A Pending JPH0461286A (en) | 1990-06-28 | 1990-06-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0461286A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009281912A (en) * | 2008-05-23 | 2009-12-03 | Espec Corp | Insulating panel and environmental test device |
| JP2010141197A (en) * | 2008-12-12 | 2010-06-24 | Shin Etsu Handotai Co Ltd | Compound semiconductor substrate, light emitting element, method of manufacturing compound semiconductor substrate, and method of manufacturing light emitting element |
-
1990
- 1990-06-28 JP JP2171751A patent/JPH0461286A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009281912A (en) * | 2008-05-23 | 2009-12-03 | Espec Corp | Insulating panel and environmental test device |
| JP2010141197A (en) * | 2008-12-12 | 2010-06-24 | Shin Etsu Handotai Co Ltd | Compound semiconductor substrate, light emitting element, method of manufacturing compound semiconductor substrate, and method of manufacturing light emitting element |
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