JPH04199812A - Semiconductor crystal growth method - Google Patents

Semiconductor crystal growth method

Info

Publication number
JPH04199812A
JPH04199812A JP33598890A JP33598890A JPH04199812A JP H04199812 A JPH04199812 A JP H04199812A JP 33598890 A JP33598890 A JP 33598890A JP 33598890 A JP33598890 A JP 33598890A JP H04199812 A JPH04199812 A JP H04199812A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor
compound semiconductor
dislocation
gaas layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33598890A
Other languages
Japanese (ja)
Inventor
Akihiro Hashimoto
明弘 橋本
Naoharu Sugiyama
直治 杉山
Masao Tamura
田村 誠男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Optoelectronics Technology Research Laboratory
Original Assignee
Optoelectronics Technology Research Laboratory
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Optoelectronics Technology Research Laboratory filed Critical Optoelectronics Technology Research Laboratory
Priority to JP33598890A priority Critical patent/JPH04199812A/en
Publication of JPH04199812A publication Critical patent/JPH04199812A/en
Pending legal-status Critical Current

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  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To make it possible to grow a compound semiconductor whose dislocation density is small on a semiconductor substrate by a method wherein, when the compound semiconductor in which lattice is not matched with the substrate is crystal-grown, an intermediate film whose dislocation propagation property is different is inserted into a growth film of the compound semiconductor. CONSTITUTION:A GaAs buffer layer 12 is grown on a Si substrate 11, and a dislocation 14 appears on a GaAs layer 13, which is grown by crystal-growing a GaAs layer 13 on the substrate 11 again due to the difference in the lattice constant, etc., from the substrate 11. Then, a Si film (intermediate film) 15 is grown on the GaAs layer 13 by lowering the temperature of the substrate 11. Finally, the GaAs layer 16 is grown by setting the temperature of the substrate 11 to 600 deg.C in a atmosphere of As. Thus, the Si film 15 has a dislocation propagation property differing from that of the GaAs layer 13 so that the dislocation occurred in the GaAs layer 13 will not be propagated to the GaAs layer 16, thereby making the GaAs layer 16 a high-quality crystal with less dislocation.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、電子デバイス、光デバイスなどの半導体デバ
イス及びその複合又は集積デバイスの作製に利用される
半導体結晶成長方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor crystal growth method used for manufacturing semiconductor devices such as electronic devices and optical devices, and composite or integrated devices thereof.

[従来の技術] 光電子集積回路等を考えた場合、同一基板上に光デバイ
ス及び電子デバイスの作製ができる半導体材料が必要で
ある。この様な半導体材料を得る方法として、Si基板
上に化合物半導体を成長させる方法がある。
[Prior Art] When considering optoelectronic integrated circuits and the like, a semiconductor material is required that allows the fabrication of optical devices and electronic devices on the same substrate. One way to obtain such a semiconductor material is to grow a compound semiconductor on a Si substrate.

一般に、Si基板上に化合物半導体を結晶成長させると
、Si基板と化合物半導体との格子定数や熱膨張係数の
違い、極性の有無等の原因により、その表面に108c
m−2程度の転位が誘起される。
Generally, when compound semiconductor crystals are grown on a Si substrate, due to differences in lattice constant and coefficient of thermal expansion between the Si substrate and the compound semiconductor, presence or absence of polarity, etc.
About m-2 dislocations are induced.

光デバイス及び電子デバイスに利用される半導体材料は
高品質のものが望まれるため、転位を低減させる努力が
成されている。
Since high quality semiconductor materials are desired for use in optical and electronic devices, efforts are being made to reduce dislocations.

従来、この転位を低減させる方法として以下に述べるよ
うな方法が知られている。
Conventionally, the following methods are known as methods for reducing this dislocation.

(1) S i基板上に化合物半導体薄膜を結晶成長し
た後、成長温度よりも高い温度で熱処理をし、成長膜中
の転位を熱運動させることによりバーガース・ベクトル
が保存されるような転位ループを形成させ、膜表面での
転位密度の減少をはがる方法(ボストアニール法)。
(1) After crystal growth of a compound semiconductor thin film on a Si substrate, heat treatment is performed at a temperature higher than the growth temperature to thermally move the dislocations in the grown film, thereby creating a dislocation loop in which the Burgers vector is preserved. A method that reduces the dislocation density on the film surface by forming

(2)化合物半導体薄膜の結晶成長を中断し、Inn 
Ga+−x As/GaAs等の歪超格子を形成した後
、再度化合物半導体薄膜の結晶成長を行うことで、化合
物半導体薄膜中に応力場を導入し、転位線の方向を界面
方向に変化させることにより、転位を基板側部へと導き
、転位の先端が膜表面に出現しないようにする方法(歪
超格子挿入法)。
(2) Interrupting the crystal growth of the compound semiconductor thin film and
After forming a strained superlattice such as Ga+-x As/GaAs, crystal growth of the compound semiconductor thin film is performed again to introduce a stress field into the compound semiconductor thin film and change the direction of dislocation lines toward the interface. A method of guiding dislocations to the side of the substrate and preventing dislocation tips from appearing on the film surface (strained superlattice insertion method).

(3)化合物半導体薄膜の結晶成長を行っている最中に
成長温度を数回上下させ、成長膜中に発生した転位の運
動を制御し転位ループを形成させたり、基板側部へ転位
を導いて、成長膜表面での転位密度を低減させる方法(
熱サイクル法)。
(3) During crystal growth of a compound semiconductor thin film, the growth temperature is raised and lowered several times to control the movement of dislocations generated in the grown film, forming dislocation loops, and guiding dislocations to the side of the substrate. A method of reducing dislocation density on the surface of a grown film (
thermal cycle method).

従来は、結晶成長法にMBE法、MOCVD法等が用い
られ、成長初期段階で低温バファ層を形成する、いわゆ
る2段階成長法に、上記方法を適宜組み合わせて転位密
度の低減をはかっている。
Conventionally, the MBE method, MOCVD method, etc. have been used as crystal growth methods, and the above-mentioned methods have been appropriately combined with a so-called two-step growth method in which a low-temperature buffer layer is formed in the initial stage of growth to reduce dislocation density.

[発明が解決しようとする課題] しかしながら、従来の方法では以下のような問題点かあ
る。
[Problems to be Solved by the Invention] However, the conventional method has the following problems.

ボストアニール法及び熱サイクル法等のように熱履歴に
より膜中の転位を運動させ、転位ループの形成や、転位
を基板側部へ逃がす方法では、転位の密度がある程度以
下になると転位同志の8会う確率が減るために、上述の
ようなメカニズムでの転位の低減は望めない。現在のと
ころその下限はSi基板上のGaAs膜の場合、〜10
6cm−2程度であるといわれている。
In methods such as the Bost annealing method and the thermal cycle method, in which dislocations in the film are moved by thermal history to form dislocation loops or to escape to the side of the substrate, when the density of dislocations falls below a certain level, dislocations become 8 Since the probability of meeting is reduced, it is not possible to reduce dislocations by the mechanism described above. Currently, the lower limit is ~10 for GaAs films on Si substrates.
It is said to be about 6 cm-2.

歪超格子挿入法では界面における歪場のために、転位は
その方向を界面方向に変える。ところが、例えばI n
GaAsとGaAsとの歪超格子を考えると、双方の膜
中での転位の振る舞い(転位の伝搬速度、転位発生の臨
界応力)は非常によく似ており、転位は歪場の揺動によ
り容易に伝搬方向を変え、膜表面に向かう。従って、こ
の方法でもある程度以上の転位密度の低減は望めない。
In the strained superlattice insertion method, dislocations change their direction toward the interface due to the strain field at the interface. However, for example, I n
Considering the strained superlattices of GaAs and GaAs, the behavior of dislocations (propagation speed of dislocations, critical stress for dislocation generation) in both films is very similar, and dislocations are easily generated by fluctuations in the strain field. The propagation direction changes and heads toward the membrane surface. Therefore, even with this method, it is not possible to reduce the dislocation density beyond a certain level.

本発明は、半導体基板上に転位密度の小さい化合物半導
体を成長させる方法を提供することを目的とする。
An object of the present invention is to provide a method for growing a compound semiconductor with a low dislocation density on a semiconductor substrate.

[課題を解決するための手段] 本発明によれば、半導体基板上に該半導体基板の格子定
数と異なる格子定数を有する化合物半導体を結晶成長さ
せる半導体結晶成長方法において、前記半導体基板上に
前記化合物半導体を結晶成長させる第1の工程と、前記
化合物半導体上に該化合物半導体の転位伝搬性質と異な
る転位伝搬性質を有する半導体薄膜を所定の膜厚以下形
成する第2の工程と、前記半導体薄膜上に前記化合物半
導体を再度結晶成長させる第3の工程を含むことを特徴
とする半導体結晶成長方法が得られる。
[Means for Solving the Problems] According to the present invention, in a semiconductor crystal growth method for crystal-growing a compound semiconductor having a lattice constant different from that of the semiconductor substrate on a semiconductor substrate, the compound semiconductor is grown on the semiconductor substrate. a first step of crystal-growing a semiconductor; a second step of forming a semiconductor thin film having a dislocation propagation property different from that of the compound semiconductor to a predetermined thickness or less on the compound semiconductor; A method for growing a semiconductor crystal is obtained, which further comprises a third step of growing the compound semiconductor again.

[実施例] 以下に図面を参照して本発明の詳細な説明する。[Example] The present invention will be described in detail below with reference to the drawings.

第1図に本発明の第1の実施例の半導体結晶成長方法の
工程図を示す。
FIG. 1 shows a process diagram of a semiconductor crystal growth method according to a first embodiment of the present invention.

まず、5i(100)基板11の表面を熱処理などによ
り清浄化する。続いて、Si  (100)基板11を
250℃に昇温し、第1図(a)に示すようにSi基板
11上にGaAsバッファ層12を約100人成長させ
る。それから基板11の温度を600℃として、再びG
aAs層13を結晶成長させる。
First, the surface of the 5i (100) substrate 11 is cleaned by heat treatment or the like. Subsequently, the temperature of the Si (100) substrate 11 is raised to 250° C., and about 100 GaAs buffer layers 12 are grown on the Si substrate 11 as shown in FIG. 1(a). Then, the temperature of the substrate 11 is set to 600°C, and G
The aAs layer 13 is grown as a crystal.

ここで、成長させたGaAs層13には、基板11との
格子定数等の違いから、転位14が生じている。
Here, dislocations 14 have occurred in the grown GaAs layer 13 due to the difference in lattice constant, etc. with the substrate 11.

次に、基板11の温度を250℃に下げ、第1図(b)
に示すようにGaAs層13の上に、Si膜(中間膜)
15を成長させる。このSi膜15の厚さは数ML (
分子層)相当、即ち、臨界膜厚以下とする。ここで臨界
膜厚とは、格子不整合に対する内部応力が弾性限界を越
えない膜厚をいう。
Next, the temperature of the substrate 11 is lowered to 250°C, and as shown in FIG.
As shown in , a Si film (intermediate film) is placed on the GaAs layer 13.
Grow 15. The thickness of this Si film 15 is several ML (
molecular layer), that is, below the critical film thickness. The critical film thickness herein refers to the film thickness at which internal stress due to lattice mismatch does not exceed the elastic limit.

最後に、As雰囲気下において基板11の温度を600
℃にし、第1図(C)に示すようにGaAs層16の成
長を行う。
Finally, the temperature of the substrate 11 was increased to 600°C in an As atmosphere.
℃, and a GaAs layer 16 is grown as shown in FIG. 1(C).

この様にGaAs層13とGaAs層16との間にSi
層15が挿入された半導体材料では、Si膜15がGa
As層13とは異なる転位伝搬性質(伝搬速度、臨界応
力等)を有しているため、GaAs層13で生じた転位
はGaAs層16へは伝搬されない。よって、GaAs
層16は極めて転位の少ない高品質の結晶となる。
In this way, Si is formed between the GaAs layer 13 and the GaAs layer 16.
In the semiconductor material in which the layer 15 is inserted, the Si film 15 is Ga
Since the GaAs layer 13 has different dislocation propagation properties (propagation speed, critical stress, etc.) from the As layer 13, dislocations generated in the GaAs layer 13 are not propagated to the GaAs layer 16. Therefore, GaAs
The layer 16 becomes a high quality crystal with extremely few dislocations.

第2図に第2の実施例を示す。FIG. 2 shows a second embodiment.

第2の実施例ではGaAs層13とSi層15とを交互
に結晶成長させ、−層のSi層15で伝搬を阻止するこ
とができない転位を徐々に阻止するようにしている。
In the second embodiment, the crystals of the GaAs layer 13 and the Si layer 15 are grown alternately to gradually block dislocations whose propagation cannot be blocked by the negative Si layer 15.

なお、上記実施例ではSi基板上にGaAs層を形成す
る方法について説明したが、これに限られるものではな
く、いわゆる格子不整合エピタキシャル系であれば、■
−■族化合物半導体、■−■族化合物半導体、または、
■族化合物半導体であってもよい。
Although the above embodiment describes the method of forming a GaAs layer on a Si substrate, the method is not limited to this, and if it is a so-called lattice mismatched epitaxial system,
−■ group compound semiconductor, ■−■ group compound semiconductor, or
It may be a group (Ⅰ) compound semiconductor.

また、本発明の半導体成長方法は従来の転位低減方法と
組み合わせることによって、さらに転位密度を低減させ
ることかできる。
Further, the semiconductor growth method of the present invention can be combined with a conventional dislocation reduction method to further reduce dislocation density.

[発明の効果] 本発明は、基板と格子整合が取れていない化合物半導体
を結晶成長させる際に、化合物半導体の成長膜中に転位
伝搬性質の異なる中間膜を挿入するようにしたことで、
中間膜の下に位置する化合物半導体に生じた転位が中間
膜の上に位置する化合物半導体へ伝搬するのを防ぐこと
ができ、高品質の半導体材料を得ることができる。
[Effects of the Invention] The present invention can achieve the following effects by inserting an intermediate film having different dislocation propagation properties into the grown compound semiconductor film when crystal-growing a compound semiconductor that is not lattice-matched with the substrate.
Dislocations generated in the compound semiconductor located below the intermediate film can be prevented from propagating to the compound semiconductor located above the intermediate film, and a high quality semiconductor material can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の実施例を説明するための工程図
、第2図は第2の実施例を説明するための構造図である
。 11・・・Si基板、12・・・GaAsバッファ層、
13− G a A s層、14−=転位、15−3 
i膜、16− G a A s層。 第1図     第2図 (b) (C)
FIG. 1 is a process diagram for explaining a first embodiment of the present invention, and FIG. 2 is a structural diagram for explaining a second embodiment. 11...Si substrate, 12...GaAs buffer layer,
13-GaAs layer, 14-=dislocation, 15-3
i film, 16-G a As layer. Figure 1 Figure 2 (b) (C)

Claims (1)

【特許請求の範囲】 1、半導体基板上に該半導体基板の格子定数と異なる格
子定数を有する化合物半導体を結晶成長させる半導体結
晶成長方法において、 前記半導体基板上に前記化合物半導体を結晶成長させる
第1の工程と、 前記化合物半導体上に該化合物半導体の転位伝搬性質と
異なる転位伝搬性質を有する半導体薄膜を所定の膜厚以
下形成する第2の工程と、 前記半導体薄膜上に前記化合物半導体を再度結晶成長さ
せる第3の工程を含むことを特徴とする半導体結晶成長
方法。 2、前記半導体基板としてSi基板を、前記化合物半導
体としてIII−V族化合物半導体を、前記半導体薄膜と
してSi薄膜を用いることを特徴とする請求項1記載の
半導体結晶成長方法。 3、Si基板と、該Si基板上に結晶成長された少なく
とも2層のIII−V族化合物半導体層と、前記III−V族
化合物半導体層に挟まれた所定膜厚以下のSi層とを有
することを特徴とする半導体ウェハー。
[Scope of Claims] 1. A semiconductor crystal growth method for crystal-growing a compound semiconductor having a lattice constant different from that of the semiconductor substrate on a semiconductor substrate, comprising: a first step of crystal-growing the compound semiconductor on the semiconductor substrate; a second step of forming a semiconductor thin film having a dislocation propagation property different from that of the compound semiconductor on the compound semiconductor to a predetermined thickness or less; and crystallizing the compound semiconductor again on the semiconductor thin film. A method for growing a semiconductor crystal, the method comprising a third step of growing a semiconductor crystal. 2. The semiconductor crystal growth method according to claim 1, wherein a Si substrate is used as the semiconductor substrate, a III-V group compound semiconductor is used as the compound semiconductor, and a Si thin film is used as the semiconductor thin film. 3. It has a Si substrate, at least two III-V group compound semiconductor layers crystal-grown on the Si substrate, and a Si layer having a predetermined thickness or less sandwiched between the III-V group compound semiconductor layers. A semiconductor wafer characterized by:
JP33598890A 1990-11-29 1990-11-29 Semiconductor crystal growth method Pending JPH04199812A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33598890A JPH04199812A (en) 1990-11-29 1990-11-29 Semiconductor crystal growth method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33598890A JPH04199812A (en) 1990-11-29 1990-11-29 Semiconductor crystal growth method

Publications (1)

Publication Number Publication Date
JPH04199812A true JPH04199812A (en) 1992-07-21

Family

ID=18294539

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33598890A Pending JPH04199812A (en) 1990-11-29 1990-11-29 Semiconductor crystal growth method

Country Status (1)

Country Link
JP (1) JPH04199812A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6351353B1 (en) * 1999-06-11 2002-02-26 Seagate Technology, Inc. Interconnect designs for micromotor, magnetic recording head and suspension assemblies
US6530991B2 (en) 1999-12-14 2003-03-11 Riken Method for the formation of semiconductor layer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01315127A (en) * 1988-03-18 1989-12-20 Fujitsu Ltd Formation of gallium arsenide layer
JPH02172900A (en) * 1988-12-23 1990-07-04 Matsushita Electric Ind Co Ltd Substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01315127A (en) * 1988-03-18 1989-12-20 Fujitsu Ltd Formation of gallium arsenide layer
JPH02172900A (en) * 1988-12-23 1990-07-04 Matsushita Electric Ind Co Ltd Substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6351353B1 (en) * 1999-06-11 2002-02-26 Seagate Technology, Inc. Interconnect designs for micromotor, magnetic recording head and suspension assemblies
US6530991B2 (en) 1999-12-14 2003-03-11 Riken Method for the formation of semiconductor layer

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