JP2712505B2 - Vapor phase epitaxy - Google Patents

Vapor phase epitaxy

Info

Publication number
JP2712505B2
JP2712505B2 JP6280489A JP6280489A JP2712505B2 JP 2712505 B2 JP2712505 B2 JP 2712505B2 JP 6280489 A JP6280489 A JP 6280489A JP 6280489 A JP6280489 A JP 6280489A JP 2712505 B2 JP2712505 B2 JP 2712505B2
Authority
JP
Japan
Prior art keywords
substrate
growth
temperature
susceptor
gaas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP6280489A
Other languages
Japanese (ja)
Other versions
JPH02243594A (en
Inventor
利一 井上
琢之 本山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6280489A priority Critical patent/JP2712505B2/en
Publication of JPH02243594A publication Critical patent/JPH02243594A/en
Application granted granted Critical
Publication of JP2712505B2 publication Critical patent/JP2712505B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)

Description

【発明の詳細な説明】 〔概 要〕 本発明は主として半導体材料の気相ヘタロエピタキシ
ャル成長に関し、 格子定数の差に起因する転位が成長層に伝播すること
の抑止を目的とし、 初期成長層中に生じた転位を成長方向に伝播しないも
のに転ずるために行われる、基板温度の急速な昇降処理
に於いて、 基板をサセプタから空間的に分離して降温させ、サセ
プタに接触させて昇温させる処理を包含して構成され
る。
DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention mainly relates to gas phase heteroepitaxial growth of semiconductor materials, and aims at suppressing dislocations caused by a difference in lattice constant from propagating to a growth layer. In the process of rapidly raising and lowering the substrate temperature, which is performed to turn the dislocations generated in the substrate into those that do not propagate in the growth direction, the substrate is spatially separated from the susceptor and cooled, and the temperature is raised by contacting the susceptor It is configured to include processing.

熱容量の大きいサセプタとは独立に温度が下降するの
で、降温速度が速められ、転位の非伝播処理の効果が高
められる。
Since the temperature falls independently of the susceptor having a large heat capacity, the temperature decreasing speed is increased, and the effect of the non-propagation treatment of dislocations is enhanced.

〔産業上の利用分野〕[Industrial applications]

本発明は、典型的にはSi基板上にGaAsのような化合物
半導体をエピタキシャル成長させる気相成長処理に関わ
り、特に格子定数の不整合によって生ずる転位を、成長
層中に伝播させないための処理に関わるものである。
The present invention generally relates to a vapor phase growth process for epitaxially growing a compound semiconductor such as GaAs on a Si substrate, and particularly to a process for preventing dislocations caused by lattice constant mismatch from propagating into a growth layer. Things.

近年、GaAsのような半導体材料に集積回路を形成する
ことが行われるようになり、そのための基板として結晶
欠陥の少ない単結晶ウエハが求められている。素子形成
領域の欠陥を少なくするにはエピタキシャル成長層を利
用することが考えられるが、経済性を考慮すれば、Siの
ように無欠陥単結晶が比較的廉価に得られる材料を下地
結晶とし、これに無欠陥或いは低欠陥のGaAs層をエピタ
キシャル成長させて集積回路を形成することが望まし
い。更に機械的強度の点でも、GaAsよりSiの方が下地基
板として優れている。
In recent years, an integrated circuit is formed on a semiconductor material such as GaAs, and a single crystal wafer with few crystal defects is required as a substrate for the purpose. In order to reduce defects in the element formation region, it is conceivable to use an epitaxial growth layer.However, in consideration of economy, a material such as Si that can obtain a defect-free single crystal at relatively low cost is used as the base crystal. It is desirable to form an integrated circuit by epitaxially growing a defect-free or low-defect GaAs layer. Further, in terms of mechanical strength, Si is superior to GaAs as a base substrate.

しかしながら、Siの格子定数は5.431Å、GaAsのそれ
は5.653Åであって、通常用いられる二段階成長法によ
ってSi基板にGaAsをエピタキシャル成長させたのでは、
この約4%の違いがミスフィット転位を発生させるの
で、低欠陥成長層を得ることが出来ない。
However, since the lattice constant of Si is 5.431 ° and that of GaAs is 5.653 °, if GaAs is epitaxially grown on a Si substrate by a commonly used two-step growth method,
Since the difference of about 4% causes misfit dislocation, a low defect growth layer cannot be obtained.

かかる格子不整合に対処する方法の一つに歪超格子を
介在させるものがある。これは格子定数の異なる2層の
夫々数原子層から成る層を交互に積層し、そこに歪を吸
収させることによって最終的なエピタキシャル成長層を
低欠陥、低応力とするものであって、有効な方法である
が、現状ではコスト面から実用性に乏しいものである。
One method for dealing with such lattice mismatch is to interpose a strained superlattice. This is a method in which two layers having different lattice constants each consisting of several atomic layers are alternately stacked, and the strain is absorbed therein to make the final epitaxial growth layer low in defect and low in stress. Although it is a method, it is currently impractical in terms of cost.

〔従来の技術〕[Conventional technology]

GaAs/Siのヘテロエピタキシャル成長ではミスフィッ
ト転位の発生は不可避であるが、これを成長層中に伝播
させない処理法として、エピタキシャル成長を一旦停止
し、これに熱衝撃を加えた後、再びエピタキシャル成長
を行うことが提案されている。これは熱衝撃の応力によ
って転位を移動させ、転位どうしを連結したり方向を変
えたりすることによって、それ以後のエピタキシャル層
への伝播を抑制しようとするものである。
Misfit dislocations are unavoidable in heteroepitaxial growth of GaAs / Si.However, as a processing method that does not propagate this into the growth layer, the epitaxial growth must be stopped once, subjected to thermal shock, and then epitaxially grown again. Has been proposed. This is intended to suppress the subsequent propagation to the epitaxial layer by moving the dislocations by the stress of thermal shock, connecting the dislocations or changing the directions.

この処理による温度履歴の1例が第2図に示されてい
る。例えば成長温度が700℃の場合、最初1〜2μmのG
aAs層を成長させ(成長Aの部分)、これを200℃/900℃
の温度幅で急速に降温と昇温を十回〜十数回繰り返した
後、再び700℃でエピタキシャル成長を行い(成長Bの
部分)、素子形成層を成長させる。
FIG. 2 shows an example of the temperature history by this processing. For example, if the growth temperature is 700 ° C., the G
aAs layer is grown (growth A part)
After the temperature is rapidly increased and decreased by ten to several tens of times within the temperature range described above, epitaxial growth is performed again at 700 ° C. (growth B portion) to grow an element formation layer.

GaAs/Siのヘテロ接合は、成長温度では結晶の歪が転
位の形で吸収されるため応力は生じないが、両者の熱膨
張係数が異なることから、第3図に示すように、成長温
度以上ではGaAsに圧縮応力が、成長温度以下では引張応
力が生じる。この正負の歪を繰り返し与えることによ
り、ヘテロ接合面から延在する転位どうしを結合させて
ループ状とし、或いは転位線の向きを変えて成長方法に
延びないようにすることができる。
At the growth temperature, the GaAs / Si heterojunction does not generate stress because the crystal strain is absorbed in the form of dislocations. However, since the two have different thermal expansion coefficients, as shown in FIG. In GaAs, a compressive stress occurs in GaAs, and a tensile stress occurs below the growth temperature. By repeatedly applying the positive and negative strains, dislocations extending from the heterojunction plane can be combined into a loop shape, or dislocation lines can be changed so that they do not extend to the growth method.

上記昇降温の繰り返しで、高温に保持する時間が設け
られているのは、転位の移動速度は温度が高いほど速い
ことから、この期間に転位を移動させるためである。
The reason why the temperature is maintained at a high temperature in the repetition of the above temperature rise / fall is to move the dislocation during this period since the dislocation movement speed is higher as the temperature is higher.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

上記処理に於いては、熱衝撃を強く与えるために基板
温度の昇降速度は速ければ速いほどよい。ところが、通
常の高周波加熱では基板はグラファイト・ブロックのよ
うなサセプタに載置されており、高周波電流を停止して
もサセプタの熱容量が大であるため、急速に降温させる
ことはできず、熱衝撃を十分に強くすることが困難であ
る。
In the above process, the faster the substrate temperature is raised or lowered, the better the thermal shock is applied. However, in normal high-frequency heating, the substrate is placed on a susceptor such as a graphite block, and even when the high-frequency current is stopped, the heat capacity of the susceptor is large. It is difficult to make it strong enough.

〔課題を解決するための手段〕[Means for solving the problem]

本発明に包含されるヘテロエピタキシャル成長の処理
では、 初期成長層中に生じた転位を成長方向に伝播しないも
のに転ずるために行われる、基板温度の急速な昇降処理
に於いて、 基板をサセプタから空間的に分離して、即ち伝導によ
る熱の流入を無くした状態で降温させ、基板温度が下降
した後サセプタに接触させて昇温させる処理が少なくと
も1回、通常は数回以上繰り返される。
In the process of heteroepitaxial growth included in the present invention, in the process of rapidly raising and lowering the substrate temperature, which is performed to convert dislocations generated in the initial growth layer to those that do not propagate in the growth direction, the substrate is moved from the susceptor to the space. The process is performed at least once, usually several times or more, in which the temperature is lowered in a state in which the flow of heat by conduction is eliminated, and the temperature is lowered by contacting the susceptor after the temperature of the substrate is lowered.

〔作 用〕(Operation)

上記手段が採用された結果、最初の成長層中に生じて
いる転位をループ状にしたり、方向を転じたりすること
が効率良く行われることになり、昇降温の繰り返し処理
の効果が高められている。
As a result of the adoption of the above means, dislocations generated in the first growth layer are formed in a loop or turned in the direction efficiently, and the effect of the repetitive treatment of temperature rise and fall is enhanced. I have.

この昇降温速度は速ければ速いほど良いから、本発明
のように熱容量の大きいサセプタからの熱伝導を無くし
て基板温度を下げれば、降温速度が速められ、転位の非
伝播処理の効果が高められる。
The higher the temperature rise / fall rate, the better. Therefore, if the substrate temperature is reduced by eliminating the heat conduction from the susceptor having a large heat capacity as in the present invention, the temperature fall rate is increased, and the effect of the non-propagation treatment of dislocations is enhanced. .

〔実施例〕〔Example〕

第1図は本発明の実施に用いられる気相成長装置の構
成を示す模式図である。図中、1は反応管、2は原料ガ
スの流れを整えて均一に成長させるための成長室、3は
グラファイト・ブロックで造られたサセプタ、4はエピ
タキシャル成長の基板で、トレイ5に載せてサセプタ上
に載置される。グラファイト製のフォーク6は基板を載
せたトレイを反応管の下流側からサセプタ上に運ぶのに
使用され、エピタキシャル成長実施時には管内の下流側
に移されている。7はサセプタ加熱用のRFコイルであ
る。更に、GaAsエピタキシャル成長の原料はH2をキャリ
ヤガスとするAsH3及びTMGである。以下、第1図及び第
2図を参照しながら本発明の処理を説明する。
FIG. 1 is a schematic view showing a configuration of a vapor phase growth apparatus used for carrying out the present invention. In the figure, 1 is a reaction tube, 2 is a growth chamber for adjusting the flow of a source gas to grow uniformly, 3 is a susceptor made of a graphite block, 4 is a substrate for epitaxial growth, and 4 is a susceptor mounted on a tray 5. Placed on top. The graphite fork 6 is used to carry the tray on which the substrate is placed from the downstream side of the reaction tube to the susceptor, and is moved to the downstream side of the tube during the epitaxial growth. Reference numeral 7 denotes an RF coil for heating the susceptor. Further, the raw materials for GaAs epitaxial growth are AsH 3 and TMG using H 2 as a carrier gas. Hereinafter, the processing of the present invention will be described with reference to FIG. 1 and FIG.

第2図の温度履歴曲線で成長Aと記されたエピタキシ
ャル成長期間は、基板結晶は第1図(a)のようにトレ
イ5を挟んでサセプタ上に載せられ、サセプタからの熱
伝導により加熱されている。この処理で1〜2μmのGa
AS層を成長させた後、原料ガスのうちTMGの供給を停止
し、またAsH3はGaAsの熱分解を抑止するだけの量に減じ
て、基板温度を900℃に上昇させ、2〜3分保持する。
During the epitaxial growth period indicated by the growth A in the temperature history curve of FIG. 2, the substrate crystal is placed on the susceptor with the tray 5 interposed therebetween as shown in FIG. 1A, and is heated by heat conduction from the susceptor. I have. In this process, 1-2 μm Ga
After growing the AS layer, the supply of TMG among the source gases is stopped, and the amount of AsH 3 is reduced to a level sufficient to suppress the thermal decomposition of GaAs, and the substrate temperature is raised to 900 ° C. for 2 to 3 minutes. Hold.

次いで高周波電流を停止すると共にフォークを操作し
て、第1図(b)の如く、基板をサセプタから持ち上
げ、200℃まで急冷する。基板が所定温度に降温するの
にタイミングを合わせて高周波電流を通電し、フォーク
を操作して基板をサセプタに接触させ、急速に加熱す
る。第1図(c)は同(b)図を上方から見た平面図で
ある。なおこの操作では、基板はトレイに載せた状態で
取り扱われ、トレイを通しての熱伝導によって加熱され
るので、トレイの熱伝導についての配慮は必要である
が、通常使用されるグラファイトや石英ガラスのトレイ
でも特に問題はない。
Next, the high-frequency current is stopped, and the fork is operated to lift the substrate from the susceptor as shown in FIG. A high-frequency current is supplied at the same time as the temperature of the substrate drops to a predetermined temperature, and the substrate is brought into contact with the susceptor by operating a fork, thereby rapidly heating the substrate. FIG. 1 (c) is a plan view of FIG. 1 (b) as viewed from above. In this operation, the substrate is handled while being placed on the tray and heated by heat conduction through the tray, so it is necessary to consider the heat conduction of the tray. But there is no particular problem.

上記の操作による基板温度の昇降を十数回繰り返した
後、基板温度を700℃に戻し、原料ガスの供給を増し
て、第2図に成長Bと示されたエピタキシャル成長を実
施する。
After the substrate temperature is repeatedly raised and lowered by more than ten times by the above operation, the substrate temperature is returned to 700 ° C., the supply of the source gas is increased, and the epitaxial growth shown as growth B in FIG. 2 is performed.

基板をサセプタから持ち上げる距離は10mm程度あれば
十分に有効である。また、エピタキシャル成長の操作で
は、基板を持ち上げてサセプタ上に運び、下降させてサ
セプタに載せることは通常の作業であり、フォークの移
動及び保持機構によって本発明の操作を支障なく行うこ
とが出来る。
A distance of about 10 mm for lifting the substrate from the susceptor is sufficiently effective. In addition, in the operation of epitaxial growth, lifting a substrate, carrying it on a susceptor, lowering the substrate, and placing the substrate on the susceptor is a normal operation, and the operation of the present invention can be performed without any trouble by a fork moving and holding mechanism.

〔発明の効果〕〔The invention's effect〕

上記実施例の処理の如く、本発明では熱衝撃を与える
ための昇降温の速度を急ならしめているため、転位を移
動させる効果が大であり、最初のエピタキシャル成長層
に生じた転位が、以後の成長層に伝播することを効果的
に抑制している。その結果、本発明の気相成長法によ
り、欠陥密度の低い化合物半導体層をエピタキシャル成
長させることが可能となった。
As in the processing of the above embodiment, in the present invention, the rate of temperature rise and fall for applying a thermal shock is increased, so that the effect of dislocation movement is great, and the dislocation generated in the first epitaxial growth layer is Propagation to the growth layer is effectively suppressed. As a result, the compound semiconductor layer having a low defect density can be epitaxially grown by the vapor phase growth method of the present invention.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の実施に使用される装置を示す模式図、 第2図は転位の伝播抑止のための熱処理履歴を示す図、 第3図は昇降温に伴う歪の状態を示す模式図であって、 図に於いて 1は反応管、 2は成長室、 3はサセプタ、 4は基板、 5はトレイ、 6はフォーク、 7はRFコイル である。 FIG. 1 is a schematic diagram showing an apparatus used for carrying out the present invention, FIG. 2 is a diagram showing a heat treatment history for suppressing dislocation propagation, and FIG. In the figure, 1 is a reaction tube, 2 is a growth chamber, 3 is a susceptor, 4 is a substrate, 5 is a tray, 6 is a fork, and 7 is an RF coil.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】気相原料を単結晶基板面に供給し、該基板
結晶とは格子定数の異なる単結晶をエピタキシャル成長
させる処理に於いて、 結晶成長期間と次の結晶成長期間の間に、前記基板を、
該基板の加熱に使用するサセプタからの熱伝導を防止し
た状態で冷却し、次いで前記サセプタからの熱伝導によ
って前記基板を加熱する処理を、少なくも1回行うこと
を特徴とする気相成長法。
In a process for supplying a vapor-phase raw material to the surface of a single crystal substrate and epitaxially growing a single crystal having a lattice constant different from that of the substrate crystal, the crystal growth period and the next crystal growth period are separated. Substrate,
A step of cooling the substrate while preventing heat conduction from a susceptor used for heating the substrate, and then heating the substrate by heat conduction from the susceptor at least once. .
JP6280489A 1989-03-15 1989-03-15 Vapor phase epitaxy Expired - Lifetime JP2712505B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6280489A JP2712505B2 (en) 1989-03-15 1989-03-15 Vapor phase epitaxy

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6280489A JP2712505B2 (en) 1989-03-15 1989-03-15 Vapor phase epitaxy

Publications (2)

Publication Number Publication Date
JPH02243594A JPH02243594A (en) 1990-09-27
JP2712505B2 true JP2712505B2 (en) 1998-02-16

Family

ID=13210890

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6280489A Expired - Lifetime JP2712505B2 (en) 1989-03-15 1989-03-15 Vapor phase epitaxy

Country Status (1)

Country Link
JP (1) JP2712505B2 (en)

Also Published As

Publication number Publication date
JPH02243594A (en) 1990-09-27

Similar Documents

Publication Publication Date Title
US4876219A (en) Method of forming a heteroepitaxial semiconductor thin film using amorphous buffer layers
KR920008121B1 (en) Heteroepitaxial growth method
JPH0864791A (en) Epitaxial growth method
US5107317A (en) Semiconductor device with first and second buffer layers
JP3982788B2 (en) Method for forming semiconductor layer
JP2003218031A (en) Method of manufacturing semiconductor wafer
JP2712505B2 (en) Vapor phase epitaxy
WO2021210390A1 (en) Method for producing semiconductor substrate, semiconductor substrate, and method for preventing crack occurrence in growth layer
JP2004307253A (en) Method for manufacturing semiconductor substrate
EP0407233B1 (en) Method for fabricating a semiconductor substrate
JPH0536605A (en) Manufacture of compound semiconductor substrate
JPH01194319A (en) Vapor growth method and device for semiconductor
JPH0551295A (en) Production of compound semiconductor substrate
JP2743351B2 (en) Vapor phase epitaxy growth method
JPH0214513A (en) Formation of compound semiconductor layer
JPH0760790B2 (en) Compound semiconductor substrate
JPH0532486A (en) Production of compound semiconductor substrate
JPH08264456A (en) Growing method for crystal of compound semiconductor
JPH04199812A (en) Semiconductor crystal growth method
JP2719868B2 (en) Semiconductor substrate and method of manufacturing the same
JP2810299B2 (en) Method for forming compound semiconductor layer
TW202426716A (en) Single crystal silicon substrate equipped with nitride semiconductor layer, and method for manufacturing single crystal silicon substrate equipped with nitride semiconductor layer
KR20140003312A (en) Method of fabricating gallium nitride substrate and gallium nitride substrate fabricated by the same
JPH05283336A (en) Formation of compound semiconductor layer
JPH047819A (en) Gaas thin film