JPH01275500A - Epitaxial growth method for semiconductor - Google Patents

Abstract

PURPOSE:To confine misfit dislocation in a thin epitaxial film and to obtain a high quality crystal on the film when epitaxial growth of GaAs and AlGaAs is carried out on an Si substrate, by using a substrate having a prescribed crystal face. CONSTITUTION:An Si substrate having (001) face inclined by 2.4 deg. toward [100] or [010] direction is prepd. Epitaxial growth of GaAs and AlGaAs is carried out on the substrate. Misfit dislocation is confined in a thin epitaxial film of 20-50nm thickness on the surface of the substrate and a high quality epitaxial layer is grown on the film.

Description

Detailed Description of the Invention [Industrial Field of Application] This invention is based on the application of high-quality GaAs or AlGa on a Si substrate.
The present invention relates to a method for epitaxially growing an As single crystal, and in particular to a method for removing strain caused by the difference in lattice constant between Si and GaAs or AlGaAs.

[Conventional technology]

Epitaxial crystal growth of GaAs and AlGaAs on Si substrates allows GaAs devices to be fabricated without using GaAs, an expensive substrate material.
This is a promising technology for realizing inexpensive, high-speed semiconductor devices. Conventionally, epitaxial growth of this heterojunction system has been carried out by methods such as molecular beam epitaxial method (MIIE method) and organic metal vapor phase growth method (MO[:VD method). has seen considerable improvement so far. However, G
The difference in lattice constant between aAs or AlGaAs and Si is as large as about 4%, and GaAs or AlGaA
Because the coefficient of thermal expansion of s is about -3 times that of Sf, etc., the G
It has been impossible to grow aAs or AlGaAs on a Si substrate6. For example, the large difference in lattice constants causes misfit dislocations due to lattice mismatch, which degrades the quality of the grown layer, and Due to the difference in expansion coefficients, wafers grown at high temperatures would "warp" during the cooling process, making it impossible to obtain a flat em.

The best growth technology for this heterojunction system that has been established so far is represented by the following process.

■ The 0-plane using (001) Si as the substrate is [110
] It is better if it is tilted several degrees in the direction. Heat this substrate to 900℃
Heat treatment is performed as described above to remove the oxide film on the surface.

■ In the early stage of growth, the MOCVD method has a temperature of about 400℃ and Mtl.
In the E method, thin G of 20 nm or less is produced at about 100 to 400℃.
When growing an aAs layer, this layer is almost amorphous. Growth is interrupted in this state.

(2) Raise this wafer to a high temperature of 700°C to 750°C and grow the desired layer thereon.

■ Anneal the grown wafer as needed.

The basis of this process is the so-called two-step growth, which is described by Akiyama et al.
.

Crystal Growth 68. 1.
(Sep, 1984) pp 21-26)
It was developed by. This allows GaAs
Although the quality of the GaAs growth layer has improved, it is still
The quality of the crystal grown on the As substrate is far from that of the crystal grown on the As substrate.
8/In GaAs, it is on the order of several 1007 cm",
With GaAs/Si, it is extremely difficult to obtain a wafer of 10'/cm2 or less. Furthermore, the wafer develops a concave warpage during the cooling process to room temperature, and in the case of a 2-inch wafer, the center of the wafer is 5 μm relative to the surrounding area with an epitaxial layer thickness of 5 μm.
The concave surface has a depth of 0 μm to 100 μm. For this reason, the processing steps for making it into an IC are difficult.

Of the above two problems, the problem of wafer warping can be improved by lowering the growth temperature, but lowering the growth temperature further deteriorates the crystal quality. However, this problem was solved by migration enhanced epitaxy technology (Japanese Patent Application Laid-open No. 222628/1983). The former problem.

In other words, the problem of high dislocation density has remained unsolved until now. However, our recent research has revealed the following.

(2) In the conventional method, regardless of the MflE method or the MO(:Vl) method, for example, when growing GaAs, crystal growth is performed under As encasing conditions. On the other hand, misfit dislocations tend to occur on the S stabilization surface, for example, in step ① above.
Even in metals that form films at low temperatures, dislocations occur sporadically.

■ Due to the generation of this small number of dislocations, the stress in the epitaxial layer decreases, and no more dislocations occur. However, as the growth of the epitaxial layer progresses, stress gradually accumulates, eventually exceeding a critical value and causing dislocations. As the growth of the epitaxial layer progresses through this repetition, misfit dislocations inevitably generated due to lattice mismatch are distributed throughout the epitaxial layer.

Figure 2 shows the pattern of dislocation generation in a GaAs/Si wafer grown by the conventional method. )
300 on a Si substrate tilted once in the [1103] direction from the surface.
The figure shows a state in which GaAs was grown to a thickness of 20 μm at ℃. l is S
The i-substrate 2 is a GaAs layer which is amorphous due to low temperature growth. 3 shows an exaggerated atomic step. (B) shows the state after heat treatment at 700° C., where the GaAs is crystallized and the surface is rippled due to the stress between it and the substrate. Here, 4 is the generated dislocation. When some dislocations occur in this way, stress is alleviated and the generation of other dislocations is suppressed. (C) shows the results of growing GaAs on top of this at the same high temperature; the stress increases as it grows, and eventually exceeds the critical value for dislocation generation, generating new dislocations 69,7. . 6 particularly indicates dislocations generated from the surface. As a result, dislocations are evenly distributed in the direction of the thickness of the grown film, significantly deteriorating the quality of the crystal near the surface that is actually used as a semiconductor layer.

(Problem to be solved by the invention) Based on this new knowledge, the present invention completely confines misfit dislocations in a thin epitaxial film 20 to 50 nm from the substrate surface, and grows a high-quality epitaxial layer on it. The purpose is to provide technology.

[Means to solve the problem]

A first aspect of the present invention is characterized in that in epitaxial growth of GaAs and AlGaAs on a 51 substrate, a (001) plane substrate tilted by 2.4 degrees in the [100] or [010] direction is used as the Si substrate. .

[100
] or in the [010] direction θ=tan-' [(a
It is characterized by using a (001) plane tilted by t - a0)/ao].

Here, I
After growing a thin layer of a III-V compound by alternately supplying group II elements and group V elements, the substrate temperature was raised to 500°C or higher to generate a dislocation network within the thin layer, and then the temperature of the substrate was lowered. A III-V compound semiconductor may be grown by lowering the temperature to 300[deg.] C. or lower and alternately adding group (1) elements and group (2) elements.

[For production]

The most important point of the present invention is that misfit dislocations, which inevitably occur due to the difference in lattice constant between the substrate and the epitaxial layer, are almost completely generated at the very early stage of epitaxial growth. An atomic step on the Si substrate crystal surface is used as a trigger for the generation of this dislocation.

FIG. 1 shows the orientation of the Si substrate in the present invention.

That is, if the lattice constant of the substrate is aO + the lattice constant of the epitaxially grown film is a, then Sj (001) substrate [
lOO] direction or [010] direction θ= jan-'
[(at a0)/aol (1)
When using a substrate tilted by 0.001, the step density and the dislocation density caused by lattice mismatch match in both the [110] and [110] directions, which are the nearest atomic arrangement directions in the (001) plane. In the figure, λ indicates the interval between steps S. Since the generation energy of dislocations in the step is low, nearly 100% misfit dislocations occur, and there is a possibility that stress can be completely removed from the epitaxial layer. This condition is true for the GaAs/St system (oog
This is achieved by using a substrate tilted by 2.4 degrees in the [100] or [0101 direction on the plane.

By using a Si substrate with the above-mentioned orientation, dislocations in the epitaxially grown layer can be significantly reduced. However, it is difficult to completely generate misfit dislocations and completely remove stress from the epitaxial layer. This is because when dislocations occur during growth, stress is alleviated, making it difficult for the next dislocation to occur even if there is a trigger called an atomic step.

Ga, As, Ga,
When approximately one atomic amount of Ga and As atoms are alternately supplied in the order of 8s... at a low temperature of 300° C. or lower, Ga-stabilized surfaces and As-stabilized surfaces alternately appear. Since the generation of dislocations is suppressed on the iGa stabilizing surface, this method
Although no dislocation occurs even when grown to 0 to 50 nm, strong stress is inherent. This wafer was heated to 500℃
When the temperature is temporarily raised to a higher temperature, stress is rapidly released and misfit dislocations occur all at once, creating a dislocation network within the thin layer.For this reason, most dislocations occur in this thin layer. Trapped within the layer. By returning the wafer to a temperature of 300° C. or lower and performing the same alternate supply growth, it is possible to realize a high-quality wafer without warping.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIG. 3 shows an embodiment of the present invention, in which a (001) Si plane tilted by 2.4 degrees in the [100] direction is used as a substrate. That is, the density of atomic steps is made equal to the density of necessary misfit dislocations, and a < shift substrate is used. After heat treating the substrate at 900℃, the temperature was increased to 300℃.
and then the Ga-atomic layer equivalent (6,4 x 1
Figure (8) shows the state in which 5 Otv of GaAs was grown on a Si substrate by alternately supplying As-atomic fractions. The substrate, 2 is a GaAs layer, and 3 is an atomic step.

The major difference from the conventional method is that the GaAs layer 8 is not amorphous but single crystal. Furthermore, since Ga stabilizing surfaces appear periodically during growth, dislocations are less likely to occur.

Figure (El) shows the state after heat treatment at 580℃ for 15 minutes.The density of misfit dislocations required due to the difference in lattice constant is equal to the density of atomic steps on the substrate, so dislocations are removed all at once by heat treatment. Dislocations occur in layer 8 t! 49, almost all the dislocations are trapped within the thin layer 8. What is important here is to change the direction of inclination of the substrate to [100
] direction, so exactly the same thing is happening in the direction perpendicular to the plane of the paper in FIG. Figure 3 (C
) After the heat treatment, the substrate was cooled to 300°C again, and Ga,
This figure shows the result of growing GaAs to 2 μm by alternately supplying 8s, and a crystal in which almost no dislocations propagate is obtained in the GaAs layer 5. In this case, no warping of the que was observed.

Even if the above-mentioned angle of inclination in the [100] or [010] direction, which is 2.4 degrees, fluctuates by approximately ±0.2 degrees, an epitaxial layer containing almost no dislocations can be grown.

Other compound semiconductors on Si, such as InP, In
Similar effects can be obtained with As etc. as long as a substrate crystal satisfying the above-mentioned formula (1) is used.

(Effects of the Invention) As explained above, according to the present invention, it is possible to obtain a crystal with almost no influence of misfit dislocations caused by the difference in lattice constants between St and GaAs. Devices can be made extremely cheaply.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the Si substrate orientation in the present invention, FIG. 2 is a schematic diagram explaining the conventional method, and FIG. 3 is a schematic diagram explaining the present invention in detail. 1... -5i substrate, 2... Amorphous GaAs thin layer, 3... Atomic step on Si substrate surface, 4... Misfit dislocation, 5... -GaΔS thick layer, 6.7... Accompanying growth Dislocation newly generated due to stress accumulation, 8...Single crystal GaAS thin layer, 9...Dislocation network. 2.4゜S [6 diagrams to explain the 0 Oi friends @
Figure 1 ↑ Enoki's diagram explaining the advantages of plain rice Figure 2

Claims (1)

[Claims] 1) A semiconductor characterized in that in epitaxial growth of GaAs and AlGaAs on a Si substrate, a (001) plane substrate tilted by 2.4 degrees in the [100] or [010] direction is used as the Si substrate. Epitaxial growth method. 2) In epitaxial growth for growing a zinc blende crystal (lattice constant: a_1) on a Si substrate (lattice constant: a_0), [100] or [010] is used as the Si substrate.
] A semiconductor epitaxial growth method characterized by using a (001) plane tilted by θ=tan^-^1 [(a_1-a_0)/a_0] in the direction. 3) 300 nm on the Si substrate according to claim 1 or 2.
By alternately supplying group III elements and group V elements at a temperature below ℃
After growing the thin layer of the III-V compound, the temperature of the substrate is raised to 500° C. or higher to generate a dislocation network within the thin layer, and then the temperature of the substrate is lowered to 300° C. or lower. A semiconductor epitaxial growth method characterized by growing a III-V group compound semiconductor by alternately adding a group element and a group V element.