JPH04271114A - Defect reduction method of compound semiconductor - Google Patents

Defect reduction method of compound semiconductor

Info

Publication number
JPH04271114A
JPH04271114A JP41612790A JP41612790A JPH04271114A JP H04271114 A JPH04271114 A JP H04271114A JP 41612790 A JP41612790 A JP 41612790A JP 41612790 A JP41612790 A JP 41612790A JP H04271114 A JPH04271114 A JP H04271114A
Authority
JP
Japan
Prior art keywords
temperature
compound semiconductor
semiconductor
crystal
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP41612790A
Other languages
Japanese (ja)
Inventor
Masayoshi Umeno
正義 梅野
Takashi Jinbo
神保 孝志
Tetsuo Soga
哲夫 曽我
Mitsuru Imaizumi
充 今泉
Takashi Saka
坂 貴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Daido Steel Co Ltd
Nagoya Institute of Technology NUC
Original Assignee
Daido Steel Co Ltd
Nagoya Institute of Technology NUC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Daido Steel Co Ltd, Nagoya Institute of Technology NUC filed Critical Daido Steel Co Ltd
Priority to JP41612790A priority Critical patent/JPH04271114A/en
Publication of JPH04271114A publication Critical patent/JPH04271114A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce defects like dislocation existing in compound semiconductor formed on a semiconductor substrate by epitaxial growth. CONSTITUTION:A semiconductor wafer 10 formed by epitaxially growing compound semiconductor 16 on a semiconductor substrate 12 is irradiated with laser light, and a boundary part 14 is locally heated. Thereby the temperature of the boundary part 14 is set higher than that of the compound semiconductor 16, which is kept at a temperature capable of crystal rearrangement wherein defects can be moved. After that, the heating with laser light is interrupted, and the temperature of the semiconductor wafer 10 is wholly decreased. Since the temperature of the boundary part 14 in which crystal defects are generated by lattice mismatch and the like at the time of decreasing the temperature is higher than the temperature of the compound semiconductor 16 because of local heating, the temperature fall is slow, and crystal of the compound semiconductor 16 is fixed in advance. Hence crystal defects generated in the boundary part 14 is prevented from spreading over the compound semiconductor 16.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、エピタキシャル成長に
よって半導体基板上に設けられた化合物半導体中に存在
する転位等の欠陥を低減する方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for reducing defects such as dislocations existing in a compound semiconductor formed on a semiconductor substrate by epitaxial growth.

【0002】0002

【従来の技術とその課題】Si等の半導体基板上に化合
物半導体をエピタキシャル成長させた半導体ウェハが、
OEIC(光電子集積回路)や太陽電池,発光ダイオー
ド,半導体レーザなどに多用されている。かかる半導体
ウェハは、半導体基板とその上に積層される化合物半導
体との間で格子定数や熱膨張係数が相違すると、エピタ
キシャル成長後の降温時に、格子不整合や熱歪によって
転位等の結晶欠陥が化合物半導体内に多数発生するとい
う問題があった。
[Prior art and its problems] A semiconductor wafer in which a compound semiconductor is epitaxially grown on a semiconductor substrate such as Si,
It is widely used in OEICs (optoelectronic integrated circuits), solar cells, light emitting diodes, semiconductor lasers, etc. In such semiconductor wafers, if the lattice constant or thermal expansion coefficient differs between the semiconductor substrate and the compound semiconductor layered thereon, crystal defects such as dislocations may form in the compound due to lattice mismatch or thermal strain when the temperature is lowered after epitaxial growth. There is a problem in that a large number of these occur in semiconductors.

【0003】本発明は以上の事情を背景として為された
もので、その目的とするところは、半導体ウェハに存在
する転位等の内部欠陥を低減することにある。
The present invention was made against the background of the above circumstances, and its purpose is to reduce internal defects such as dislocations existing in semiconductor wafers.

【0004】0004

【課題を解決するための手段】かかる目的を達成するた
めに、本発明は、半導体基板上にその半導体基板とは格
子定数または熱膨張係数が異なる化合物半導体をエピタ
キシャル成長させた半導体ウェハにレーザ光を照射し、
その半導体基板と化合物半導体との境界部分のみを局部
加熱することにより、その境界部分の温度がその化合物
半導体の温度よりも相対的に高く且つその化合物半導体
の温度が結晶の再配列が可能な温度となるようにし、そ
の後、前記レーザ光による局部加熱を中止してその半導
体ウェハを降温させることを特徴とする。
[Means for Solving the Problems] In order to achieve the above object, the present invention provides a semiconductor wafer in which a compound semiconductor having a lattice constant or thermal expansion coefficient different from that of the semiconductor substrate is epitaxially grown, and a laser beam is applied to the semiconductor wafer. irradiate,
By locally heating only the boundary portion between the semiconductor substrate and the compound semiconductor, the temperature of the boundary portion is relatively higher than the temperature of the compound semiconductor, and the temperature of the compound semiconductor is a temperature at which the crystals can be rearranged. The method is characterized in that the local heating by the laser beam is stopped and the temperature of the semiconductor wafer is lowered.

【0005】[0005]

【作用および発明の効果】すなわち、エピタキシャル成
長させられた化合物半導体内の欠陥には、エピタキシャ
ル成長後の降温時に結晶内の転位が凍結する際に、格子
不整合や熱歪に起因して化合物半導体と半導体基板との
境界付近に生じる結晶欠陥が化合物半導体内に波及した
ものが多く含まれているため、これを防止するには、結
晶欠陥が発生する境界部分の温度を化合物半導体の温度
よりも高くした状態で温度降下させて化合物半導体の結
晶を先に固定化すれば良く、本発明は、半導体ウェハに
レーザ光を照射して上記境界部分のみを局部加熱するこ
とにより、その境界部分の温度を化合物半導体の温度よ
りも相対的に高くし、且つその化合物半導体の温度を結
晶の再配列が可能な温度となるようにし、その後、レー
ザ光による局部加熱を中止して半導体ウェハを降温させ
るようにしたのである。これにより、半導体ウェハの降
温時には、化合物半導体の結晶が境界部分よりも先に固
定化され、その後に格子不整合等によって境界部分に結
晶欠陥が生じても、その結晶欠陥が化合物半導体内に波
及することがなく、化合物半導体内の欠陥が低減される
[Operation and Effects of the Invention] In other words, defects in an epitaxially grown compound semiconductor are caused by lattice mismatch and thermal strain when dislocations in the crystal freeze when the temperature drops after epitaxial growth. Many crystal defects that occur near the boundary with the substrate spread into the compound semiconductor, so to prevent this, the temperature at the boundary where crystal defects occur is made higher than the temperature of the compound semiconductor. It is sufficient to first fix the crystal of the compound semiconductor by lowering the temperature while the semiconductor wafer is in a state of The temperature of the compound semiconductor is made relatively higher than that of the semiconductor, and the temperature of the compound semiconductor is set to a temperature that allows crystal rearrangement, and then local heating by laser light is stopped and the temperature of the semiconductor wafer is lowered. It is. As a result, when the semiconductor wafer cools down, the crystals of the compound semiconductor are fixed before the boundary area, and even if crystal defects are subsequently generated at the boundary area due to lattice mismatch, the crystal defects will spread to the compound semiconductor. This reduces defects within the compound semiconductor.

【0006】ここで、レーザ光により半導体基板と化合
物半導体との境界部分のみを局部加熱する方法は、半導
体基板および化合物半導体の何れか一方を透過して他方
に吸収される光エネルギーのレーザ光を用いれば良く、
具体的には両半導体のバンドギャップエネルギーの中間
の光エネルギーを有するレーザ光を、バンドギャップエ
ネルギーが大きい方から照射することとなる。なお、半
導体基板と化合物半導体との間に中間層を形成し、その
中間層において光エネルギーが吸収されるようにしても
差支えない。
Here, a method of locally heating only the boundary area between a semiconductor substrate and a compound semiconductor using a laser beam is to use a laser beam whose optical energy is transmitted through either the semiconductor substrate or the compound semiconductor and absorbed by the other. Just use it,
Specifically, laser light having a light energy intermediate between the band gap energies of both semiconductors is irradiated from the one with the larger band gap energy. Note that an intermediate layer may be formed between the semiconductor substrate and the compound semiconductor, and light energy may be absorbed in the intermediate layer.

【0007】また、上記レーザ光の照射は、半導体ウェ
ハが室温などの低温に保持された状態において行なわれ
、境界部分の局部加熱の熱伝導によって化合物半導体が
結晶再配列可能な温度まで昇温させられるようにしても
良いが、エピタキシャル成長後の降温時など化合物半導
体を含む半導体ウェハの温度が未だ結晶再配列可能な温
度に維持されている状態でレーザ光を照射し、境界部分
の温度をその化合物半導体の温度よりも相対的に高くす
るようにしても差支えない。
[0007] Furthermore, the laser beam irradiation is performed while the semiconductor wafer is kept at a low temperature such as room temperature, and the temperature is raised to a temperature at which the compound semiconductor crystals can be rearranged by thermal conduction of local heating at the boundary. However, when the temperature of a semiconductor wafer containing a compound semiconductor is still maintained at a temperature that allows crystal rearrangement, such as when the temperature is lowered after epitaxial growth, laser light is irradiated to reduce the temperature of the boundary part to that of the compound. There is no problem in making the temperature relatively higher than the temperature of the semiconductor.

【0008】[0008]

【実施例】図1は、本発明方法を適用して製造された半
導体ウェハ10の構成を説明する図で、板厚が300〜
500μm程度のSi基板12上には、中間層として膜
厚が0.5μm程度のGaAs層14が設けられ、その
GaAs層14上には更に膜厚が2μm程度のGaP層
16が設けられている。GaAs層14およびGaP層
16は、有機金属化学気相成長(MOCVD;Meta
l Organic Chemical Vapor 
Deposition)法を用いてSi基板12上にエ
ピタキシャル成長させられたものであり、Si基板12
は半導体基板に相当し、GaP層16は化合物半導体に
相当する。また、GaAs層14はそれ等の境界部分に
相当する。なお、これ等の半導体Si,GaAs,Ga
Pの格子定数(Å),熱膨張係数(℃−1),およびバ
ンドギャップエネルギーEg(eV)は表1の通りであ
り、SiおよびGaPはその格子定数および熱膨張係数
が共に相違している。
[Example] Fig. 1 is a diagram illustrating the structure of a semiconductor wafer 10 manufactured by applying the method of the present invention.
A GaAs layer 14 with a thickness of about 0.5 μm is provided as an intermediate layer on the Si substrate 12 with a thickness of about 500 μm, and a GaP layer 16 with a thickness of about 2 μm is further provided on the GaAs layer 14. . The GaAs layer 14 and the GaP layer 16 are formed by metal organic chemical vapor deposition (MOCVD).
l Organic Chemical Vapor
This is epitaxially grown on the Si substrate 12 using the Si substrate 12 deposition method.
corresponds to a semiconductor substrate, and the GaP layer 16 corresponds to a compound semiconductor. Further, the GaAs layer 14 corresponds to the boundary portion between them. Note that these semiconductors Si, GaAs, Ga
The lattice constant (Å), thermal expansion coefficient (°C-1), and band gap energy Eg (eV) of P are shown in Table 1, and Si and GaP have different lattice constants and thermal expansion coefficients. .

【0009】[0009]

【0010】上記GaAs層14およびGaP層16の
エピタキシャル成長について、図2のタイムチャートを
参照しつつ具体的に説明すると、先ず、Si基板12を
MOCVD装置の反応炉内にセットした後、1000℃
程度の高温でベーキングを行って表面を浄化する。次に
、加熱温度を450℃程度まで降下させた後、2段階成
長法にてそのSi基板12上にGaAs層14をエピタ
キシャル成長させる。2段階成長は、先ず450℃程度
の低温で反応炉内にGaAsの原料ガスを導入して結晶
成長させ、その後750℃程度まで昇温して再びGaA
sの原料ガスを導入して結晶成長させるものである。 高温時のGaAs原料ガスの導入時間は、形成すべきG
aAs層14の膜厚に応じて定められ、これにより、S
i基板12上に0.5μm程度の膜厚のGaAs層14
が形成される。続いて、加熱温度を850℃程度まで昇
温し、反応炉内にGaPの原料ガスを導入することによ
り、上記GaAs層14上に2μm程度のGaP層16
をエピタキシャル成長させる。この場合のGaP原料ガ
スの導入時間も、形成すべきGaP層16の膜厚に応じ
て定められ、これにより、Si基板12上にGaAs層
14およびGaP層16をエピタキシャル成長させた半
導体ウェハ10が得られる。
The epitaxial growth of the GaAs layer 14 and the GaP layer 16 will be explained in detail with reference to the time chart shown in FIG.
Clean the surface by baking at a moderately high temperature. Next, after lowering the heating temperature to about 450° C., a GaAs layer 14 is epitaxially grown on the Si substrate 12 by a two-step growth method. In the two-step growth, GaAs raw material gas is first introduced into the reactor at a low temperature of about 450°C to grow the crystal, and then the temperature is raised to about 750°C to grow GaAs again.
In this method, a raw material gas of s is introduced to cause crystal growth. The introduction time of GaAs raw material gas at high temperature is determined by the amount of G to be formed.
It is determined according to the film thickness of the aAs layer 14, so that S
A GaAs layer 14 with a thickness of about 0.5 μm is formed on the i-substrate 12.
is formed. Subsequently, the heating temperature is raised to about 850° C. and a GaP raw material gas is introduced into the reactor, thereby forming a GaP layer 16 of about 2 μm on the GaAs layer 14.
grown epitaxially. The introduction time of the GaP raw material gas in this case is also determined according to the thickness of the GaP layer 16 to be formed, and thereby a semiconductor wafer 10 in which the GaAs layer 14 and the GaP layer 16 are epitaxially grown on the Si substrate 12 is obtained. It will be done.

【0011】その後、かかる半導体ウェハ10には、本
発明の欠陥低減法に従って欠陥低減処理が施される。す
なわち、半導体ウェハ10を上記MOCVD装置の反応
炉から取り出した後、GaP層16側から半導体ウェハ
10の全面にルビーレーザ光を連続して照射するととも
に、同時に半導体ウェハ10の表面および裏面をファン
で空気冷却し、これを約2時間継続した後、そのファン
による空気冷却を更に継続したままルビーレーザ光の照
射を停止して、半導体ウェハ10を室温まで降温させる
のである。ルビーレーザ光の光エネルギーは約1.79
eVであるため、それよりもバンドギャップエネルギー
Egが大きいGaP層16をルビーレーザ光は透過し、
バンドギャップエネルギーEgが1.79eVよりも小
さいGaAs層14で吸収される。このため、そのGa
As層14およびGaAs/GaP界面近傍のみが局部
加熱されるとともに、その熱が所定の温度勾配をもって
GaP層16に伝導する。この時のレーザ出力は、Ga
P層16の大部分が400〜500℃程度、すなわちG
aPの結晶の再配列が可能で転位等の結晶欠陥が移動で
きる温度となるように設定され、本実施例では500m
Wである。また、局部加熱されるGaAs層14および
GaAs/GaP界面近傍では、上記GaP層16より
も充分に高い温度となり、2時間後にレーザ光の照射が
停止されることにより、GaAs層14およびGaP層
16は所定の温度差を有する状態で温度降下させられる
Thereafter, the semiconductor wafer 10 is subjected to a defect reduction process according to the defect reduction method of the present invention. That is, after the semiconductor wafer 10 is taken out from the reactor of the MOCVD apparatus, the entire surface of the semiconductor wafer 10 is continuously irradiated with ruby laser light from the GaP layer 16 side, and at the same time, the front and back surfaces of the semiconductor wafer 10 are irradiated with a fan. After cooling with air and continuing this for about 2 hours, irradiation of ruby laser light is stopped while cooling with air by the fan is continued, and the temperature of the semiconductor wafer 10 is lowered to room temperature. The optical energy of ruby laser light is approximately 1.79
eV, the ruby laser light passes through the GaP layer 16 whose band gap energy Eg is larger than that,
It is absorbed by the GaAs layer 14 whose band gap energy Eg is smaller than 1.79 eV. For this reason, the Ga
Only the As layer 14 and the vicinity of the GaAs/GaP interface are locally heated, and the heat is conducted to the GaP layer 16 with a predetermined temperature gradient. The laser output at this time is Ga
Most of the P layer 16 is at about 400 to 500°C, that is, G
The temperature is set so that the aP crystal can be rearranged and crystal defects such as dislocations can move, and in this example, the temperature is set at 500 m.
It is W. In addition, the locally heated GaAs layer 14 and the vicinity of the GaAs/GaP interface reach a temperature sufficiently higher than that of the GaP layer 16, and the laser beam irradiation is stopped after 2 hours. is lowered in temperature with a predetermined temperature difference.

【0012】このようにGaP層16が400〜500
℃程度まで昇温されると、そのGaP層16はアニール
されて転位等の内部欠陥が減少する。また、その後の降
温時には、GaP層16がGaAs層14よりも低温で
あるためそのGaP層16の結晶が先に凍結され、その
後にGaAs層14やGaAs/GaP界面近傍の結晶
が凍結されることとなり、格子定数や熱膨張係数の相違
に起因してGaAs層14やGaAs/GaP界面近傍
に転位等の結晶欠陥が発生しても、それがGaP層16
内へ波及することはなく、上記アニールによるGaP層
16内の結晶欠陥の低減状態が良好に維持される。
[0012] In this way, the GaP layer 16 has a thickness of 400 to 500
When the temperature is raised to about .degree. C., the GaP layer 16 is annealed and internal defects such as dislocations are reduced. Furthermore, when the temperature subsequently decreases, since the GaP layer 16 is at a lower temperature than the GaAs layer 14, the crystals of the GaP layer 16 are frozen first, and then the GaAs layer 14 and the crystals near the GaAs/GaP interface are frozen. Therefore, even if crystal defects such as dislocations occur in the GaAs layer 14 or near the GaAs/GaP interface due to differences in lattice constants and thermal expansion coefficients, they will not occur in the GaP layer 16.
The crystal defects in the GaP layer 16 are kept well reduced by the annealing.

【0013】因に、上記レーザ照射による欠陥低減処理
を行った本実施例の半導体ウェハ10と、欠陥低減処理
を行わない従来の半導体ウェハとを用いて、フッ酸およ
び硝酸を混合したエッチング液によりGaP層16の表
面をエッチングし、欠陥によって生じるエッチピットの
密度を調べたところ、本実施例品では3×107 (個
/cm2 )であるのに対し、従来品は7×107 (
個/cm2 )であり、結晶欠陥の数が半分以下となっ
た。図3は本実施例品におけるエッチング表面の結晶構
造を示す光学顕微鏡写真で、図4は従来品におけるエッ
チング表面の結晶構造を示す光学顕微鏡写真であり、本
実施例品ではエッチピットの数が略半減していることが
判る。
Incidentally, using the semiconductor wafer 10 of this embodiment subjected to the defect reduction treatment by laser irradiation and a conventional semiconductor wafer not subjected to the defect reduction treatment, an etching solution containing a mixture of hydrofluoric acid and nitric acid was used. When the surface of the GaP layer 16 was etched and the density of etch pits caused by defects was investigated, the density of etch pits caused by defects was found to be 3 x 107 (pits/cm2) in the product of this example, while it was 7 x 107 (pits/cm2) in the conventional product.
crystal defects/cm2), and the number of crystal defects was reduced to less than half. Figure 3 is an optical microscope photograph showing the crystal structure of the etched surface of the product of this example, and Figure 4 is an optical microscope photograph showing the crystal structure of the etched surface of the conventional product. It can be seen that it has been reduced by half.

【0014】以上、本発明の一実施例を図面に基づいて
詳細に説明したが、本発明は他の態様で実施することも
できる。
Although one embodiment of the present invention has been described above in detail with reference to the drawings, the present invention can also be implemented in other embodiments.

【0015】例えば、前記実施例では半導体基板として
Si基板12が用いられているが、化合物半導体から成
る半導体基板を用いることも可能である。その半導体基
板上にエピタキシャル成長させられる化合物半導体につ
いても、GaP以外の III−V族化合物半導体やそ
の他の化合物半導体を採用できる。使用するレーザ光の
種類やレーザ光の照射条件は半導体の種類に応じて適宜
定められ、例えばSi基板上にGaAsをエピタキシャ
ル成長させただけの半導体ウェハの場合には、光エネル
ギーが約1.16eVのYAGレーザなどが好適に用い
られる。
For example, in the embodiment described above, the Si substrate 12 is used as the semiconductor substrate, but it is also possible to use a semiconductor substrate made of a compound semiconductor. As for the compound semiconductor epitaxially grown on the semiconductor substrate, a III-V compound semiconductor other than GaP or other compound semiconductors can be used. The type of laser light to be used and the conditions for irradiation of the laser light are determined as appropriate depending on the type of semiconductor. For example, in the case of a semiconductor wafer that is simply epitaxial growth of GaAs on a Si substrate, the light energy is approximately 1.16 eV. A YAG laser or the like is preferably used.

【0016】また、前記実施例ではレーザ光の照射によ
ってGaP層16を結晶再配列可能温度まで昇温してい
るが、例えばエピタキシャル成長後の降温過程でレーザ
光を照射することにより、GaAs層14をGaP層1
6よりも高温度とし、その後レーザ光の照射を停止して
それ等が温度差を有する状態で降温させても良い。レー
ザ光の照射は必ずしも連続である必要はなく、所定の時
間間隔でパルス照射するようにしても良い。
Furthermore, in the embodiment described above, the temperature of the GaP layer 16 is raised to a temperature at which crystal rearrangement is possible by irradiation with a laser beam, but the GaAs layer 14 can be GaP layer 1
The temperature may be set higher than 6, and then the laser beam irradiation may be stopped and the temperature may be lowered while there is a temperature difference between them. Laser light irradiation does not necessarily have to be continuous, and pulse irradiation may be performed at predetermined time intervals.

【0017】また、前記実施例ではMOCVD装置を用
いて有機金属化学気相成長法により化合物半導体をエピ
タキシャル成長させる場合について説明したが、分子線
エピタキシー法によるものなど、他のエピタキシャル成
長装置を用いることもできる。化合物半導体をエピタキ
シャル成長させる際の温度条件等についても適宜変更で
きる。
Furthermore, in the above embodiment, the case where a compound semiconductor is epitaxially grown by a metal organic chemical vapor deposition method using an MOCVD apparatus has been described, but other epitaxial growth apparatuses such as those using a molecular beam epitaxy method can also be used. . The temperature conditions and the like when epitaxially growing a compound semiconductor can also be changed as appropriate.

【0018】また、前記実施例では中間層としてGaA
s層14が設けられているが、かかるGaAs層14を
省略してSi基板12上に直接GaP層16をエピタキ
シャル成長させることもできるし、GaAs層14の代
わりにバンドギャップエネルギーEgが小さいInGa
As等を中間層として設けることもできる。
Further, in the above embodiment, GaA is used as the intermediate layer.
Although the s-layer 14 is provided, the GaP layer 16 can be epitaxially grown directly on the Si substrate 12 by omitting the GaAs layer 14, or the GaP layer 16 can be epitaxially grown directly on the Si substrate 12, or InGa having a small band gap energy Eg can be used instead of the GaAs layer 14.
As or the like can also be provided as an intermediate layer.

【0019】また、前記実施例ではGaP層16が一層
設けられているだけであるが、ヘテロ構造などを構成す
る複数の化合物半導体層を備えた半導体ウェハにも本発
明は適用され得る。
Further, in the above embodiment, only one GaP layer 16 is provided, but the present invention can also be applied to a semiconductor wafer having a plurality of compound semiconductor layers constituting a heterostructure or the like.

【0020】また、前記実施例では半導体ウェハ10の
表面および裏面をファンにより空気冷却し、GaAs層
14とGaP層16との温度差が大きくなるようにして
いるが、ファンによる空気冷却は必ずしも必須なもので
はない。
Furthermore, in the embodiment described above, the front and back surfaces of the semiconductor wafer 10 are air-cooled by a fan to increase the temperature difference between the GaAs layer 14 and the GaP layer 16, but air cooling by a fan is not always necessary. It's not something.

【0021】その他一々例示はしないが、本発明は当業
者の知識に基づいて種々の変更,改良を加えた態様で実
施することができる。
Although no other examples are given, the present invention can be implemented with various modifications and improvements based on the knowledge of those skilled in the art.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明による欠陥低減処理が施された半導体ウ
ェハの一例を説明する構成図である。
FIG. 1 is a configuration diagram illustrating an example of a semiconductor wafer that has been subjected to defect reduction processing according to the present invention.

【図2】図1の半導体ウェハのエピタキシャル層形成時
における温度履歴を示すタイムチャートである。
FIG. 2 is a time chart showing the temperature history during the formation of an epitaxial layer of the semiconductor wafer in FIG. 1;

【図3】図1の半導体ウェハのエッチング表面の結晶構
造を示す光学顕微鏡写真である。
FIG. 3 is an optical micrograph showing the crystal structure of the etched surface of the semiconductor wafer in FIG. 1;

【図4】本発明による欠陥低減処理を施さなかった半導
体ウェハのエッチング表面の結晶構造を示す光学顕微鏡
写真である。
FIG. 4 is an optical micrograph showing the crystal structure of the etched surface of a semiconductor wafer that was not subjected to the defect reduction treatment according to the present invention.

【符号の説明】[Explanation of symbols]

10:半導体ウェハ 12:Si基板(半導体基板) 14:GaAs層(境界部分) 16:GaP層(化合物半導体) 10: Semiconductor wafer 12: Si substrate (semiconductor substrate) 14: GaAs layer (boundary part) 16: GaP layer (compound semiconductor)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  半導体基板上に該半導体基板とは格子
定数または熱膨張係数が異なる化合物半導体をエピタキ
シャル成長させた半導体ウェハにレーザ光を照射し、該
半導体基板と化合物半導体との境界部分のみを局部加熱
することにより、該境界部分の温度が該化合物半導体の
温度よりも相対的に高く且つ該化合物半導体の温度が結
晶の再配列が可能な温度となるようにし、その後、前記
レーザ光による局部加熱を中止して該半導体ウェハを降
温させることを特徴とする化合物半導体の欠陥低減法。
1. A semiconductor wafer in which a compound semiconductor having a lattice constant or thermal expansion coefficient different from that of the semiconductor substrate is epitaxially grown is irradiated with a laser beam, and only the boundary portion between the semiconductor substrate and the compound semiconductor is locally grown. By heating, the temperature of the boundary portion is made relatively higher than the temperature of the compound semiconductor and the temperature of the compound semiconductor becomes a temperature at which the crystals can be rearranged, and then local heating by the laser beam is performed. 1. A method for reducing defects in compound semiconductors, which comprises stopping the process and cooling the semiconductor wafer.
JP41612790A 1990-12-27 1990-12-27 Defect reduction method of compound semiconductor Pending JPH04271114A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP41612790A JPH04271114A (en) 1990-12-27 1990-12-27 Defect reduction method of compound semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP41612790A JPH04271114A (en) 1990-12-27 1990-12-27 Defect reduction method of compound semiconductor

Publications (1)

Publication Number Publication Date
JPH04271114A true JPH04271114A (en) 1992-09-28

Family

ID=18524368

Family Applications (1)

Application Number Title Priority Date Filing Date
JP41612790A Pending JPH04271114A (en) 1990-12-27 1990-12-27 Defect reduction method of compound semiconductor

Country Status (1)

Country Link
JP (1) JPH04271114A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012504857A (en) * 2008-10-01 2012-02-23 インターナショナル・ビジネス・マシーンズ・コーポレーション Method and system for eliminating dislocations in an active region of a semiconductor body

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012504857A (en) * 2008-10-01 2012-02-23 インターナショナル・ビジネス・マシーンズ・コーポレーション Method and system for eliminating dislocations in an active region of a semiconductor body
US8865571B2 (en) 2008-10-01 2014-10-21 International Business Machines Corporation Dislocation engineering using a scanned laser
US8865572B2 (en) 2008-10-01 2014-10-21 International Business Machines Corporation Dislocation engineering using a scanned laser

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