JPH0263115A - Selective growth of thin film - Google Patents

Selective growth of thin film

Info

Publication number
JPH0263115A
JPH0263115A JP21553588A JP21553588A JPH0263115A JP H0263115 A JPH0263115 A JP H0263115A JP 21553588 A JP21553588 A JP 21553588A JP 21553588 A JP21553588 A JP 21553588A JP H0263115 A JPH0263115 A JP H0263115A
Authority
JP
Japan
Prior art keywords
grown
substrate
thin film
window part
growth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21553588A
Other languages
Japanese (ja)
Inventor
Koichi Ishida
石田 宏一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21553588A priority Critical patent/JPH0263115A/en
Publication of JPH0263115A publication Critical patent/JPH0263115A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To sharply reduce a lattice defect density at the upper part of a selective epitaxial growth layer by a method wherein a thin film is grown in such a way that a ratio of a height to a width of a groove satisfies a specific condition. CONSTITUTION:SiO2 12 with a film thickness of (h) is grown on a (100) Si substrate 11 by thermal oxidation; then, a square window part where a <110> direction is used as one side of a length (w) is formed in an SiO2 mask material by a dry etching operation. Then, the substrate is installed in a low-pressure MOCVD apparatus so as to obtain h>w tantheta; the surface of Si exposed on the bottom of the window part is cleaned in AsH3 which has been diluted by H2; then, GaAs 13 is grown selectively in the window part in an atomic-layer growth mode by using diethyl gallium chloride (DEGaA) and AsH3 as raw materials.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は格子欠陥密度の低い薄膜の選択成長方法に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) This invention relates to a method for selectively growing thin films with low lattice defect density.

(従来の技術) これまで基板と格子定数の大きく異なるエピタキシャル
薄膜、たとえばSi基板上のGaAs薄膜の成長は主に
有機金属気相成長法(MOCVD)、分子線エピタキシ
ャル成長法(MBE)を用い、2段階成長法と呼ばれて
いる方法によって行なわれていた。この方法では、まず
低温の成長温度で薄いバッファ層を成長する。このバッ
ファ層と基板との界面にはミスフィツト転位が導入され
、エピタキシャル層と基板との格子定数の相異による応
力は緩和され、バッファ層の格子は本来の格子にもどる
(Prior art) Up until now, epitaxial thin films with significantly different lattice constants from the substrate, such as GaAs thin films on Si substrates, have mainly been grown using metal organic chemical vapor deposition (MOCVD) and molecular beam epitaxial growth (MBE). This was done using a method called the stepwise growth method. In this method, a thin buffer layer is first grown at a low growth temperature. Misfit dislocations are introduced into the interface between the buffer layer and the substrate, the stress due to the difference in lattice constant between the epitaxial layer and the substrate is relaxed, and the lattice of the buffer layer returns to its original lattice.

よってこのバッファ層の上に高温成長時に容易にエピタ
キシャル層を成長することができる。
Therefore, an epitaxial layer can be easily grown on this buffer layer during high temperature growth.

(発明が解決しようとしている問題点)しかし、このよ
うに成長したエピタキシャル薄膜の転位密度は109〜
108cm−2と非常に多い。この転位の一部はミスフ
ィツト転位の端部であり、その他は成長中において局所
的な応力の集中によって生じたものである。
(Problem to be solved by the invention) However, the dislocation density of the epitaxial thin film grown in this way is 109~
It is very large at 108 cm-2. Some of these dislocations are ends of misfit dislocations, and others are caused by local stress concentration during growth.

このエピタキシャル層中の転位密度を低減するために、
エピタキシャル層成長中に歪超格子を加えることや、成
長後に熱処理をすることなどが試みられている。しかし
ながら、このような処理をほどこしても、エピタキシャ
ル層中の転位密度はたかだか10’cm−2程度までし
か減少しない。また、歪超格子を加えたり、熱処理をほ
どこすことは、エピタキシャル層の製造方法が非常に煩
雑になる。
To reduce the dislocation density in this epitaxial layer,
Attempts have been made to add a strained superlattice during epitaxial layer growth and to perform heat treatment after growth. However, even with such treatment, the dislocation density in the epitaxial layer is reduced to only about 10'cm-2 at most. Furthermore, adding a strained superlattice or applying heat treatment makes the manufacturing method of the epitaxial layer extremely complicated.

本発明の目的はこの問題を解決した簡便な低転位密度の
エピタキシャル薄膜の製造方法を提供することにある。
An object of the present invention is to provide a simple method for manufacturing an epitaxial thin film with a low dislocation density, which solves this problem.

(問題点を解決するための手段) この発明の要旨とするところは溝部分への(111J面
を転位のすべり面として有する薄膜の選択成長において
溝の高さhと幅Wの比をh>wtanθを満たすように
大きくとることにより(θは(111)面と基板表面の
法線のなす角)、格子欠陥の薄膜の上方への伝播を抑制
することにある。
(Means for Solving the Problems) The gist of the present invention is to selectively grow a thin film having a 111J plane as a dislocation slip plane on a groove portion by changing the ratio of the height h and width W of the groove to h> By setting wtan θ large enough to satisfy wtan θ (θ is the angle between the (111) plane and the normal to the substrate surface), the purpose is to suppress the propagation of lattice defects upward in the thin film.

(作用) 一般にヘテロエピタキシャル層中の格子欠陥は、その多
くは界面近傍で発生し、上方に伝播する。格子欠陥は界
面に発生するミスフィツト転位の端部や、局所的な応力
の集中によって生じるすべり転位や、積層欠陥などがあ
る。ジンクブレンド型の結晶において、転位のすべり面
は(111)面であり、転位線の方向は<110>方向
を向く傾向がある。従って多くの場合、転位はエピタキ
シャル膜中において(111)面上の<110>方向を
斜め上方に進み、基板の法線方向平行に上方に伝播する
ことは稀である。また、積層欠陥は常に(111)面上
にある。
(Function) Generally, most of the lattice defects in the heteroepitaxial layer occur near the interface and propagate upward. Lattice defects include the ends of misfit dislocations that occur at interfaces, slip dislocations that occur due to local stress concentration, and stacking faults. In zinc blend crystals, the slip plane of dislocations is the (111) plane, and the direction of the dislocation lines tends to be in the <110> direction. Therefore, in many cases, dislocations propagate diagonally upward in the <110> direction on the (111) plane in the epitaxial film, and rarely propagate upward parallel to the normal direction of the substrate. Further, stacking faults are always on the (111) plane.

ここでマスク開口部または溝の高さを51幅をWとし、
基板表面と(111)面の法線のなす角をθとする。上
にのべたことより、選択成長において、マスク開口部の
高さと幅がh>wtanθの条件をみたするように高さ
を大きくとれば、界面近傍で発生した格子欠陥の多くは
(111)面上を斜め上方に伝播し、マスク材の側面に
到達し、そこで消滅する。
Here, the height of the mask opening or groove is 51, the width is W,
Let θ be the angle between the substrate surface and the normal to the (111) plane. From what has been said above, in selective growth, if the height and width of the mask opening are made large enough to satisfy the condition h>wtanθ, most of the lattice defects generated near the interface will be in the (111) plane. It propagates diagonally upward, reaches the side of the mask material, and disappears there.

よって、選択エピタキシャル成長層上方の格子欠陥密度
を大幅に低減することができる。
Therefore, the lattice defect density above the selective epitaxial growth layer can be significantly reduced.

本発明は原理的に(111)面を転位のすべり面とする
ような結晶であれば有効であり、ジンクブレンド型、ダ
イヤモンド型、面心立方構造の各種結晶に応用可能であ
る。
In principle, the present invention is effective for crystals in which the (111) plane is a dislocation slip plane, and can be applied to various crystals of zinc blend type, diamond type, and face-centered cubic structure.

(実施例) 以下、図示の実施例により、選択へテロエピタキシャル
薄膜の製造方法を説明する。
(Example) Hereinafter, a method for manufacturing a selective heteroepitaxial thin film will be explained with reference to an illustrated example.

(1)第1図はこの発明に係る製造方法の一実施例を説
明するための試料要部断面図である。(100)Siの
基板11に熱酸化により膜厚りが4pmのSiO□12
を成長した。次にドライエツチングによりSiO2マス
ク材中に<110>方向を一辺とする長さWが2.5p
mの正方形ウィンド部を形成し、h>wtanθとなる
ようにした。この基板を減圧MOCVD装置に装着し、
900°Cで2分間H2で希釈したAsH3中でウィン
ド部の底部に露出しているSi表面を清浄化した。次に
ジエチルガリウムクロライド(DEGaCl)とAsH
aを原料として原子層成長モードでGaAs13をウィ
ンド部に選択成長した。基板温度は600°Cである。
(1) FIG. 1 is a sectional view of the main part of a sample for explaining an embodiment of the manufacturing method according to the present invention. (100) SiO□12 with a film thickness of 4 pm is formed by thermal oxidation on a Si substrate 11.
grew up. Next, by dry etching, the length W with the <110> direction as one side is 2.5p in the SiO2 mask material.
A square window portion of m was formed so that h>wtanθ. This substrate is mounted on a low pressure MOCVD equipment,
The exposed Si surface at the bottom of the window was cleaned in AsH3 diluted with H2 for 2 minutes at 900°C. Next, diethyl gallium chloride (DEGaCl) and AsH
GaAs13 was selectively grown in the window portion using a as a raw material in atomic layer growth mode. The substrate temperature was 600°C.

(2)第2図は他の実施例を説明するための試料要部断
面図である。本実施例はGaAsの成長方法は実施例(
1)と同じであるが基板の形成方法が異なる。まずSi
上21に一辺が<110>方向にある正方形の幅4pm
1深さ7pmのトレンチをドライエツチングにより形成
する。次に熱酸化により0.4pmの5t02膜22を
成長し、さらにトレンチ底部のSiO2膜のみをドライ
エツチングにより除去する。このトレンチ内に実施例(
1)と同じ方法でGaAs23を成長した。
(2) FIG. 2 is a sectional view of the main part of a sample for explaining another embodiment. In this example, the GaAs growth method is described in Example (
This is the same as 1), but the method of forming the substrate is different. First, Si
The width of the square with one side in the <110> direction on 21 above is 4 pm.
1. A trench with a depth of 7 pm is formed by dry etching. Next, a 5t02 film 22 of 0.4 pm is grown by thermal oxidation, and only the SiO2 film at the bottom of the trench is removed by dry etching. In this trench, the embodiment (
GaAs23 was grown using the same method as in 1).

第3図は以上により作製した本発明の薄膜と従来例との
カソードルミネッセンスを比較して示す図である。すな
わち77°Kにおけるカソードルミネッセンスによる選
択成長部のGaAsの発光強度31を通常のSi基板上
に全面GaAsをした場合32と比較して示しである。
FIG. 3 is a diagram showing a comparison of cathodoluminescence between the thin film of the present invention produced as described above and a conventional example. That is, the emission intensity 31 of GaAs in the selectively grown portion by cathodoluminescence at 77°K is compared with 32 when GaAs is formed on the entire surface of a normal Si substrate.

実施例(1)と(2)の場合、発光強度は同程度であり
その強度は全面に成長した場合に較らべて約3倍強度が
強かった。
In the cases of Examples (1) and (2), the emission intensity was about the same, and the intensity was about three times stronger than that in the case of full-surface growth.

以上の実施例においてはGaAsを用いたが、GaAs
以外の他のジンクブレンド型結晶例えばInPAIGa
Asダイヤモンド型結晶のSiなど及び面心立方構造の
At Agなどにも適用可能である。またマスク材はS
iO□膜に限らすSiNx膜や半導体材料や金属材料で
も、構わない。成長方法は原子層エピタキシャル成長方
法に限らずガスソース分子線エピタキシャル成長方法、
スパッタ法など各種成長方法に応用できる。
Although GaAs was used in the above embodiments, GaAs
Other zinc blend crystals such as InPAIGa
It is also applicable to As diamond-type crystal Si, etc., and face-centered cubic structure At Ag. Also, the mask material is S.
It is not limited to the iO□ film, but may also be a SiNx film, a semiconductor material, or a metal material. The growth method is not limited to atomic layer epitaxial growth method, but also gas source molecular beam epitaxial growth method,
It can be applied to various growth methods such as sputtering.

(発明の効果) このように本方法により選択的に成長したエピタキシャ
ル薄膜は発光強度が増大しており、このことは格子欠陥
が大幅に減少していることを示している。従って本発明
によれば極めて良質のへテロエピタキシャル膜を成長で
きることを示している。
(Effects of the Invention) As described above, the epitaxial thin film selectively grown by the present method has an increased emission intensity, which indicates that lattice defects are significantly reduced. Therefore, it is shown that according to the present invention, a heteroepitaxial film of extremely high quality can be grown.

またこのように選択成長したエピタキシャル層を種とし
てSiO2膜上に横方向にエピタキシャル膜を成長する
ことも可能であり、この場合には格子欠陥密度の低い、
半導体l絶縁膜の構造のエピタキシャル膜を形成するこ
とができる。
It is also possible to grow an epitaxial film laterally on the SiO2 film using the selectively grown epitaxial layer as a seed.
An epitaxial film having the structure of a semiconductor l insulating film can be formed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図と第2図はこの発明に係る成長方法の実施例を説
明するための選択へテロエピタキシャル薄膜の構造を示
す図、第3図はこの発明の効果を示すためのカソードル
ミネッセンスの結果を示す図である。 11、21・・・Si基板、12,22・・・SiO2
膜、13,23・・・GaA4゜
FIGS. 1 and 2 are diagrams showing the structure of a selected heteroepitaxial thin film to explain an embodiment of the growth method according to the present invention, and FIG. 3 is a diagram showing the results of cathodoluminescence to demonstrate the effects of this invention. FIG. 11, 21...Si substrate, 12,22...SiO2
Membrane, 13,23...GaA4゜

Claims (1)

【特許請求の範囲】[Claims] 基板上に設けられた溝部分に{111}面を転位のすべ
り面として有する薄膜を選択的に成長させる方法におい
て、溝部分の幅をw、高さをh、基板表面と{111}
面の法線のなす角をθとすると、h>wtanθである
ことを特徴とする薄膜の選択成長方法。
In a method for selectively growing a thin film having a {111} plane as a dislocation slip plane in a groove portion provided on a substrate, the width of the groove portion is w, the height is h, and the substrate surface and {111}
A method for selectively growing a thin film, characterized in that h>wtanθ, where θ is the angle formed by the normal to the surface.
JP21553588A 1988-08-29 1988-08-29 Selective growth of thin film Pending JPH0263115A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21553588A JPH0263115A (en) 1988-08-29 1988-08-29 Selective growth of thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21553588A JPH0263115A (en) 1988-08-29 1988-08-29 Selective growth of thin film

Publications (1)

Publication Number Publication Date
JPH0263115A true JPH0263115A (en) 1990-03-02

Family

ID=16674037

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21553588A Pending JPH0263115A (en) 1988-08-29 1988-08-29 Selective growth of thin film

Country Status (1)

Country Link
JP (1) JPH0263115A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008546181A (en) * 2005-05-17 2008-12-18 アンバーウェーブ システムズ コーポレイション Lattice-mismatched semiconductor structure with low dislocation defect density and related device manufacturing method
US7732325B2 (en) 2002-01-26 2010-06-08 Applied Materials, Inc. Plasma-enhanced cyclic layer deposition process for barrier layers
US7781326B2 (en) 2001-02-02 2010-08-24 Applied Materials, Inc. Formation of a tantalum-nitride layer
US10280509B2 (en) 2001-07-16 2019-05-07 Applied Materials, Inc. Lid assembly for a processing system to facilitate sequential deposition techniques

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7781326B2 (en) 2001-02-02 2010-08-24 Applied Materials, Inc. Formation of a tantalum-nitride layer
US10280509B2 (en) 2001-07-16 2019-05-07 Applied Materials, Inc. Lid assembly for a processing system to facilitate sequential deposition techniques
US7732325B2 (en) 2002-01-26 2010-06-08 Applied Materials, Inc. Plasma-enhanced cyclic layer deposition process for barrier layers
JP2008546181A (en) * 2005-05-17 2008-12-18 アンバーウェーブ システムズ コーポレイション Lattice-mismatched semiconductor structure with low dislocation defect density and related device manufacturing method

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