JPH0414836A - Si substrate - Google Patents
Si substrateInfo
- Publication number
- JPH0414836A JPH0414836A JP11816390A JP11816390A JPH0414836A JP H0414836 A JPH0414836 A JP H0414836A JP 11816390 A JP11816390 A JP 11816390A JP 11816390 A JP11816390 A JP 11816390A JP H0414836 A JPH0414836 A JP H0414836A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline
- substrate
- deposited
- sio2
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 59
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 55
- 238000000034 method Methods 0.000 claims abstract description 24
- 239000011248 coating agent Substances 0.000 claims abstract description 7
- 238000000576 coating method Methods 0.000 claims abstract description 7
- 238000001947 vapour-phase growth Methods 0.000 claims description 10
- 238000010304 firing Methods 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 42
- 239000000377 silicon dioxide Substances 0.000 abstract description 21
- 229910052681 coesite Inorganic materials 0.000 abstract description 20
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 20
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 20
- 229910052682 stishovite Inorganic materials 0.000 abstract description 20
- 229910052905 tridymite Inorganic materials 0.000 abstract description 20
- 230000000694 effects Effects 0.000 abstract description 13
- 238000005247 gettering Methods 0.000 abstract description 13
- 239000013078 crystal Substances 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 2
- 238000004519 manufacturing process Methods 0.000 description 12
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 239000010419 fine particle Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 229910001385 heavy metal Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 241001655798 Taku Species 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005422 blasting Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000002485 combustion reaction Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000002459 sustained effect Effects 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、大規模集積回路等の半導体装置の製造に供さ
れるＳｉ基板に関し、特に、エクストリンシックゲッタ
リング能力付与のため、裏面に多結晶Ｓｉ膜を堆積した
Ｓｉ基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a Si substrate used for manufacturing semiconductor devices such as large-scale integrated circuits. The present invention relates to a Si substrate on which a crystalline Si film is deposited.
今日、大規模集積回路等の半導体装置は、極めて清浄な
環境下で製造されているが、ドライエツチング等、多く
の工程を得る間にＳｉ基板は極微量ながら鉄、銅、ニッ
ケル等の重金属元素により汚染される。これら重金属汚
染は半導体装置の特性劣化（接合リーク増大、薄い絶縁
膜の耐圧低下）を引き起こし、ひいては、製品の歩留り
低下の原因となる事が知られている。Today, semiconductor devices such as large-scale integrated circuits are manufactured in extremely clean environments, but during many processes such as dry etching, Si substrates are exposed to extremely small amounts of heavy metal elements such as iron, copper, and nickel. contaminated by It is known that these heavy metal contaminations cause deterioration of the characteristics of semiconductor devices (increase in junction leakage, decrease in breakdown voltage of thin insulating films), and in turn cause a decrease in product yield.
この様な汚染不純物を半導体装置形成領域であるＳｉ基
板表面から除去するゲッタリンダ技術としてエクストリ
ンシックゲッタリング（ＥｘｔｒｉｎｓｉｃＧｅｔｔｅ
ｒｉｎｇ 、以下ＥＧと略す）が広く知られている。Extrinsic gettering is a getter-linda technology that removes such contaminant impurities from the surface of a Si substrate, which is a semiconductor device formation region.
ring (hereinafter abbreviated as EG) is widely known.
ＥＧは主にＳｉ基板裏面に、結晶欠陥等の歪を導入し、
これをゲッタリング源として、８１基板表面の汚染不純
物を裏面側に捕獲・固着するものである。従来、ＥＧ技
術としてはＳｉ基板裏面にシリカ等の細粒を打ちつけ、
機械的に損傷を与えるサイドブラスト法が広く利用され
ていたが、Ｓｉ基板裏面よりＳｉあるいはＳｉＯ２の微
粒子が発生するという欠点がある事から、第２図に示し
たようにＳｉ基板裏面に多結晶Ｓｉを堆積し、この多結
晶Ｓｉの結晶粒界等をゲッタリング源とする手法が提案
されている（ ＶＬＳＩ Ｔｅｃｈｎｏｌｏｇｙ ２ｎ
ｄｅｄｉｔｉｏｎ、 Ｓ、 Ｍ、 Ｓｚｅ、 ＭｃＧｒ
ａｗ−Ｈｉｌｌ Ｂｏｏｋ Ｃｏｍｐａｎｙ）。この手
法によれば、Ｓｉ基板裏面からの微粒子の発生は抑制さ
れる。EG mainly introduces distortion such as crystal defects into the back surface of the Si substrate,
This is used as a gettering source to capture and fix contaminant impurities on the surface of the substrate 81 to the back surface side. Conventionally, EG technology involves pounding fine particles such as silica onto the back side of a Si substrate.
Side blasting, which causes mechanical damage, has been widely used, but it has the drawback of generating Si or SiO2 fine particles from the back surface of the Si substrate, so as shown in Figure 2, polycrystalline A method has been proposed in which Si is deposited and the grain boundaries of this polycrystalline Si are used as gettering sources (VLSI Technology 2n
dedition, S, M, Sze, McGr
aw-Hill Book Company). According to this method, generation of fine particles from the back surface of the Si substrate is suppressed.
従来の多結晶ＳｉによるＥＧでは、ゲッタリング効果が
接続せず、半導体装置製造工程の初期のみに有効で充分
なゲッタリング効果が得られないという欠点があった。Conventional EG using polycrystalline Si has the drawback that the gettering effect does not connect and is effective only at the initial stage of the semiconductor device manufacturing process, and a sufficient gettering effect cannot be obtained.
これは、半導体装置の製造工程におけるアニル、酸化の
ための熱処理により、堆積当初は数十〜数百ｎｍ程度の
サイズを有した多結晶８１粒が成長し、ゲッタリング能
力が徐々に減退し、さらに酸化処理により多結晶Ｓｉ膜
膜体体ＳｉＯ２膜となりゲッタリング源として多結晶Ｓ
ｉ膜が徐々に失われる事による。This is because due to the heat treatment for anilization and oxidation in the manufacturing process of semiconductor devices, 81 polycrystalline grains with a size of several tens to hundreds of nanometers initially grow, and the gettering ability gradually decreases. Furthermore, by oxidation treatment, the polycrystalline Si film becomes a polycrystalline SiO2 film as a gettering source.
This is due to the gradual loss of the i-film.
本発明のＳｉ基板は、Ｓｉ基板裏面に多結晶Ｓｉ膜を堆
積した後、この多結晶Ｓｉ膜を気相成長法もしくは塗布
焼成法によるＳｉＯ□膜もしくは気相成長法による８１
３Ｎ４膜で被覆する事を特徴とする。また、多結晶Ｓｉ
膜の堆積に先立ってＳｉ基板裏面に複数の溝を設け、こ
の溝を埋設するようにＳｉ基板裏面に多結晶Ｓｉ膜を堆
積した後、この多結晶Ｓｉ膜を気相成長法もしくは塗布
焼成法によるＳ ｉ Ｏ２膜もしくは気相成長法による
５ｉ３Ｎｔ膜で被覆する事を特徴とする。The Si substrate of the present invention is produced by depositing a polycrystalline Si film on the back surface of the Si substrate, and then converting this polycrystalline Si film into an SiO
It is characterized by being coated with a 3N4 film. In addition, polycrystalline Si
Prior to film deposition, a plurality of grooves are formed on the back surface of the Si substrate, and after a polycrystalline Si film is deposited on the back surface of the Si substrate so as to fill the grooves, this polycrystalline Si film is deposited using a vapor phase growth method or a coating baking method. It is characterized by being coated with a SiO2 film produced by the method or a 5i3Nt film produced by the vapor phase growth method.
ここで、多結晶Ｓｉ膜を被覆するＳｉ、Ｏｚ膜もしくは
５ｉ３Ｎｔ膜は、酸化熱処理時、酸素が多結晶Ｓｉ膜に
達するのを抑制する作用を持ち、ゲッタリング源となる
多結晶Ｓｉ膜が酸化され膜厚が減少するのを抑制する作
用を有する。Here, the Si, Oz film or 5i3Nt film that covers the polycrystalline Si film has the effect of suppressing oxygen from reaching the polycrystalline Si film during oxidation heat treatment, and the polycrystalline Si film, which is a gettering source, is oxidized. This has the effect of suppressing the decrease in film thickness.
次に本実施例について図面を参照して説明する。 Next, the present embodiment will be described with reference to the drawings.
第１図は本発明の第１の実施例の８１基板の製造工程の
概略を示すＳｉ基板の断面図である。FIG. 1 is a sectional view of a Si substrate schematically showing the manufacturing process of the 81 substrate of the first embodiment of the present invention.
Ｓｉ単結晶インゴットより切り圧された粗研磨Ｓｉ基板
１の全面に、気相成長技術を用いて多結晶Ｓｉ膜２を所
望の厚さで堆積させる（第１−１図）。A polycrystalline Si film 2 is deposited to a desired thickness on the entire surface of a roughly polished Si substrate 1 cut from a Si single crystal ingot using a vapor phase growth technique (FIG. 1-1).
続いて、気相成長技術を用いてＳｉＯ２膜３を全面に堆
積させる（第１−２図）。この後、〜・主面のＳｉＯ２
膜３を選択的に除去し、さらにこの主面を鏡面研磨し、
Ｓｉ基板４とする。Subsequently, a SiO2 film 3 is deposited on the entire surface using a vapor phase growth technique (FIGS. 1-2). After this, ~・SiO2 on the main surface
The film 3 is selectively removed, and the main surface is mirror-polished.
A Si substrate 4 is used.
堆積する多結晶Ｓｉ膜、５ｉＣｈ膜の膜厚は、Ｓｉ基板
の反りに影響を及ぼすが、これはＳｉ基板の直径及び厚
さに依存するため一義的に決定する事はてきない。しか
し、直径１５０〜２００ｍｍ。The thickness of the deposited polycrystalline Si film and 5iCh film affects the warpage of the Si substrate, but this cannot be determined uniquely because it depends on the diameter and thickness of the Si substrate. However, the diameter is 150-200mm.
厚さ０．６〜０．７５ｍｍの範囲のＳｉ基板であれば、
多結晶Ｓｉ膜及びＳｉＯ２膜の膜厚は１〜１．５μｍの
範囲である事が望ましい。If the Si substrate has a thickness of 0.6 to 0.75 mm,
The thickness of the polycrystalline Si film and SiO2 film is preferably in the range of 1 to 1.5 μm.
本実施例によるＳｉ基板（多結晶Ｓｉ膜１．０μｍ。Si substrate (polycrystalline Si film 1.0 μm thick) according to this example.
ＳｉＯ２膜１．５μｍ）第２−１図及び従来技術による
Ｓｉ基・板（裏面を１．０μｍの多結晶Ｓｉ膜のみで被
覆）（第２−１図）上にＭＯＳグイオートを作製し、Ｍ
ＯＳ Ｃ−を法による小数キャリア生成ライフタイム
（τｇ）の比較を試みた。SiO2 film 1.5 μm) (Fig. 2-1) and a conventional Si substrate/plate (back side covered only with 1.0 μm polycrystalline Si film) (Fig. 2-1) were fabricated with MOS guiot.
An attempt was made to compare the fractional carrier generation lifetime (τg) using the OS C-method.
両Ｓｉ基板に０ＭＯ８製造の初期工程を模した熱処理（
１０００℃水素燃焼酸化２時間、 １２００℃乾燥０２
酸化４時間）を行ない、Ｓｉ基板５上に０．７μｍの熱
ＳｉＯ□膜を形成した後、表面の熱５ｉｎ２膜を選択的
に除去した（第２−２図）。この時点で本実施例による
Ｓｉ基板の裏面には０．８μｍの多結晶Ｓｉ膜６が残存
していたのに対し、従来技術のものでは、０．４μｍま
で膜厚が減少していた。続いて、Ｓｉの選択酸化技術に
よりフィールド５ｉＣｈ膜８を形成し、この後、’ｒ”
−）Ｓｉｎ２膜９．ゲート電極１０を形成してＭＯＳダ
イオードを完成したく第２−３図）。このＭＯＳダイオ
ードについてＭＯ３Ｃ−を法
表１
τｇ ５〜６ｍ冠 ０．５〜４ｍ５ｅｃ
によりτｇを測定した結果、本実施例では５〜７ｍ５ｅ
ｃの値が得られ、従来技術によった場合の０．５〜４ｍ
５ｅｃと比較して明らかなゲッタリング効果の優位性が
確認された。Both Si substrates were subjected to heat treatment (
Hydrogen combustion oxidation at 1000°C for 2 hours, drying at 1200°C 02
After 4 hours of oxidation to form a 0.7 μm thermal SiO□ film on the Si substrate 5, the thermal 5in2 film on the surface was selectively removed (Figure 2-2). At this point, a polycrystalline Si film 6 of 0.8 .mu.m remained on the back surface of the Si substrate according to the present example, whereas in the conventional technique, the film thickness had decreased to 0.4 .mu.m. Subsequently, a field 5iCh film 8 is formed using Si selective oxidation technology, and then 'r'
-) Sin2 film9. 2-3) to complete the MOS diode by forming the gate electrode 10. For this MOS diode, MO3C- is calculated using Table 1: τg 5~6m crown 0.5~4m5ec
As a result of measuring τg, in this example, it was 5 to 7 m5e.
The value of c is obtained and is 0.5 to 4 m when using conventional technology.
A clear superiority of gettering effect was confirmed compared to 5ec.
なお、本実施例では多結晶Ｓｉ膜を被覆する膜として気
相成長法によるＳ ｉ Ｏｚ膜を用いたが、塗布焼成法
による５ｉＣｈ膜を用いても同等の結果が得られている
。また、ＳｉＯ□膜の代わりに気相成長法によるＳｉ３
Ｎ４膜を用いても良い。In this example, a SiOz film produced by a vapor phase growth method was used as a film to cover the polycrystalline Si film, but similar results were obtained using a 5iCh film produced by a coating and firing method. In addition, instead of SiO□ film, Si3
An N4 film may also be used.
第３図は本発明の第２の実施例のＳｉ基板の製造工程の
概略を示す断面図である。FIG. 3 is a cross-sectional view schematically showing the manufacturing process of a Si substrate according to a second embodiment of the present invention.
第３−１図のように粗研磨Ｓｉ基板１１の一主面に溝１
２を設ける。続いて、第３−２図のように粗研磨Ｓｉ基
板１１の全面に多結晶Ｓｉ膜１３を堆積する。この際溝
１２は多結晶Ｓｉ膜１３で完全に埋設する。この後、全
面にＳ ｉ Ｏ２膜１４を気相成長法により堆積する。As shown in FIG. 3-1, a groove 1 is formed on one main surface of the roughly polished Si substrate 11.
2 will be provided. Subsequently, as shown in FIG. 3-2, a polycrystalline Si film 13 is deposited on the entire surface of the roughly polished Si substrate 11. At this time, the groove 12 is completely filled with the polycrystalline Si film 13. Thereafter, a SiO2 film 14 is deposited on the entire surface by vapor phase growth.
続いて、第３−３図のように、溝１２が形成されていな
い側の主面を鏡面研磨しＳｉ基板１５とする。Subsequently, as shown in FIG. 3-3, the main surface on the side where the grooves 12 are not formed is mirror-polished to form a Si substrate 15.
なお、溝１２の形状、数は任意に設定可能であるが、多
結晶Ｓｉ膜１３の堆積により、溝が完全に埋設される様
溝寸法と多結晶Ｓｉ膜の膜厚を設定する必要がある。Note that the shape and number of the grooves 12 can be set arbitrarily, but it is necessary to set the groove dimensions and the thickness of the polycrystalline Si film so that the grooves are completely buried by depositing the polycrystalline Si film 13. .
本実施例においては、ゲッタリング源となる多結晶Ｓｉ
が溝内に埋設されているため、第４図のようにより長時
間の酸化処理を経て、裏面の多結晶Ｓｉが全て酸化され
ても溝内に多結晶Ｓｉが残存し、高いゲッタリング効果
をより長く持続できる。In this example, polycrystalline Si serves as a gettering source.
is buried in the groove, so even if all the polycrystalline Si on the back side is oxidized through a longer oxidation process as shown in Figure 4, the polycrystalline Si remains in the groove, resulting in a high gettering effect. Can last longer.
本実施例により幅１．０μｍ、深さ２．０μｍの溝を格
子状に形成し、多結晶Ｓｉ膜０．７μｍ、ＳｉＯ２膜１
．０μｍを堆積したＳｉ基板を作製し、第１の実施例と
同様にＭＯＳダイオードを作製（第２図）しτｇを測定
した結果、７ｇ２７〜９ｍ５ｅｃと極めて良好な結果を
得た。In this example, grooves with a width of 1.0 μm and a depth of 2.0 μm were formed in a lattice shape, a polycrystalline Si film of 0.7 μm, and an SiO2 film of 1
．． A Si substrate having a thickness of 0 μm deposited thereon was prepared, and a MOS diode was prepared in the same manner as in the first embodiment (FIG. 2). As a result of measuring τg, an extremely good result of 7 g 27 to 9 m 5 ec was obtained.
なお、本実施例においても、多結晶Ｓｉ膜を被覆する膜
として、塗布焼成によるＳｉＯ□膜を使用する事が可能
であり、気相成長によるＳ ｉＯ２膜を用いた場合と同
等のτｇが得られる事を確認した。In this example as well, it is possible to use a coated and fired SiO□ film as a film to cover the polycrystalline Si film, and it is possible to obtain the same τg as when using a vapor-phase grown SiO2 film. I confirmed that it is possible.
第５図は本発明の第３の実施例の製造工程の概略を示す
断面図である。FIG. 5 is a sectional view schematically showing the manufacturing process of a third embodiment of the present invention.
第５−１図のように粗研磨Ｓｉ基板１６の一主面に溝１
７を設ける。続いて、第５−２図のように粗研磨Ｓｉ基
板１６の全面に多結晶Ｓｉ膜１８を堆積する。この際、
溝１７は、多結晶Ｓｉ膜１８で完全に埋設する。この後
、全面に５ｉｓＮｔ膜１９を気相成長法により堆積する
。続いて、第５−３図のように、溝が形成されていない
側の主面を鏡面研磨しＳｉ基板２０とする。As shown in FIG. 5-1, a groove 1 is formed on one main surface of the roughly polished Si substrate 16.
7 will be provided. Subsequently, as shown in FIG. 5-2, a polycrystalline Si film 18 is deposited on the entire surface of the roughly polished Si substrate 16. On this occasion,
The groove 17 is completely filled with a polycrystalline Si film 18. Thereafter, a 5isNt film 19 is deposited on the entire surface by vapor phase growth. Subsequently, as shown in FIG. 5-3, the main surface on the side where no grooves are formed is mirror-polished to form a Si substrate 20.
溝形状・数等、及び多結晶Ｓｉ膜１８の膜厚等は任意に
設定可能であるが、第２の実施例と同様に溝は多結晶Ｓ
ｉ膜１８で完全に埋設される様に設定される必要がある
。本実施例では多結晶Ｓｉ膜１８の被覆にＳｉ！Ｎ４膜
１９を膜用９ているが、Ｓｉ３Ｎ＜膜は０２の遮へい能
力が高い事からＳ ｉ ３Ｎ １膜の膜厚は５０ｎｍ程
度で充分な効果を得られる。Although the groove shape, number, etc., and the film thickness of the polycrystalline Si film 18 can be set arbitrarily, the grooves are made of polycrystalline Si as in the second embodiment.
It is necessary to set it so that it is completely buried with the i-film 18. In this embodiment, the polycrystalline Si film 18 is coated with Si! Although the N4 film 19 is used as the film 9, since the Si3N<02 film has a high shielding ability, a sufficient effect can be obtained with the thickness of the Si3N1 film of about 50 nm.
本実施例においても第１第２の実施例と同様、ＭＯＳタ
イオードによるτｇ測定を行ったが、７ｇ２７〜９ｍ５
ｅｃと第２の実施例と同等の結果を得た。In this example, as in the first and second examples, τg was measured using a MOS diode.
Results equivalent to those of ec and the second example were obtained.
以上説明したように、本発明は、Ｓｉ基板裏面に堆積し
た多結晶Ｓｉ膜を気相成長法によるＳｉＯ２膜あるいは
５ｉｉＮｉ膜、もしくは塗布焼成による５ｉＣｈ膜で被
覆した事により、裏面多結晶Ｓｉ膜のゲッタリング効果
が長く持続させられるという効果を有する。また、Ｓｉ
基板裏面に溝を形成した後、多結晶Ｓｉ膜を堆積し、先
述のＳｉＯ□膜あるいは５ｉｘＮｓ膜で被覆した場合に
は、通常、裏面多結晶Ｓｉ膜が完全に酸化されてしまう
ような半導体装置の製造条件においても、溝内に多結晶
Ｓｉを残存させる事が可能で、より持続性の高いゲッタ
リンダ能力をＳｉ基板に付与できる効果を有する。As explained above, the present invention covers the polycrystalline Si film deposited on the back surface of the Si substrate with an SiO2 film or 5iiNi film formed by vapor phase growth, or a 5iCh film formed by coating and baking. This has the effect that the gettering effect can be sustained for a long time. Also, Si
When a polycrystalline Si film is deposited after forming a groove on the back side of the substrate and then covered with the aforementioned SiO□ film or 5ixNs film, the back side polycrystalline Si film is usually completely oxidized in a semiconductor device. Even under these manufacturing conditions, it is possible to leave polycrystalline Si in the groove, which has the effect of imparting a more sustainable getter-linda ability to the Si substrate.
第１〜１図乃至第１−３図は、本発明の第１の実施例に
よるＳｉ基板の製造工程の概略を示す断面図、第２−１
図乃至第２−３図は、第１の実施例及び従来技術による
Ｓｉ基板により、ＭＯＳダイオードを作製する工程の概
略を示す断面図、第３−１図乃至第３−３図は、本発明
の第２の実施例によるＳｉ基板の製造工程の概略を示す
断面図、第４図は第２の実施例によるＳｉ基板において
、Ｓｉ基板裏面の多結晶Ｓｉ膜が完全に酸化されても溝
内に多結晶Ｓｉ膜が残存する事を示す断面図、第５−１
図乃至第５−３図は本発明の第３の実施例によるＳｉ基
板の製造工程の概略を示す断面図である。
１・・・・・・粗研磨Ｓｉ基板、２・・・・・・多結晶
Ｓｉ膜、３・・・・・・ＳｉＯ２膜、４・・・・・・Ｓ
ｉ基板、５・・・・・・Ｓｉ基板、６・・・・・多結晶
Ｓｉ膜、７・・・・・ＳｉＯ２膜、８・・・・・・フィ
ールドＳｉｎ、膜、９・・・・・・ゲー）ＳｉＯ□膜、
１０・・・・・・ゲート電極、１１・・・・・粗研磨Ｓ
ｉ基板、１２・・・・・・溝、１３・・・・・・多結晶
Ｓｉ膜、１４・・・・・・ＳｉＯ２膜、Ｉ５・・・・・
Ｓｉ基板、１６・・・・・・粗研磨Ｓ】基板、１７・・
・・・・溝、１８・・・・・・多結晶Ｓｉ膜、１９・・
山Ｓ １３Ｎ４膜、２０・・・・・・Ｓｉ基板。
代理人 弁理士 内 原 晋
本寅施例
従来我町
第ｒ−ｒ図
第２−１図
第１−２図
第２−２図
第１−３図
第 １ 図
第２−３図
第２図
拓
図
第
図1 to 1 to 1-3 are cross-sectional views schematically showing the manufacturing process of a Si substrate according to the first embodiment of the present invention, and FIG.
Figures 2-3 are cross-sectional views schematically showing the process of manufacturing a MOS diode using a Si substrate according to the first embodiment and the prior art, and Figures 3-1 to 3-3 are cross-sectional views showing the process of manufacturing a MOS diode according to the present invention. FIG. 4 is a cross-sectional view showing an outline of the manufacturing process of the Si substrate according to the second embodiment. Cross-sectional view showing that the polycrystalline Si film remains in 5-1
5-3 are cross-sectional views schematically showing the manufacturing process of a Si substrate according to a third embodiment of the present invention. 1... Roughly polished Si substrate, 2... Polycrystalline Si film, 3... SiO2 film, 4... S
i substrate, 5... Si substrate, 6... polycrystalline Si film, 7... SiO2 film, 8... field Sin, film, 9... ... Game) SiO□ film,
10...Gate electrode, 11...Rough polishing S
i substrate, 12...groove, 13...polycrystalline Si film, 14...SiO2 film, I5...
Si substrate, 16... Rough polishing S] Substrate, 17...
...Groove, 18...Polycrystalline Si film, 19...
Mountain S 13N4 film, 20...Si substrate. Agent Patent Attorney Shinmoto Tora UchiharaExampleConventionalWamachi No. rrFigure 2-1Figure 1-2Figure 2-2Figure 1-3Figure 1Figure 2-3Figure 2 Taku map
Claims (1)
いて、該多結晶Ｓｉ膜の全面が、気相成長法もしくは、
塗布焼成法によるＳｉＯ＿２膜で被覆されている事を特
徴とするＳｉ基板 ２、裏面に多結晶Ｓｉ膜が堆積されているＳｉ基板にお
いて、該多結晶Ｓｉ膜が気相成長法によるＳｉ＿３Ｎ＿
４膜で被覆されている事を特徴とするＳｉ基板 ３、裏面に複数の溝が形成され、この溝が完全に埋設さ
れるよう該裏面に多結晶Ｓｉ膜が堆積され、かつ、該裏
面の多結晶Ｓｉ膜の全面が気相成長法もしくは塗布焼成
法によるＳｉＯ＿２膜で被覆されている事を特徴とする
特許請求の範囲第１項記載のＳｉ基板 ４、裏面に複数の溝が形成され、この溝が完全に埋設さ
れる様該裏面に多結晶Ｓｉ膜が堆積され、かつ、該裏面
の多結晶Ｓｉ膜の全面が気相成長法によるＳｉ＿３Ｎ＿
４膜で被覆されている事を特徴とする特許請求の範囲第
２項記載のＳｉ基板[Claims] 1. In a Si substrate on which a polycrystalline Si film is deposited on the back surface, the entire surface of the polycrystalline Si film is grown by vapor phase growth or
A Si substrate 2 characterized in that it is coated with a SiO_2 film formed by coating and firing, and a Si substrate having a polycrystalline Si film deposited on the back surface, in which the polycrystalline Si film is coated with a Si_3N_ film formed by vapor phase growth.
A polycrystalline Si substrate 3 is characterized in that it is coated with 4 films, a plurality of grooves are formed on the back surface, a polycrystalline Si film is deposited on the back surface so that the grooves are completely buried, and The Si substrate 4 according to claim 1, characterized in that the entire surface of the polycrystalline Si film is coated with a SiO_2 film by a vapor growth method or a coating and firing method, and a plurality of grooves are formed on the back surface, A polycrystalline Si film is deposited on the back surface so that this groove is completely buried, and the entire surface of the polycrystalline Si film on the back surface is made of Si_3N_
The Si substrate according to claim 2, characterized in that the Si substrate is coated with four films.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11816390A JPH0414836A (en) | 1990-05-08 | 1990-05-08 | Si substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11816390A JPH0414836A (en) | 1990-05-08 | 1990-05-08 | Si substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0414836A true JPH0414836A (en) | 1992-01-20 |
Family
ID=14729668
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11816390A Pending JPH0414836A (en) | 1990-05-08 | 1990-05-08 | Si substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0414836A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06104268A (en) * | 1992-09-21 | 1994-04-15 | Mitsubishi Electric Corp | Semiconductor substrate having gettering effect and its manufacturing method |
| JPH07161724A (en) * | 1993-12-13 | 1995-06-23 | Nec Corp | Silicon semiconductor substrate |
| US6229196B1 (en) | 1997-07-30 | 2001-05-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and fabrication method thereof |
| JP2012129312A (en) * | 2010-12-14 | 2012-07-05 | Canon Inc | Semiconductor device manufacturing method |
-
1990
- 1990-05-08 JP JP11816390A patent/JPH0414836A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06104268A (en) * | 1992-09-21 | 1994-04-15 | Mitsubishi Electric Corp | Semiconductor substrate having gettering effect and its manufacturing method |
| JPH07161724A (en) * | 1993-12-13 | 1995-06-23 | Nec Corp | Silicon semiconductor substrate |
| US6229196B1 (en) | 1997-07-30 | 2001-05-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and fabrication method thereof |
| JP2012129312A (en) * | 2010-12-14 | 2012-07-05 | Canon Inc | Semiconductor device manufacturing method |
| US8426291B2 (en) | 2010-12-14 | 2013-04-23 | Canon Kabushiki Kaisha | Method for isolation formation in manufacturing semiconductor device |
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