JPS61214515A - Susceptor for semiconductor substrate - Google Patents

Susceptor for semiconductor substrate

Info

Publication number
JPS61214515A
JPS61214515A JP5653185A JP5653185A JPS61214515A JP S61214515 A JPS61214515 A JP S61214515A JP 5653185 A JP5653185 A JP 5653185A JP 5653185 A JP5653185 A JP 5653185A JP S61214515 A JPS61214515 A JP S61214515A
Authority
JP
Japan
Prior art keywords
substrate
susceptor
semiconductor substrate
thermal expansion
coefficient
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5653185A
Other languages
Japanese (ja)
Inventor
Shuichi Samata
秀一 佐俣
Yoshiaki Matsushita
松下 嘉明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP5653185A priority Critical patent/JPS61214515A/en
Publication of JPS61214515A publication Critical patent/JPS61214515A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02529Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)

Abstract

PURPOSE:To suppress the infiltration of impurity contamination into a substrate while a growing method is performed by a method wherein a circular recessed part is provided on the surface of the susceptor which retains a semiconductor substrate on which a vapor-phase growing method is going to be performed, said recessed part is filled up with an amorphous material having the coefficient of thermal expansion smaller than that of the substrate, the substrate is placed thereon, and a vapor-phase growing method is performed. CONSTITUTION:A circular recessed part 32 is provided on the surface of the susceptor main body 31 consisting of high purity graphite whereon SiC is coated, the recessed part is filled up with the SiO2 having the coefficient of thermal expansion smaller than that of the Si substrate 34 which is grown on the recessed part 32, and it is used as a substrate retaining stand 33. No impurities are infiltrated into the substrate 34 and no etching pit and the like are generated while a growing method is performed, if the susceptor is constituted as above, an Si substrate 34 is placed on the retaining stand 33, they are placed in a vapor-phase growing device and an epitaxial growing method is performed. SiO2 is used for the retaining stand 33, but Si3N4 may be used instead of the SiO2.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、主として気相成長に使用される半導体基板用
サセプタに関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a susceptor for semiconductor substrates mainly used for vapor phase growth.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

従来、シリコン気相成長技術は半導体産業において重要
な位置を占めて来た。%に1バイポーラICにおいては
、動作速度を上げるため特殊な構造が要求され、シリコ
ン気相成長技術は不可欠の技術である。また、近年MO
8LSIの分野でも高集積化、高密度化に伴いシリコン
気相成長技術を用いたエピタキシャルウェハが用いられ
てきておp、1.2μm以下のデデインルールに対して
MO8LSIではシリコンエピタキシャルウェハは不可
欠であると言われている。このように、シリコン気相技
術は近年共々その重要性を増している。ところで、従来
、バイポーラLSI用及びMO8LSI用のシリコンエ
ピタキシャル成長用気相成長装置としては、第2図に示
す如く縦型のもの、あるいは第5図に示す如くシリンダ
ー型のものが知られている。
Traditionally, silicon vapor phase growth technology has occupied an important position in the semiconductor industry. % bipolar IC requires a special structure to increase the operating speed, and silicon vapor phase growth technology is an essential technology. In addition, in recent years MO
In the field of 8LSI, epitaxial wafers using silicon vapor phase growth technology are being used as the integration and density increases, and silicon epitaxial wafers are indispensable for MO8LSI in response to the design rule of 1.2 μm or less. It is said. Thus, silicon vapor phase technology has been gaining importance in recent years. By the way, conventionally, as a vapor phase growth apparatus for silicon epitaxial growth for bipolar LSI and MO8LSI, a vertical type as shown in FIG. 2 or a cylindrical type as shown in FIG. 5 are known.

第2図において、1は下部中央に回転軸2を有した合成
石英製の反応管である。前記回転軸2の上部には、半導
体基板用サセプタ3が設けられ、該サセプタ3に複数の
半導体基板4・・・がセットされている。なお、回転軸
2により前記すセグタ3が回転する。前記回転軸2、サ
セプタ3の中央は空洞となっておシ、この空洞部に反応
ガス導入管5が設けられている。この反応ガス噴出口6
が設けられている。前記サセプタ3の下方で回転軸2の
周囲には、高周波加熱用コイル7が設けられている。前
記反応管2の下部には、反応ガス排出管8が設けられて
いる。
In FIG. 2, reference numeral 1 denotes a reaction tube made of synthetic quartz and having a rotating shaft 2 at the center of its lower part. A semiconductor substrate susceptor 3 is provided above the rotating shaft 2, and a plurality of semiconductor substrates 4 are set on the susceptor 3. Incidentally, the aforementioned segmenter 3 is rotated by the rotating shaft 2. The center of the rotating shaft 2 and the susceptor 3 is hollow, and a reaction gas introduction pipe 5 is provided in the hollow. This reaction gas outlet 6
is provided. A high-frequency heating coil 7 is provided below the susceptor 3 and around the rotating shaft 2 . A reaction gas exhaust pipe 8 is provided at the bottom of the reaction tube 2 .

第3図におい°て、11は合成石英製の反応管である。In FIG. 3, 11 is a reaction tube made of synthetic quartz.

この反応管11内には、回転軸12によって貫通された
形状の半導体基板用サセプタ13が設けられている。こ
のサセプタ13の側面には、複数の半導体基板14が設
けられている。前記反応管11の上部には反応ガス導入
管15が設けられ、同反応管11の下部には反応ガス排
出管16が設けられている。前記反応管11の周側部に
は複数のハロゲンランプ17・・・が設けられ、このハ
ロゲンランプ17の外側に反射鏡18が設けられている
。また、反応管11の周囲には冷却水・やイf19・・
・が設けられ、前記半導体基板14・・・をハロゲン2
ング17・・・で集中的に熱するようになっている。
A semiconductor substrate susceptor 13 having a shape penetrated by a rotating shaft 12 is provided inside the reaction tube 11 . A plurality of semiconductor substrates 14 are provided on the side surface of this susceptor 13. A reaction gas introduction pipe 15 is provided at the top of the reaction tube 11, and a reaction gas discharge pipe 16 is provided at the bottom of the reaction tube 11. A plurality of halogen lamps 17 are provided on the peripheral side of the reaction tube 11, and a reflecting mirror 18 is provided on the outside of the halogen lamps 17. Also, around the reaction tube 11 there is cooling water, etc.
. is provided, and the semiconductor substrate 14 is treated with halogen 2.
It is designed to heat up intensively with ng 17....

前述した気相成長装置において、半導体基板用サセプタ
を部分的に拡大して示すと第3図のようになる。図中の
21は、サセプタ本体である。このサセプタ本体21に
は、半導体基板22をセットするための該基板22より
僅かに大きい凹部23が設けられている。ここで、半導
体基板22は、サセプタ本体21の凹部23にその裏面
を接してセットされている。
In the above-mentioned vapor phase growth apparatus, a partially enlarged view of the susceptor for a semiconductor substrate is shown in FIG. 21 in the figure is a susceptor body. This susceptor body 21 is provided with a recess 23 slightly larger than the substrate 22 for setting the semiconductor substrate 22 therein. Here, the semiconductor substrate 22 is set with its back surface in contact with the recess 23 of the susceptor body 21.

ところで、従来、エピタキシャル成長を行なう際の不純
物汚染対策としてBSD (Back SideDam
age )等によるダウタリング法が用いられている。
By the way, BSD (Back Side Dam) has conventionally been used as a countermeasure against impurity contamination during epitaxial growth.
The doutering method is used by et al.

これは、半導体基板の裏面に研磨剤等を吹きつけて傷を
つけることによって、基板の裏面近傍に転位を発生させ
、不純物を捕獲しようとするものである。しかしながら
、BSD法ではエピタキシャル成長以前のプロセス工程
で効果が無くなったシ、基板に傷を付ける際基板裏面に
クラックが発生し、このクラックに傷を付けるための微
粒子が入シ込む等の問題が生ずる。
This is an attempt to generate dislocations near the back surface of a semiconductor substrate and capture impurities by spraying an abrasive or the like on the back surface of the semiconductor substrate to cause scratches. However, the BSD method has problems such as ineffectiveness in process steps before epitaxial growth, cracks occurring on the back surface of the substrate when scratching the substrate, and fine particles entering the cracks to cause scratches.

〔発明の目的〕[Purpose of the invention]

本発明は上記事情に鑑みてなされたもので、半導体基板
に弾性歪みを与えることにより、気相成長中の不純物汚
染が半導体基板中の活性領域侵入するのを抑制し得る半
導体基板用サセプタを提供することを目的とする。
The present invention has been made in view of the above circumstances, and provides a susceptor for a semiconductor substrate that can suppress impurity contamination during vapor phase growth from entering an active region in the semiconductor substrate by applying elastic strain to the semiconductor substrate. The purpose is to

〔発明の概要〕[Summary of the invention]

本発明は、サセプタ本体の上部に、半導体基板に弾性歪
みを与える基板支持台を設けることにより、気相成長中
の不純物汚染が半導体基板中の活性領域に侵入するのを
抑制し得るものである。
The present invention is capable of suppressing impurity contamination during vapor phase growth from entering the active region of the semiconductor substrate by providing a substrate support that applies elastic strain to the semiconductor substrate on the upper part of the susceptor body. .

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を第1図及び第5図を参照して説
明する。
Embodiments of the present invention will be described below with reference to FIGS. 1 and 5.

実施例1 第1図において、31は、例えば高純度グラファイト上
にSICコートを施したサセプタ本体である。このサセ
プタ本体3ノの上部には、円形状の凹部32が設けられ
ている。この凹部32には、これより僅かに径が小さい
基板支持台33が設けられている。この基板支持台33
は、例えば該支持台33にセットされるシリコン基板3
4より熱膨張係数の小さい非晶質二酸化シリコン(st
o2)からなる。
Embodiment 1 In FIG. 1, numeral 31 is a susceptor body made of, for example, high-purity graphite coated with SIC. A circular recess 32 is provided in the upper part of the susceptor main body 3. This recess 32 is provided with a substrate support 33 having a slightly smaller diameter. This board support stand 33
For example, the silicon substrate 3 set on the support stand 33
Amorphous silicon dioxide (st
o2).

しかして、本発明によれば、サセプタ本体31の凹部3
2にシリコン基板34より熱膨張係数の小さい非晶質5
tO2からなる基板支持台33を設けた構造となりてい
るため、縦型気相成長装置を用いてシリコンエピタキシ
ャル成長を行なったところ、熱膨張により基板34の裏
面に弾性歪みが生じ、これにより気相成長中の不純物汚
染を捕獲できる。
Therefore, according to the present invention, the recess 3 of the susceptor body 31
2, an amorphous material 5 having a smaller coefficient of thermal expansion than the silicon substrate 34;
Since the structure includes a substrate support 33 made of tO2, when silicon epitaxial growth is performed using a vertical vapor phase growth apparatus, elastic strain occurs on the back surface of the substrate 34 due to thermal expansion, and this causes vapor phase growth. It can capture impurity contamination inside.

次に、上記実施例の半導体基板用サセプタを用い、縦型
気相成長装置でシリコンウニノーを気相成長した。この
際、シリコンウニノ・は、P型(100)で比抵抗1Ω
・鐸である。また、気相成長は5IH2Ct2を用いて
1200℃、15分間行ない、厚さ10μmのエピタキ
シャル層を有したシリコンエピタキシャルウェハ・を得
た。また、比較例として、従来(第4図)の半導体基板
用サセプタを用い前記と同条件でシリコンエピタキシャ
ルウェハを形成した。そして、これらウェハをライトエ
ッチを90秒行ない、微分干渉顕微鏡でウェハ表面を観
察したところ、比較例のウェハでは多数のエッチビット
が確認されたが、実施例のウェハには見られなかった。
Next, using the susceptor for semiconductor substrates of the above example, silicon unioxide was grown in a vapor phase using a vertical vapor phase growth apparatus. At this time, Silicon Unino is P type (100) with a specific resistance of 1Ω.
・It is a bell. Further, vapor phase growth was performed using 5IH2Ct2 at 1200 DEG C. for 15 minutes to obtain a silicon epitaxial wafer having an epitaxial layer with a thickness of 10 .mu.m. As a comparative example, a silicon epitaxial wafer was formed using a conventional susceptor for semiconductor substrates (FIG. 4) under the same conditions as above. When these wafers were subjected to light etching for 90 seconds and the wafer surfaces were observed using a differential interference microscope, a large number of etched bits were observed on the wafers of the comparative example, but none were observed on the wafers of the example.

また、これらウェハにMOSキャノJ?ジターを作りD
LTS法(D@ep Level Transitio
n 5peetoroacopy )を用いてエピタキ
シャル層中の不純物分析を行なったところ、比較例では
Ni、F・が検出されたが、実施例では何も検出されな
かった。以上により、本発明の半導体基板用サセプタが
従来のそれと比べ優れていることが明らかである。
Also, are there any MOS capacitors on these wafers? Make a jitter D
LTS method (D@ep Level Transitio
When impurities in the epitaxial layer were analyzed using a method using a method of analyzing impurities in the epitaxial layer, Ni and F were detected in the comparative example, but nothing was detected in the example. From the above, it is clear that the susceptor for semiconductor substrates of the present invention is superior to conventional susceptors.

なお、上記実施例では、基板支持台の材料が非晶質51
02である場合について述べたが、これに限らず窒化シ
リコン(Sl、N4)でもよい。
In the above embodiment, the material of the substrate support is amorphous 51.
02, but the material is not limited to this, and silicon nitride (Sl, N4) may be used.

実施例2 第5図において、41は、サセプタ本体41の凹部32
に設けられたシリコン基板34と熱膨張係数が等しいシ
リコン単結晶からなる部材である。この部材41の上部
の開口部には、熱膨張係数が前記基板34より大きい。
Embodiment 2 In FIG. 5, 41 indicates the recess 32 of the susceptor body 41.
It is a member made of silicon single crystal having the same coefficient of thermal expansion as the silicon substrate 34 provided on the substrate. The opening at the top of this member 41 has a larger coefficient of thermal expansion than the substrate 34 .

例えば酸化アルミニウム(At20.)からなる環状の
部材42が設けられている。ここで、前記部材41゜4
2分総称して基板支持台43と呼ぶ。
For example, an annular member 42 made of aluminum oxide (At20.) is provided. Here, the member 41°4
The two parts are collectively called a substrate support stand 43.

しかして、第5図の半導体基板用サセプタは、気相成長
時に基板3.4より熱膨張係数の大きい部材41が相対
的に膨張するため、基板34の裏面に弾性歪みが生じ、
実施例1と同様な効果を得ることができる。
Therefore, in the semiconductor substrate susceptor shown in FIG. 5, since the member 41 having a larger coefficient of thermal expansion than the substrate 3.4 expands relatively during vapor phase growth, elastic strain occurs on the back surface of the substrate 34.
The same effects as in Example 1 can be obtained.

なお、上記実施例2では、部材41がシリコン単結晶か
らなる場合について述べたが、これに限らず、非晶質S
 102. S l、N4等のシリコン基板34の熱膨
張係数が小さい物質でもよい。
In the second embodiment, a case has been described in which the member 41 is made of silicon single crystal, but is not limited to this.
102. A material having a small coefficient of thermal expansion for the silicon substrate 34, such as S1 or N4, may be used.

また、上記実施例2では、部材42がAt203からな
る場合について述べたが、これに限らず、水晶、炭化珪
素(SiC)等でもよい。
Further, in the second embodiment, the case where the member 42 is made of At203 has been described, but the material is not limited to this, and may be made of quartz, silicon carbide (SiC), or the like.

〔発明の効果〕〔Effect of the invention〕

以上詳述した如く本発明によれば、気相成長中の不純物
汚染が半導体基板中へ侵入するのを抑制し得る高信頼性
の半導体基板用サセプタを提供することを目的とする。
As detailed above, according to the present invention, it is an object of the present invention to provide a highly reliable susceptor for a semiconductor substrate that can suppress impurity contamination during vapor phase growth from penetrating into the semiconductor substrate.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例に係る半導体基板用サセプタ
の断面図、第2図は縦型のシリコンエピタキシャル成長
用気相成長装置の断面図、第3図はシリンダー型のシリ
コンエピタキシャル成長用気相装置の断面図、第4図は
従来の半導体基板用サセプタの断面図、第5図は本発明
の他の実施例に係る半導体基板用サセプタの断面図であ
る。 1.11・・・反応管、1,12・・・回転軸、5゜1
5・・・反応ガス導入管、6・・・反応ガス噴出口、7
・・・高周波加熱用コイル、8.16・・・反応ガス排
出管、11・・・反応管、17・・・ハロダンランプ、
18・・・反射鏡、19・・・冷却水、31・・・サセ
プタ本体、33.43・・・基板支持台、34・・・シ
リコン基板。 出願人代理人 弁理士  鈴 江 武 彦第1図 1ム 312図 第3図 第4図 η 第5図
FIG. 1 is a sectional view of a susceptor for semiconductor substrates according to an embodiment of the present invention, FIG. 2 is a sectional view of a vertical type vapor phase growth apparatus for silicon epitaxial growth, and FIG. 3 is a sectional view of a cylindrical type vapor phase growth apparatus for silicon epitaxial growth. FIG. 4 is a cross-sectional view of a conventional susceptor for semiconductor substrates, and FIG. 5 is a cross-sectional view of a susceptor for semiconductor substrates according to another embodiment of the present invention. 1.11...Reaction tube, 1,12... Rotating shaft, 5゜1
5... Reactive gas introduction pipe, 6... Reactive gas outlet, 7
... High frequency heating coil, 8.16... Reaction gas discharge pipe, 11... Reaction tube, 17... Halodan lamp,
18...Reflector, 19...Cooling water, 31...Susceptor main body, 33.43...Substrate support stand, 34...Silicon substrate. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 1 312 Figure 3 Figure 4 η Figure 5

Claims (5)

【特許請求の範囲】[Claims] (1)半導体基板を気相成長する際に用いられる半導体
基板用サセプタにおいて、サセプタ本体と、このサセプ
タ本体の上部に設けられ半導体基板に弾性歪みを与える
基板支持台とを具備することを特徴とする半導体基板用
サセプタ。
(1) A susceptor for a semiconductor substrate used in vapor phase growth of a semiconductor substrate is characterized by comprising a susceptor body and a substrate support that is provided on the top of the susceptor body and applies elastic strain to the semiconductor substrate. Susceptor for semiconductor substrates.
(2)基板支持台が半導体基板より熱膨張係数の小さい
物質からなることを特徴とする特許請求の範囲第1項記
載の半導体基板用サセプタ。
(2) The susceptor for a semiconductor substrate according to claim 1, wherein the substrate support is made of a material having a coefficient of thermal expansion smaller than that of the semiconductor substrate.
(3)基板支持台が、半導体基板に対し環状に密着して
設けられた前記基板より熱膨張係数の大きい物質からな
る第1の部材と、この第1の部材及び基板の夫々の裏面
及び前記部材の側壁と密着して設けられた前記基板より
熱膨張係数が同等以下の物質からなる第2の部材から構
成されることを特徴とする特許請求の範囲第1項記載の
半導体基板用サセプタ。
(3) The substrate support includes a first member made of a material having a coefficient of thermal expansion larger than that of the substrate, which is provided in close contact with the semiconductor substrate in an annular shape, and a back surface of each of the first member and the substrate, and 2. The susceptor for a semiconductor substrate according to claim 1, further comprising a second member made of a material having a coefficient of thermal expansion equal to or lower than that of the substrate, which is provided in close contact with a side wall of the member.
(4)半導体基板としてシリコン基板を用い、かつ熱膨
張係数の小さい物質が酸化アルミニウム、水晶あるいは
炭化珪素であることを特徴とする特許請求の範囲第2項
記載の半導体基板用サセプタ。
(4) The susceptor for a semiconductor substrate according to claim 2, wherein a silicon substrate is used as the semiconductor substrate, and the substance with a small coefficient of thermal expansion is aluminum oxide, crystal, or silicon carbide.
(5)半導体基板としてシリコン基板を用いるとともに
、熱膨張係数の小さい物質が酸化アルミニウム、水晶あ
るいは炭化ケイ素であり、かつ熱膨張係数が基板と同等
以下の物質が非晶質二酸化シリコン、窒化シリコンであ
ることを特徴とする特許請求の範囲第3項記載の半導体
基板用サセプタ。
(5) In addition to using a silicon substrate as the semiconductor substrate, the material with a small coefficient of thermal expansion is aluminum oxide, crystal, or silicon carbide, and the material with a coefficient of thermal expansion equal to or lower than that of the substrate is amorphous silicon dioxide or silicon nitride. A susceptor for a semiconductor substrate according to claim 3, characterized in that:
JP5653185A 1985-03-20 1985-03-20 Susceptor for semiconductor substrate Pending JPS61214515A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5653185A JPS61214515A (en) 1985-03-20 1985-03-20 Susceptor for semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5653185A JPS61214515A (en) 1985-03-20 1985-03-20 Susceptor for semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS61214515A true JPS61214515A (en) 1986-09-24

Family

ID=13029676

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5653185A Pending JPS61214515A (en) 1985-03-20 1985-03-20 Susceptor for semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS61214515A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63140085A (en) * 1986-11-29 1988-06-11 Kyocera Corp Film forming device
US5820686A (en) * 1993-01-21 1998-10-13 Moore Epitaxial, Inc. Multi-layer susceptor for rapid thermal process reactors
JP2008198800A (en) * 2007-02-13 2008-08-28 Bridgestone Corp Heat treatment tool

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63140085A (en) * 1986-11-29 1988-06-11 Kyocera Corp Film forming device
US5820686A (en) * 1993-01-21 1998-10-13 Moore Epitaxial, Inc. Multi-layer susceptor for rapid thermal process reactors
JP2008198800A (en) * 2007-02-13 2008-08-28 Bridgestone Corp Heat treatment tool

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