JPS6116529A - Flattening method for surface of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device with its flat surface having no both protrusion and void by a method wherein insulating films are selectively formed in the etched parts of the surface of the device without taking out the device from the reaction chamber used for performing an etching on the surface of the semiconductor device. CONSTITUTION:A silicon substrate 11, whereon an SiO2 film 12 and an aluminum thin film 13 are formed, is thrown in the reaction chamber and chlorine reaction gas is introduced in the reaction chamber. Then, when light is selectively irradiated in irradiation extents 15, the aluminum thin film 13 is etched and wiring layers 13 and gaps 14 are formed. Cl2 is exhausted from the reaction chamber, and SiH4 and NH3, for example, are introduced in the reaction chamber. When light is irradiated in irradiation extents 15', Si3N4 films 16 are formed and the gaps 14 are buried in. As the width of the Si3N4 films 16 can be changed according to the forming conditions of optical intensity and so forth, a condition of enabling to form most flatly the surface of this semiconductor device can be easily obtained. In this series of the etching and film forming processes, there is no need to draw out this silicon substrate outside the reaction chamber.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for flattening the surface of a semiconductor device, and more specifically, a method for planarizing the surface of a semiconductor device, in particular, by filling a recess formed on the surface of the device with an insulator or the like.
The present invention relates to a method for flattening a surface.

Conventional configurations and their problems In recent years, as semiconductor integrated circuits have become more highly integrated, the processing dimensions of elements have been steadily decreasing. However, the thickness of the wiring metal layer cannot be reduced proportionally because of the increase in wiring resistance, and the thickness of the element isolation layer cannot be reduced proportionally because of the increase in the parasitic transistor effect. Therefore, taking a wiring metal layer as an example, its width and thickness are approximately the same, and as a result, the surface of the semiconductor device becomes extremely uneven. Such surface irregularities can cause wire breakage at stepped portions of the wiring metal formed on top of the surface, leading to a significant drop in device yield. Various methods have been proposed. An example of a conventional surface flattening method will be schematically described below with reference to the drawings.

FIGS. 1(a) and 1(b) are flowcharts showing a conventional surface flattening method in the order of steps.

FIG. 1(-) is a cross-sectional view of the semiconductor device at the time when the metal wiring forming process is completed, in which a thermal oxide film 2. A metal wiring layer 3 is formed.

The minimum width and thickness of the metal wiring layer 3 are approximately the same size,
In addition, gaps 4 are formed between adjacent metal wiring layers 3 such that the minimum width and depth are approximately the same.

Next, as shown in FIG. 1(b), a silicon oxide film (hereinafter referred to as 5102 film) 5 formed by the CVD method to a thickness similar to that of the metal wiring layer 3 is grown on the entire surface. Sio on the metal wiring layer 3 is
2 film 6 is removed. As a result, the gap 4 can be filled, but since it is generally impossible to reduce the mask misalignment to zero with the photolithography method, as a result, the protrusion 6 on the metal wiring layer 3 and the metal wiring layer 3 and 5i
Either one or both of the gaps 7 between the n2 film 6 and the n2 film 6 are formed. Removing the protrusions 6 or filling in the voids 7 to make the surface flat requires a very complicated process, which involves a large number of processes and is not easy to control, which results in a decrease in yield. may invite

In order to prevent mask misalignment, a method has also been proposed in which the 3102 film on the metal wiring layer 3 is removed in a self-aligned manner (by a lift-off method using photoresist) and the gap 4 is filled in, but the metal wiring A gap is formed between the layer and the SiO2 film, and a complicated process is still required to fill the gap.

OBJECTS OF THE INVENTION The present invention solves the problems of the conventional methods as described above, and provides a method for planarizing the surface of a semiconductor device that has a simple process and is suitable for high integration. .

Components of the Invention In summary, the present invention comprises a step of selectively etching a part of the surface of a semiconductor device by a photochemical reaction, and a step of selectively etching a part of the surface of a semiconductor device by a photochemical reaction, and etching the semiconductor device without taking the semiconductor device out of the reaction chamber used for etching. This is a surface planarization method for semiconductor devices that includes a step of selectively forming an insulating film by a photochemical reaction on roughly the same part as the part etched by the etching process. It is possible to realize a semiconductor device having a flat surface without cracks.

Description of examples The present invention will be described in detail below with reference to Examples.

FIGS. 2(a), 2(b), and 2(C) are flowcharts showing, in order of process, the process of planarizing the surface of a wiring metal layer of an integrated circuit as an embodiment of the present invention.

FIG. 2(a) shows an S x O2 film 12 formed on a silicon substrate 11 by a thermal oxidation method. Aluminum thin film 1
3 has been formed. The substrate in this state is placed in the reaction chamber (
(not shown), and the reaction chamber is evacuated at a pressure of about 10 to 1 o-'Pa.

Next, a chlorine-based reaction gas, for example, Cl3, is added to this reaction chamber.
is introduced to a pressure of 100 to several thousand P and several thousand Pa.

Next, when the irradiation range 15 shown in FIG. 2(b) is selectively irradiated with light using a well-known technique such as projection exposure, the aluminum thin film 13 is etched in the irradiation range 16 due to a photochemical reaction. , a wiring layer 13',
A gap 14 is formed.

The temperature of the silicon substrate 11 during this etching may be room temperature, or may be heated to about 200°C.Next, Cl3 is discharged from the reaction chamber, and the temperature is 10-5 to 10°C again.
- Reactant gas containing silicon after being brought to a pressure of P
For example, S I H4 and a reactant gas containing nitrogen, such as N
H3 is introduced to a pressure of about 10 to 100 Pa.

In this state, while heating the silicon substrate 11 to a temperature of about 200 to 400° C., as shown in FIG. 2(c), That is, when the irradiation range 16' is irradiated with light, the Si3N4 film 16 is formed in the irradiation range 15' due to a photochemical reaction, and the gap 14 is filled in.

At this time, it is appropriate that the thickness of the Si3N4 film 16 be approximately the same as the thickness of the wiring layer 13'. In addition, the Si3N4 film 16
Since the zero width can be changed depending on the formation conditions such as light intensity, it is easy to obtain the conditions that give the flattest surface.

In the series of etching and film forming processes described above, it is not necessary to take the silicon substrate 11 out of the reaction chamber. In addition, since there is no need to replace or move the photomask used for projection exposure, if the silicon substrate 11 is fixed in the reaction chamber, the Si3
The light irradiation range can be the same as when forming the N4 film 16,
No positional deviation occurs between processes. Furthermore, even when using the so-called step-and-repeat method as the exposure method,
The positional deviation of the irradiation range during etching and during film formation is determined only by the mechanical feed accuracy of the pedestal to which the substrate is fixed. This feeding accuracy has been achieved on the order of several nanometers in recent devices, and is not a major problem. Furthermore, expansion and contraction of the substrate due to the difference in substrate temperature between etching and film formation can be easily dealt with by mechanically changing the magnification of the image during projection.

In the above embodiments, aluminum was used as the film to be etched, but by changing the etching conditions, the film may be etched with polycrystalline silicon, single crystal silicon, S102 film, or other materials. Although a Si3N4 film is used as an example of the warped film, a S z O2 film, a polycrystalline silicon film, etc. can also be formed. Furthermore, it goes without saying that materials other than silicon can be used for the semiconductor substrate.

Effect of the invention According to the present invention, there are the following effects.

First, since surface planarization can be achieved with a small number of steps, semiconductor devices with good device yields can be obtained.

Second, since the effects of ions and plasma are not used in etching and film formation, there is little damage to the device, and a semiconductor device with good electrical characteristics can be obtained.

Thirdly, the alignment between the etched area and the embedded area is determined only by the mechanical precision of the device at worst, and so-called misalignment between processes hardly occurs, so minute protrusions and gaps are formed on the surface. never be done.

[Brief explanation of the drawing]

FIGS. 1(a) and 1-(b) are process flowcharts of a conventional surface flattening method, and FIGS. 2(a) to (C) are process flowcharts of an embodiment of the present invention. 1.11... Silicon substrate, 2.12. Moe... Thermal oxide film, 3... Metal wiring layer, 4.14...
Gap, 6...CVD oxide film, 6...Protrusion, 7...Gap, 13...Aluminum thin film, 13'... Wiring layer, 15, 15'
....Irradiation range, 16...S 1 s
N4 membrane. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
figure

Claims (1)

[Claims] A step of selectively etching a part of the surface of a semiconductor device by a photochemical reaction, and a step of etching a part of the surface of a semiconductor device by photochemical reaction; A method for planarizing the surface of a semiconductor device, which includes a step of selectively forming an insulating film through a photochemical reaction.