JPS5762542A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5762542A
JPS5762542A JP55137912A JP13791280A JPS5762542A JP S5762542 A JPS5762542 A JP S5762542A JP 55137912 A JP55137912 A JP 55137912A JP 13791280 A JP13791280 A JP 13791280A JP S5762542 A JPS5762542 A JP S5762542A
Authority
JP
Japan
Prior art keywords
film
pattern
aluminum
protective film
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55137912A
Other languages
Japanese (ja)
Other versions
JPS6217862B2 (en
Inventor
Satoru Maeda
Hiroshi Iwai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55137912A priority Critical patent/JPS5762542A/en
Priority to US06/307,877 priority patent/US4560421A/en
Publication of JPS5762542A publication Critical patent/JPS5762542A/en
Publication of JPS6217862B2 publication Critical patent/JPS6217862B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To carry out high performance and high integration of a semiconductor device by forming a protective film, preventing the reduction in the etched film of a field insulating film and securing a sufficient field inversion voltage. CONSTITUTION:An SiO2 film 102 is formed on a P type silicon substrate 101, and an Si3N4 film 103 is formed as a protective film thereon. After a resist pattern 104 is then formed, with the pattern as a mask boron ions are injected to form a P type inversion preventive layer 105 on the substrate 101. Then, an aluminum film 106 is accumulated on the overall surface. Subsequently, the resist pattern 104 is removed, the aluminum film part 1061 thereon is lifted off, with the remaining aluminum pattern 1062 as a mask the films 103, 102 are etched and removed to eliminate the aluminum pattern, thereby forming a field oxidized film 107 covered with the protective film (Si3N4 film) 103 on the upper surface. Thereafter, an element is formed.
JP55137912A 1980-10-02 1980-10-02 Manufacture of semiconductor device Granted JPS5762542A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP55137912A JPS5762542A (en) 1980-10-02 1980-10-02 Manufacture of semiconductor device
US06/307,877 US4560421A (en) 1980-10-02 1981-10-02 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55137912A JPS5762542A (en) 1980-10-02 1980-10-02 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5762542A true JPS5762542A (en) 1982-04-15
JPS6217862B2 JPS6217862B2 (en) 1987-04-20

Family

ID=15209580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55137912A Granted JPS5762542A (en) 1980-10-02 1980-10-02 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5762542A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9269765B2 (en) 2013-10-21 2016-02-23 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device having gate wire disposed on roughened field insulating film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9269765B2 (en) 2013-10-21 2016-02-23 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device having gate wire disposed on roughened field insulating film

Also Published As

Publication number Publication date
JPS6217862B2 (en) 1987-04-20

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