JPS56144556A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS56144556A
JPS56144556A JP4782080A JP4782080A JPS56144556A JP S56144556 A JPS56144556 A JP S56144556A JP 4782080 A JP4782080 A JP 4782080A JP 4782080 A JP4782080 A JP 4782080A JP S56144556 A JPS56144556 A JP S56144556A
Authority
JP
Japan
Prior art keywords
sio2
si3n4
polycrystalline
substrate
damaged
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4782080A
Other languages
Japanese (ja)
Inventor
Hideaki Ozawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4782080A priority Critical patent/JPS56144556A/en
Publication of JPS56144556A publication Critical patent/JPS56144556A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To prevent the Si substrate in the element forming region from being damaged, by performing the plasma etching of the wiring polycrystalline Si after protecting the Si3N4 used to form an element separating oxide film with SiO2. CONSTITUTION:On a P type Si substrate 1, an SiO2 film 11 is formed and thereon, a mask of double-layer structure comprising Si3N4 12 and SiO2 16 is formed. Then, a thick SiO2 13 is formed by a heat treatment and coated with a doped polycrystalline Si 14. A resist mask is applied, and the polycrystalline Si 14 is plasma-etched to form a wiring 14A on the element separating layer. Thereby, being protected by the SiO2 16, the Si3N4 12 is kept from the plasma etching. Then, SiO2 15 is formed as an interlayer insulating film. Thereafter, the whole except for the element forming region is covered with a resist mask and successively etched until the substrate surface 17 is exposed, and an FET, for example, is formed. Because the FET forming surface has not been damaged, a highly reliable device, which has stable characteristics, can be obtained.
JP4782080A 1980-04-11 1980-04-11 Manufacture of semiconductor device Pending JPS56144556A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4782080A JPS56144556A (en) 1980-04-11 1980-04-11 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4782080A JPS56144556A (en) 1980-04-11 1980-04-11 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56144556A true JPS56144556A (en) 1981-11-10

Family

ID=12785986

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4782080A Pending JPS56144556A (en) 1980-04-11 1980-04-11 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56144556A (en)

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